2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
32 #include <net/switchdev.h>
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65
[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
81 /* BCM63xx MIB counters */
82 static const struct b53_mib_desc b53_mibs_63xx
[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
130 static const struct b53_mib_desc b53_mibs
[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
170 static const struct b53_mib_desc b53_mibs_58xx
[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
229 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
233 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
235 for (i
= 0; i
< 10; i
++) {
238 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
239 if (!(vta
& VTA_START_CMD
))
242 usleep_range(100, 200);
248 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
,
249 struct b53_vlan
*vlan
)
255 entry
= ((vlan
->untag
& VA_UNTAG_MASK_25
) <<
256 VA_UNTAG_S_25
) | vlan
->members
;
257 if (dev
->core_rev
>= 3)
258 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
260 entry
|= VA_VALID_25
;
263 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
264 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
265 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
266 } else if (is5365(dev
)) {
270 entry
= ((vlan
->untag
& VA_UNTAG_MASK_65
) <<
271 VA_UNTAG_S_65
) | vlan
->members
| VA_VALID_65
;
273 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
274 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
275 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
277 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
278 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
279 (vlan
->untag
<< VTE_UNTAG_S
) | vlan
->members
);
281 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
284 dev_dbg(dev
->ds
->dev
, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid
, vlan
->members
, vlan
->untag
);
288 static void b53_get_vlan_entry(struct b53_device
*dev
, u16 vid
,
289 struct b53_vlan
*vlan
)
294 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
295 VTA_RW_STATE_RD
| VTA_RW_OP_EN
);
296 b53_read32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, &entry
);
298 if (dev
->core_rev
>= 3)
299 vlan
->valid
= !!(entry
& VA_VALID_25_R4
);
301 vlan
->valid
= !!(entry
& VA_VALID_25
);
302 vlan
->members
= entry
& VA_MEMBER_MASK
;
303 vlan
->untag
= (entry
>> VA_UNTAG_S_25
) & VA_UNTAG_MASK_25
;
305 } else if (is5365(dev
)) {
308 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
309 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
310 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, &entry
);
312 vlan
->valid
= !!(entry
& VA_VALID_65
);
313 vlan
->members
= entry
& VA_MEMBER_MASK
;
314 vlan
->untag
= (entry
>> VA_UNTAG_S_65
) & VA_UNTAG_MASK_65
;
318 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
319 b53_do_vlan_op(dev
, VTA_CMD_READ
);
320 b53_read32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2], &entry
);
321 vlan
->members
= entry
& VTE_MEMBERS
;
322 vlan
->untag
= (entry
>> VTE_UNTAG_S
) & VTE_MEMBERS
;
327 static void b53_set_forwarding(struct b53_device
*dev
, int enable
)
331 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
334 mgmt
|= SM_SW_FWD_EN
;
336 mgmt
&= ~SM_SW_FWD_EN
;
338 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
341 static void b53_enable_vlan(struct b53_device
*dev
, bool enable
)
343 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
345 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
346 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
347 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
349 if (is5325(dev
) || is5365(dev
)) {
350 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
351 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
352 } else if (is63xx(dev
)) {
353 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
354 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
356 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
357 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
360 mgmt
&= ~SM_SW_FWD_MODE
;
363 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
364 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
365 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
366 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
367 vc5
|= VC5_DROP_VTABLE_MISS
;
370 vc0
&= ~VC0_RESERVED_1
;
372 if (is5325(dev
) || is5365(dev
))
373 vc1
|= VC1_RX_MCST_TAG_EN
;
376 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
377 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
378 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
379 vc5
&= ~VC5_DROP_VTABLE_MISS
;
381 if (is5325(dev
) || is5365(dev
))
382 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
384 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
386 if (is5325(dev
) || is5365(dev
))
387 vc1
&= ~VC1_RX_MCST_TAG_EN
;
390 if (!is5325(dev
) && !is5365(dev
))
391 vc5
&= ~VC5_VID_FFF_EN
;
393 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
394 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
396 if (is5325(dev
) || is5365(dev
)) {
397 /* enable the high 8 bit vid check on 5325 */
398 if (is5325(dev
) && enable
)
399 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
402 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
404 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
405 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
406 } else if (is63xx(dev
)) {
407 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
408 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
409 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
411 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
412 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
413 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
416 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
419 static int b53_set_jumbo(struct b53_device
*dev
, bool enable
, bool allow_10_100
)
422 u16 max_size
= JMS_MIN_SIZE
;
424 if (is5325(dev
) || is5365(dev
))
428 port_mask
= dev
->enabled_ports
;
429 max_size
= JMS_MAX_SIZE
;
431 port_mask
|= JPM_10_100_JUMBO_EN
;
434 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
435 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
438 static int b53_flush_arl(struct b53_device
*dev
, u8 mask
)
442 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
443 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| mask
);
445 for (i
= 0; i
< 10; i
++) {
448 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
451 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
459 /* Only age dynamic entries (default behavior) */
460 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
, FAST_AGE_DYNAMIC
);
464 static int b53_fast_age_port(struct b53_device
*dev
, int port
)
466 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_PORT_CTRL
, port
);
468 return b53_flush_arl(dev
, FAST_AGE_PORT
);
471 static int b53_fast_age_vlan(struct b53_device
*dev
, u16 vid
)
473 b53_write16(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_VID_CTRL
, vid
);
475 return b53_flush_arl(dev
, FAST_AGE_VLAN
);
478 static void b53_imp_vlan_setup(struct dsa_switch
*ds
, int cpu_port
)
480 struct b53_device
*dev
= ds
->priv
;
484 /* Enable the IMP port to be in the same VLAN as the other ports
485 * on a per-port basis such that we only have Port i and IMP in
488 b53_for_each_port(dev
, i
) {
489 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), &pvlan
);
490 pvlan
|= BIT(cpu_port
);
491 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), pvlan
);
495 static int b53_enable_port(struct dsa_switch
*ds
, int port
,
496 struct phy_device
*phy
)
498 struct b53_device
*dev
= ds
->priv
;
499 unsigned int cpu_port
= dev
->cpu_port
;
502 /* Clear the Rx and Tx disable bits and set to no spanning tree */
503 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), 0);
505 /* Set this port, and only this one to be in the default VLAN,
506 * if member of a bridge, restore its membership prior to
507 * bringing down this port.
509 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
512 pvlan
|= dev
->ports
[port
].vlan_ctl_mask
;
513 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
515 b53_imp_vlan_setup(ds
, cpu_port
);
520 static void b53_disable_port(struct dsa_switch
*ds
, int port
,
521 struct phy_device
*phy
)
523 struct b53_device
*dev
= ds
->priv
;
526 /* Disable Tx/Rx for the port */
527 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), ®
);
528 reg
|= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
529 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), reg
);
532 static void b53_enable_cpu_port(struct b53_device
*dev
)
534 unsigned int cpu_port
= dev
->cpu_port
;
537 /* BCM5325 CPU port is at 8 */
538 if ((is5325(dev
) || is5365(dev
)) && cpu_port
== B53_CPU_PORT_25
)
539 cpu_port
= B53_CPU_PORT
;
541 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
542 PORT_CTRL_RX_MCST_EN
|
543 PORT_CTRL_RX_UCST_EN
;
544 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(cpu_port
), port_ctrl
);
547 static void b53_enable_mib(struct b53_device
*dev
)
551 b53_read8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
552 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
553 b53_write8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
);
556 static int b53_configure_vlan(struct b53_device
*dev
)
558 struct b53_vlan vl
= { 0 };
561 /* clear all vlan entries */
562 if (is5325(dev
) || is5365(dev
)) {
563 for (i
= 1; i
< dev
->num_vlans
; i
++)
564 b53_set_vlan_entry(dev
, i
, &vl
);
566 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
569 b53_enable_vlan(dev
, false);
571 b53_for_each_port(dev
, i
)
572 b53_write16(dev
, B53_VLAN_PAGE
,
573 B53_VLAN_PORT_DEF_TAG(i
), 1);
575 if (!is5325(dev
) && !is5365(dev
))
576 b53_set_jumbo(dev
, dev
->enable_jumbo
, false);
581 static void b53_switch_reset_gpio(struct b53_device
*dev
)
583 int gpio
= dev
->reset_gpio
;
588 /* Reset sequence: RESET low(50ms)->high(20ms)
590 gpio_set_value(gpio
, 0);
593 gpio_set_value(gpio
, 1);
596 dev
->current_page
= 0xff;
599 static int b53_switch_reset(struct b53_device
*dev
)
603 b53_switch_reset_gpio(dev
);
606 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
607 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
610 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
612 if (!(mgmt
& SM_SW_FWD_EN
)) {
613 mgmt
&= ~SM_SW_FWD_MODE
;
614 mgmt
|= SM_SW_FWD_EN
;
616 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
617 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
619 if (!(mgmt
& SM_SW_FWD_EN
)) {
620 dev_err(dev
->dev
, "Failed to enable switch!\n");
627 return b53_flush_arl(dev
, FAST_AGE_STATIC
);
630 static int b53_phy_read16(struct dsa_switch
*ds
, int addr
, int reg
)
632 struct b53_device
*priv
= ds
->priv
;
636 if (priv
->ops
->phy_read16
)
637 ret
= priv
->ops
->phy_read16(priv
, addr
, reg
, &value
);
639 ret
= b53_read16(priv
, B53_PORT_MII_PAGE(addr
),
642 return ret
? ret
: value
;
645 static int b53_phy_write16(struct dsa_switch
*ds
, int addr
, int reg
, u16 val
)
647 struct b53_device
*priv
= ds
->priv
;
649 if (priv
->ops
->phy_write16
)
650 return priv
->ops
->phy_write16(priv
, addr
, reg
, val
);
652 return b53_write16(priv
, B53_PORT_MII_PAGE(addr
), reg
* 2, val
);
655 static int b53_reset_switch(struct b53_device
*priv
)
658 priv
->enable_jumbo
= false;
660 memset(priv
->vlans
, 0, sizeof(*priv
->vlans
) * priv
->num_vlans
);
661 memset(priv
->ports
, 0, sizeof(*priv
->ports
) * priv
->num_ports
);
663 return b53_switch_reset(priv
);
666 static int b53_apply_config(struct b53_device
*priv
)
668 /* disable switching */
669 b53_set_forwarding(priv
, 0);
671 b53_configure_vlan(priv
);
673 /* enable switching */
674 b53_set_forwarding(priv
, 1);
679 static void b53_reset_mib(struct b53_device
*priv
)
683 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
685 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
687 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
691 static const struct b53_mib_desc
*b53_get_mib(struct b53_device
*dev
)
695 else if (is63xx(dev
))
696 return b53_mibs_63xx
;
697 else if (is58xx(dev
))
698 return b53_mibs_58xx
;
703 static unsigned int b53_get_mib_size(struct b53_device
*dev
)
706 return B53_MIBS_65_SIZE
;
707 else if (is63xx(dev
))
708 return B53_MIBS_63XX_SIZE
;
709 else if (is58xx(dev
))
710 return B53_MIBS_58XX_SIZE
;
712 return B53_MIBS_SIZE
;
715 void b53_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
717 struct b53_device
*dev
= ds
->priv
;
718 const struct b53_mib_desc
*mibs
= b53_get_mib(dev
);
719 unsigned int mib_size
= b53_get_mib_size(dev
);
722 for (i
= 0; i
< mib_size
; i
++)
723 memcpy(data
+ i
* ETH_GSTRING_LEN
,
724 mibs
[i
].name
, ETH_GSTRING_LEN
);
726 EXPORT_SYMBOL(b53_get_strings
);
728 void b53_get_ethtool_stats(struct dsa_switch
*ds
, int port
, uint64_t *data
)
730 struct b53_device
*dev
= ds
->priv
;
731 const struct b53_mib_desc
*mibs
= b53_get_mib(dev
);
732 unsigned int mib_size
= b53_get_mib_size(dev
);
733 const struct b53_mib_desc
*s
;
737 if (is5365(dev
) && port
== 5)
740 mutex_lock(&dev
->stats_mutex
);
742 for (i
= 0; i
< mib_size
; i
++) {
746 b53_read64(dev
, B53_MIB_PAGE(port
), s
->offset
, &val
);
750 b53_read32(dev
, B53_MIB_PAGE(port
), s
->offset
,
757 mutex_unlock(&dev
->stats_mutex
);
759 EXPORT_SYMBOL(b53_get_ethtool_stats
);
761 int b53_get_sset_count(struct dsa_switch
*ds
)
763 struct b53_device
*dev
= ds
->priv
;
765 return b53_get_mib_size(dev
);
767 EXPORT_SYMBOL(b53_get_sset_count
);
769 static int b53_setup(struct dsa_switch
*ds
)
771 struct b53_device
*dev
= ds
->priv
;
775 ret
= b53_reset_switch(dev
);
777 dev_err(ds
->dev
, "failed to reset switch\n");
783 ret
= b53_apply_config(dev
);
785 dev_err(ds
->dev
, "failed to apply configuration\n");
787 for (port
= 0; port
< dev
->num_ports
; port
++) {
788 if (BIT(port
) & ds
->enabled_port_mask
)
789 b53_enable_port(ds
, port
, NULL
);
790 else if (dsa_is_cpu_port(ds
, port
))
791 b53_enable_cpu_port(dev
);
793 b53_disable_port(ds
, port
, NULL
);
799 static void b53_adjust_link(struct dsa_switch
*ds
, int port
,
800 struct phy_device
*phydev
)
802 struct b53_device
*dev
= ds
->priv
;
803 u8 rgmii_ctrl
= 0, reg
= 0, off
;
805 if (!phy_is_pseudo_fixed_link(phydev
))
808 /* Override the port settings */
809 if (port
== dev
->cpu_port
) {
810 off
= B53_PORT_OVERRIDE_CTRL
;
811 reg
= PORT_OVERRIDE_EN
;
813 off
= B53_GMII_PORT_OVERRIDE_CTRL(port
);
817 /* Set the link UP */
819 reg
|= PORT_OVERRIDE_LINK
;
821 if (phydev
->duplex
== DUPLEX_FULL
)
822 reg
|= PORT_OVERRIDE_FULL_DUPLEX
;
824 switch (phydev
->speed
) {
826 reg
|= PORT_OVERRIDE_SPEED_2000M
;
829 reg
|= PORT_OVERRIDE_SPEED_1000M
;
832 reg
|= PORT_OVERRIDE_SPEED_100M
;
835 reg
|= PORT_OVERRIDE_SPEED_10M
;
838 dev_err(ds
->dev
, "unknown speed: %d\n", phydev
->speed
);
842 /* Enable flow control on BCM5301x's CPU port */
843 if (is5301x(dev
) && port
== dev
->cpu_port
)
844 reg
|= PORT_OVERRIDE_RX_FLOW
| PORT_OVERRIDE_TX_FLOW
;
847 if (phydev
->asym_pause
)
848 reg
|= PORT_OVERRIDE_TX_FLOW
;
849 reg
|= PORT_OVERRIDE_RX_FLOW
;
852 b53_write8(dev
, B53_CTRL_PAGE
, off
, reg
);
854 if (is531x5(dev
) && phy_interface_is_rgmii(phydev
)) {
856 off
= B53_RGMII_CTRL_IMP
;
858 off
= B53_RGMII_CTRL_P(port
);
860 /* Configure the port RGMII clock delay by DLL disabled and
861 * tx_clk aligned timing (restoring to reset defaults)
863 b53_read8(dev
, B53_CTRL_PAGE
, off
, &rgmii_ctrl
);
864 rgmii_ctrl
&= ~(RGMII_CTRL_DLL_RXC
| RGMII_CTRL_DLL_TXC
|
865 RGMII_CTRL_TIMING_SEL
);
867 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
868 * sure that we enable the port TX clock internal delay to
869 * account for this internal delay that is inserted, otherwise
870 * the switch won't be able to receive correctly.
872 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
873 * any delay neither on transmission nor reception, so the
874 * BCM53125 must also be configured accordingly to account for
875 * the lack of delay and introduce
877 * The BCM53125 switch has its RX clock and TX clock control
878 * swapped, hence the reason why we modify the TX clock path in
881 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
882 rgmii_ctrl
|= RGMII_CTRL_DLL_TXC
;
883 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII
)
884 rgmii_ctrl
|= RGMII_CTRL_DLL_TXC
| RGMII_CTRL_DLL_RXC
;
885 rgmii_ctrl
|= RGMII_CTRL_TIMING_SEL
;
886 b53_write8(dev
, B53_CTRL_PAGE
, off
, rgmii_ctrl
);
888 dev_info(ds
->dev
, "Configured port %d for %s\n", port
,
889 phy_modes(phydev
->interface
));
892 /* configure MII port if necessary */
894 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
897 /* reverse mii needs to be enabled */
898 if (!(reg
& PORT_OVERRIDE_RV_MII_25
)) {
899 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
900 reg
| PORT_OVERRIDE_RV_MII_25
);
901 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
904 if (!(reg
& PORT_OVERRIDE_RV_MII_25
)) {
906 "Failed to enable reverse MII mode\n");
910 } else if (is5301x(dev
)) {
911 if (port
!= dev
->cpu_port
) {
912 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(dev
->cpu_port
);
915 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
916 gmii_po
|= GMII_PO_LINK
|
921 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
926 int b53_vlan_filtering(struct dsa_switch
*ds
, int port
, bool vlan_filtering
)
930 EXPORT_SYMBOL(b53_vlan_filtering
);
932 int b53_vlan_prepare(struct dsa_switch
*ds
, int port
,
933 const struct switchdev_obj_port_vlan
*vlan
,
934 struct switchdev_trans
*trans
)
936 struct b53_device
*dev
= ds
->priv
;
938 if ((is5325(dev
) || is5365(dev
)) && vlan
->vid_begin
== 0)
941 if (vlan
->vid_end
> dev
->num_vlans
)
944 b53_enable_vlan(dev
, true);
948 EXPORT_SYMBOL(b53_vlan_prepare
);
950 void b53_vlan_add(struct dsa_switch
*ds
, int port
,
951 const struct switchdev_obj_port_vlan
*vlan
,
952 struct switchdev_trans
*trans
)
954 struct b53_device
*dev
= ds
->priv
;
955 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
956 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
957 unsigned int cpu_port
= dev
->cpu_port
;
961 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
962 vl
= &dev
->vlans
[vid
];
964 b53_get_vlan_entry(dev
, vid
, vl
);
966 vl
->members
|= BIT(port
) | BIT(cpu_port
);
968 vl
->untag
|= BIT(port
);
970 vl
->untag
&= ~BIT(port
);
971 vl
->untag
&= ~BIT(cpu_port
);
973 b53_set_vlan_entry(dev
, vid
, vl
);
974 b53_fast_age_vlan(dev
, vid
);
978 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
),
980 b53_fast_age_vlan(dev
, vid
);
983 EXPORT_SYMBOL(b53_vlan_add
);
985 int b53_vlan_del(struct dsa_switch
*ds
, int port
,
986 const struct switchdev_obj_port_vlan
*vlan
)
988 struct b53_device
*dev
= ds
->priv
;
989 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
994 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
), &pvid
);
996 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
997 vl
= &dev
->vlans
[vid
];
999 b53_get_vlan_entry(dev
, vid
, vl
);
1001 vl
->members
&= ~BIT(port
);
1004 if (is5325(dev
) || is5365(dev
))
1011 vl
->untag
&= ~(BIT(port
));
1013 b53_set_vlan_entry(dev
, vid
, vl
);
1014 b53_fast_age_vlan(dev
, vid
);
1017 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
), pvid
);
1018 b53_fast_age_vlan(dev
, pvid
);
1022 EXPORT_SYMBOL(b53_vlan_del
);
1024 int b53_vlan_dump(struct dsa_switch
*ds
, int port
,
1025 struct switchdev_obj_port_vlan
*vlan
,
1026 int (*cb
)(struct switchdev_obj
*obj
))
1028 struct b53_device
*dev
= ds
->priv
;
1029 u16 vid
, vid_start
= 0, pvid
;
1030 struct b53_vlan
*vl
;
1033 if (is5325(dev
) || is5365(dev
))
1036 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
), &pvid
);
1038 /* Use our software cache for dumps, since we do not have any HW
1039 * operation returning only the used/valid VLANs
1041 for (vid
= vid_start
; vid
< dev
->num_vlans
; vid
++) {
1042 vl
= &dev
->vlans
[vid
];
1047 if (!(vl
->members
& BIT(port
)))
1050 vlan
->vid_begin
= vlan
->vid_end
= vid
;
1053 if (vl
->untag
& BIT(port
))
1054 vlan
->flags
|= BRIDGE_VLAN_INFO_UNTAGGED
;
1056 vlan
->flags
|= BRIDGE_VLAN_INFO_PVID
;
1058 err
= cb(&vlan
->obj
);
1065 EXPORT_SYMBOL(b53_vlan_dump
);
1067 /* Address Resolution Logic routines */
1068 static int b53_arl_op_wait(struct b53_device
*dev
)
1070 unsigned int timeout
= 10;
1074 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, ®
);
1075 if (!(reg
& ARLTBL_START_DONE
))
1078 usleep_range(1000, 2000);
1079 } while (timeout
--);
1081 dev_warn(dev
->dev
, "timeout waiting for ARL to finish: 0x%02x\n", reg
);
1086 static int b53_arl_rw_op(struct b53_device
*dev
, unsigned int op
)
1093 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, ®
);
1094 reg
|= ARLTBL_START_DONE
;
1099 b53_write8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, reg
);
1101 return b53_arl_op_wait(dev
);
1104 static int b53_arl_read(struct b53_device
*dev
, u64 mac
,
1105 u16 vid
, struct b53_arl_entry
*ent
, u8
*idx
,
1111 ret
= b53_arl_op_wait(dev
);
1116 for (i
= 0; i
< dev
->num_arl_entries
; i
++) {
1120 b53_read64(dev
, B53_ARLIO_PAGE
,
1121 B53_ARLTBL_MAC_VID_ENTRY(i
), &mac_vid
);
1122 b53_read32(dev
, B53_ARLIO_PAGE
,
1123 B53_ARLTBL_DATA_ENTRY(i
), &fwd_entry
);
1124 b53_arl_to_entry(ent
, mac_vid
, fwd_entry
);
1126 if (!(fwd_entry
& ARLTBL_VALID
))
1128 if ((mac_vid
& ARLTBL_MAC_MASK
) != mac
)
1136 static int b53_arl_op(struct b53_device
*dev
, int op
, int port
,
1137 const unsigned char *addr
, u16 vid
, bool is_valid
)
1139 struct b53_arl_entry ent
;
1141 u64 mac
, mac_vid
= 0;
1145 /* Convert the array into a 64-bit MAC */
1146 mac
= ether_addr_to_u64(addr
);
1148 /* Perform a read for the given MAC and VID */
1149 b53_write48(dev
, B53_ARLIO_PAGE
, B53_MAC_ADDR_IDX
, mac
);
1150 b53_write16(dev
, B53_ARLIO_PAGE
, B53_VLAN_ID_IDX
, vid
);
1152 /* Issue a read operation for this MAC */
1153 ret
= b53_arl_rw_op(dev
, 1);
1157 ret
= b53_arl_read(dev
, mac
, vid
, &ent
, &idx
, is_valid
);
1158 /* If this is a read, just finish now */
1162 /* We could not find a matching MAC, so reset to a new entry */
1168 memset(&ent
, 0, sizeof(ent
));
1170 ent
.is_valid
= is_valid
;
1172 ent
.is_static
= true;
1173 memcpy(ent
.mac
, addr
, ETH_ALEN
);
1174 b53_arl_from_entry(&mac_vid
, &fwd_entry
, &ent
);
1176 b53_write64(dev
, B53_ARLIO_PAGE
,
1177 B53_ARLTBL_MAC_VID_ENTRY(idx
), mac_vid
);
1178 b53_write32(dev
, B53_ARLIO_PAGE
,
1179 B53_ARLTBL_DATA_ENTRY(idx
), fwd_entry
);
1181 return b53_arl_rw_op(dev
, 0);
1184 int b53_fdb_prepare(struct dsa_switch
*ds
, int port
,
1185 const struct switchdev_obj_port_fdb
*fdb
,
1186 struct switchdev_trans
*trans
)
1188 struct b53_device
*priv
= ds
->priv
;
1190 /* 5325 and 5365 require some more massaging, but could
1191 * be supported eventually
1193 if (is5325(priv
) || is5365(priv
))
1198 EXPORT_SYMBOL(b53_fdb_prepare
);
1200 void b53_fdb_add(struct dsa_switch
*ds
, int port
,
1201 const struct switchdev_obj_port_fdb
*fdb
,
1202 struct switchdev_trans
*trans
)
1204 struct b53_device
*priv
= ds
->priv
;
1206 if (b53_arl_op(priv
, 0, port
, fdb
->addr
, fdb
->vid
, true))
1207 pr_err("%s: failed to add MAC address\n", __func__
);
1209 EXPORT_SYMBOL(b53_fdb_add
);
1211 int b53_fdb_del(struct dsa_switch
*ds
, int port
,
1212 const struct switchdev_obj_port_fdb
*fdb
)
1214 struct b53_device
*priv
= ds
->priv
;
1216 return b53_arl_op(priv
, 0, port
, fdb
->addr
, fdb
->vid
, false);
1218 EXPORT_SYMBOL(b53_fdb_del
);
1220 static int b53_arl_search_wait(struct b53_device
*dev
)
1222 unsigned int timeout
= 1000;
1226 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARL_SRCH_CTL
, ®
);
1227 if (!(reg
& ARL_SRCH_STDN
))
1230 if (reg
& ARL_SRCH_VLID
)
1233 usleep_range(1000, 2000);
1234 } while (timeout
--);
1239 static void b53_arl_search_rd(struct b53_device
*dev
, u8 idx
,
1240 struct b53_arl_entry
*ent
)
1245 b53_read64(dev
, B53_ARLIO_PAGE
,
1246 B53_ARL_SRCH_RSTL_MACVID(idx
), &mac_vid
);
1247 b53_read32(dev
, B53_ARLIO_PAGE
,
1248 B53_ARL_SRCH_RSTL(idx
), &fwd_entry
);
1249 b53_arl_to_entry(ent
, mac_vid
, fwd_entry
);
1252 static int b53_fdb_copy(struct net_device
*dev
, int port
,
1253 const struct b53_arl_entry
*ent
,
1254 struct switchdev_obj_port_fdb
*fdb
,
1255 int (*cb
)(struct switchdev_obj
*obj
))
1260 if (port
!= ent
->port
)
1263 ether_addr_copy(fdb
->addr
, ent
->mac
);
1264 fdb
->vid
= ent
->vid
;
1265 fdb
->ndm_state
= ent
->is_static
? NUD_NOARP
: NUD_REACHABLE
;
1267 return cb(&fdb
->obj
);
1270 int b53_fdb_dump(struct dsa_switch
*ds
, int port
,
1271 struct switchdev_obj_port_fdb
*fdb
,
1272 int (*cb
)(struct switchdev_obj
*obj
))
1274 struct b53_device
*priv
= ds
->priv
;
1275 struct net_device
*dev
= ds
->ports
[port
].netdev
;
1276 struct b53_arl_entry results
[2];
1277 unsigned int count
= 0;
1281 /* Start search operation */
1282 reg
= ARL_SRCH_STDN
;
1283 b53_write8(priv
, B53_ARLIO_PAGE
, B53_ARL_SRCH_CTL
, reg
);
1286 ret
= b53_arl_search_wait(priv
);
1290 b53_arl_search_rd(priv
, 0, &results
[0]);
1291 ret
= b53_fdb_copy(dev
, port
, &results
[0], fdb
, cb
);
1295 if (priv
->num_arl_entries
> 2) {
1296 b53_arl_search_rd(priv
, 1, &results
[1]);
1297 ret
= b53_fdb_copy(dev
, port
, &results
[1], fdb
, cb
);
1301 if (!results
[0].is_valid
&& !results
[1].is_valid
)
1305 } while (count
++ < 1024);
1309 EXPORT_SYMBOL(b53_fdb_dump
);
1311 int b53_br_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1313 struct b53_device
*dev
= ds
->priv
;
1314 s8 cpu_port
= ds
->dst
->cpu_port
;
1318 /* Make this port leave the all VLANs join since we will have proper
1319 * VLAN entries from now on
1322 b53_read16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, ®
);
1324 if ((reg
& BIT(cpu_port
)) == BIT(cpu_port
))
1325 reg
&= ~BIT(cpu_port
);
1326 b53_write16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, reg
);
1329 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
1331 b53_for_each_port(dev
, i
) {
1332 if (ds
->ports
[i
].bridge_dev
!= br
)
1335 /* Add this local port to the remote port VLAN control
1336 * membership and update the remote port bitmask
1338 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), ®
);
1340 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), reg
);
1341 dev
->ports
[i
].vlan_ctl_mask
= reg
;
1346 /* Configure the local port VLAN control membership to include
1347 * remote ports and update the local port bitmask
1349 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
1350 dev
->ports
[port
].vlan_ctl_mask
= pvlan
;
1354 EXPORT_SYMBOL(b53_br_join
);
1356 void b53_br_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1358 struct b53_device
*dev
= ds
->priv
;
1359 struct b53_vlan
*vl
= &dev
->vlans
[0];
1360 s8 cpu_port
= ds
->dst
->cpu_port
;
1362 u16 pvlan
, reg
, pvid
;
1364 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
1366 b53_for_each_port(dev
, i
) {
1367 /* Don't touch the remaining ports */
1368 if (ds
->ports
[i
].bridge_dev
!= br
)
1371 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), ®
);
1373 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), reg
);
1374 dev
->ports
[port
].vlan_ctl_mask
= reg
;
1376 /* Prevent self removal to preserve isolation */
1381 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
1382 dev
->ports
[port
].vlan_ctl_mask
= pvlan
;
1384 if (is5325(dev
) || is5365(dev
))
1389 /* Make this port join all VLANs without VLAN entries */
1391 b53_read16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, ®
);
1393 if (!(reg
& BIT(cpu_port
)))
1394 reg
|= BIT(cpu_port
);
1395 b53_write16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, reg
);
1397 b53_get_vlan_entry(dev
, pvid
, vl
);
1398 vl
->members
|= BIT(port
) | BIT(dev
->cpu_port
);
1399 vl
->untag
|= BIT(port
) | BIT(dev
->cpu_port
);
1400 b53_set_vlan_entry(dev
, pvid
, vl
);
1403 EXPORT_SYMBOL(b53_br_leave
);
1405 void b53_br_set_stp_state(struct dsa_switch
*ds
, int port
, u8 state
)
1407 struct b53_device
*dev
= ds
->priv
;
1412 case BR_STATE_DISABLED
:
1413 hw_state
= PORT_CTRL_DIS_STATE
;
1415 case BR_STATE_LISTENING
:
1416 hw_state
= PORT_CTRL_LISTEN_STATE
;
1418 case BR_STATE_LEARNING
:
1419 hw_state
= PORT_CTRL_LEARN_STATE
;
1421 case BR_STATE_FORWARDING
:
1422 hw_state
= PORT_CTRL_FWD_STATE
;
1424 case BR_STATE_BLOCKING
:
1425 hw_state
= PORT_CTRL_BLOCK_STATE
;
1428 dev_err(ds
->dev
, "invalid STP state: %d\n", state
);
1432 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), ®
);
1433 reg
&= ~PORT_CTRL_STP_STATE_MASK
;
1435 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), reg
);
1437 EXPORT_SYMBOL(b53_br_set_stp_state
);
1439 void b53_br_fast_age(struct dsa_switch
*ds
, int port
)
1441 struct b53_device
*dev
= ds
->priv
;
1443 if (b53_fast_age_port(dev
, port
))
1444 dev_err(ds
->dev
, "fast ageing failed\n");
1446 EXPORT_SYMBOL(b53_br_fast_age
);
1448 static enum dsa_tag_protocol
b53_get_tag_protocol(struct dsa_switch
*ds
)
1450 return DSA_TAG_PROTO_NONE
;
1453 int b53_mirror_add(struct dsa_switch
*ds
, int port
,
1454 struct dsa_mall_mirror_tc_entry
*mirror
, bool ingress
)
1456 struct b53_device
*dev
= ds
->priv
;
1460 loc
= B53_IG_MIR_CTL
;
1462 loc
= B53_EG_MIR_CTL
;
1464 b53_read16(dev
, B53_MGMT_PAGE
, loc
, ®
);
1465 reg
&= ~MIRROR_MASK
;
1467 b53_write16(dev
, B53_MGMT_PAGE
, loc
, reg
);
1469 b53_read16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, ®
);
1470 reg
&= ~CAP_PORT_MASK
;
1471 reg
|= mirror
->to_local_port
;
1473 b53_write16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, reg
);
1477 EXPORT_SYMBOL(b53_mirror_add
);
1479 void b53_mirror_del(struct dsa_switch
*ds
, int port
,
1480 struct dsa_mall_mirror_tc_entry
*mirror
)
1482 struct b53_device
*dev
= ds
->priv
;
1483 bool loc_disable
= false, other_loc_disable
= false;
1486 if (mirror
->ingress
)
1487 loc
= B53_IG_MIR_CTL
;
1489 loc
= B53_EG_MIR_CTL
;
1491 /* Update the desired ingress/egress register */
1492 b53_read16(dev
, B53_MGMT_PAGE
, loc
, ®
);
1494 if (!(reg
& MIRROR_MASK
))
1496 b53_write16(dev
, B53_MGMT_PAGE
, loc
, reg
);
1498 /* Now look at the other one to know if we can disable mirroring
1501 if (mirror
->ingress
)
1502 b53_read16(dev
, B53_MGMT_PAGE
, B53_EG_MIR_CTL
, ®
);
1504 b53_read16(dev
, B53_MGMT_PAGE
, B53_IG_MIR_CTL
, ®
);
1505 if (!(reg
& MIRROR_MASK
))
1506 other_loc_disable
= true;
1508 b53_read16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, ®
);
1509 /* Both no longer have ports, let's disable mirroring */
1510 if (loc_disable
&& other_loc_disable
) {
1512 reg
&= ~mirror
->to_local_port
;
1514 b53_write16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, reg
);
1516 EXPORT_SYMBOL(b53_mirror_del
);
1518 static const struct dsa_switch_ops b53_switch_ops
= {
1519 .get_tag_protocol
= b53_get_tag_protocol
,
1521 .get_strings
= b53_get_strings
,
1522 .get_ethtool_stats
= b53_get_ethtool_stats
,
1523 .get_sset_count
= b53_get_sset_count
,
1524 .phy_read
= b53_phy_read16
,
1525 .phy_write
= b53_phy_write16
,
1526 .adjust_link
= b53_adjust_link
,
1527 .port_enable
= b53_enable_port
,
1528 .port_disable
= b53_disable_port
,
1529 .port_bridge_join
= b53_br_join
,
1530 .port_bridge_leave
= b53_br_leave
,
1531 .port_stp_state_set
= b53_br_set_stp_state
,
1532 .port_fast_age
= b53_br_fast_age
,
1533 .port_vlan_filtering
= b53_vlan_filtering
,
1534 .port_vlan_prepare
= b53_vlan_prepare
,
1535 .port_vlan_add
= b53_vlan_add
,
1536 .port_vlan_del
= b53_vlan_del
,
1537 .port_vlan_dump
= b53_vlan_dump
,
1538 .port_fdb_prepare
= b53_fdb_prepare
,
1539 .port_fdb_dump
= b53_fdb_dump
,
1540 .port_fdb_add
= b53_fdb_add
,
1541 .port_fdb_del
= b53_fdb_del
,
1542 .port_mirror_add
= b53_mirror_add
,
1543 .port_mirror_del
= b53_mirror_del
,
1546 struct b53_chip_data
{
1548 const char *dev_name
;
1559 #define B53_VTA_REGS \
1560 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1561 #define B53_VTA_REGS_9798 \
1562 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1563 #define B53_VTA_REGS_63XX \
1564 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1566 static const struct b53_chip_data b53_switch_chips
[] = {
1568 .chip_id
= BCM5325_DEVICE_ID
,
1569 .dev_name
= "BCM5325",
1571 .enabled_ports
= 0x1f,
1573 .cpu_port
= B53_CPU_PORT_25
,
1574 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1577 .chip_id
= BCM5365_DEVICE_ID
,
1578 .dev_name
= "BCM5365",
1580 .enabled_ports
= 0x1f,
1582 .cpu_port
= B53_CPU_PORT_25
,
1583 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1586 .chip_id
= BCM5395_DEVICE_ID
,
1587 .dev_name
= "BCM5395",
1589 .enabled_ports
= 0x1f,
1591 .cpu_port
= B53_CPU_PORT
,
1592 .vta_regs
= B53_VTA_REGS
,
1593 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1594 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1595 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1598 .chip_id
= BCM5397_DEVICE_ID
,
1599 .dev_name
= "BCM5397",
1601 .enabled_ports
= 0x1f,
1603 .cpu_port
= B53_CPU_PORT
,
1604 .vta_regs
= B53_VTA_REGS_9798
,
1605 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1606 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1607 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1610 .chip_id
= BCM5398_DEVICE_ID
,
1611 .dev_name
= "BCM5398",
1613 .enabled_ports
= 0x7f,
1615 .cpu_port
= B53_CPU_PORT
,
1616 .vta_regs
= B53_VTA_REGS_9798
,
1617 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1618 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1619 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1622 .chip_id
= BCM53115_DEVICE_ID
,
1623 .dev_name
= "BCM53115",
1625 .enabled_ports
= 0x1f,
1627 .vta_regs
= B53_VTA_REGS
,
1628 .cpu_port
= B53_CPU_PORT
,
1629 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1630 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1631 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1634 .chip_id
= BCM53125_DEVICE_ID
,
1635 .dev_name
= "BCM53125",
1637 .enabled_ports
= 0xff,
1638 .cpu_port
= B53_CPU_PORT
,
1639 .vta_regs
= B53_VTA_REGS
,
1640 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1641 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1642 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1645 .chip_id
= BCM53128_DEVICE_ID
,
1646 .dev_name
= "BCM53128",
1648 .enabled_ports
= 0x1ff,
1650 .cpu_port
= B53_CPU_PORT
,
1651 .vta_regs
= B53_VTA_REGS
,
1652 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1653 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1654 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1657 .chip_id
= BCM63XX_DEVICE_ID
,
1658 .dev_name
= "BCM63xx",
1660 .enabled_ports
= 0, /* pdata must provide them */
1662 .cpu_port
= B53_CPU_PORT
,
1663 .vta_regs
= B53_VTA_REGS_63XX
,
1664 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1665 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1666 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1669 .chip_id
= BCM53010_DEVICE_ID
,
1670 .dev_name
= "BCM53010",
1672 .enabled_ports
= 0x1f,
1674 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1675 .vta_regs
= B53_VTA_REGS
,
1676 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1677 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1678 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1681 .chip_id
= BCM53011_DEVICE_ID
,
1682 .dev_name
= "BCM53011",
1684 .enabled_ports
= 0x1bf,
1686 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1687 .vta_regs
= B53_VTA_REGS
,
1688 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1689 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1690 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1693 .chip_id
= BCM53012_DEVICE_ID
,
1694 .dev_name
= "BCM53012",
1696 .enabled_ports
= 0x1bf,
1698 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1699 .vta_regs
= B53_VTA_REGS
,
1700 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1701 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1702 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1705 .chip_id
= BCM53018_DEVICE_ID
,
1706 .dev_name
= "BCM53018",
1708 .enabled_ports
= 0x1f,
1710 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1711 .vta_regs
= B53_VTA_REGS
,
1712 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1713 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1714 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1717 .chip_id
= BCM53019_DEVICE_ID
,
1718 .dev_name
= "BCM53019",
1720 .enabled_ports
= 0x1f,
1722 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1723 .vta_regs
= B53_VTA_REGS
,
1724 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1725 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1726 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1729 .chip_id
= BCM58XX_DEVICE_ID
,
1730 .dev_name
= "BCM585xx/586xx/88312",
1732 .enabled_ports
= 0x1ff,
1734 .cpu_port
= B53_CPU_PORT_25
,
1735 .vta_regs
= B53_VTA_REGS
,
1736 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1737 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1738 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1741 .chip_id
= BCM7445_DEVICE_ID
,
1742 .dev_name
= "BCM7445",
1744 .enabled_ports
= 0x1ff,
1746 .cpu_port
= B53_CPU_PORT
,
1747 .vta_regs
= B53_VTA_REGS
,
1748 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1749 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1750 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1753 .chip_id
= BCM7278_DEVICE_ID
,
1754 .dev_name
= "BCM7278",
1756 .enabled_ports
= 0x1ff,
1758 .cpu_port
= B53_CPU_PORT
,
1759 .vta_regs
= B53_VTA_REGS
,
1760 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1761 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1762 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1766 static int b53_switch_init(struct b53_device
*dev
)
1771 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1772 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1774 if (chip
->chip_id
== dev
->chip_id
) {
1775 if (!dev
->enabled_ports
)
1776 dev
->enabled_ports
= chip
->enabled_ports
;
1777 dev
->name
= chip
->dev_name
;
1778 dev
->duplex_reg
= chip
->duplex_reg
;
1779 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1780 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1781 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1782 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1783 dev
->cpu_port
= chip
->cpu_port
;
1784 dev
->num_vlans
= chip
->vlans
;
1785 dev
->num_arl_entries
= chip
->arl_entries
;
1790 /* check which BCM5325x version we have */
1794 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1796 /* check reserved bits */
1802 /* BCM5325F - do not use port 4 */
1803 dev
->enabled_ports
&= ~BIT(4);
1806 /* On the BCM47XX SoCs this is the supported internal switch.*/
1807 #ifndef CONFIG_BCM47XX
1814 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1817 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1818 /* use second IMP port if GMII is enabled */
1819 if (strap_value
& SV_GMII_CTRL_115
)
1823 /* cpu port is always last */
1824 dev
->num_ports
= dev
->cpu_port
+ 1;
1825 dev
->enabled_ports
|= BIT(dev
->cpu_port
);
1827 dev
->ports
= devm_kzalloc(dev
->dev
,
1828 sizeof(struct b53_port
) * dev
->num_ports
,
1833 dev
->vlans
= devm_kzalloc(dev
->dev
,
1834 sizeof(struct b53_vlan
) * dev
->num_vlans
,
1839 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1840 if (dev
->reset_gpio
>= 0) {
1841 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
,
1842 GPIOF_OUT_INIT_HIGH
, "robo_reset");
1850 struct b53_device
*b53_switch_alloc(struct device
*base
,
1851 const struct b53_io_ops
*ops
,
1854 struct dsa_switch
*ds
;
1855 struct b53_device
*dev
;
1857 ds
= dsa_switch_alloc(base
, DSA_MAX_PORTS
);
1861 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
1871 ds
->ops
= &b53_switch_ops
;
1872 mutex_init(&dev
->reg_mutex
);
1873 mutex_init(&dev
->stats_mutex
);
1877 EXPORT_SYMBOL(b53_switch_alloc
);
1879 int b53_switch_detect(struct b53_device
*dev
)
1886 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
1892 /* BCM5325 and BCM5365 do not have this register so reads
1893 * return 0. But the read operation did succeed, so assume this
1896 * Next check if we can write to the 5325's VTA register; for
1897 * 5365 it is read only.
1899 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
1900 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
1903 dev
->chip_id
= BCM5325_DEVICE_ID
;
1905 dev
->chip_id
= BCM5365_DEVICE_ID
;
1907 case BCM5395_DEVICE_ID
:
1908 case BCM5397_DEVICE_ID
:
1909 case BCM5398_DEVICE_ID
:
1913 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
1918 case BCM53115_DEVICE_ID
:
1919 case BCM53125_DEVICE_ID
:
1920 case BCM53128_DEVICE_ID
:
1921 case BCM53010_DEVICE_ID
:
1922 case BCM53011_DEVICE_ID
:
1923 case BCM53012_DEVICE_ID
:
1924 case BCM53018_DEVICE_ID
:
1925 case BCM53019_DEVICE_ID
:
1926 dev
->chip_id
= id32
;
1929 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1935 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
1936 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
1939 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
1942 EXPORT_SYMBOL(b53_switch_detect
);
1944 int b53_switch_register(struct b53_device
*dev
)
1949 dev
->chip_id
= dev
->pdata
->chip_id
;
1950 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
1953 if (!dev
->chip_id
&& b53_switch_detect(dev
))
1956 ret
= b53_switch_init(dev
);
1960 pr_info("found switch: %s, rev %i\n", dev
->name
, dev
->core_rev
);
1962 return dsa_register_switch(dev
->ds
, dev
->ds
->dev
);
1964 EXPORT_SYMBOL(b53_switch_register
);
1966 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1967 MODULE_DESCRIPTION("B53 switch library");
1968 MODULE_LICENSE("Dual BSD/GPL");