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net: dsa: b53: Add BCM5389 support
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
31 #include <net/dsa.h>
32
33 #include "b53_regs.h"
34 #include "b53_priv.h"
35
36 struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40 };
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 };
77
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124 };
125
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 };
166
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224 };
225
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229 {
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245 }
246
247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
249 {
250 if (is5325(dev)) {
251 u32 entry = 0;
252
253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285 }
286
287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289 {
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
324 }
325
326 static void b53_set_forwarding(struct b53_device *dev, int enable)
327 {
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
338
339 /* Include IMP port in dumb forwarding mode
340 */
341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
344 }
345
346 static void b53_enable_vlan(struct b53_device *dev, bool enable)
347 {
348 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
349
350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
353
354 if (is5325(dev) || is5365(dev)) {
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
357 } else if (is63xx(dev)) {
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
360 } else {
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
363 }
364
365 mgmt &= ~SM_SW_FWD_MODE;
366
367 if (enable) {
368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
370 vc4 &= ~VC4_ING_VID_CHECK_MASK;
371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
372 vc5 |= VC5_DROP_VTABLE_MISS;
373
374 if (is5325(dev))
375 vc0 &= ~VC0_RESERVED_1;
376
377 if (is5325(dev) || is5365(dev))
378 vc1 |= VC1_RX_MCST_TAG_EN;
379
380 } else {
381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
383 vc4 &= ~VC4_ING_VID_CHECK_MASK;
384 vc5 &= ~VC5_DROP_VTABLE_MISS;
385
386 if (is5325(dev) || is5365(dev))
387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
388 else
389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 &= ~VC1_RX_MCST_TAG_EN;
393 }
394
395 if (!is5325(dev) && !is5365(dev))
396 vc5 &= ~VC5_VID_FFF_EN;
397
398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
400
401 if (is5325(dev) || is5365(dev)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev) && enable)
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
405 VC3_HIGH_8BIT_EN);
406 else
407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
408
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
411 } else if (is63xx(dev)) {
412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
415 } else {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
419 }
420
421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
422 }
423
424 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
425 {
426 u32 port_mask = 0;
427 u16 max_size = JMS_MIN_SIZE;
428
429 if (is5325(dev) || is5365(dev))
430 return -EINVAL;
431
432 if (enable) {
433 port_mask = dev->enabled_ports;
434 max_size = JMS_MAX_SIZE;
435 if (allow_10_100)
436 port_mask |= JPM_10_100_JUMBO_EN;
437 }
438
439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
441 }
442
443 static int b53_flush_arl(struct b53_device *dev, u8 mask)
444 {
445 unsigned int i;
446
447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
449
450 for (i = 0; i < 10; i++) {
451 u8 fast_age_ctrl;
452
453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
454 &fast_age_ctrl);
455
456 if (!(fast_age_ctrl & FAST_AGE_DONE))
457 goto out;
458
459 msleep(1);
460 }
461
462 return -ETIMEDOUT;
463 out:
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
466 return 0;
467 }
468
469 static int b53_fast_age_port(struct b53_device *dev, int port)
470 {
471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
472
473 return b53_flush_arl(dev, FAST_AGE_PORT);
474 }
475
476 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
477 {
478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
479
480 return b53_flush_arl(dev, FAST_AGE_VLAN);
481 }
482
483 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
484 {
485 struct b53_device *dev = ds->priv;
486 unsigned int i;
487 u16 pvlan;
488
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
491 * the same VLAN.
492 */
493 b53_for_each_port(dev, i) {
494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
495 pvlan |= BIT(cpu_port);
496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
497 }
498 }
499 EXPORT_SYMBOL(b53_imp_vlan_setup);
500
501 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
502 {
503 struct b53_device *dev = ds->priv;
504 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
505 u16 pvlan;
506
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
509
510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
513 */
514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
515 pvlan &= ~0x1ff;
516 pvlan |= BIT(port);
517 pvlan |= dev->ports[port].vlan_ctl_mask;
518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
519
520 b53_imp_vlan_setup(ds, cpu_port);
521
522 /* If EEE was enabled, restore it */
523 if (dev->ports[port].eee.eee_enabled)
524 b53_eee_enable_set(ds, port, true);
525
526 return 0;
527 }
528 EXPORT_SYMBOL(b53_enable_port);
529
530 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
531 {
532 struct b53_device *dev = ds->priv;
533 u8 reg;
534
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
539 }
540 EXPORT_SYMBOL(b53_disable_port);
541
542 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
543 {
544 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
545 DSA_TAG_PROTO_NONE);
546 struct b53_device *dev = ds->priv;
547 u8 hdr_ctl, val;
548 u16 reg;
549
550 /* Resolve which bit controls the Broadcom tag */
551 switch (port) {
552 case 8:
553 val = BRCM_HDR_P8_EN;
554 break;
555 case 7:
556 val = BRCM_HDR_P7_EN;
557 break;
558 case 5:
559 val = BRCM_HDR_P5_EN;
560 break;
561 default:
562 val = 0;
563 break;
564 }
565
566 /* Enable Broadcom tags for IMP port */
567 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
568 if (tag_en)
569 hdr_ctl |= val;
570 else
571 hdr_ctl &= ~val;
572 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
573
574 /* Registers below are only accessible on newer devices */
575 if (!is58xx(dev))
576 return;
577
578 /* Enable reception Broadcom tag for CPU TX (switch RX) to
579 * allow us to tag outgoing frames
580 */
581 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
582 if (tag_en)
583 reg &= ~BIT(port);
584 else
585 reg |= BIT(port);
586 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
587
588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
589 * allow delivering frames to the per-port net_devices
590 */
591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
592 if (tag_en)
593 reg &= ~BIT(port);
594 else
595 reg |= BIT(port);
596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
597 }
598 EXPORT_SYMBOL(b53_brcm_hdr_setup);
599
600 static void b53_enable_cpu_port(struct b53_device *dev, int port)
601 {
602 u8 port_ctrl;
603
604 /* BCM5325 CPU port is at 8 */
605 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
606 port = B53_CPU_PORT;
607
608 port_ctrl = PORT_CTRL_RX_BCST_EN |
609 PORT_CTRL_RX_MCST_EN |
610 PORT_CTRL_RX_UCST_EN;
611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
612
613 b53_brcm_hdr_setup(dev->ds, port);
614 }
615
616 static void b53_enable_mib(struct b53_device *dev)
617 {
618 u8 gc;
619
620 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
621 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
622 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
623 }
624
625 int b53_configure_vlan(struct dsa_switch *ds)
626 {
627 struct b53_device *dev = ds->priv;
628 struct b53_vlan vl = { 0 };
629 int i;
630
631 /* clear all vlan entries */
632 if (is5325(dev) || is5365(dev)) {
633 for (i = 1; i < dev->num_vlans; i++)
634 b53_set_vlan_entry(dev, i, &vl);
635 } else {
636 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
637 }
638
639 b53_enable_vlan(dev, false);
640
641 b53_for_each_port(dev, i)
642 b53_write16(dev, B53_VLAN_PAGE,
643 B53_VLAN_PORT_DEF_TAG(i), 1);
644
645 if (!is5325(dev) && !is5365(dev))
646 b53_set_jumbo(dev, dev->enable_jumbo, false);
647
648 return 0;
649 }
650 EXPORT_SYMBOL(b53_configure_vlan);
651
652 static void b53_switch_reset_gpio(struct b53_device *dev)
653 {
654 int gpio = dev->reset_gpio;
655
656 if (gpio < 0)
657 return;
658
659 /* Reset sequence: RESET low(50ms)->high(20ms)
660 */
661 gpio_set_value(gpio, 0);
662 mdelay(50);
663
664 gpio_set_value(gpio, 1);
665 mdelay(20);
666
667 dev->current_page = 0xff;
668 }
669
670 static int b53_switch_reset(struct b53_device *dev)
671 {
672 unsigned int timeout = 1000;
673 u8 mgmt, reg;
674
675 b53_switch_reset_gpio(dev);
676
677 if (is539x(dev)) {
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
680 }
681
682 /* This is specific to 58xx devices here, do not use is58xx() which
683 * covers the larger Starfigther 2 family, including 7445/7278 which
684 * still use this driver as a library and need to perform the reset
685 * earlier.
686 */
687 if (dev->chip_id == BCM58XX_DEVICE_ID ||
688 dev->chip_id == BCM583XX_DEVICE_ID) {
689 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
690 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
691 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
692
693 do {
694 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
695 if (!(reg & SW_RST))
696 break;
697
698 usleep_range(1000, 2000);
699 } while (timeout-- > 0);
700
701 if (timeout == 0)
702 return -ETIMEDOUT;
703 }
704
705 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
706
707 if (!(mgmt & SM_SW_FWD_EN)) {
708 mgmt &= ~SM_SW_FWD_MODE;
709 mgmt |= SM_SW_FWD_EN;
710
711 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
712 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
713
714 if (!(mgmt & SM_SW_FWD_EN)) {
715 dev_err(dev->dev, "Failed to enable switch!\n");
716 return -EINVAL;
717 }
718 }
719
720 b53_enable_mib(dev);
721
722 return b53_flush_arl(dev, FAST_AGE_STATIC);
723 }
724
725 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
726 {
727 struct b53_device *priv = ds->priv;
728 u16 value = 0;
729 int ret;
730
731 if (priv->ops->phy_read16)
732 ret = priv->ops->phy_read16(priv, addr, reg, &value);
733 else
734 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
735 reg * 2, &value);
736
737 return ret ? ret : value;
738 }
739
740 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
741 {
742 struct b53_device *priv = ds->priv;
743
744 if (priv->ops->phy_write16)
745 return priv->ops->phy_write16(priv, addr, reg, val);
746
747 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
748 }
749
750 static int b53_reset_switch(struct b53_device *priv)
751 {
752 /* reset vlans */
753 priv->enable_jumbo = false;
754
755 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
756 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
757
758 return b53_switch_reset(priv);
759 }
760
761 static int b53_apply_config(struct b53_device *priv)
762 {
763 /* disable switching */
764 b53_set_forwarding(priv, 0);
765
766 b53_configure_vlan(priv->ds);
767
768 /* enable switching */
769 b53_set_forwarding(priv, 1);
770
771 return 0;
772 }
773
774 static void b53_reset_mib(struct b53_device *priv)
775 {
776 u8 gc;
777
778 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
779
780 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
781 msleep(1);
782 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
783 msleep(1);
784 }
785
786 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
787 {
788 if (is5365(dev))
789 return b53_mibs_65;
790 else if (is63xx(dev))
791 return b53_mibs_63xx;
792 else if (is58xx(dev))
793 return b53_mibs_58xx;
794 else
795 return b53_mibs;
796 }
797
798 static unsigned int b53_get_mib_size(struct b53_device *dev)
799 {
800 if (is5365(dev))
801 return B53_MIBS_65_SIZE;
802 else if (is63xx(dev))
803 return B53_MIBS_63XX_SIZE;
804 else if (is58xx(dev))
805 return B53_MIBS_58XX_SIZE;
806 else
807 return B53_MIBS_SIZE;
808 }
809
810 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
811 {
812 struct b53_device *dev = ds->priv;
813 const struct b53_mib_desc *mibs = b53_get_mib(dev);
814 unsigned int mib_size = b53_get_mib_size(dev);
815 unsigned int i;
816
817 for (i = 0; i < mib_size; i++)
818 memcpy(data + i * ETH_GSTRING_LEN,
819 mibs[i].name, ETH_GSTRING_LEN);
820 }
821 EXPORT_SYMBOL(b53_get_strings);
822
823 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
824 {
825 struct b53_device *dev = ds->priv;
826 const struct b53_mib_desc *mibs = b53_get_mib(dev);
827 unsigned int mib_size = b53_get_mib_size(dev);
828 const struct b53_mib_desc *s;
829 unsigned int i;
830 u64 val = 0;
831
832 if (is5365(dev) && port == 5)
833 port = 8;
834
835 mutex_lock(&dev->stats_mutex);
836
837 for (i = 0; i < mib_size; i++) {
838 s = &mibs[i];
839
840 if (s->size == 8) {
841 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
842 } else {
843 u32 val32;
844
845 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
846 &val32);
847 val = val32;
848 }
849 data[i] = (u64)val;
850 }
851
852 mutex_unlock(&dev->stats_mutex);
853 }
854 EXPORT_SYMBOL(b53_get_ethtool_stats);
855
856 int b53_get_sset_count(struct dsa_switch *ds)
857 {
858 struct b53_device *dev = ds->priv;
859
860 return b53_get_mib_size(dev);
861 }
862 EXPORT_SYMBOL(b53_get_sset_count);
863
864 static int b53_setup(struct dsa_switch *ds)
865 {
866 struct b53_device *dev = ds->priv;
867 unsigned int port;
868 int ret;
869
870 ret = b53_reset_switch(dev);
871 if (ret) {
872 dev_err(ds->dev, "failed to reset switch\n");
873 return ret;
874 }
875
876 b53_reset_mib(dev);
877
878 ret = b53_apply_config(dev);
879 if (ret)
880 dev_err(ds->dev, "failed to apply configuration\n");
881
882 /* Configure IMP/CPU port, disable unused ports. Enabled
883 * ports will be configured with .port_enable
884 */
885 for (port = 0; port < dev->num_ports; port++) {
886 if (dsa_is_cpu_port(ds, port))
887 b53_enable_cpu_port(dev, port);
888 else if (dsa_is_unused_port(ds, port))
889 b53_disable_port(ds, port, NULL);
890 }
891
892 return ret;
893 }
894
895 static void b53_adjust_link(struct dsa_switch *ds, int port,
896 struct phy_device *phydev)
897 {
898 struct b53_device *dev = ds->priv;
899 struct ethtool_eee *p = &dev->ports[port].eee;
900 u8 rgmii_ctrl = 0, reg = 0, off;
901
902 if (!phy_is_pseudo_fixed_link(phydev))
903 return;
904
905 /* Override the port settings */
906 if (port == dev->cpu_port) {
907 off = B53_PORT_OVERRIDE_CTRL;
908 reg = PORT_OVERRIDE_EN;
909 } else {
910 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
911 reg = GMII_PO_EN;
912 }
913
914 /* Set the link UP */
915 if (phydev->link)
916 reg |= PORT_OVERRIDE_LINK;
917
918 if (phydev->duplex == DUPLEX_FULL)
919 reg |= PORT_OVERRIDE_FULL_DUPLEX;
920
921 switch (phydev->speed) {
922 case 2000:
923 reg |= PORT_OVERRIDE_SPEED_2000M;
924 /* fallthrough */
925 case SPEED_1000:
926 reg |= PORT_OVERRIDE_SPEED_1000M;
927 break;
928 case SPEED_100:
929 reg |= PORT_OVERRIDE_SPEED_100M;
930 break;
931 case SPEED_10:
932 reg |= PORT_OVERRIDE_SPEED_10M;
933 break;
934 default:
935 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
936 return;
937 }
938
939 /* Enable flow control on BCM5301x's CPU port */
940 if (is5301x(dev) && port == dev->cpu_port)
941 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
942
943 if (phydev->pause) {
944 if (phydev->asym_pause)
945 reg |= PORT_OVERRIDE_TX_FLOW;
946 reg |= PORT_OVERRIDE_RX_FLOW;
947 }
948
949 b53_write8(dev, B53_CTRL_PAGE, off, reg);
950
951 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
952 if (port == 8)
953 off = B53_RGMII_CTRL_IMP;
954 else
955 off = B53_RGMII_CTRL_P(port);
956
957 /* Configure the port RGMII clock delay by DLL disabled and
958 * tx_clk aligned timing (restoring to reset defaults)
959 */
960 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
961 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
962 RGMII_CTRL_TIMING_SEL);
963
964 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
965 * sure that we enable the port TX clock internal delay to
966 * account for this internal delay that is inserted, otherwise
967 * the switch won't be able to receive correctly.
968 *
969 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
970 * any delay neither on transmission nor reception, so the
971 * BCM53125 must also be configured accordingly to account for
972 * the lack of delay and introduce
973 *
974 * The BCM53125 switch has its RX clock and TX clock control
975 * swapped, hence the reason why we modify the TX clock path in
976 * the "RGMII" case
977 */
978 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
979 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
980 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
981 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
982 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
983 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
984
985 dev_info(ds->dev, "Configured port %d for %s\n", port,
986 phy_modes(phydev->interface));
987 }
988
989 /* configure MII port if necessary */
990 if (is5325(dev)) {
991 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
992 &reg);
993
994 /* reverse mii needs to be enabled */
995 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
996 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
997 reg | PORT_OVERRIDE_RV_MII_25);
998 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
999 &reg);
1000
1001 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1002 dev_err(ds->dev,
1003 "Failed to enable reverse MII mode\n");
1004 return;
1005 }
1006 }
1007 } else if (is5301x(dev)) {
1008 if (port != dev->cpu_port) {
1009 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1010 u8 gmii_po;
1011
1012 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1013 gmii_po |= GMII_PO_LINK |
1014 GMII_PO_RX_FLOW |
1015 GMII_PO_TX_FLOW |
1016 GMII_PO_EN |
1017 GMII_PO_SPEED_2000M;
1018 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1019 }
1020 }
1021
1022 /* Re-negotiate EEE if it was enabled already */
1023 p->eee_enabled = b53_eee_init(ds, port, phydev);
1024 }
1025
1026 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1027 {
1028 return 0;
1029 }
1030 EXPORT_SYMBOL(b53_vlan_filtering);
1031
1032 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1033 const struct switchdev_obj_port_vlan *vlan,
1034 struct switchdev_trans *trans)
1035 {
1036 struct b53_device *dev = ds->priv;
1037
1038 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1039 return -EOPNOTSUPP;
1040
1041 if (vlan->vid_end > dev->num_vlans)
1042 return -ERANGE;
1043
1044 b53_enable_vlan(dev, true);
1045
1046 return 0;
1047 }
1048 EXPORT_SYMBOL(b53_vlan_prepare);
1049
1050 void b53_vlan_add(struct dsa_switch *ds, int port,
1051 const struct switchdev_obj_port_vlan *vlan,
1052 struct switchdev_trans *trans)
1053 {
1054 struct b53_device *dev = ds->priv;
1055 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1056 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1057 struct b53_vlan *vl;
1058 u16 vid;
1059
1060 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1061 vl = &dev->vlans[vid];
1062
1063 b53_get_vlan_entry(dev, vid, vl);
1064
1065 vl->members |= BIT(port);
1066 if (untagged)
1067 vl->untag |= BIT(port);
1068 else
1069 vl->untag &= ~BIT(port);
1070
1071 b53_set_vlan_entry(dev, vid, vl);
1072 b53_fast_age_vlan(dev, vid);
1073 }
1074
1075 if (pvid) {
1076 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1077 vlan->vid_end);
1078 b53_fast_age_vlan(dev, vid);
1079 }
1080 }
1081 EXPORT_SYMBOL(b53_vlan_add);
1082
1083 int b53_vlan_del(struct dsa_switch *ds, int port,
1084 const struct switchdev_obj_port_vlan *vlan)
1085 {
1086 struct b53_device *dev = ds->priv;
1087 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1088 struct b53_vlan *vl;
1089 u16 vid;
1090 u16 pvid;
1091
1092 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1093
1094 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1095 vl = &dev->vlans[vid];
1096
1097 b53_get_vlan_entry(dev, vid, vl);
1098
1099 vl->members &= ~BIT(port);
1100
1101 if (pvid == vid) {
1102 if (is5325(dev) || is5365(dev))
1103 pvid = 1;
1104 else
1105 pvid = 0;
1106 }
1107
1108 if (untagged)
1109 vl->untag &= ~(BIT(port));
1110
1111 b53_set_vlan_entry(dev, vid, vl);
1112 b53_fast_age_vlan(dev, vid);
1113 }
1114
1115 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1116 b53_fast_age_vlan(dev, pvid);
1117
1118 return 0;
1119 }
1120 EXPORT_SYMBOL(b53_vlan_del);
1121
1122 /* Address Resolution Logic routines */
1123 static int b53_arl_op_wait(struct b53_device *dev)
1124 {
1125 unsigned int timeout = 10;
1126 u8 reg;
1127
1128 do {
1129 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1130 if (!(reg & ARLTBL_START_DONE))
1131 return 0;
1132
1133 usleep_range(1000, 2000);
1134 } while (timeout--);
1135
1136 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1137
1138 return -ETIMEDOUT;
1139 }
1140
1141 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1142 {
1143 u8 reg;
1144
1145 if (op > ARLTBL_RW)
1146 return -EINVAL;
1147
1148 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1149 reg |= ARLTBL_START_DONE;
1150 if (op)
1151 reg |= ARLTBL_RW;
1152 else
1153 reg &= ~ARLTBL_RW;
1154 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1155
1156 return b53_arl_op_wait(dev);
1157 }
1158
1159 static int b53_arl_read(struct b53_device *dev, u64 mac,
1160 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1161 bool is_valid)
1162 {
1163 unsigned int i;
1164 int ret;
1165
1166 ret = b53_arl_op_wait(dev);
1167 if (ret)
1168 return ret;
1169
1170 /* Read the bins */
1171 for (i = 0; i < dev->num_arl_entries; i++) {
1172 u64 mac_vid;
1173 u32 fwd_entry;
1174
1175 b53_read64(dev, B53_ARLIO_PAGE,
1176 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1177 b53_read32(dev, B53_ARLIO_PAGE,
1178 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1179 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1180
1181 if (!(fwd_entry & ARLTBL_VALID))
1182 continue;
1183 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1184 continue;
1185 *idx = i;
1186 }
1187
1188 return -ENOENT;
1189 }
1190
1191 static int b53_arl_op(struct b53_device *dev, int op, int port,
1192 const unsigned char *addr, u16 vid, bool is_valid)
1193 {
1194 struct b53_arl_entry ent;
1195 u32 fwd_entry;
1196 u64 mac, mac_vid = 0;
1197 u8 idx = 0;
1198 int ret;
1199
1200 /* Convert the array into a 64-bit MAC */
1201 mac = ether_addr_to_u64(addr);
1202
1203 /* Perform a read for the given MAC and VID */
1204 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1205 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1206
1207 /* Issue a read operation for this MAC */
1208 ret = b53_arl_rw_op(dev, 1);
1209 if (ret)
1210 return ret;
1211
1212 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1213 /* If this is a read, just finish now */
1214 if (op)
1215 return ret;
1216
1217 /* We could not find a matching MAC, so reset to a new entry */
1218 if (ret) {
1219 fwd_entry = 0;
1220 idx = 1;
1221 }
1222
1223 memset(&ent, 0, sizeof(ent));
1224 ent.port = port;
1225 ent.is_valid = is_valid;
1226 ent.vid = vid;
1227 ent.is_static = true;
1228 memcpy(ent.mac, addr, ETH_ALEN);
1229 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1230
1231 b53_write64(dev, B53_ARLIO_PAGE,
1232 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1233 b53_write32(dev, B53_ARLIO_PAGE,
1234 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1235
1236 return b53_arl_rw_op(dev, 0);
1237 }
1238
1239 int b53_fdb_add(struct dsa_switch *ds, int port,
1240 const unsigned char *addr, u16 vid)
1241 {
1242 struct b53_device *priv = ds->priv;
1243
1244 /* 5325 and 5365 require some more massaging, but could
1245 * be supported eventually
1246 */
1247 if (is5325(priv) || is5365(priv))
1248 return -EOPNOTSUPP;
1249
1250 return b53_arl_op(priv, 0, port, addr, vid, true);
1251 }
1252 EXPORT_SYMBOL(b53_fdb_add);
1253
1254 int b53_fdb_del(struct dsa_switch *ds, int port,
1255 const unsigned char *addr, u16 vid)
1256 {
1257 struct b53_device *priv = ds->priv;
1258
1259 return b53_arl_op(priv, 0, port, addr, vid, false);
1260 }
1261 EXPORT_SYMBOL(b53_fdb_del);
1262
1263 static int b53_arl_search_wait(struct b53_device *dev)
1264 {
1265 unsigned int timeout = 1000;
1266 u8 reg;
1267
1268 do {
1269 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1270 if (!(reg & ARL_SRCH_STDN))
1271 return 0;
1272
1273 if (reg & ARL_SRCH_VLID)
1274 return 0;
1275
1276 usleep_range(1000, 2000);
1277 } while (timeout--);
1278
1279 return -ETIMEDOUT;
1280 }
1281
1282 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1283 struct b53_arl_entry *ent)
1284 {
1285 u64 mac_vid;
1286 u32 fwd_entry;
1287
1288 b53_read64(dev, B53_ARLIO_PAGE,
1289 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1290 b53_read32(dev, B53_ARLIO_PAGE,
1291 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1292 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1293 }
1294
1295 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1296 dsa_fdb_dump_cb_t *cb, void *data)
1297 {
1298 if (!ent->is_valid)
1299 return 0;
1300
1301 if (port != ent->port)
1302 return 0;
1303
1304 return cb(ent->mac, ent->vid, ent->is_static, data);
1305 }
1306
1307 int b53_fdb_dump(struct dsa_switch *ds, int port,
1308 dsa_fdb_dump_cb_t *cb, void *data)
1309 {
1310 struct b53_device *priv = ds->priv;
1311 struct b53_arl_entry results[2];
1312 unsigned int count = 0;
1313 int ret;
1314 u8 reg;
1315
1316 /* Start search operation */
1317 reg = ARL_SRCH_STDN;
1318 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1319
1320 do {
1321 ret = b53_arl_search_wait(priv);
1322 if (ret)
1323 return ret;
1324
1325 b53_arl_search_rd(priv, 0, &results[0]);
1326 ret = b53_fdb_copy(port, &results[0], cb, data);
1327 if (ret)
1328 return ret;
1329
1330 if (priv->num_arl_entries > 2) {
1331 b53_arl_search_rd(priv, 1, &results[1]);
1332 ret = b53_fdb_copy(port, &results[1], cb, data);
1333 if (ret)
1334 return ret;
1335
1336 if (!results[0].is_valid && !results[1].is_valid)
1337 break;
1338 }
1339
1340 } while (count++ < 1024);
1341
1342 return 0;
1343 }
1344 EXPORT_SYMBOL(b53_fdb_dump);
1345
1346 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1347 {
1348 struct b53_device *dev = ds->priv;
1349 s8 cpu_port = ds->ports[port].cpu_dp->index;
1350 u16 pvlan, reg;
1351 unsigned int i;
1352
1353 /* Make this port leave the all VLANs join since we will have proper
1354 * VLAN entries from now on
1355 */
1356 if (is58xx(dev)) {
1357 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1358 reg &= ~BIT(port);
1359 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1360 reg &= ~BIT(cpu_port);
1361 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1362 }
1363
1364 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1365
1366 b53_for_each_port(dev, i) {
1367 if (dsa_to_port(ds, i)->bridge_dev != br)
1368 continue;
1369
1370 /* Add this local port to the remote port VLAN control
1371 * membership and update the remote port bitmask
1372 */
1373 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1374 reg |= BIT(port);
1375 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1376 dev->ports[i].vlan_ctl_mask = reg;
1377
1378 pvlan |= BIT(i);
1379 }
1380
1381 /* Configure the local port VLAN control membership to include
1382 * remote ports and update the local port bitmask
1383 */
1384 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1385 dev->ports[port].vlan_ctl_mask = pvlan;
1386
1387 return 0;
1388 }
1389 EXPORT_SYMBOL(b53_br_join);
1390
1391 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1392 {
1393 struct b53_device *dev = ds->priv;
1394 struct b53_vlan *vl = &dev->vlans[0];
1395 s8 cpu_port = ds->ports[port].cpu_dp->index;
1396 unsigned int i;
1397 u16 pvlan, reg, pvid;
1398
1399 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1400
1401 b53_for_each_port(dev, i) {
1402 /* Don't touch the remaining ports */
1403 if (dsa_to_port(ds, i)->bridge_dev != br)
1404 continue;
1405
1406 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1407 reg &= ~BIT(port);
1408 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1409 dev->ports[port].vlan_ctl_mask = reg;
1410
1411 /* Prevent self removal to preserve isolation */
1412 if (port != i)
1413 pvlan &= ~BIT(i);
1414 }
1415
1416 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1417 dev->ports[port].vlan_ctl_mask = pvlan;
1418
1419 if (is5325(dev) || is5365(dev))
1420 pvid = 1;
1421 else
1422 pvid = 0;
1423
1424 /* Make this port join all VLANs without VLAN entries */
1425 if (is58xx(dev)) {
1426 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1427 reg |= BIT(port);
1428 if (!(reg & BIT(cpu_port)))
1429 reg |= BIT(cpu_port);
1430 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1431 } else {
1432 b53_get_vlan_entry(dev, pvid, vl);
1433 vl->members |= BIT(port) | BIT(cpu_port);
1434 vl->untag |= BIT(port) | BIT(cpu_port);
1435 b53_set_vlan_entry(dev, pvid, vl);
1436 }
1437 }
1438 EXPORT_SYMBOL(b53_br_leave);
1439
1440 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1441 {
1442 struct b53_device *dev = ds->priv;
1443 u8 hw_state;
1444 u8 reg;
1445
1446 switch (state) {
1447 case BR_STATE_DISABLED:
1448 hw_state = PORT_CTRL_DIS_STATE;
1449 break;
1450 case BR_STATE_LISTENING:
1451 hw_state = PORT_CTRL_LISTEN_STATE;
1452 break;
1453 case BR_STATE_LEARNING:
1454 hw_state = PORT_CTRL_LEARN_STATE;
1455 break;
1456 case BR_STATE_FORWARDING:
1457 hw_state = PORT_CTRL_FWD_STATE;
1458 break;
1459 case BR_STATE_BLOCKING:
1460 hw_state = PORT_CTRL_BLOCK_STATE;
1461 break;
1462 default:
1463 dev_err(ds->dev, "invalid STP state: %d\n", state);
1464 return;
1465 }
1466
1467 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1468 reg &= ~PORT_CTRL_STP_STATE_MASK;
1469 reg |= hw_state;
1470 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1471 }
1472 EXPORT_SYMBOL(b53_br_set_stp_state);
1473
1474 void b53_br_fast_age(struct dsa_switch *ds, int port)
1475 {
1476 struct b53_device *dev = ds->priv;
1477
1478 if (b53_fast_age_port(dev, port))
1479 dev_err(ds->dev, "fast ageing failed\n");
1480 }
1481 EXPORT_SYMBOL(b53_br_fast_age);
1482
1483 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1484 {
1485 /* Broadcom switches will accept enabling Broadcom tags on the
1486 * following ports: 5, 7 and 8, any other port is not supported
1487 */
1488 switch (port) {
1489 case B53_CPU_PORT_25:
1490 case 7:
1491 case B53_CPU_PORT:
1492 return true;
1493 }
1494
1495 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", port);
1496 return false;
1497 }
1498
1499 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds,
1500 int port)
1501 {
1502 struct b53_device *dev = ds->priv;
1503
1504 /* Older models (5325, 5365) support a different tag format that we do
1505 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1506 * mode to be turned on which means we need to specifically manage ARL
1507 * misses on multicast addresses (TBD).
1508 */
1509 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1510 !b53_can_enable_brcm_tags(ds, port))
1511 return DSA_TAG_PROTO_NONE;
1512
1513 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1514 * which requires us to use the prepended Broadcom tag type
1515 */
1516 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1517 return DSA_TAG_PROTO_BRCM_PREPEND;
1518
1519 return DSA_TAG_PROTO_BRCM;
1520 }
1521
1522 int b53_mirror_add(struct dsa_switch *ds, int port,
1523 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1524 {
1525 struct b53_device *dev = ds->priv;
1526 u16 reg, loc;
1527
1528 if (ingress)
1529 loc = B53_IG_MIR_CTL;
1530 else
1531 loc = B53_EG_MIR_CTL;
1532
1533 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1534 reg &= ~MIRROR_MASK;
1535 reg |= BIT(port);
1536 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1537
1538 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1539 reg &= ~CAP_PORT_MASK;
1540 reg |= mirror->to_local_port;
1541 reg |= MIRROR_EN;
1542 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1543
1544 return 0;
1545 }
1546 EXPORT_SYMBOL(b53_mirror_add);
1547
1548 void b53_mirror_del(struct dsa_switch *ds, int port,
1549 struct dsa_mall_mirror_tc_entry *mirror)
1550 {
1551 struct b53_device *dev = ds->priv;
1552 bool loc_disable = false, other_loc_disable = false;
1553 u16 reg, loc;
1554
1555 if (mirror->ingress)
1556 loc = B53_IG_MIR_CTL;
1557 else
1558 loc = B53_EG_MIR_CTL;
1559
1560 /* Update the desired ingress/egress register */
1561 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1562 reg &= ~BIT(port);
1563 if (!(reg & MIRROR_MASK))
1564 loc_disable = true;
1565 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1566
1567 /* Now look at the other one to know if we can disable mirroring
1568 * entirely
1569 */
1570 if (mirror->ingress)
1571 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1572 else
1573 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1574 if (!(reg & MIRROR_MASK))
1575 other_loc_disable = true;
1576
1577 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1578 /* Both no longer have ports, let's disable mirroring */
1579 if (loc_disable && other_loc_disable) {
1580 reg &= ~MIRROR_EN;
1581 reg &= ~mirror->to_local_port;
1582 }
1583 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1584 }
1585 EXPORT_SYMBOL(b53_mirror_del);
1586
1587 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1588 {
1589 struct b53_device *dev = ds->priv;
1590 u16 reg;
1591
1592 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1593 if (enable)
1594 reg |= BIT(port);
1595 else
1596 reg &= ~BIT(port);
1597 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1598 }
1599 EXPORT_SYMBOL(b53_eee_enable_set);
1600
1601
1602 /* Returns 0 if EEE was not enabled, or 1 otherwise
1603 */
1604 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1605 {
1606 int ret;
1607
1608 ret = phy_init_eee(phy, 0);
1609 if (ret)
1610 return 0;
1611
1612 b53_eee_enable_set(ds, port, true);
1613
1614 return 1;
1615 }
1616 EXPORT_SYMBOL(b53_eee_init);
1617
1618 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1619 {
1620 struct b53_device *dev = ds->priv;
1621 struct ethtool_eee *p = &dev->ports[port].eee;
1622 u16 reg;
1623
1624 if (is5325(dev) || is5365(dev))
1625 return -EOPNOTSUPP;
1626
1627 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1628 e->eee_enabled = p->eee_enabled;
1629 e->eee_active = !!(reg & BIT(port));
1630
1631 return 0;
1632 }
1633 EXPORT_SYMBOL(b53_get_mac_eee);
1634
1635 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1636 {
1637 struct b53_device *dev = ds->priv;
1638 struct ethtool_eee *p = &dev->ports[port].eee;
1639
1640 if (is5325(dev) || is5365(dev))
1641 return -EOPNOTSUPP;
1642
1643 p->eee_enabled = e->eee_enabled;
1644 b53_eee_enable_set(ds, port, e->eee_enabled);
1645
1646 return 0;
1647 }
1648 EXPORT_SYMBOL(b53_set_mac_eee);
1649
1650 static const struct dsa_switch_ops b53_switch_ops = {
1651 .get_tag_protocol = b53_get_tag_protocol,
1652 .setup = b53_setup,
1653 .get_strings = b53_get_strings,
1654 .get_ethtool_stats = b53_get_ethtool_stats,
1655 .get_sset_count = b53_get_sset_count,
1656 .phy_read = b53_phy_read16,
1657 .phy_write = b53_phy_write16,
1658 .adjust_link = b53_adjust_link,
1659 .port_enable = b53_enable_port,
1660 .port_disable = b53_disable_port,
1661 .get_mac_eee = b53_get_mac_eee,
1662 .set_mac_eee = b53_set_mac_eee,
1663 .port_bridge_join = b53_br_join,
1664 .port_bridge_leave = b53_br_leave,
1665 .port_stp_state_set = b53_br_set_stp_state,
1666 .port_fast_age = b53_br_fast_age,
1667 .port_vlan_filtering = b53_vlan_filtering,
1668 .port_vlan_prepare = b53_vlan_prepare,
1669 .port_vlan_add = b53_vlan_add,
1670 .port_vlan_del = b53_vlan_del,
1671 .port_fdb_dump = b53_fdb_dump,
1672 .port_fdb_add = b53_fdb_add,
1673 .port_fdb_del = b53_fdb_del,
1674 .port_mirror_add = b53_mirror_add,
1675 .port_mirror_del = b53_mirror_del,
1676 };
1677
1678 struct b53_chip_data {
1679 u32 chip_id;
1680 const char *dev_name;
1681 u16 vlans;
1682 u16 enabled_ports;
1683 u8 cpu_port;
1684 u8 vta_regs[3];
1685 u8 arl_entries;
1686 u8 duplex_reg;
1687 u8 jumbo_pm_reg;
1688 u8 jumbo_size_reg;
1689 };
1690
1691 #define B53_VTA_REGS \
1692 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1693 #define B53_VTA_REGS_9798 \
1694 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1695 #define B53_VTA_REGS_63XX \
1696 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1697
1698 static const struct b53_chip_data b53_switch_chips[] = {
1699 {
1700 .chip_id = BCM5325_DEVICE_ID,
1701 .dev_name = "BCM5325",
1702 .vlans = 16,
1703 .enabled_ports = 0x1f,
1704 .arl_entries = 2,
1705 .cpu_port = B53_CPU_PORT_25,
1706 .duplex_reg = B53_DUPLEX_STAT_FE,
1707 },
1708 {
1709 .chip_id = BCM5365_DEVICE_ID,
1710 .dev_name = "BCM5365",
1711 .vlans = 256,
1712 .enabled_ports = 0x1f,
1713 .arl_entries = 2,
1714 .cpu_port = B53_CPU_PORT_25,
1715 .duplex_reg = B53_DUPLEX_STAT_FE,
1716 },
1717 {
1718 .chip_id = BCM5389_DEVICE_ID,
1719 .dev_name = "BCM5389",
1720 .vlans = 4096,
1721 .enabled_ports = 0x1f,
1722 .arl_entries = 4,
1723 .cpu_port = B53_CPU_PORT,
1724 .vta_regs = B53_VTA_REGS,
1725 .duplex_reg = B53_DUPLEX_STAT_GE,
1726 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1727 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1728 },
1729 {
1730 .chip_id = BCM5395_DEVICE_ID,
1731 .dev_name = "BCM5395",
1732 .vlans = 4096,
1733 .enabled_ports = 0x1f,
1734 .arl_entries = 4,
1735 .cpu_port = B53_CPU_PORT,
1736 .vta_regs = B53_VTA_REGS,
1737 .duplex_reg = B53_DUPLEX_STAT_GE,
1738 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1739 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1740 },
1741 {
1742 .chip_id = BCM5397_DEVICE_ID,
1743 .dev_name = "BCM5397",
1744 .vlans = 4096,
1745 .enabled_ports = 0x1f,
1746 .arl_entries = 4,
1747 .cpu_port = B53_CPU_PORT,
1748 .vta_regs = B53_VTA_REGS_9798,
1749 .duplex_reg = B53_DUPLEX_STAT_GE,
1750 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1751 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1752 },
1753 {
1754 .chip_id = BCM5398_DEVICE_ID,
1755 .dev_name = "BCM5398",
1756 .vlans = 4096,
1757 .enabled_ports = 0x7f,
1758 .arl_entries = 4,
1759 .cpu_port = B53_CPU_PORT,
1760 .vta_regs = B53_VTA_REGS_9798,
1761 .duplex_reg = B53_DUPLEX_STAT_GE,
1762 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1763 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1764 },
1765 {
1766 .chip_id = BCM53115_DEVICE_ID,
1767 .dev_name = "BCM53115",
1768 .vlans = 4096,
1769 .enabled_ports = 0x1f,
1770 .arl_entries = 4,
1771 .vta_regs = B53_VTA_REGS,
1772 .cpu_port = B53_CPU_PORT,
1773 .duplex_reg = B53_DUPLEX_STAT_GE,
1774 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1775 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1776 },
1777 {
1778 .chip_id = BCM53125_DEVICE_ID,
1779 .dev_name = "BCM53125",
1780 .vlans = 4096,
1781 .enabled_ports = 0xff,
1782 .arl_entries = 4,
1783 .cpu_port = B53_CPU_PORT,
1784 .vta_regs = B53_VTA_REGS,
1785 .duplex_reg = B53_DUPLEX_STAT_GE,
1786 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1787 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1788 },
1789 {
1790 .chip_id = BCM53128_DEVICE_ID,
1791 .dev_name = "BCM53128",
1792 .vlans = 4096,
1793 .enabled_ports = 0x1ff,
1794 .arl_entries = 4,
1795 .cpu_port = B53_CPU_PORT,
1796 .vta_regs = B53_VTA_REGS,
1797 .duplex_reg = B53_DUPLEX_STAT_GE,
1798 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1799 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1800 },
1801 {
1802 .chip_id = BCM63XX_DEVICE_ID,
1803 .dev_name = "BCM63xx",
1804 .vlans = 4096,
1805 .enabled_ports = 0, /* pdata must provide them */
1806 .arl_entries = 4,
1807 .cpu_port = B53_CPU_PORT,
1808 .vta_regs = B53_VTA_REGS_63XX,
1809 .duplex_reg = B53_DUPLEX_STAT_63XX,
1810 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1811 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1812 },
1813 {
1814 .chip_id = BCM53010_DEVICE_ID,
1815 .dev_name = "BCM53010",
1816 .vlans = 4096,
1817 .enabled_ports = 0x1f,
1818 .arl_entries = 4,
1819 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1820 .vta_regs = B53_VTA_REGS,
1821 .duplex_reg = B53_DUPLEX_STAT_GE,
1822 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1823 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1824 },
1825 {
1826 .chip_id = BCM53011_DEVICE_ID,
1827 .dev_name = "BCM53011",
1828 .vlans = 4096,
1829 .enabled_ports = 0x1bf,
1830 .arl_entries = 4,
1831 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1832 .vta_regs = B53_VTA_REGS,
1833 .duplex_reg = B53_DUPLEX_STAT_GE,
1834 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1835 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1836 },
1837 {
1838 .chip_id = BCM53012_DEVICE_ID,
1839 .dev_name = "BCM53012",
1840 .vlans = 4096,
1841 .enabled_ports = 0x1bf,
1842 .arl_entries = 4,
1843 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1844 .vta_regs = B53_VTA_REGS,
1845 .duplex_reg = B53_DUPLEX_STAT_GE,
1846 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1847 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1848 },
1849 {
1850 .chip_id = BCM53018_DEVICE_ID,
1851 .dev_name = "BCM53018",
1852 .vlans = 4096,
1853 .enabled_ports = 0x1f,
1854 .arl_entries = 4,
1855 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1856 .vta_regs = B53_VTA_REGS,
1857 .duplex_reg = B53_DUPLEX_STAT_GE,
1858 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1859 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1860 },
1861 {
1862 .chip_id = BCM53019_DEVICE_ID,
1863 .dev_name = "BCM53019",
1864 .vlans = 4096,
1865 .enabled_ports = 0x1f,
1866 .arl_entries = 4,
1867 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1868 .vta_regs = B53_VTA_REGS,
1869 .duplex_reg = B53_DUPLEX_STAT_GE,
1870 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1871 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1872 },
1873 {
1874 .chip_id = BCM58XX_DEVICE_ID,
1875 .dev_name = "BCM585xx/586xx/88312",
1876 .vlans = 4096,
1877 .enabled_ports = 0x1ff,
1878 .arl_entries = 4,
1879 .cpu_port = B53_CPU_PORT,
1880 .vta_regs = B53_VTA_REGS,
1881 .duplex_reg = B53_DUPLEX_STAT_GE,
1882 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1883 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1884 },
1885 {
1886 .chip_id = BCM583XX_DEVICE_ID,
1887 .dev_name = "BCM583xx/11360",
1888 .vlans = 4096,
1889 .enabled_ports = 0x103,
1890 .arl_entries = 4,
1891 .cpu_port = B53_CPU_PORT,
1892 .vta_regs = B53_VTA_REGS,
1893 .duplex_reg = B53_DUPLEX_STAT_GE,
1894 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1895 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1896 },
1897 {
1898 .chip_id = BCM7445_DEVICE_ID,
1899 .dev_name = "BCM7445",
1900 .vlans = 4096,
1901 .enabled_ports = 0x1ff,
1902 .arl_entries = 4,
1903 .cpu_port = B53_CPU_PORT,
1904 .vta_regs = B53_VTA_REGS,
1905 .duplex_reg = B53_DUPLEX_STAT_GE,
1906 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1907 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1908 },
1909 {
1910 .chip_id = BCM7278_DEVICE_ID,
1911 .dev_name = "BCM7278",
1912 .vlans = 4096,
1913 .enabled_ports = 0x1ff,
1914 .arl_entries= 4,
1915 .cpu_port = B53_CPU_PORT,
1916 .vta_regs = B53_VTA_REGS,
1917 .duplex_reg = B53_DUPLEX_STAT_GE,
1918 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1919 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1920 },
1921 };
1922
1923 static int b53_switch_init(struct b53_device *dev)
1924 {
1925 unsigned int i;
1926 int ret;
1927
1928 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1929 const struct b53_chip_data *chip = &b53_switch_chips[i];
1930
1931 if (chip->chip_id == dev->chip_id) {
1932 if (!dev->enabled_ports)
1933 dev->enabled_ports = chip->enabled_ports;
1934 dev->name = chip->dev_name;
1935 dev->duplex_reg = chip->duplex_reg;
1936 dev->vta_regs[0] = chip->vta_regs[0];
1937 dev->vta_regs[1] = chip->vta_regs[1];
1938 dev->vta_regs[2] = chip->vta_regs[2];
1939 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1940 dev->cpu_port = chip->cpu_port;
1941 dev->num_vlans = chip->vlans;
1942 dev->num_arl_entries = chip->arl_entries;
1943 break;
1944 }
1945 }
1946
1947 /* check which BCM5325x version we have */
1948 if (is5325(dev)) {
1949 u8 vc4;
1950
1951 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1952
1953 /* check reserved bits */
1954 switch (vc4 & 3) {
1955 case 1:
1956 /* BCM5325E */
1957 break;
1958 case 3:
1959 /* BCM5325F - do not use port 4 */
1960 dev->enabled_ports &= ~BIT(4);
1961 break;
1962 default:
1963 /* On the BCM47XX SoCs this is the supported internal switch.*/
1964 #ifndef CONFIG_BCM47XX
1965 /* BCM5325M */
1966 return -EINVAL;
1967 #else
1968 break;
1969 #endif
1970 }
1971 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1972 u64 strap_value;
1973
1974 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1975 /* use second IMP port if GMII is enabled */
1976 if (strap_value & SV_GMII_CTRL_115)
1977 dev->cpu_port = 5;
1978 }
1979
1980 /* cpu port is always last */
1981 dev->num_ports = dev->cpu_port + 1;
1982 dev->enabled_ports |= BIT(dev->cpu_port);
1983
1984 dev->ports = devm_kzalloc(dev->dev,
1985 sizeof(struct b53_port) * dev->num_ports,
1986 GFP_KERNEL);
1987 if (!dev->ports)
1988 return -ENOMEM;
1989
1990 dev->vlans = devm_kzalloc(dev->dev,
1991 sizeof(struct b53_vlan) * dev->num_vlans,
1992 GFP_KERNEL);
1993 if (!dev->vlans)
1994 return -ENOMEM;
1995
1996 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1997 if (dev->reset_gpio >= 0) {
1998 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1999 GPIOF_OUT_INIT_HIGH, "robo_reset");
2000 if (ret)
2001 return ret;
2002 }
2003
2004 return 0;
2005 }
2006
2007 struct b53_device *b53_switch_alloc(struct device *base,
2008 const struct b53_io_ops *ops,
2009 void *priv)
2010 {
2011 struct dsa_switch *ds;
2012 struct b53_device *dev;
2013
2014 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2015 if (!ds)
2016 return NULL;
2017
2018 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2019 if (!dev)
2020 return NULL;
2021
2022 ds->priv = dev;
2023 dev->dev = base;
2024
2025 dev->ds = ds;
2026 dev->priv = priv;
2027 dev->ops = ops;
2028 ds->ops = &b53_switch_ops;
2029 mutex_init(&dev->reg_mutex);
2030 mutex_init(&dev->stats_mutex);
2031
2032 return dev;
2033 }
2034 EXPORT_SYMBOL(b53_switch_alloc);
2035
2036 int b53_switch_detect(struct b53_device *dev)
2037 {
2038 u32 id32;
2039 u16 tmp;
2040 u8 id8;
2041 int ret;
2042
2043 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2044 if (ret)
2045 return ret;
2046
2047 switch (id8) {
2048 case 0:
2049 /* BCM5325 and BCM5365 do not have this register so reads
2050 * return 0. But the read operation did succeed, so assume this
2051 * is one of them.
2052 *
2053 * Next check if we can write to the 5325's VTA register; for
2054 * 5365 it is read only.
2055 */
2056 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2057 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2058
2059 if (tmp == 0xf)
2060 dev->chip_id = BCM5325_DEVICE_ID;
2061 else
2062 dev->chip_id = BCM5365_DEVICE_ID;
2063 break;
2064 case BCM5389_DEVICE_ID:
2065 case BCM5395_DEVICE_ID:
2066 case BCM5397_DEVICE_ID:
2067 case BCM5398_DEVICE_ID:
2068 dev->chip_id = id8;
2069 break;
2070 default:
2071 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2072 if (ret)
2073 return ret;
2074
2075 switch (id32) {
2076 case BCM53115_DEVICE_ID:
2077 case BCM53125_DEVICE_ID:
2078 case BCM53128_DEVICE_ID:
2079 case BCM53010_DEVICE_ID:
2080 case BCM53011_DEVICE_ID:
2081 case BCM53012_DEVICE_ID:
2082 case BCM53018_DEVICE_ID:
2083 case BCM53019_DEVICE_ID:
2084 dev->chip_id = id32;
2085 break;
2086 default:
2087 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2088 id8, id32);
2089 return -ENODEV;
2090 }
2091 }
2092
2093 if (dev->chip_id == BCM5325_DEVICE_ID)
2094 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2095 &dev->core_rev);
2096 else
2097 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2098 &dev->core_rev);
2099 }
2100 EXPORT_SYMBOL(b53_switch_detect);
2101
2102 int b53_switch_register(struct b53_device *dev)
2103 {
2104 int ret;
2105
2106 if (dev->pdata) {
2107 dev->chip_id = dev->pdata->chip_id;
2108 dev->enabled_ports = dev->pdata->enabled_ports;
2109 }
2110
2111 if (!dev->chip_id && b53_switch_detect(dev))
2112 return -EINVAL;
2113
2114 ret = b53_switch_init(dev);
2115 if (ret)
2116 return ret;
2117
2118 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2119
2120 return dsa_register_switch(dev->ds);
2121 }
2122 EXPORT_SYMBOL(b53_switch_register);
2123
2124 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2125 MODULE_DESCRIPTION("B53 switch library");
2126 MODULE_LICENSE("Dual BSD/GPL");
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