2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65
[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx
[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
129 static const struct b53_mib_desc b53_mibs
[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169 static const struct b53_mib_desc b53_mibs_58xx
[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
232 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
234 for (i
= 0; i
< 10; i
++) {
237 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
238 if (!(vta
& VTA_START_CMD
))
241 usleep_range(100, 200);
247 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
,
248 struct b53_vlan
*vlan
)
254 entry
= ((vlan
->untag
& VA_UNTAG_MASK_25
) <<
255 VA_UNTAG_S_25
) | vlan
->members
;
256 if (dev
->core_rev
>= 3)
257 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
259 entry
|= VA_VALID_25
;
262 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
263 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
264 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
265 } else if (is5365(dev
)) {
269 entry
= ((vlan
->untag
& VA_UNTAG_MASK_65
) <<
270 VA_UNTAG_S_65
) | vlan
->members
| VA_VALID_65
;
272 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
273 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
274 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
276 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
277 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
278 (vlan
->untag
<< VTE_UNTAG_S
) | vlan
->members
);
280 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
283 dev_dbg(dev
->ds
->dev
, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid
, vlan
->members
, vlan
->untag
);
287 static void b53_get_vlan_entry(struct b53_device
*dev
, u16 vid
,
288 struct b53_vlan
*vlan
)
293 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
294 VTA_RW_STATE_RD
| VTA_RW_OP_EN
);
295 b53_read32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, &entry
);
297 if (dev
->core_rev
>= 3)
298 vlan
->valid
= !!(entry
& VA_VALID_25_R4
);
300 vlan
->valid
= !!(entry
& VA_VALID_25
);
301 vlan
->members
= entry
& VA_MEMBER_MASK
;
302 vlan
->untag
= (entry
>> VA_UNTAG_S_25
) & VA_UNTAG_MASK_25
;
304 } else if (is5365(dev
)) {
307 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
308 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
309 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, &entry
);
311 vlan
->valid
= !!(entry
& VA_VALID_65
);
312 vlan
->members
= entry
& VA_MEMBER_MASK
;
313 vlan
->untag
= (entry
>> VA_UNTAG_S_65
) & VA_UNTAG_MASK_65
;
317 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
318 b53_do_vlan_op(dev
, VTA_CMD_READ
);
319 b53_read32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2], &entry
);
320 vlan
->members
= entry
& VTE_MEMBERS
;
321 vlan
->untag
= (entry
>> VTE_UNTAG_S
) & VTE_MEMBERS
;
326 static void b53_set_forwarding(struct b53_device
*dev
, int enable
)
330 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
333 mgmt
|= SM_SW_FWD_EN
;
335 mgmt
&= ~SM_SW_FWD_EN
;
337 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
339 /* Include IMP port in dumb forwarding mode
341 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_CTRL
, &mgmt
);
342 mgmt
|= B53_MII_DUMB_FWDG_EN
;
343 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_CTRL
, mgmt
);
346 static void b53_enable_vlan(struct b53_device
*dev
, bool enable
)
348 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
350 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
351 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
352 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
354 if (is5325(dev
) || is5365(dev
)) {
355 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
356 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
357 } else if (is63xx(dev
)) {
358 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
359 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
361 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
362 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
365 mgmt
&= ~SM_SW_FWD_MODE
;
368 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
369 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
370 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
371 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
372 vc5
|= VC5_DROP_VTABLE_MISS
;
375 vc0
&= ~VC0_RESERVED_1
;
377 if (is5325(dev
) || is5365(dev
))
378 vc1
|= VC1_RX_MCST_TAG_EN
;
381 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
382 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
383 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
384 vc5
&= ~VC5_DROP_VTABLE_MISS
;
386 if (is5325(dev
) || is5365(dev
))
387 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
389 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
391 if (is5325(dev
) || is5365(dev
))
392 vc1
&= ~VC1_RX_MCST_TAG_EN
;
395 if (!is5325(dev
) && !is5365(dev
))
396 vc5
&= ~VC5_VID_FFF_EN
;
398 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
399 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
401 if (is5325(dev
) || is5365(dev
)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev
) && enable
)
404 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
407 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
409 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
410 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
411 } else if (is63xx(dev
)) {
412 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
413 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
414 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
416 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
417 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
418 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
421 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
424 static int b53_set_jumbo(struct b53_device
*dev
, bool enable
, bool allow_10_100
)
427 u16 max_size
= JMS_MIN_SIZE
;
429 if (is5325(dev
) || is5365(dev
))
433 port_mask
= dev
->enabled_ports
;
434 max_size
= JMS_MAX_SIZE
;
436 port_mask
|= JPM_10_100_JUMBO_EN
;
439 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
440 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
443 static int b53_flush_arl(struct b53_device
*dev
, u8 mask
)
447 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
448 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| mask
);
450 for (i
= 0; i
< 10; i
++) {
453 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
456 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
, FAST_AGE_DYNAMIC
);
469 static int b53_fast_age_port(struct b53_device
*dev
, int port
)
471 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_PORT_CTRL
, port
);
473 return b53_flush_arl(dev
, FAST_AGE_PORT
);
476 static int b53_fast_age_vlan(struct b53_device
*dev
, u16 vid
)
478 b53_write16(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_VID_CTRL
, vid
);
480 return b53_flush_arl(dev
, FAST_AGE_VLAN
);
483 void b53_imp_vlan_setup(struct dsa_switch
*ds
, int cpu_port
)
485 struct b53_device
*dev
= ds
->priv
;
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
493 b53_for_each_port(dev
, i
) {
494 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), &pvlan
);
495 pvlan
|= BIT(cpu_port
);
496 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), pvlan
);
499 EXPORT_SYMBOL(b53_imp_vlan_setup
);
501 int b53_enable_port(struct dsa_switch
*ds
, int port
, struct phy_device
*phy
)
503 struct b53_device
*dev
= ds
->priv
;
504 unsigned int cpu_port
= ds
->ports
[port
].cpu_dp
->index
;
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), 0);
510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
514 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
517 pvlan
|= dev
->ports
[port
].vlan_ctl_mask
;
518 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
520 b53_imp_vlan_setup(ds
, cpu_port
);
522 /* If EEE was enabled, restore it */
523 if (dev
->ports
[port
].eee
.eee_enabled
)
524 b53_eee_enable_set(ds
, port
, true);
528 EXPORT_SYMBOL(b53_enable_port
);
530 void b53_disable_port(struct dsa_switch
*ds
, int port
, struct phy_device
*phy
)
532 struct b53_device
*dev
= ds
->priv
;
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), ®
);
537 reg
|= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
538 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), reg
);
540 EXPORT_SYMBOL(b53_disable_port
);
542 void b53_brcm_hdr_setup(struct dsa_switch
*ds
, int port
)
544 bool tag_en
= !(ds
->ops
->get_tag_protocol(ds
, port
) ==
546 struct b53_device
*dev
= ds
->priv
;
550 /* Resolve which bit controls the Broadcom tag */
553 val
= BRCM_HDR_P8_EN
;
556 val
= BRCM_HDR_P7_EN
;
559 val
= BRCM_HDR_P5_EN
;
566 /* Enable Broadcom tags for IMP port */
567 b53_read8(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR
, &hdr_ctl
);
572 b53_write8(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR
, hdr_ctl
);
574 /* Registers below are only accessible on newer devices */
578 /* Enable reception Broadcom tag for CPU TX (switch RX) to
579 * allow us to tag outgoing frames
581 b53_read16(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR_RX_DIS
, ®
);
586 b53_write16(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR_RX_DIS
, reg
);
588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
589 * allow delivering frames to the per-port net_devices
591 b53_read16(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR_TX_DIS
, ®
);
596 b53_write16(dev
, B53_MGMT_PAGE
, B53_BRCM_HDR_TX_DIS
, reg
);
598 EXPORT_SYMBOL(b53_brcm_hdr_setup
);
600 static void b53_enable_cpu_port(struct b53_device
*dev
, int port
)
604 /* BCM5325 CPU port is at 8 */
605 if ((is5325(dev
) || is5365(dev
)) && port
== B53_CPU_PORT_25
)
608 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
609 PORT_CTRL_RX_MCST_EN
|
610 PORT_CTRL_RX_UCST_EN
;
611 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), port_ctrl
);
613 b53_brcm_hdr_setup(dev
->ds
, port
);
616 static void b53_enable_mib(struct b53_device
*dev
)
620 b53_read8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
621 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
622 b53_write8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
);
625 int b53_configure_vlan(struct dsa_switch
*ds
)
627 struct b53_device
*dev
= ds
->priv
;
628 struct b53_vlan vl
= { 0 };
631 /* clear all vlan entries */
632 if (is5325(dev
) || is5365(dev
)) {
633 for (i
= 1; i
< dev
->num_vlans
; i
++)
634 b53_set_vlan_entry(dev
, i
, &vl
);
636 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
639 b53_enable_vlan(dev
, false);
641 b53_for_each_port(dev
, i
)
642 b53_write16(dev
, B53_VLAN_PAGE
,
643 B53_VLAN_PORT_DEF_TAG(i
), 1);
645 if (!is5325(dev
) && !is5365(dev
))
646 b53_set_jumbo(dev
, dev
->enable_jumbo
, false);
650 EXPORT_SYMBOL(b53_configure_vlan
);
652 static void b53_switch_reset_gpio(struct b53_device
*dev
)
654 int gpio
= dev
->reset_gpio
;
659 /* Reset sequence: RESET low(50ms)->high(20ms)
661 gpio_set_value(gpio
, 0);
664 gpio_set_value(gpio
, 1);
667 dev
->current_page
= 0xff;
670 static int b53_switch_reset(struct b53_device
*dev
)
672 unsigned int timeout
= 1000;
675 b53_switch_reset_gpio(dev
);
678 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
679 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
682 /* This is specific to 58xx devices here, do not use is58xx() which
683 * covers the larger Starfigther 2 family, including 7445/7278 which
684 * still use this driver as a library and need to perform the reset
687 if (dev
->chip_id
== BCM58XX_DEVICE_ID
) {
688 b53_read8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, ®
);
689 reg
|= SW_RST
| EN_SW_RST
| EN_CH_RST
;
690 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, reg
);
693 b53_read8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, ®
);
697 usleep_range(1000, 2000);
698 } while (timeout
-- > 0);
704 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
706 if (!(mgmt
& SM_SW_FWD_EN
)) {
707 mgmt
&= ~SM_SW_FWD_MODE
;
708 mgmt
|= SM_SW_FWD_EN
;
710 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
711 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
713 if (!(mgmt
& SM_SW_FWD_EN
)) {
714 dev_err(dev
->dev
, "Failed to enable switch!\n");
721 return b53_flush_arl(dev
, FAST_AGE_STATIC
);
724 static int b53_phy_read16(struct dsa_switch
*ds
, int addr
, int reg
)
726 struct b53_device
*priv
= ds
->priv
;
730 if (priv
->ops
->phy_read16
)
731 ret
= priv
->ops
->phy_read16(priv
, addr
, reg
, &value
);
733 ret
= b53_read16(priv
, B53_PORT_MII_PAGE(addr
),
736 return ret
? ret
: value
;
739 static int b53_phy_write16(struct dsa_switch
*ds
, int addr
, int reg
, u16 val
)
741 struct b53_device
*priv
= ds
->priv
;
743 if (priv
->ops
->phy_write16
)
744 return priv
->ops
->phy_write16(priv
, addr
, reg
, val
);
746 return b53_write16(priv
, B53_PORT_MII_PAGE(addr
), reg
* 2, val
);
749 static int b53_reset_switch(struct b53_device
*priv
)
752 priv
->enable_jumbo
= false;
754 memset(priv
->vlans
, 0, sizeof(*priv
->vlans
) * priv
->num_vlans
);
755 memset(priv
->ports
, 0, sizeof(*priv
->ports
) * priv
->num_ports
);
757 return b53_switch_reset(priv
);
760 static int b53_apply_config(struct b53_device
*priv
)
762 /* disable switching */
763 b53_set_forwarding(priv
, 0);
765 b53_configure_vlan(priv
->ds
);
767 /* enable switching */
768 b53_set_forwarding(priv
, 1);
773 static void b53_reset_mib(struct b53_device
*priv
)
777 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
779 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
781 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
785 static const struct b53_mib_desc
*b53_get_mib(struct b53_device
*dev
)
789 else if (is63xx(dev
))
790 return b53_mibs_63xx
;
791 else if (is58xx(dev
))
792 return b53_mibs_58xx
;
797 static unsigned int b53_get_mib_size(struct b53_device
*dev
)
800 return B53_MIBS_65_SIZE
;
801 else if (is63xx(dev
))
802 return B53_MIBS_63XX_SIZE
;
803 else if (is58xx(dev
))
804 return B53_MIBS_58XX_SIZE
;
806 return B53_MIBS_SIZE
;
809 void b53_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
811 struct b53_device
*dev
= ds
->priv
;
812 const struct b53_mib_desc
*mibs
= b53_get_mib(dev
);
813 unsigned int mib_size
= b53_get_mib_size(dev
);
816 for (i
= 0; i
< mib_size
; i
++)
817 memcpy(data
+ i
* ETH_GSTRING_LEN
,
818 mibs
[i
].name
, ETH_GSTRING_LEN
);
820 EXPORT_SYMBOL(b53_get_strings
);
822 void b53_get_ethtool_stats(struct dsa_switch
*ds
, int port
, uint64_t *data
)
824 struct b53_device
*dev
= ds
->priv
;
825 const struct b53_mib_desc
*mibs
= b53_get_mib(dev
);
826 unsigned int mib_size
= b53_get_mib_size(dev
);
827 const struct b53_mib_desc
*s
;
831 if (is5365(dev
) && port
== 5)
834 mutex_lock(&dev
->stats_mutex
);
836 for (i
= 0; i
< mib_size
; i
++) {
840 b53_read64(dev
, B53_MIB_PAGE(port
), s
->offset
, &val
);
844 b53_read32(dev
, B53_MIB_PAGE(port
), s
->offset
,
851 mutex_unlock(&dev
->stats_mutex
);
853 EXPORT_SYMBOL(b53_get_ethtool_stats
);
855 int b53_get_sset_count(struct dsa_switch
*ds
)
857 struct b53_device
*dev
= ds
->priv
;
859 return b53_get_mib_size(dev
);
861 EXPORT_SYMBOL(b53_get_sset_count
);
863 static int b53_setup(struct dsa_switch
*ds
)
865 struct b53_device
*dev
= ds
->priv
;
869 ret
= b53_reset_switch(dev
);
871 dev_err(ds
->dev
, "failed to reset switch\n");
877 ret
= b53_apply_config(dev
);
879 dev_err(ds
->dev
, "failed to apply configuration\n");
881 /* Configure IMP/CPU port, disable unused ports. Enabled
882 * ports will be configured with .port_enable
884 for (port
= 0; port
< dev
->num_ports
; port
++) {
885 if (dsa_is_cpu_port(ds
, port
))
886 b53_enable_cpu_port(dev
, port
);
887 else if (dsa_is_unused_port(ds
, port
))
888 b53_disable_port(ds
, port
, NULL
);
894 static void b53_adjust_link(struct dsa_switch
*ds
, int port
,
895 struct phy_device
*phydev
)
897 struct b53_device
*dev
= ds
->priv
;
898 struct ethtool_eee
*p
= &dev
->ports
[port
].eee
;
899 u8 rgmii_ctrl
= 0, reg
= 0, off
;
901 if (!phy_is_pseudo_fixed_link(phydev
))
904 /* Override the port settings */
905 if (port
== dev
->cpu_port
) {
906 off
= B53_PORT_OVERRIDE_CTRL
;
907 reg
= PORT_OVERRIDE_EN
;
909 off
= B53_GMII_PORT_OVERRIDE_CTRL(port
);
913 /* Set the link UP */
915 reg
|= PORT_OVERRIDE_LINK
;
917 if (phydev
->duplex
== DUPLEX_FULL
)
918 reg
|= PORT_OVERRIDE_FULL_DUPLEX
;
920 switch (phydev
->speed
) {
922 reg
|= PORT_OVERRIDE_SPEED_2000M
;
925 reg
|= PORT_OVERRIDE_SPEED_1000M
;
928 reg
|= PORT_OVERRIDE_SPEED_100M
;
931 reg
|= PORT_OVERRIDE_SPEED_10M
;
934 dev_err(ds
->dev
, "unknown speed: %d\n", phydev
->speed
);
938 /* Enable flow control on BCM5301x's CPU port */
939 if (is5301x(dev
) && port
== dev
->cpu_port
)
940 reg
|= PORT_OVERRIDE_RX_FLOW
| PORT_OVERRIDE_TX_FLOW
;
943 if (phydev
->asym_pause
)
944 reg
|= PORT_OVERRIDE_TX_FLOW
;
945 reg
|= PORT_OVERRIDE_RX_FLOW
;
948 b53_write8(dev
, B53_CTRL_PAGE
, off
, reg
);
950 if (is531x5(dev
) && phy_interface_is_rgmii(phydev
)) {
952 off
= B53_RGMII_CTRL_IMP
;
954 off
= B53_RGMII_CTRL_P(port
);
956 /* Configure the port RGMII clock delay by DLL disabled and
957 * tx_clk aligned timing (restoring to reset defaults)
959 b53_read8(dev
, B53_CTRL_PAGE
, off
, &rgmii_ctrl
);
960 rgmii_ctrl
&= ~(RGMII_CTRL_DLL_RXC
| RGMII_CTRL_DLL_TXC
|
961 RGMII_CTRL_TIMING_SEL
);
963 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
964 * sure that we enable the port TX clock internal delay to
965 * account for this internal delay that is inserted, otherwise
966 * the switch won't be able to receive correctly.
968 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
969 * any delay neither on transmission nor reception, so the
970 * BCM53125 must also be configured accordingly to account for
971 * the lack of delay and introduce
973 * The BCM53125 switch has its RX clock and TX clock control
974 * swapped, hence the reason why we modify the TX clock path in
977 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
978 rgmii_ctrl
|= RGMII_CTRL_DLL_TXC
;
979 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII
)
980 rgmii_ctrl
|= RGMII_CTRL_DLL_TXC
| RGMII_CTRL_DLL_RXC
;
981 rgmii_ctrl
|= RGMII_CTRL_TIMING_SEL
;
982 b53_write8(dev
, B53_CTRL_PAGE
, off
, rgmii_ctrl
);
984 dev_info(ds
->dev
, "Configured port %d for %s\n", port
,
985 phy_modes(phydev
->interface
));
988 /* configure MII port if necessary */
990 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
993 /* reverse mii needs to be enabled */
994 if (!(reg
& PORT_OVERRIDE_RV_MII_25
)) {
995 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
996 reg
| PORT_OVERRIDE_RV_MII_25
);
997 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
1000 if (!(reg
& PORT_OVERRIDE_RV_MII_25
)) {
1002 "Failed to enable reverse MII mode\n");
1006 } else if (is5301x(dev
)) {
1007 if (port
!= dev
->cpu_port
) {
1008 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(dev
->cpu_port
);
1011 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
1012 gmii_po
|= GMII_PO_LINK
|
1016 GMII_PO_SPEED_2000M
;
1017 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
1021 /* Re-negotiate EEE if it was enabled already */
1022 p
->eee_enabled
= b53_eee_init(ds
, port
, phydev
);
1025 int b53_vlan_filtering(struct dsa_switch
*ds
, int port
, bool vlan_filtering
)
1029 EXPORT_SYMBOL(b53_vlan_filtering
);
1031 int b53_vlan_prepare(struct dsa_switch
*ds
, int port
,
1032 const struct switchdev_obj_port_vlan
*vlan
,
1033 struct switchdev_trans
*trans
)
1035 struct b53_device
*dev
= ds
->priv
;
1037 if ((is5325(dev
) || is5365(dev
)) && vlan
->vid_begin
== 0)
1040 if (vlan
->vid_end
> dev
->num_vlans
)
1043 b53_enable_vlan(dev
, true);
1047 EXPORT_SYMBOL(b53_vlan_prepare
);
1049 void b53_vlan_add(struct dsa_switch
*ds
, int port
,
1050 const struct switchdev_obj_port_vlan
*vlan
,
1051 struct switchdev_trans
*trans
)
1053 struct b53_device
*dev
= ds
->priv
;
1054 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1055 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1056 struct b53_vlan
*vl
;
1059 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1060 vl
= &dev
->vlans
[vid
];
1062 b53_get_vlan_entry(dev
, vid
, vl
);
1064 vl
->members
|= BIT(port
);
1066 vl
->untag
|= BIT(port
);
1068 vl
->untag
&= ~BIT(port
);
1070 b53_set_vlan_entry(dev
, vid
, vl
);
1071 b53_fast_age_vlan(dev
, vid
);
1075 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
),
1077 b53_fast_age_vlan(dev
, vid
);
1080 EXPORT_SYMBOL(b53_vlan_add
);
1082 int b53_vlan_del(struct dsa_switch
*ds
, int port
,
1083 const struct switchdev_obj_port_vlan
*vlan
)
1085 struct b53_device
*dev
= ds
->priv
;
1086 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1087 struct b53_vlan
*vl
;
1091 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
), &pvid
);
1093 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1094 vl
= &dev
->vlans
[vid
];
1096 b53_get_vlan_entry(dev
, vid
, vl
);
1098 vl
->members
&= ~BIT(port
);
1101 if (is5325(dev
) || is5365(dev
))
1108 vl
->untag
&= ~(BIT(port
));
1110 b53_set_vlan_entry(dev
, vid
, vl
);
1111 b53_fast_age_vlan(dev
, vid
);
1114 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_PORT_DEF_TAG(port
), pvid
);
1115 b53_fast_age_vlan(dev
, pvid
);
1119 EXPORT_SYMBOL(b53_vlan_del
);
1121 /* Address Resolution Logic routines */
1122 static int b53_arl_op_wait(struct b53_device
*dev
)
1124 unsigned int timeout
= 10;
1128 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, ®
);
1129 if (!(reg
& ARLTBL_START_DONE
))
1132 usleep_range(1000, 2000);
1133 } while (timeout
--);
1135 dev_warn(dev
->dev
, "timeout waiting for ARL to finish: 0x%02x\n", reg
);
1140 static int b53_arl_rw_op(struct b53_device
*dev
, unsigned int op
)
1147 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, ®
);
1148 reg
|= ARLTBL_START_DONE
;
1153 b53_write8(dev
, B53_ARLIO_PAGE
, B53_ARLTBL_RW_CTRL
, reg
);
1155 return b53_arl_op_wait(dev
);
1158 static int b53_arl_read(struct b53_device
*dev
, u64 mac
,
1159 u16 vid
, struct b53_arl_entry
*ent
, u8
*idx
,
1165 ret
= b53_arl_op_wait(dev
);
1170 for (i
= 0; i
< dev
->num_arl_entries
; i
++) {
1174 b53_read64(dev
, B53_ARLIO_PAGE
,
1175 B53_ARLTBL_MAC_VID_ENTRY(i
), &mac_vid
);
1176 b53_read32(dev
, B53_ARLIO_PAGE
,
1177 B53_ARLTBL_DATA_ENTRY(i
), &fwd_entry
);
1178 b53_arl_to_entry(ent
, mac_vid
, fwd_entry
);
1180 if (!(fwd_entry
& ARLTBL_VALID
))
1182 if ((mac_vid
& ARLTBL_MAC_MASK
) != mac
)
1190 static int b53_arl_op(struct b53_device
*dev
, int op
, int port
,
1191 const unsigned char *addr
, u16 vid
, bool is_valid
)
1193 struct b53_arl_entry ent
;
1195 u64 mac
, mac_vid
= 0;
1199 /* Convert the array into a 64-bit MAC */
1200 mac
= ether_addr_to_u64(addr
);
1202 /* Perform a read for the given MAC and VID */
1203 b53_write48(dev
, B53_ARLIO_PAGE
, B53_MAC_ADDR_IDX
, mac
);
1204 b53_write16(dev
, B53_ARLIO_PAGE
, B53_VLAN_ID_IDX
, vid
);
1206 /* Issue a read operation for this MAC */
1207 ret
= b53_arl_rw_op(dev
, 1);
1211 ret
= b53_arl_read(dev
, mac
, vid
, &ent
, &idx
, is_valid
);
1212 /* If this is a read, just finish now */
1216 /* We could not find a matching MAC, so reset to a new entry */
1222 memset(&ent
, 0, sizeof(ent
));
1224 ent
.is_valid
= is_valid
;
1226 ent
.is_static
= true;
1227 memcpy(ent
.mac
, addr
, ETH_ALEN
);
1228 b53_arl_from_entry(&mac_vid
, &fwd_entry
, &ent
);
1230 b53_write64(dev
, B53_ARLIO_PAGE
,
1231 B53_ARLTBL_MAC_VID_ENTRY(idx
), mac_vid
);
1232 b53_write32(dev
, B53_ARLIO_PAGE
,
1233 B53_ARLTBL_DATA_ENTRY(idx
), fwd_entry
);
1235 return b53_arl_rw_op(dev
, 0);
1238 int b53_fdb_add(struct dsa_switch
*ds
, int port
,
1239 const unsigned char *addr
, u16 vid
)
1241 struct b53_device
*priv
= ds
->priv
;
1243 /* 5325 and 5365 require some more massaging, but could
1244 * be supported eventually
1246 if (is5325(priv
) || is5365(priv
))
1249 return b53_arl_op(priv
, 0, port
, addr
, vid
, true);
1251 EXPORT_SYMBOL(b53_fdb_add
);
1253 int b53_fdb_del(struct dsa_switch
*ds
, int port
,
1254 const unsigned char *addr
, u16 vid
)
1256 struct b53_device
*priv
= ds
->priv
;
1258 return b53_arl_op(priv
, 0, port
, addr
, vid
, false);
1260 EXPORT_SYMBOL(b53_fdb_del
);
1262 static int b53_arl_search_wait(struct b53_device
*dev
)
1264 unsigned int timeout
= 1000;
1268 b53_read8(dev
, B53_ARLIO_PAGE
, B53_ARL_SRCH_CTL
, ®
);
1269 if (!(reg
& ARL_SRCH_STDN
))
1272 if (reg
& ARL_SRCH_VLID
)
1275 usleep_range(1000, 2000);
1276 } while (timeout
--);
1281 static void b53_arl_search_rd(struct b53_device
*dev
, u8 idx
,
1282 struct b53_arl_entry
*ent
)
1287 b53_read64(dev
, B53_ARLIO_PAGE
,
1288 B53_ARL_SRCH_RSTL_MACVID(idx
), &mac_vid
);
1289 b53_read32(dev
, B53_ARLIO_PAGE
,
1290 B53_ARL_SRCH_RSTL(idx
), &fwd_entry
);
1291 b53_arl_to_entry(ent
, mac_vid
, fwd_entry
);
1294 static int b53_fdb_copy(int port
, const struct b53_arl_entry
*ent
,
1295 dsa_fdb_dump_cb_t
*cb
, void *data
)
1300 if (port
!= ent
->port
)
1303 return cb(ent
->mac
, ent
->vid
, ent
->is_static
, data
);
1306 int b53_fdb_dump(struct dsa_switch
*ds
, int port
,
1307 dsa_fdb_dump_cb_t
*cb
, void *data
)
1309 struct b53_device
*priv
= ds
->priv
;
1310 struct b53_arl_entry results
[2];
1311 unsigned int count
= 0;
1315 /* Start search operation */
1316 reg
= ARL_SRCH_STDN
;
1317 b53_write8(priv
, B53_ARLIO_PAGE
, B53_ARL_SRCH_CTL
, reg
);
1320 ret
= b53_arl_search_wait(priv
);
1324 b53_arl_search_rd(priv
, 0, &results
[0]);
1325 ret
= b53_fdb_copy(port
, &results
[0], cb
, data
);
1329 if (priv
->num_arl_entries
> 2) {
1330 b53_arl_search_rd(priv
, 1, &results
[1]);
1331 ret
= b53_fdb_copy(port
, &results
[1], cb
, data
);
1335 if (!results
[0].is_valid
&& !results
[1].is_valid
)
1339 } while (count
++ < 1024);
1343 EXPORT_SYMBOL(b53_fdb_dump
);
1345 int b53_br_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1347 struct b53_device
*dev
= ds
->priv
;
1348 s8 cpu_port
= ds
->ports
[port
].cpu_dp
->index
;
1352 /* Make this port leave the all VLANs join since we will have proper
1353 * VLAN entries from now on
1356 b53_read16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, ®
);
1358 if ((reg
& BIT(cpu_port
)) == BIT(cpu_port
))
1359 reg
&= ~BIT(cpu_port
);
1360 b53_write16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, reg
);
1363 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
1365 b53_for_each_port(dev
, i
) {
1366 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1369 /* Add this local port to the remote port VLAN control
1370 * membership and update the remote port bitmask
1372 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), ®
);
1374 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), reg
);
1375 dev
->ports
[i
].vlan_ctl_mask
= reg
;
1380 /* Configure the local port VLAN control membership to include
1381 * remote ports and update the local port bitmask
1383 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
1384 dev
->ports
[port
].vlan_ctl_mask
= pvlan
;
1388 EXPORT_SYMBOL(b53_br_join
);
1390 void b53_br_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1392 struct b53_device
*dev
= ds
->priv
;
1393 struct b53_vlan
*vl
= &dev
->vlans
[0];
1394 s8 cpu_port
= ds
->ports
[port
].cpu_dp
->index
;
1396 u16 pvlan
, reg
, pvid
;
1398 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), &pvlan
);
1400 b53_for_each_port(dev
, i
) {
1401 /* Don't touch the remaining ports */
1402 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1405 b53_read16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), ®
);
1407 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
), reg
);
1408 dev
->ports
[port
].vlan_ctl_mask
= reg
;
1410 /* Prevent self removal to preserve isolation */
1415 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(port
), pvlan
);
1416 dev
->ports
[port
].vlan_ctl_mask
= pvlan
;
1418 if (is5325(dev
) || is5365(dev
))
1423 /* Make this port join all VLANs without VLAN entries */
1425 b53_read16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, ®
);
1427 if (!(reg
& BIT(cpu_port
)))
1428 reg
|= BIT(cpu_port
);
1429 b53_write16(dev
, B53_VLAN_PAGE
, B53_JOIN_ALL_VLAN_EN
, reg
);
1431 b53_get_vlan_entry(dev
, pvid
, vl
);
1432 vl
->members
|= BIT(port
) | BIT(cpu_port
);
1433 vl
->untag
|= BIT(port
) | BIT(cpu_port
);
1434 b53_set_vlan_entry(dev
, pvid
, vl
);
1437 EXPORT_SYMBOL(b53_br_leave
);
1439 void b53_br_set_stp_state(struct dsa_switch
*ds
, int port
, u8 state
)
1441 struct b53_device
*dev
= ds
->priv
;
1446 case BR_STATE_DISABLED
:
1447 hw_state
= PORT_CTRL_DIS_STATE
;
1449 case BR_STATE_LISTENING
:
1450 hw_state
= PORT_CTRL_LISTEN_STATE
;
1452 case BR_STATE_LEARNING
:
1453 hw_state
= PORT_CTRL_LEARN_STATE
;
1455 case BR_STATE_FORWARDING
:
1456 hw_state
= PORT_CTRL_FWD_STATE
;
1458 case BR_STATE_BLOCKING
:
1459 hw_state
= PORT_CTRL_BLOCK_STATE
;
1462 dev_err(ds
->dev
, "invalid STP state: %d\n", state
);
1466 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), ®
);
1467 reg
&= ~PORT_CTRL_STP_STATE_MASK
;
1469 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(port
), reg
);
1471 EXPORT_SYMBOL(b53_br_set_stp_state
);
1473 void b53_br_fast_age(struct dsa_switch
*ds
, int port
)
1475 struct b53_device
*dev
= ds
->priv
;
1477 if (b53_fast_age_port(dev
, port
))
1478 dev_err(ds
->dev
, "fast ageing failed\n");
1480 EXPORT_SYMBOL(b53_br_fast_age
);
1482 static bool b53_can_enable_brcm_tags(struct dsa_switch
*ds
, int port
)
1484 /* Broadcom switches will accept enabling Broadcom tags on the
1485 * following ports: 5, 7 and 8, any other port is not supported
1488 case B53_CPU_PORT_25
:
1494 dev_warn(ds
->dev
, "Port %d is not Broadcom tag capable\n", port
);
1498 static enum dsa_tag_protocol
b53_get_tag_protocol(struct dsa_switch
*ds
,
1501 struct b53_device
*dev
= ds
->priv
;
1503 /* Older models support a different tag format that we do not
1504 * support in net/dsa/tag_brcm.c yet.
1506 if (is5325(dev
) || is5365(dev
) || !b53_can_enable_brcm_tags(ds
, port
))
1507 return DSA_TAG_PROTO_NONE
;
1509 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1510 * which requires us to use the prepended Broadcom tag type
1512 if (dev
->chip_id
== BCM58XX_DEVICE_ID
&& port
== B53_CPU_PORT
)
1513 return DSA_TAG_PROTO_BRCM_PREPEND
;
1515 return DSA_TAG_PROTO_BRCM
;
1518 int b53_mirror_add(struct dsa_switch
*ds
, int port
,
1519 struct dsa_mall_mirror_tc_entry
*mirror
, bool ingress
)
1521 struct b53_device
*dev
= ds
->priv
;
1525 loc
= B53_IG_MIR_CTL
;
1527 loc
= B53_EG_MIR_CTL
;
1529 b53_read16(dev
, B53_MGMT_PAGE
, loc
, ®
);
1530 reg
&= ~MIRROR_MASK
;
1532 b53_write16(dev
, B53_MGMT_PAGE
, loc
, reg
);
1534 b53_read16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, ®
);
1535 reg
&= ~CAP_PORT_MASK
;
1536 reg
|= mirror
->to_local_port
;
1538 b53_write16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, reg
);
1542 EXPORT_SYMBOL(b53_mirror_add
);
1544 void b53_mirror_del(struct dsa_switch
*ds
, int port
,
1545 struct dsa_mall_mirror_tc_entry
*mirror
)
1547 struct b53_device
*dev
= ds
->priv
;
1548 bool loc_disable
= false, other_loc_disable
= false;
1551 if (mirror
->ingress
)
1552 loc
= B53_IG_MIR_CTL
;
1554 loc
= B53_EG_MIR_CTL
;
1556 /* Update the desired ingress/egress register */
1557 b53_read16(dev
, B53_MGMT_PAGE
, loc
, ®
);
1559 if (!(reg
& MIRROR_MASK
))
1561 b53_write16(dev
, B53_MGMT_PAGE
, loc
, reg
);
1563 /* Now look at the other one to know if we can disable mirroring
1566 if (mirror
->ingress
)
1567 b53_read16(dev
, B53_MGMT_PAGE
, B53_EG_MIR_CTL
, ®
);
1569 b53_read16(dev
, B53_MGMT_PAGE
, B53_IG_MIR_CTL
, ®
);
1570 if (!(reg
& MIRROR_MASK
))
1571 other_loc_disable
= true;
1573 b53_read16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, ®
);
1574 /* Both no longer have ports, let's disable mirroring */
1575 if (loc_disable
&& other_loc_disable
) {
1577 reg
&= ~mirror
->to_local_port
;
1579 b53_write16(dev
, B53_MGMT_PAGE
, B53_MIR_CAP_CTL
, reg
);
1581 EXPORT_SYMBOL(b53_mirror_del
);
1583 void b53_eee_enable_set(struct dsa_switch
*ds
, int port
, bool enable
)
1585 struct b53_device
*dev
= ds
->priv
;
1588 b53_read16(dev
, B53_EEE_PAGE
, B53_EEE_EN_CTRL
, ®
);
1593 b53_write16(dev
, B53_EEE_PAGE
, B53_EEE_EN_CTRL
, reg
);
1595 EXPORT_SYMBOL(b53_eee_enable_set
);
1598 /* Returns 0 if EEE was not enabled, or 1 otherwise
1600 int b53_eee_init(struct dsa_switch
*ds
, int port
, struct phy_device
*phy
)
1604 ret
= phy_init_eee(phy
, 0);
1608 b53_eee_enable_set(ds
, port
, true);
1612 EXPORT_SYMBOL(b53_eee_init
);
1614 int b53_get_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1616 struct b53_device
*dev
= ds
->priv
;
1617 struct ethtool_eee
*p
= &dev
->ports
[port
].eee
;
1620 if (is5325(dev
) || is5365(dev
))
1623 b53_read16(dev
, B53_EEE_PAGE
, B53_EEE_LPI_INDICATE
, ®
);
1624 e
->eee_enabled
= p
->eee_enabled
;
1625 e
->eee_active
= !!(reg
& BIT(port
));
1629 EXPORT_SYMBOL(b53_get_mac_eee
);
1631 int b53_set_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1633 struct b53_device
*dev
= ds
->priv
;
1634 struct ethtool_eee
*p
= &dev
->ports
[port
].eee
;
1636 if (is5325(dev
) || is5365(dev
))
1639 p
->eee_enabled
= e
->eee_enabled
;
1640 b53_eee_enable_set(ds
, port
, e
->eee_enabled
);
1644 EXPORT_SYMBOL(b53_set_mac_eee
);
1646 static const struct dsa_switch_ops b53_switch_ops
= {
1647 .get_tag_protocol
= b53_get_tag_protocol
,
1649 .get_strings
= b53_get_strings
,
1650 .get_ethtool_stats
= b53_get_ethtool_stats
,
1651 .get_sset_count
= b53_get_sset_count
,
1652 .phy_read
= b53_phy_read16
,
1653 .phy_write
= b53_phy_write16
,
1654 .adjust_link
= b53_adjust_link
,
1655 .port_enable
= b53_enable_port
,
1656 .port_disable
= b53_disable_port
,
1657 .get_mac_eee
= b53_get_mac_eee
,
1658 .set_mac_eee
= b53_set_mac_eee
,
1659 .port_bridge_join
= b53_br_join
,
1660 .port_bridge_leave
= b53_br_leave
,
1661 .port_stp_state_set
= b53_br_set_stp_state
,
1662 .port_fast_age
= b53_br_fast_age
,
1663 .port_vlan_filtering
= b53_vlan_filtering
,
1664 .port_vlan_prepare
= b53_vlan_prepare
,
1665 .port_vlan_add
= b53_vlan_add
,
1666 .port_vlan_del
= b53_vlan_del
,
1667 .port_fdb_dump
= b53_fdb_dump
,
1668 .port_fdb_add
= b53_fdb_add
,
1669 .port_fdb_del
= b53_fdb_del
,
1670 .port_mirror_add
= b53_mirror_add
,
1671 .port_mirror_del
= b53_mirror_del
,
1674 struct b53_chip_data
{
1676 const char *dev_name
;
1687 #define B53_VTA_REGS \
1688 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1689 #define B53_VTA_REGS_9798 \
1690 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1691 #define B53_VTA_REGS_63XX \
1692 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1694 static const struct b53_chip_data b53_switch_chips
[] = {
1696 .chip_id
= BCM5325_DEVICE_ID
,
1697 .dev_name
= "BCM5325",
1699 .enabled_ports
= 0x1f,
1701 .cpu_port
= B53_CPU_PORT_25
,
1702 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1705 .chip_id
= BCM5365_DEVICE_ID
,
1706 .dev_name
= "BCM5365",
1708 .enabled_ports
= 0x1f,
1710 .cpu_port
= B53_CPU_PORT_25
,
1711 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1714 .chip_id
= BCM5395_DEVICE_ID
,
1715 .dev_name
= "BCM5395",
1717 .enabled_ports
= 0x1f,
1719 .cpu_port
= B53_CPU_PORT
,
1720 .vta_regs
= B53_VTA_REGS
,
1721 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1722 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1723 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1726 .chip_id
= BCM5397_DEVICE_ID
,
1727 .dev_name
= "BCM5397",
1729 .enabled_ports
= 0x1f,
1731 .cpu_port
= B53_CPU_PORT
,
1732 .vta_regs
= B53_VTA_REGS_9798
,
1733 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1734 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1735 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1738 .chip_id
= BCM5398_DEVICE_ID
,
1739 .dev_name
= "BCM5398",
1741 .enabled_ports
= 0x7f,
1743 .cpu_port
= B53_CPU_PORT
,
1744 .vta_regs
= B53_VTA_REGS_9798
,
1745 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1746 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1747 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1750 .chip_id
= BCM53115_DEVICE_ID
,
1751 .dev_name
= "BCM53115",
1753 .enabled_ports
= 0x1f,
1755 .vta_regs
= B53_VTA_REGS
,
1756 .cpu_port
= B53_CPU_PORT
,
1757 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1758 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1759 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1762 .chip_id
= BCM53125_DEVICE_ID
,
1763 .dev_name
= "BCM53125",
1765 .enabled_ports
= 0xff,
1767 .cpu_port
= B53_CPU_PORT
,
1768 .vta_regs
= B53_VTA_REGS
,
1769 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1770 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1771 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1774 .chip_id
= BCM53128_DEVICE_ID
,
1775 .dev_name
= "BCM53128",
1777 .enabled_ports
= 0x1ff,
1779 .cpu_port
= B53_CPU_PORT
,
1780 .vta_regs
= B53_VTA_REGS
,
1781 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1782 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1783 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1786 .chip_id
= BCM63XX_DEVICE_ID
,
1787 .dev_name
= "BCM63xx",
1789 .enabled_ports
= 0, /* pdata must provide them */
1791 .cpu_port
= B53_CPU_PORT
,
1792 .vta_regs
= B53_VTA_REGS_63XX
,
1793 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1794 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1795 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1798 .chip_id
= BCM53010_DEVICE_ID
,
1799 .dev_name
= "BCM53010",
1801 .enabled_ports
= 0x1f,
1803 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1804 .vta_regs
= B53_VTA_REGS
,
1805 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1806 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1807 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1810 .chip_id
= BCM53011_DEVICE_ID
,
1811 .dev_name
= "BCM53011",
1813 .enabled_ports
= 0x1bf,
1815 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1816 .vta_regs
= B53_VTA_REGS
,
1817 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1818 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1819 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1822 .chip_id
= BCM53012_DEVICE_ID
,
1823 .dev_name
= "BCM53012",
1825 .enabled_ports
= 0x1bf,
1827 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1828 .vta_regs
= B53_VTA_REGS
,
1829 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1830 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1831 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1834 .chip_id
= BCM53018_DEVICE_ID
,
1835 .dev_name
= "BCM53018",
1837 .enabled_ports
= 0x1f,
1839 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1840 .vta_regs
= B53_VTA_REGS
,
1841 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1842 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1843 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1846 .chip_id
= BCM53019_DEVICE_ID
,
1847 .dev_name
= "BCM53019",
1849 .enabled_ports
= 0x1f,
1851 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1852 .vta_regs
= B53_VTA_REGS
,
1853 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1854 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1855 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1858 .chip_id
= BCM58XX_DEVICE_ID
,
1859 .dev_name
= "BCM585xx/586xx/88312",
1861 .enabled_ports
= 0x1ff,
1863 .cpu_port
= B53_CPU_PORT
,
1864 .vta_regs
= B53_VTA_REGS
,
1865 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1866 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1867 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1870 .chip_id
= BCM7445_DEVICE_ID
,
1871 .dev_name
= "BCM7445",
1873 .enabled_ports
= 0x1ff,
1875 .cpu_port
= B53_CPU_PORT
,
1876 .vta_regs
= B53_VTA_REGS
,
1877 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1878 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1879 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1882 .chip_id
= BCM7278_DEVICE_ID
,
1883 .dev_name
= "BCM7278",
1885 .enabled_ports
= 0x1ff,
1887 .cpu_port
= B53_CPU_PORT
,
1888 .vta_regs
= B53_VTA_REGS
,
1889 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1890 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1891 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1895 static int b53_switch_init(struct b53_device
*dev
)
1900 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1901 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1903 if (chip
->chip_id
== dev
->chip_id
) {
1904 if (!dev
->enabled_ports
)
1905 dev
->enabled_ports
= chip
->enabled_ports
;
1906 dev
->name
= chip
->dev_name
;
1907 dev
->duplex_reg
= chip
->duplex_reg
;
1908 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1909 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1910 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1911 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1912 dev
->cpu_port
= chip
->cpu_port
;
1913 dev
->num_vlans
= chip
->vlans
;
1914 dev
->num_arl_entries
= chip
->arl_entries
;
1919 /* check which BCM5325x version we have */
1923 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1925 /* check reserved bits */
1931 /* BCM5325F - do not use port 4 */
1932 dev
->enabled_ports
&= ~BIT(4);
1935 /* On the BCM47XX SoCs this is the supported internal switch.*/
1936 #ifndef CONFIG_BCM47XX
1943 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1946 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1947 /* use second IMP port if GMII is enabled */
1948 if (strap_value
& SV_GMII_CTRL_115
)
1952 /* cpu port is always last */
1953 dev
->num_ports
= dev
->cpu_port
+ 1;
1954 dev
->enabled_ports
|= BIT(dev
->cpu_port
);
1956 dev
->ports
= devm_kzalloc(dev
->dev
,
1957 sizeof(struct b53_port
) * dev
->num_ports
,
1962 dev
->vlans
= devm_kzalloc(dev
->dev
,
1963 sizeof(struct b53_vlan
) * dev
->num_vlans
,
1968 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1969 if (dev
->reset_gpio
>= 0) {
1970 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
,
1971 GPIOF_OUT_INIT_HIGH
, "robo_reset");
1979 struct b53_device
*b53_switch_alloc(struct device
*base
,
1980 const struct b53_io_ops
*ops
,
1983 struct dsa_switch
*ds
;
1984 struct b53_device
*dev
;
1986 ds
= dsa_switch_alloc(base
, DSA_MAX_PORTS
);
1990 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
2000 ds
->ops
= &b53_switch_ops
;
2001 mutex_init(&dev
->reg_mutex
);
2002 mutex_init(&dev
->stats_mutex
);
2006 EXPORT_SYMBOL(b53_switch_alloc
);
2008 int b53_switch_detect(struct b53_device
*dev
)
2015 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
2021 /* BCM5325 and BCM5365 do not have this register so reads
2022 * return 0. But the read operation did succeed, so assume this
2025 * Next check if we can write to the 5325's VTA register; for
2026 * 5365 it is read only.
2028 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
2029 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
2032 dev
->chip_id
= BCM5325_DEVICE_ID
;
2034 dev
->chip_id
= BCM5365_DEVICE_ID
;
2036 case BCM5395_DEVICE_ID
:
2037 case BCM5397_DEVICE_ID
:
2038 case BCM5398_DEVICE_ID
:
2042 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
2047 case BCM53115_DEVICE_ID
:
2048 case BCM53125_DEVICE_ID
:
2049 case BCM53128_DEVICE_ID
:
2050 case BCM53010_DEVICE_ID
:
2051 case BCM53011_DEVICE_ID
:
2052 case BCM53012_DEVICE_ID
:
2053 case BCM53018_DEVICE_ID
:
2054 case BCM53019_DEVICE_ID
:
2055 dev
->chip_id
= id32
;
2058 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2064 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
2065 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
2068 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
2071 EXPORT_SYMBOL(b53_switch_detect
);
2073 int b53_switch_register(struct b53_device
*dev
)
2078 dev
->chip_id
= dev
->pdata
->chip_id
;
2079 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
2082 if (!dev
->chip_id
&& b53_switch_detect(dev
))
2085 ret
= b53_switch_init(dev
);
2089 pr_info("found switch: %s, rev %i\n", dev
->name
, dev
->core_rev
);
2091 return dsa_register_switch(dev
->ds
);
2093 EXPORT_SYMBOL(b53_switch_register
);
2095 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2096 MODULE_DESCRIPTION("B53 switch library");
2097 MODULE_LICENSE("Dual BSD/GPL");