2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
38 static enum dsa_tag_protocol
bcm_sf2_sw_get_tag_protocol(struct dsa_switch
*ds
,
41 return DSA_TAG_PROTO_BRCM
;
44 static void bcm_sf2_imp_setup(struct dsa_switch
*ds
, int port
)
46 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
50 if (priv
->type
== BCM7445_DEVICE_ID
)
51 offset
= CORE_STS_OVERRIDE_IMP
;
53 offset
= CORE_STS_OVERRIDE_IMP2
;
55 /* Enable the port memories */
56 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
57 reg
&= ~P_TXQ_PSM_VDD(port
);
58 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
60 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
61 reg
= core_readl(priv
, CORE_IMP_CTL
);
62 reg
|= (RX_BCST_EN
| RX_MCST_EN
| RX_UCST_EN
);
63 reg
&= ~(RX_DIS
| TX_DIS
);
64 core_writel(priv
, reg
, CORE_IMP_CTL
);
66 /* Enable forwarding */
67 core_writel(priv
, SW_FWDG_EN
, CORE_SWMODE
);
69 /* Enable IMP port in dumb mode */
70 reg
= core_readl(priv
, CORE_SWITCH_CTRL
);
71 reg
|= MII_DUMB_FWDG_EN
;
72 core_writel(priv
, reg
, CORE_SWITCH_CTRL
);
74 /* Configure Traffic Class to QoS mapping, allow each priority to map
75 * to a different queue number
77 reg
= core_readl(priv
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
78 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++)
79 reg
|= i
<< (PRT_TO_QID_SHIFT
* i
);
80 core_writel(priv
, reg
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
82 b53_brcm_hdr_setup(ds
, port
);
84 /* Force link status for IMP port */
85 reg
= core_readl(priv
, offset
);
86 reg
|= (MII_SW_OR
| LINK_STS
);
87 core_writel(priv
, reg
, offset
);
90 static void bcm_sf2_gphy_enable_set(struct dsa_switch
*ds
, bool enable
)
92 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
95 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
98 reg
&= ~(EXT_PWR_DOWN
| IDDQ_BIAS
| CK25_DIS
);
99 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
101 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
104 reg
|= EXT_PWR_DOWN
| IDDQ_BIAS
| PHY_RESET
;
105 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
109 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
111 /* Use PHY-driven LED signaling */
113 reg
= reg_readl(priv
, REG_LED_CNTRL(0));
114 reg
|= SPDLNK_SRC_SEL
;
115 reg_writel(priv
, reg
, REG_LED_CNTRL(0));
119 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv
*priv
,
129 /* Port 0 interrupts are located on the first bank */
130 intrl2_0_mask_clear(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
133 off
= P_IRQ_OFF(port
);
137 intrl2_1_mask_clear(priv
, P_IRQ_MASK(off
));
140 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv
*priv
,
150 /* Port 0 interrupts are located on the first bank */
151 intrl2_0_mask_set(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
152 intrl2_0_writel(priv
, P_IRQ_MASK(P0_IRQ_OFF
), INTRL2_CPU_CLEAR
);
155 off
= P_IRQ_OFF(port
);
159 intrl2_1_mask_set(priv
, P_IRQ_MASK(off
));
160 intrl2_1_writel(priv
, P_IRQ_MASK(off
), INTRL2_CPU_CLEAR
);
163 static int bcm_sf2_port_setup(struct dsa_switch
*ds
, int port
,
164 struct phy_device
*phy
)
166 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
170 /* Clear the memory power down */
171 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
172 reg
&= ~P_TXQ_PSM_VDD(port
);
173 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
175 /* Enable Broadcom tags for that port if requested */
176 if (priv
->brcm_tag_mask
& BIT(port
))
177 b53_brcm_hdr_setup(ds
, port
);
179 /* Configure Traffic Class to QoS mapping, allow each priority to map
180 * to a different queue number
182 reg
= core_readl(priv
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
183 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++)
184 reg
|= i
<< (PRT_TO_QID_SHIFT
* i
);
185 core_writel(priv
, reg
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
187 /* Re-enable the GPHY and re-apply workarounds */
188 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1) {
189 bcm_sf2_gphy_enable_set(ds
, true);
191 /* if phy_stop() has been called before, phy
192 * will be in halted state, and phy_start()
195 * the resume path does not configure back
196 * autoneg settings, and since we hard reset
197 * the phy manually here, we need to reset the
198 * state machine also.
200 phy
->state
= PHY_READY
;
205 /* Enable MoCA port interrupts to get notified */
206 if (port
== priv
->moca_port
)
207 bcm_sf2_port_intr_enable(priv
, port
);
209 /* Set per-queue pause threshold to 32 */
210 core_writel(priv
, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port
));
212 /* Set ACB threshold to 24 */
213 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++) {
214 reg
= acb_readl(priv
, ACB_QUEUE_CFG(port
*
215 SF2_NUM_EGRESS_QUEUES
+ i
));
216 reg
&= ~XOFF_THRESHOLD_MASK
;
218 acb_writel(priv
, reg
, ACB_QUEUE_CFG(port
*
219 SF2_NUM_EGRESS_QUEUES
+ i
));
222 return b53_enable_port(ds
, port
, phy
);
225 static void bcm_sf2_port_disable(struct dsa_switch
*ds
, int port
,
226 struct phy_device
*phy
)
228 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
231 if (priv
->wol_ports_mask
& (1 << port
))
234 if (port
== priv
->moca_port
)
235 bcm_sf2_port_intr_disable(priv
, port
);
237 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1)
238 bcm_sf2_gphy_enable_set(ds
, false);
240 if (dsa_is_cpu_port(ds
, port
))
243 off
= CORE_G_PCTL_PORT(port
);
245 b53_disable_port(ds
, port
, phy
);
247 /* Power down the port memory */
248 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
249 reg
|= P_TXQ_PSM_VDD(port
);
250 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
254 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv
*priv
, int op
, int addr
,
260 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
261 reg
|= MDIO_MASTER_SEL
;
262 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
264 /* Page << 8 | offset */
267 core_writel(priv
, addr
, reg
);
269 /* Page << 8 | offset */
270 reg
= 0x80 << 8 | regnum
<< 1;
274 ret
= core_readl(priv
, reg
);
276 core_writel(priv
, val
, reg
);
278 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
279 reg
&= ~MDIO_MASTER_SEL
;
280 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
285 static int bcm_sf2_sw_mdio_read(struct mii_bus
*bus
, int addr
, int regnum
)
287 struct bcm_sf2_priv
*priv
= bus
->priv
;
289 /* Intercept reads from Broadcom pseudo-PHY address, else, send
290 * them to our master MDIO bus controller
292 if (addr
== BRCM_PSEUDO_PHY_ADDR
&& priv
->indir_phy_mask
& BIT(addr
))
293 return bcm_sf2_sw_indir_rw(priv
, 1, addr
, regnum
, 0);
295 return mdiobus_read_nested(priv
->master_mii_bus
, addr
, regnum
);
298 static int bcm_sf2_sw_mdio_write(struct mii_bus
*bus
, int addr
, int regnum
,
301 struct bcm_sf2_priv
*priv
= bus
->priv
;
303 /* Intercept writes to the Broadcom pseudo-PHY address, else,
304 * send them to our master MDIO bus controller
306 if (addr
== BRCM_PSEUDO_PHY_ADDR
&& priv
->indir_phy_mask
& BIT(addr
))
307 bcm_sf2_sw_indir_rw(priv
, 0, addr
, regnum
, val
);
309 mdiobus_write_nested(priv
->master_mii_bus
, addr
, regnum
, val
);
314 static irqreturn_t
bcm_sf2_switch_0_isr(int irq
, void *dev_id
)
316 struct bcm_sf2_priv
*priv
= dev_id
;
318 priv
->irq0_stat
= intrl2_0_readl(priv
, INTRL2_CPU_STATUS
) &
320 intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
325 static irqreturn_t
bcm_sf2_switch_1_isr(int irq
, void *dev_id
)
327 struct bcm_sf2_priv
*priv
= dev_id
;
329 priv
->irq1_stat
= intrl2_1_readl(priv
, INTRL2_CPU_STATUS
) &
331 intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
333 if (priv
->irq1_stat
& P_LINK_UP_IRQ(P7_IRQ_OFF
))
334 priv
->port_sts
[7].link
= 1;
335 if (priv
->irq1_stat
& P_LINK_DOWN_IRQ(P7_IRQ_OFF
))
336 priv
->port_sts
[7].link
= 0;
341 static int bcm_sf2_sw_rst(struct bcm_sf2_priv
*priv
)
343 unsigned int timeout
= 1000;
346 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
347 reg
|= SOFTWARE_RESET
| EN_CHIP_RST
| EN_SW_RESET
;
348 core_writel(priv
, reg
, CORE_WATCHDOG_CTRL
);
351 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
352 if (!(reg
& SOFTWARE_RESET
))
355 usleep_range(1000, 2000);
356 } while (timeout
-- > 0);
364 static void bcm_sf2_intr_disable(struct bcm_sf2_priv
*priv
)
366 intrl2_0_mask_set(priv
, 0xffffffff);
367 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
368 intrl2_1_mask_set(priv
, 0xffffffff);
369 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
372 static void bcm_sf2_identify_ports(struct bcm_sf2_priv
*priv
,
373 struct device_node
*dn
)
375 struct device_node
*port
;
377 unsigned int port_num
;
379 priv
->moca_port
= -1;
381 for_each_available_child_of_node(dn
, port
) {
382 if (of_property_read_u32(port
, "reg", &port_num
))
385 /* Internal PHYs get assigned a specific 'phy-mode' property
386 * value: "internal" to help flag them before MDIO probing
387 * has completed, since they might be turned off at that
390 mode
= of_get_phy_mode(port
);
394 if (mode
== PHY_INTERFACE_MODE_INTERNAL
)
395 priv
->int_phy_mask
|= 1 << port_num
;
397 if (mode
== PHY_INTERFACE_MODE_MOCA
)
398 priv
->moca_port
= port_num
;
400 if (of_property_read_bool(port
, "brcm,use-bcm-hdr"))
401 priv
->brcm_tag_mask
|= 1 << port_num
;
405 static int bcm_sf2_mdio_register(struct dsa_switch
*ds
)
407 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
408 struct device_node
*dn
;
412 /* Find our integrated MDIO bus node */
413 dn
= of_find_compatible_node(NULL
, NULL
, "brcm,unimac-mdio");
414 priv
->master_mii_bus
= of_mdio_find_bus(dn
);
415 if (!priv
->master_mii_bus
)
416 return -EPROBE_DEFER
;
418 get_device(&priv
->master_mii_bus
->dev
);
419 priv
->master_mii_dn
= dn
;
421 priv
->slave_mii_bus
= devm_mdiobus_alloc(ds
->dev
);
422 if (!priv
->slave_mii_bus
)
425 priv
->slave_mii_bus
->priv
= priv
;
426 priv
->slave_mii_bus
->name
= "sf2 slave mii";
427 priv
->slave_mii_bus
->read
= bcm_sf2_sw_mdio_read
;
428 priv
->slave_mii_bus
->write
= bcm_sf2_sw_mdio_write
;
429 snprintf(priv
->slave_mii_bus
->id
, MII_BUS_ID_SIZE
, "sf2-%d",
431 priv
->slave_mii_bus
->dev
.of_node
= dn
;
433 /* Include the pseudo-PHY address to divert reads towards our
434 * workaround. This is only required for 7445D0, since 7445E0
435 * disconnects the internal switch pseudo-PHY such that we can use the
436 * regular SWITCH_MDIO master controller instead.
438 * Here we flag the pseudo PHY as needing special treatment and would
439 * otherwise make all other PHY read/writes go to the master MDIO bus
440 * controller that comes with this switch backed by the "mdio-unimac"
443 if (of_machine_is_compatible("brcm,bcm7445d0"))
444 priv
->indir_phy_mask
|= (1 << BRCM_PSEUDO_PHY_ADDR
);
446 priv
->indir_phy_mask
= 0;
448 ds
->phys_mii_mask
= priv
->indir_phy_mask
;
449 ds
->slave_mii_bus
= priv
->slave_mii_bus
;
450 priv
->slave_mii_bus
->parent
= ds
->dev
->parent
;
451 priv
->slave_mii_bus
->phy_mask
= ~priv
->indir_phy_mask
;
454 err
= of_mdiobus_register(priv
->slave_mii_bus
, dn
);
456 err
= mdiobus_register(priv
->slave_mii_bus
);
464 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv
*priv
)
466 mdiobus_unregister(priv
->slave_mii_bus
);
467 if (priv
->master_mii_dn
)
468 of_node_put(priv
->master_mii_dn
);
471 static u32
bcm_sf2_sw_get_phy_flags(struct dsa_switch
*ds
, int port
)
473 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
475 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
476 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
477 * the REG_PHY_REVISION register layout is.
480 return priv
->hw_params
.gphy_rev
;
483 static void bcm_sf2_sw_adjust_link(struct dsa_switch
*ds
, int port
,
484 struct phy_device
*phydev
)
486 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
487 struct ethtool_eee
*p
= &priv
->dev
->ports
[port
].eee
;
488 u32 id_mode_dis
= 0, port_mode
;
489 const char *str
= NULL
;
492 if (priv
->type
== BCM7445_DEVICE_ID
)
493 offset
= CORE_STS_OVERRIDE_GMIIP_PORT(port
);
495 offset
= CORE_STS_OVERRIDE_GMIIP2_PORT(port
);
497 switch (phydev
->interface
) {
498 case PHY_INTERFACE_MODE_RGMII
:
499 str
= "RGMII (no delay)";
501 case PHY_INTERFACE_MODE_RGMII_TXID
:
503 str
= "RGMII (TX delay)";
504 port_mode
= EXT_GPHY
;
506 case PHY_INTERFACE_MODE_MII
:
508 port_mode
= EXT_EPHY
;
510 case PHY_INTERFACE_MODE_REVMII
:
512 port_mode
= EXT_REVMII
;
515 /* All other PHYs: internal and MoCA */
519 /* If the link is down, just disable the interface to conserve power */
521 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
522 reg
&= ~RGMII_MODE_EN
;
523 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
527 /* Clear id_mode_dis bit, and the existing port mode, but
528 * make sure we enable the RGMII block for data to pass
530 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
532 reg
&= ~(PORT_MODE_MASK
<< PORT_MODE_SHIFT
);
533 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
535 reg
|= port_mode
| RGMII_MODE_EN
;
540 if (phydev
->asym_pause
)
545 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
547 pr_info("Port %d configured for %s\n", port
, str
);
550 /* Force link settings detected from the PHY */
552 switch (phydev
->speed
) {
554 reg
|= SPDSTS_1000
<< SPEED_SHIFT
;
557 reg
|= SPDSTS_100
<< SPEED_SHIFT
;
563 if (phydev
->duplex
== DUPLEX_FULL
)
566 core_writel(priv
, reg
, offset
);
568 if (!phydev
->is_pseudo_fixed_link
)
569 p
->eee_enabled
= b53_eee_init(ds
, port
, phydev
);
572 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch
*ds
, int port
,
573 struct fixed_phy_status
*status
)
575 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
576 u32 duplex
, pause
, offset
;
579 if (priv
->type
== BCM7445_DEVICE_ID
)
580 offset
= CORE_STS_OVERRIDE_GMIIP_PORT(port
);
582 offset
= CORE_STS_OVERRIDE_GMIIP2_PORT(port
);
584 duplex
= core_readl(priv
, CORE_DUPSTS
);
585 pause
= core_readl(priv
, CORE_PAUSESTS
);
589 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
590 * which means that we need to force the link at the port override
591 * level to get the data to flow. We do use what the interrupt handler
592 * did determine before.
594 * For the other ports, we just force the link status, since this is
595 * a fixed PHY device.
597 if (port
== priv
->moca_port
) {
598 status
->link
= priv
->port_sts
[port
].link
;
599 /* For MoCA interfaces, also force a link down notification
600 * since some version of the user-space daemon (mocad) use
601 * cmd->autoneg to force the link, which messes up the PHY
602 * state machine and make it go in PHY_FORCING state instead.
605 netif_carrier_off(ds
->ports
[port
].slave
);
609 status
->duplex
= !!(duplex
& (1 << port
));
612 reg
= core_readl(priv
, offset
);
618 core_writel(priv
, reg
, offset
);
620 if ((pause
& (1 << port
)) &&
621 (pause
& (1 << (port
+ PAUSESTS_TX_PAUSE_SHIFT
)))) {
622 status
->asym_pause
= 1;
626 if (pause
& (1 << port
))
630 static void bcm_sf2_enable_acb(struct dsa_switch
*ds
)
632 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
635 /* Enable ACB globally */
636 reg
= acb_readl(priv
, ACB_CONTROL
);
637 reg
|= (ACB_FLUSH_MASK
<< ACB_FLUSH_SHIFT
);
638 acb_writel(priv
, reg
, ACB_CONTROL
);
639 reg
&= ~(ACB_FLUSH_MASK
<< ACB_FLUSH_SHIFT
);
640 reg
|= ACB_EN
| ACB_ALGORITHM
;
641 acb_writel(priv
, reg
, ACB_CONTROL
);
644 static int bcm_sf2_sw_suspend(struct dsa_switch
*ds
)
646 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
649 bcm_sf2_intr_disable(priv
);
651 /* Disable all ports physically present including the IMP
652 * port, the other ones have already been disabled during
655 for (port
= 0; port
< DSA_MAX_PORTS
; port
++) {
656 if (dsa_is_user_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
657 bcm_sf2_port_disable(ds
, port
, NULL
);
663 static int bcm_sf2_sw_resume(struct dsa_switch
*ds
)
665 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
669 ret
= bcm_sf2_sw_rst(priv
);
671 pr_err("%s: failed to software reset switch\n", __func__
);
675 if (priv
->hw_params
.num_gphy
== 1)
676 bcm_sf2_gphy_enable_set(ds
, true);
678 for (port
= 0; port
< DSA_MAX_PORTS
; port
++) {
679 if (dsa_is_user_port(ds
, port
))
680 bcm_sf2_port_setup(ds
, port
, NULL
);
681 else if (dsa_is_cpu_port(ds
, port
))
682 bcm_sf2_imp_setup(ds
, port
);
685 bcm_sf2_enable_acb(ds
);
690 static void bcm_sf2_sw_get_wol(struct dsa_switch
*ds
, int port
,
691 struct ethtool_wolinfo
*wol
)
693 struct net_device
*p
= ds
->ports
[port
].cpu_dp
->master
;
694 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
695 struct ethtool_wolinfo pwol
;
697 /* Get the parent device WoL settings */
698 p
->ethtool_ops
->get_wol(p
, &pwol
);
700 /* Advertise the parent device supported settings */
701 wol
->supported
= pwol
.supported
;
702 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
704 if (pwol
.wolopts
& WAKE_MAGICSECURE
)
705 memcpy(&wol
->sopass
, pwol
.sopass
, sizeof(wol
->sopass
));
707 if (priv
->wol_ports_mask
& (1 << port
))
708 wol
->wolopts
= pwol
.wolopts
;
713 static int bcm_sf2_sw_set_wol(struct dsa_switch
*ds
, int port
,
714 struct ethtool_wolinfo
*wol
)
716 struct net_device
*p
= ds
->ports
[port
].cpu_dp
->master
;
717 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
718 s8 cpu_port
= ds
->ports
[port
].cpu_dp
->index
;
719 struct ethtool_wolinfo pwol
;
721 p
->ethtool_ops
->get_wol(p
, &pwol
);
722 if (wol
->wolopts
& ~pwol
.supported
)
726 priv
->wol_ports_mask
|= (1 << port
);
728 priv
->wol_ports_mask
&= ~(1 << port
);
730 /* If we have at least one port enabled, make sure the CPU port
731 * is also enabled. If the CPU port is the last one enabled, we disable
732 * it since this configuration does not make sense.
734 if (priv
->wol_ports_mask
&& priv
->wol_ports_mask
!= (1 << cpu_port
))
735 priv
->wol_ports_mask
|= (1 << cpu_port
);
737 priv
->wol_ports_mask
&= ~(1 << cpu_port
);
739 return p
->ethtool_ops
->set_wol(p
, wol
);
742 static int bcm_sf2_sw_setup(struct dsa_switch
*ds
)
744 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
747 /* Enable all valid ports and disable those unused */
748 for (port
= 0; port
< priv
->hw_params
.num_ports
; port
++) {
749 /* IMP port receives special treatment */
750 if (dsa_is_user_port(ds
, port
))
751 bcm_sf2_port_setup(ds
, port
, NULL
);
752 else if (dsa_is_cpu_port(ds
, port
))
753 bcm_sf2_imp_setup(ds
, port
);
755 bcm_sf2_port_disable(ds
, port
, NULL
);
758 b53_configure_vlan(ds
);
759 bcm_sf2_enable_acb(ds
);
764 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
765 * register basis so we need to translate that into an address that the
766 * bus-glue understands.
768 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
770 static int bcm_sf2_core_read8(struct b53_device
*dev
, u8 page
, u8 reg
,
773 struct bcm_sf2_priv
*priv
= dev
->priv
;
775 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
780 static int bcm_sf2_core_read16(struct b53_device
*dev
, u8 page
, u8 reg
,
783 struct bcm_sf2_priv
*priv
= dev
->priv
;
785 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
790 static int bcm_sf2_core_read32(struct b53_device
*dev
, u8 page
, u8 reg
,
793 struct bcm_sf2_priv
*priv
= dev
->priv
;
795 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
800 static int bcm_sf2_core_read64(struct b53_device
*dev
, u8 page
, u8 reg
,
803 struct bcm_sf2_priv
*priv
= dev
->priv
;
805 *val
= core_readq(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
810 static int bcm_sf2_core_write8(struct b53_device
*dev
, u8 page
, u8 reg
,
813 struct bcm_sf2_priv
*priv
= dev
->priv
;
815 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
820 static int bcm_sf2_core_write16(struct b53_device
*dev
, u8 page
, u8 reg
,
823 struct bcm_sf2_priv
*priv
= dev
->priv
;
825 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
830 static int bcm_sf2_core_write32(struct b53_device
*dev
, u8 page
, u8 reg
,
833 struct bcm_sf2_priv
*priv
= dev
->priv
;
835 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
840 static int bcm_sf2_core_write64(struct b53_device
*dev
, u8 page
, u8 reg
,
843 struct bcm_sf2_priv
*priv
= dev
->priv
;
845 core_writeq(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
850 static const struct b53_io_ops bcm_sf2_io_ops
= {
851 .read8
= bcm_sf2_core_read8
,
852 .read16
= bcm_sf2_core_read16
,
853 .read32
= bcm_sf2_core_read32
,
854 .read48
= bcm_sf2_core_read64
,
855 .read64
= bcm_sf2_core_read64
,
856 .write8
= bcm_sf2_core_write8
,
857 .write16
= bcm_sf2_core_write16
,
858 .write32
= bcm_sf2_core_write32
,
859 .write48
= bcm_sf2_core_write64
,
860 .write64
= bcm_sf2_core_write64
,
863 static const struct dsa_switch_ops bcm_sf2_ops
= {
864 .get_tag_protocol
= bcm_sf2_sw_get_tag_protocol
,
865 .setup
= bcm_sf2_sw_setup
,
866 .get_strings
= b53_get_strings
,
867 .get_ethtool_stats
= b53_get_ethtool_stats
,
868 .get_sset_count
= b53_get_sset_count
,
869 .get_phy_flags
= bcm_sf2_sw_get_phy_flags
,
870 .adjust_link
= bcm_sf2_sw_adjust_link
,
871 .fixed_link_update
= bcm_sf2_sw_fixed_link_update
,
872 .suspend
= bcm_sf2_sw_suspend
,
873 .resume
= bcm_sf2_sw_resume
,
874 .get_wol
= bcm_sf2_sw_get_wol
,
875 .set_wol
= bcm_sf2_sw_set_wol
,
876 .port_enable
= bcm_sf2_port_setup
,
877 .port_disable
= bcm_sf2_port_disable
,
878 .get_mac_eee
= b53_get_mac_eee
,
879 .set_mac_eee
= b53_set_mac_eee
,
880 .port_bridge_join
= b53_br_join
,
881 .port_bridge_leave
= b53_br_leave
,
882 .port_stp_state_set
= b53_br_set_stp_state
,
883 .port_fast_age
= b53_br_fast_age
,
884 .port_vlan_filtering
= b53_vlan_filtering
,
885 .port_vlan_prepare
= b53_vlan_prepare
,
886 .port_vlan_add
= b53_vlan_add
,
887 .port_vlan_del
= b53_vlan_del
,
888 .port_fdb_dump
= b53_fdb_dump
,
889 .port_fdb_add
= b53_fdb_add
,
890 .port_fdb_del
= b53_fdb_del
,
891 .get_rxnfc
= bcm_sf2_get_rxnfc
,
892 .set_rxnfc
= bcm_sf2_set_rxnfc
,
893 .port_mirror_add
= b53_mirror_add
,
894 .port_mirror_del
= b53_mirror_del
,
897 struct bcm_sf2_of_data
{
899 const u16
*reg_offsets
;
900 unsigned int core_reg_align
;
901 unsigned int num_cfp_rules
;
904 /* Register offsets for the SWITCH_REG_* block */
905 static const u16 bcm_sf2_7445_reg_offsets
[] = {
906 [REG_SWITCH_CNTRL
] = 0x00,
907 [REG_SWITCH_STATUS
] = 0x04,
908 [REG_DIR_DATA_WRITE
] = 0x08,
909 [REG_DIR_DATA_READ
] = 0x0C,
910 [REG_SWITCH_REVISION
] = 0x18,
911 [REG_PHY_REVISION
] = 0x1C,
912 [REG_SPHY_CNTRL
] = 0x2C,
913 [REG_RGMII_0_CNTRL
] = 0x34,
914 [REG_RGMII_1_CNTRL
] = 0x40,
915 [REG_RGMII_2_CNTRL
] = 0x4c,
916 [REG_LED_0_CNTRL
] = 0x90,
917 [REG_LED_1_CNTRL
] = 0x94,
918 [REG_LED_2_CNTRL
] = 0x98,
921 static const struct bcm_sf2_of_data bcm_sf2_7445_data
= {
922 .type
= BCM7445_DEVICE_ID
,
924 .reg_offsets
= bcm_sf2_7445_reg_offsets
,
925 .num_cfp_rules
= 256,
928 static const u16 bcm_sf2_7278_reg_offsets
[] = {
929 [REG_SWITCH_CNTRL
] = 0x00,
930 [REG_SWITCH_STATUS
] = 0x04,
931 [REG_DIR_DATA_WRITE
] = 0x08,
932 [REG_DIR_DATA_READ
] = 0x0c,
933 [REG_SWITCH_REVISION
] = 0x10,
934 [REG_PHY_REVISION
] = 0x14,
935 [REG_SPHY_CNTRL
] = 0x24,
936 [REG_RGMII_0_CNTRL
] = 0xe0,
937 [REG_RGMII_1_CNTRL
] = 0xec,
938 [REG_RGMII_2_CNTRL
] = 0xf8,
939 [REG_LED_0_CNTRL
] = 0x40,
940 [REG_LED_1_CNTRL
] = 0x4c,
941 [REG_LED_2_CNTRL
] = 0x58,
944 static const struct bcm_sf2_of_data bcm_sf2_7278_data
= {
945 .type
= BCM7278_DEVICE_ID
,
947 .reg_offsets
= bcm_sf2_7278_reg_offsets
,
948 .num_cfp_rules
= 128,
951 static const struct of_device_id bcm_sf2_of_match
[] = {
952 { .compatible
= "brcm,bcm7445-switch-v4.0",
953 .data
= &bcm_sf2_7445_data
955 { .compatible
= "brcm,bcm7278-switch-v4.0",
956 .data
= &bcm_sf2_7278_data
960 MODULE_DEVICE_TABLE(of
, bcm_sf2_of_match
);
962 static int bcm_sf2_sw_probe(struct platform_device
*pdev
)
964 const char *reg_names
[BCM_SF2_REGS_NUM
] = BCM_SF2_REGS_NAME
;
965 struct device_node
*dn
= pdev
->dev
.of_node
;
966 const struct of_device_id
*of_id
= NULL
;
967 const struct bcm_sf2_of_data
*data
;
968 struct b53_platform_data
*pdata
;
969 struct dsa_switch_ops
*ops
;
970 struct bcm_sf2_priv
*priv
;
971 struct b53_device
*dev
;
972 struct dsa_switch
*ds
;
979 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
983 ops
= devm_kzalloc(&pdev
->dev
, sizeof(*ops
), GFP_KERNEL
);
987 dev
= b53_switch_alloc(&pdev
->dev
, &bcm_sf2_io_ops
, priv
);
991 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
995 of_id
= of_match_node(bcm_sf2_of_match
, dn
);
996 if (!of_id
|| !of_id
->data
)
1001 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1002 priv
->type
= data
->type
;
1003 priv
->reg_offsets
= data
->reg_offsets
;
1004 priv
->core_reg_align
= data
->core_reg_align
;
1005 priv
->num_cfp_rules
= data
->num_cfp_rules
;
1007 /* Auto-detection using standard registers will not work, so
1008 * provide an indication of what kind of device we are for
1009 * b53_common to work with
1011 pdata
->chip_id
= priv
->type
;
1016 ds
->ops
= &bcm_sf2_ops
;
1018 /* Advertise the 8 egress queues */
1019 ds
->num_tx_queues
= SF2_NUM_EGRESS_QUEUES
;
1021 dev_set_drvdata(&pdev
->dev
, priv
);
1023 spin_lock_init(&priv
->indir_lock
);
1024 mutex_init(&priv
->stats_mutex
);
1025 mutex_init(&priv
->cfp
.lock
);
1027 /* CFP rule #0 cannot be used for specific classifications, flag it as
1030 set_bit(0, priv
->cfp
.used
);
1031 set_bit(0, priv
->cfp
.unique
);
1033 bcm_sf2_identify_ports(priv
, dn
->child
);
1035 priv
->irq0
= irq_of_parse_and_map(dn
, 0);
1036 priv
->irq1
= irq_of_parse_and_map(dn
, 1);
1039 for (i
= 0; i
< BCM_SF2_REGS_NUM
; i
++) {
1040 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
1041 *base
= devm_ioremap_resource(&pdev
->dev
, r
);
1042 if (IS_ERR(*base
)) {
1043 pr_err("unable to find register: %s\n", reg_names
[i
]);
1044 return PTR_ERR(*base
);
1049 ret
= bcm_sf2_sw_rst(priv
);
1051 pr_err("unable to software reset switch: %d\n", ret
);
1055 ret
= bcm_sf2_mdio_register(ds
);
1057 pr_err("failed to register MDIO bus\n");
1061 ret
= bcm_sf2_cfp_rst(priv
);
1063 pr_err("failed to reset CFP\n");
1067 /* Disable all interrupts and request them */
1068 bcm_sf2_intr_disable(priv
);
1070 ret
= devm_request_irq(&pdev
->dev
, priv
->irq0
, bcm_sf2_switch_0_isr
, 0,
1073 pr_err("failed to request switch_0 IRQ\n");
1077 ret
= devm_request_irq(&pdev
->dev
, priv
->irq1
, bcm_sf2_switch_1_isr
, 0,
1080 pr_err("failed to request switch_1 IRQ\n");
1084 /* Reset the MIB counters */
1085 reg
= core_readl(priv
, CORE_GMNCFGCFG
);
1087 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
1088 reg
&= ~RST_MIB_CNT
;
1089 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
1091 /* Get the maximum number of ports for this switch */
1092 priv
->hw_params
.num_ports
= core_readl(priv
, CORE_IMP0_PRT_ID
) + 1;
1093 if (priv
->hw_params
.num_ports
> DSA_MAX_PORTS
)
1094 priv
->hw_params
.num_ports
= DSA_MAX_PORTS
;
1096 /* Assume a single GPHY setup if we can't read that property */
1097 if (of_property_read_u32(dn
, "brcm,num-gphy",
1098 &priv
->hw_params
.num_gphy
))
1099 priv
->hw_params
.num_gphy
= 1;
1101 rev
= reg_readl(priv
, REG_SWITCH_REVISION
);
1102 priv
->hw_params
.top_rev
= (rev
>> SWITCH_TOP_REV_SHIFT
) &
1103 SWITCH_TOP_REV_MASK
;
1104 priv
->hw_params
.core_rev
= (rev
& SF2_REV_MASK
);
1106 rev
= reg_readl(priv
, REG_PHY_REVISION
);
1107 priv
->hw_params
.gphy_rev
= rev
& PHY_REVISION_MASK
;
1109 ret
= b53_switch_register(dev
);
1113 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1114 priv
->hw_params
.top_rev
>> 8, priv
->hw_params
.top_rev
& 0xff,
1115 priv
->hw_params
.core_rev
>> 8, priv
->hw_params
.core_rev
& 0xff,
1116 priv
->core
, priv
->irq0
, priv
->irq1
);
1121 bcm_sf2_mdio_unregister(priv
);
1125 static int bcm_sf2_sw_remove(struct platform_device
*pdev
)
1127 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1129 /* Disable all ports and interrupts */
1130 priv
->wol_ports_mask
= 0;
1131 bcm_sf2_sw_suspend(priv
->dev
->ds
);
1132 dsa_unregister_switch(priv
->dev
->ds
);
1133 bcm_sf2_mdio_unregister(priv
);
1138 static void bcm_sf2_sw_shutdown(struct platform_device
*pdev
)
1140 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1142 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1143 * successful MDIO bus scan to occur. If we did turn off the GPHY
1144 * before (e.g: port_disable), this will also power it back on.
1146 * Do not rely on kexec_in_progress, just power the PHY on.
1148 if (priv
->hw_params
.num_gphy
== 1)
1149 bcm_sf2_gphy_enable_set(priv
->dev
->ds
, true);
1152 #ifdef CONFIG_PM_SLEEP
1153 static int bcm_sf2_suspend(struct device
*dev
)
1155 struct platform_device
*pdev
= to_platform_device(dev
);
1156 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1158 return dsa_switch_suspend(priv
->dev
->ds
);
1161 static int bcm_sf2_resume(struct device
*dev
)
1163 struct platform_device
*pdev
= to_platform_device(dev
);
1164 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1166 return dsa_switch_resume(priv
->dev
->ds
);
1168 #endif /* CONFIG_PM_SLEEP */
1170 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops
,
1171 bcm_sf2_suspend
, bcm_sf2_resume
);
1174 static struct platform_driver bcm_sf2_driver
= {
1175 .probe
= bcm_sf2_sw_probe
,
1176 .remove
= bcm_sf2_sw_remove
,
1177 .shutdown
= bcm_sf2_sw_shutdown
,
1180 .of_match_table
= bcm_sf2_of_match
,
1181 .pm
= &bcm_sf2_pm_ops
,
1184 module_platform_driver(bcm_sf2_driver
);
1186 MODULE_AUTHOR("Broadcom Corporation");
1187 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1188 MODULE_LICENSE("GPL");
1189 MODULE_ALIAS("platform:brcm-sf2");