1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom Starfighter 2 DSA switch driver
5 * Copyright (C) 2014, Broadcom Corporation
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/of_net.h>
21 #include <linux/of_mdio.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_bridge.h>
25 #include <linux/brcmphy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/platform_data/b53.h>
30 #include "bcm_sf2_regs.h"
31 #include "b53/b53_priv.h"
32 #include "b53/b53_regs.h"
34 static void bcm_sf2_imp_setup(struct dsa_switch
*ds
, int port
)
36 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
40 /* Enable the port memories */
41 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
42 reg
&= ~P_TXQ_PSM_VDD(port
);
43 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
45 /* Enable forwarding */
46 core_writel(priv
, SW_FWDG_EN
, CORE_SWMODE
);
48 /* Enable IMP port in dumb mode */
49 reg
= core_readl(priv
, CORE_SWITCH_CTRL
);
50 reg
|= MII_DUMB_FWDG_EN
;
51 core_writel(priv
, reg
, CORE_SWITCH_CTRL
);
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
56 reg
= core_readl(priv
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
57 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++)
58 reg
|= i
<< (PRT_TO_QID_SHIFT
* i
);
59 core_writel(priv
, reg
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
61 b53_brcm_hdr_setup(ds
, port
);
64 if (priv
->type
== BCM7445_DEVICE_ID
)
65 offset
= CORE_STS_OVERRIDE_IMP
;
67 offset
= CORE_STS_OVERRIDE_IMP2
;
69 /* Force link status for IMP port */
70 reg
= core_readl(priv
, offset
);
71 reg
|= (MII_SW_OR
| LINK_STS
);
72 reg
&= ~GMII_SPEED_UP_2G
;
73 core_writel(priv
, reg
, offset
);
75 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
76 reg
= core_readl(priv
, CORE_IMP_CTL
);
77 reg
|= (RX_BCST_EN
| RX_MCST_EN
| RX_UCST_EN
);
78 reg
&= ~(RX_DIS
| TX_DIS
);
79 core_writel(priv
, reg
, CORE_IMP_CTL
);
81 reg
= core_readl(priv
, CORE_G_PCTL_PORT(port
));
82 reg
&= ~(RX_DIS
| TX_DIS
);
83 core_writel(priv
, reg
, CORE_G_PCTL_PORT(port
));
87 static void bcm_sf2_gphy_enable_set(struct dsa_switch
*ds
, bool enable
)
89 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
92 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
95 reg
&= ~(EXT_PWR_DOWN
| IDDQ_BIAS
| IDDQ_GLOBAL_PWR
| CK25_DIS
);
96 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
98 reg
= reg_readl(priv
, REG_SPHY_CNTRL
);
101 reg
|= EXT_PWR_DOWN
| IDDQ_BIAS
| PHY_RESET
;
102 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
106 reg_writel(priv
, reg
, REG_SPHY_CNTRL
);
108 /* Use PHY-driven LED signaling */
110 reg
= reg_readl(priv
, REG_LED_CNTRL(0));
111 reg
|= SPDLNK_SRC_SEL
;
112 reg_writel(priv
, reg
, REG_LED_CNTRL(0));
116 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv
*priv
,
126 /* Port 0 interrupts are located on the first bank */
127 intrl2_0_mask_clear(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
130 off
= P_IRQ_OFF(port
);
134 intrl2_1_mask_clear(priv
, P_IRQ_MASK(off
));
137 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv
*priv
,
147 /* Port 0 interrupts are located on the first bank */
148 intrl2_0_mask_set(priv
, P_IRQ_MASK(P0_IRQ_OFF
));
149 intrl2_0_writel(priv
, P_IRQ_MASK(P0_IRQ_OFF
), INTRL2_CPU_CLEAR
);
152 off
= P_IRQ_OFF(port
);
156 intrl2_1_mask_set(priv
, P_IRQ_MASK(off
));
157 intrl2_1_writel(priv
, P_IRQ_MASK(off
), INTRL2_CPU_CLEAR
);
160 static int bcm_sf2_port_setup(struct dsa_switch
*ds
, int port
,
161 struct phy_device
*phy
)
163 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
167 if (!dsa_is_user_port(ds
, port
))
170 /* Clear the memory power down */
171 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
172 reg
&= ~P_TXQ_PSM_VDD(port
);
173 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
175 /* Enable learning */
176 reg
= core_readl(priv
, CORE_DIS_LEARN
);
178 core_writel(priv
, reg
, CORE_DIS_LEARN
);
180 /* Enable Broadcom tags for that port if requested */
181 if (priv
->brcm_tag_mask
& BIT(port
))
182 b53_brcm_hdr_setup(ds
, port
);
184 /* Configure Traffic Class to QoS mapping, allow each priority to map
185 * to a different queue number
187 reg
= core_readl(priv
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
188 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++)
189 reg
|= i
<< (PRT_TO_QID_SHIFT
* i
);
190 core_writel(priv
, reg
, CORE_PORT_TC2_QOS_MAP_PORT(port
));
192 /* Re-enable the GPHY and re-apply workarounds */
193 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1) {
194 bcm_sf2_gphy_enable_set(ds
, true);
196 /* if phy_stop() has been called before, phy
197 * will be in halted state, and phy_start()
200 * the resume path does not configure back
201 * autoneg settings, and since we hard reset
202 * the phy manually here, we need to reset the
203 * state machine also.
205 phy
->state
= PHY_READY
;
210 /* Enable MoCA port interrupts to get notified */
211 if (port
== priv
->moca_port
)
212 bcm_sf2_port_intr_enable(priv
, port
);
214 /* Set per-queue pause threshold to 32 */
215 core_writel(priv
, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port
));
217 /* Set ACB threshold to 24 */
218 for (i
= 0; i
< SF2_NUM_EGRESS_QUEUES
; i
++) {
219 reg
= acb_readl(priv
, ACB_QUEUE_CFG(port
*
220 SF2_NUM_EGRESS_QUEUES
+ i
));
221 reg
&= ~XOFF_THRESHOLD_MASK
;
223 acb_writel(priv
, reg
, ACB_QUEUE_CFG(port
*
224 SF2_NUM_EGRESS_QUEUES
+ i
));
227 return b53_enable_port(ds
, port
, phy
);
230 static void bcm_sf2_port_disable(struct dsa_switch
*ds
, int port
)
232 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
235 /* Disable learning while in WoL mode */
236 if (priv
->wol_ports_mask
& (1 << port
)) {
237 reg
= core_readl(priv
, CORE_DIS_LEARN
);
239 core_writel(priv
, reg
, CORE_DIS_LEARN
);
243 if (port
== priv
->moca_port
)
244 bcm_sf2_port_intr_disable(priv
, port
);
246 if (priv
->int_phy_mask
& 1 << port
&& priv
->hw_params
.num_gphy
== 1)
247 bcm_sf2_gphy_enable_set(ds
, false);
249 b53_disable_port(ds
, port
);
251 /* Power down the port memory */
252 reg
= core_readl(priv
, CORE_MEM_PSM_VDD_CTRL
);
253 reg
|= P_TXQ_PSM_VDD(port
);
254 core_writel(priv
, reg
, CORE_MEM_PSM_VDD_CTRL
);
258 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv
*priv
, int op
, int addr
,
264 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
265 reg
|= MDIO_MASTER_SEL
;
266 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
268 /* Page << 8 | offset */
271 core_writel(priv
, addr
, reg
);
273 /* Page << 8 | offset */
274 reg
= 0x80 << 8 | regnum
<< 1;
278 ret
= core_readl(priv
, reg
);
280 core_writel(priv
, val
, reg
);
282 reg
= reg_readl(priv
, REG_SWITCH_CNTRL
);
283 reg
&= ~MDIO_MASTER_SEL
;
284 reg_writel(priv
, reg
, REG_SWITCH_CNTRL
);
289 static int bcm_sf2_sw_mdio_read(struct mii_bus
*bus
, int addr
, int regnum
)
291 struct bcm_sf2_priv
*priv
= bus
->priv
;
293 /* Intercept reads from Broadcom pseudo-PHY address, else, send
294 * them to our master MDIO bus controller
296 if (addr
== BRCM_PSEUDO_PHY_ADDR
&& priv
->indir_phy_mask
& BIT(addr
))
297 return bcm_sf2_sw_indir_rw(priv
, 1, addr
, regnum
, 0);
299 return mdiobus_read_nested(priv
->master_mii_bus
, addr
, regnum
);
302 static int bcm_sf2_sw_mdio_write(struct mii_bus
*bus
, int addr
, int regnum
,
305 struct bcm_sf2_priv
*priv
= bus
->priv
;
307 /* Intercept writes to the Broadcom pseudo-PHY address, else,
308 * send them to our master MDIO bus controller
310 if (addr
== BRCM_PSEUDO_PHY_ADDR
&& priv
->indir_phy_mask
& BIT(addr
))
311 return bcm_sf2_sw_indir_rw(priv
, 0, addr
, regnum
, val
);
313 return mdiobus_write_nested(priv
->master_mii_bus
, addr
,
317 static irqreturn_t
bcm_sf2_switch_0_isr(int irq
, void *dev_id
)
319 struct dsa_switch
*ds
= dev_id
;
320 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
322 priv
->irq0_stat
= intrl2_0_readl(priv
, INTRL2_CPU_STATUS
) &
324 intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
329 static irqreturn_t
bcm_sf2_switch_1_isr(int irq
, void *dev_id
)
331 struct dsa_switch
*ds
= dev_id
;
332 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
334 priv
->irq1_stat
= intrl2_1_readl(priv
, INTRL2_CPU_STATUS
) &
336 intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
338 if (priv
->irq1_stat
& P_LINK_UP_IRQ(P7_IRQ_OFF
)) {
339 priv
->port_sts
[7].link
= true;
340 dsa_port_phylink_mac_change(ds
, 7, true);
342 if (priv
->irq1_stat
& P_LINK_DOWN_IRQ(P7_IRQ_OFF
)) {
343 priv
->port_sts
[7].link
= false;
344 dsa_port_phylink_mac_change(ds
, 7, false);
350 static int bcm_sf2_sw_rst(struct bcm_sf2_priv
*priv
)
352 unsigned int timeout
= 1000;
356 /* The watchdog reset does not work on 7278, we need to hit the
357 * "external" reset line through the reset controller.
359 if (priv
->type
== BCM7278_DEVICE_ID
&& !IS_ERR(priv
->rcdev
)) {
360 ret
= reset_control_assert(priv
->rcdev
);
364 return reset_control_deassert(priv
->rcdev
);
367 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
368 reg
|= SOFTWARE_RESET
| EN_CHIP_RST
| EN_SW_RESET
;
369 core_writel(priv
, reg
, CORE_WATCHDOG_CTRL
);
372 reg
= core_readl(priv
, CORE_WATCHDOG_CTRL
);
373 if (!(reg
& SOFTWARE_RESET
))
376 usleep_range(1000, 2000);
377 } while (timeout
-- > 0);
385 static void bcm_sf2_intr_disable(struct bcm_sf2_priv
*priv
)
387 intrl2_0_mask_set(priv
, 0xffffffff);
388 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
389 intrl2_1_mask_set(priv
, 0xffffffff);
390 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
393 static void bcm_sf2_identify_ports(struct bcm_sf2_priv
*priv
,
394 struct device_node
*dn
)
396 struct device_node
*port
;
397 unsigned int port_num
;
398 phy_interface_t mode
;
401 priv
->moca_port
= -1;
403 for_each_available_child_of_node(dn
, port
) {
404 if (of_property_read_u32(port
, "reg", &port_num
))
407 /* Internal PHYs get assigned a specific 'phy-mode' property
408 * value: "internal" to help flag them before MDIO probing
409 * has completed, since they might be turned off at that
412 err
= of_get_phy_mode(port
, &mode
);
416 if (mode
== PHY_INTERFACE_MODE_INTERNAL
)
417 priv
->int_phy_mask
|= 1 << port_num
;
419 if (mode
== PHY_INTERFACE_MODE_MOCA
)
420 priv
->moca_port
= port_num
;
422 if (of_property_read_bool(port
, "brcm,use-bcm-hdr"))
423 priv
->brcm_tag_mask
|= 1 << port_num
;
427 static int bcm_sf2_mdio_register(struct dsa_switch
*ds
)
429 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
430 struct device_node
*dn
;
434 /* Find our integrated MDIO bus node */
435 dn
= of_find_compatible_node(NULL
, NULL
, "brcm,unimac-mdio");
436 priv
->master_mii_bus
= of_mdio_find_bus(dn
);
437 if (!priv
->master_mii_bus
)
438 return -EPROBE_DEFER
;
440 get_device(&priv
->master_mii_bus
->dev
);
441 priv
->master_mii_dn
= dn
;
443 priv
->slave_mii_bus
= devm_mdiobus_alloc(ds
->dev
);
444 if (!priv
->slave_mii_bus
)
447 priv
->slave_mii_bus
->priv
= priv
;
448 priv
->slave_mii_bus
->name
= "sf2 slave mii";
449 priv
->slave_mii_bus
->read
= bcm_sf2_sw_mdio_read
;
450 priv
->slave_mii_bus
->write
= bcm_sf2_sw_mdio_write
;
451 snprintf(priv
->slave_mii_bus
->id
, MII_BUS_ID_SIZE
, "sf2-%d",
453 priv
->slave_mii_bus
->dev
.of_node
= dn
;
455 /* Include the pseudo-PHY address to divert reads towards our
456 * workaround. This is only required for 7445D0, since 7445E0
457 * disconnects the internal switch pseudo-PHY such that we can use the
458 * regular SWITCH_MDIO master controller instead.
460 * Here we flag the pseudo PHY as needing special treatment and would
461 * otherwise make all other PHY read/writes go to the master MDIO bus
462 * controller that comes with this switch backed by the "mdio-unimac"
465 if (of_machine_is_compatible("brcm,bcm7445d0"))
466 priv
->indir_phy_mask
|= (1 << BRCM_PSEUDO_PHY_ADDR
);
468 priv
->indir_phy_mask
= 0;
470 ds
->phys_mii_mask
= priv
->indir_phy_mask
;
471 ds
->slave_mii_bus
= priv
->slave_mii_bus
;
472 priv
->slave_mii_bus
->parent
= ds
->dev
->parent
;
473 priv
->slave_mii_bus
->phy_mask
= ~priv
->indir_phy_mask
;
475 err
= of_mdiobus_register(priv
->slave_mii_bus
, dn
);
482 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv
*priv
)
484 mdiobus_unregister(priv
->slave_mii_bus
);
485 of_node_put(priv
->master_mii_dn
);
488 static u32
bcm_sf2_sw_get_phy_flags(struct dsa_switch
*ds
, int port
)
490 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
492 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
493 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
494 * the REG_PHY_REVISION register layout is.
497 return priv
->hw_params
.gphy_rev
;
500 static void bcm_sf2_sw_validate(struct dsa_switch
*ds
, int port
,
501 unsigned long *supported
,
502 struct phylink_link_state
*state
)
504 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
505 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
507 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
508 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
509 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
510 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
511 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
512 state
->interface
!= PHY_INTERFACE_MODE_MOCA
) {
513 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
514 if (port
!= core_readl(priv
, CORE_IMP0_PRT_ID
))
516 "Unsupported interface: %d for port %d\n",
517 state
->interface
, port
);
521 /* Allow all the expected bits */
522 phylink_set(mask
, Autoneg
);
523 phylink_set_port_modes(mask
);
524 phylink_set(mask
, Pause
);
525 phylink_set(mask
, Asym_Pause
);
527 /* With the exclusion of MII and Reverse MII, we support Gigabit,
528 * including Half duplex
530 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
531 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
532 phylink_set(mask
, 1000baseT_Full
);
533 phylink_set(mask
, 1000baseT_Half
);
536 phylink_set(mask
, 10baseT_Half
);
537 phylink_set(mask
, 10baseT_Full
);
538 phylink_set(mask
, 100baseT_Half
);
539 phylink_set(mask
, 100baseT_Full
);
541 bitmap_and(supported
, supported
, mask
,
542 __ETHTOOL_LINK_MODE_MASK_NBITS
);
543 bitmap_and(state
->advertising
, state
->advertising
, mask
,
544 __ETHTOOL_LINK_MODE_MASK_NBITS
);
547 static void bcm_sf2_sw_mac_config(struct dsa_switch
*ds
, int port
,
549 const struct phylink_link_state
*state
)
551 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
552 u32 id_mode_dis
= 0, port_mode
;
555 if (port
== core_readl(priv
, CORE_IMP0_PRT_ID
))
558 if (priv
->type
== BCM7445_DEVICE_ID
)
559 offset
= CORE_STS_OVERRIDE_GMIIP_PORT(port
);
561 offset
= CORE_STS_OVERRIDE_GMIIP2_PORT(port
);
563 switch (state
->interface
) {
564 case PHY_INTERFACE_MODE_RGMII
:
567 case PHY_INTERFACE_MODE_RGMII_TXID
:
568 port_mode
= EXT_GPHY
;
570 case PHY_INTERFACE_MODE_MII
:
571 port_mode
= EXT_EPHY
;
573 case PHY_INTERFACE_MODE_REVMII
:
574 port_mode
= EXT_REVMII
;
577 /* all other PHYs: internal and MoCA */
581 /* Clear id_mode_dis bit, and the existing port mode, let
582 * RGMII_MODE_EN bet set by mac_link_{up,down}
584 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
586 reg
&= ~(PORT_MODE_MASK
<< PORT_MODE_SHIFT
);
587 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
593 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
594 if (state
->pause
& MLO_PAUSE_TX
)
599 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
602 /* Force link settings detected from the PHY */
604 switch (state
->speed
) {
606 reg
|= SPDSTS_1000
<< SPEED_SHIFT
;
609 reg
|= SPDSTS_100
<< SPEED_SHIFT
;
615 if (state
->duplex
== DUPLEX_FULL
)
618 core_writel(priv
, reg
, offset
);
621 static void bcm_sf2_sw_mac_link_set(struct dsa_switch
*ds
, int port
,
622 phy_interface_t interface
, bool link
)
624 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
627 if (!phy_interface_mode_is_rgmii(interface
) &&
628 interface
!= PHY_INTERFACE_MODE_MII
&&
629 interface
!= PHY_INTERFACE_MODE_REVMII
)
632 /* If the link is down, just disable the interface to conserve power */
633 reg
= reg_readl(priv
, REG_RGMII_CNTRL_P(port
));
635 reg
|= RGMII_MODE_EN
;
637 reg
&= ~RGMII_MODE_EN
;
638 reg_writel(priv
, reg
, REG_RGMII_CNTRL_P(port
));
641 static void bcm_sf2_sw_mac_link_down(struct dsa_switch
*ds
, int port
,
643 phy_interface_t interface
)
645 bcm_sf2_sw_mac_link_set(ds
, port
, interface
, false);
648 static void bcm_sf2_sw_mac_link_up(struct dsa_switch
*ds
, int port
,
650 phy_interface_t interface
,
651 struct phy_device
*phydev
)
653 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
654 struct ethtool_eee
*p
= &priv
->dev
->ports
[port
].eee
;
656 bcm_sf2_sw_mac_link_set(ds
, port
, interface
, true);
658 if (mode
== MLO_AN_PHY
&& phydev
)
659 p
->eee_enabled
= b53_eee_init(ds
, port
, phydev
);
662 static void bcm_sf2_sw_fixed_state(struct dsa_switch
*ds
, int port
,
663 struct phylink_link_state
*status
)
665 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
667 status
->link
= false;
669 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
670 * which means that we need to force the link at the port override
671 * level to get the data to flow. We do use what the interrupt handler
672 * did determine before.
674 * For the other ports, we just force the link status, since this is
675 * a fixed PHY device.
677 if (port
== priv
->moca_port
) {
678 status
->link
= priv
->port_sts
[port
].link
;
679 /* For MoCA interfaces, also force a link down notification
680 * since some version of the user-space daemon (mocad) use
681 * cmd->autoneg to force the link, which messes up the PHY
682 * state machine and make it go in PHY_FORCING state instead.
685 netif_carrier_off(dsa_to_port(ds
, port
)->slave
);
686 status
->duplex
= DUPLEX_FULL
;
692 static void bcm_sf2_enable_acb(struct dsa_switch
*ds
)
694 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
697 /* Enable ACB globally */
698 reg
= acb_readl(priv
, ACB_CONTROL
);
699 reg
|= (ACB_FLUSH_MASK
<< ACB_FLUSH_SHIFT
);
700 acb_writel(priv
, reg
, ACB_CONTROL
);
701 reg
&= ~(ACB_FLUSH_MASK
<< ACB_FLUSH_SHIFT
);
702 reg
|= ACB_EN
| ACB_ALGORITHM
;
703 acb_writel(priv
, reg
, ACB_CONTROL
);
706 static int bcm_sf2_sw_suspend(struct dsa_switch
*ds
)
708 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
711 bcm_sf2_intr_disable(priv
);
713 /* Disable all ports physically present including the IMP
714 * port, the other ones have already been disabled during
717 for (port
= 0; port
< ds
->num_ports
; port
++) {
718 if (dsa_is_user_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
719 bcm_sf2_port_disable(ds
, port
);
725 static int bcm_sf2_sw_resume(struct dsa_switch
*ds
)
727 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
730 ret
= bcm_sf2_sw_rst(priv
);
732 pr_err("%s: failed to software reset switch\n", __func__
);
736 ret
= bcm_sf2_cfp_resume(ds
);
740 if (priv
->hw_params
.num_gphy
== 1)
741 bcm_sf2_gphy_enable_set(ds
, true);
748 static void bcm_sf2_sw_get_wol(struct dsa_switch
*ds
, int port
,
749 struct ethtool_wolinfo
*wol
)
751 struct net_device
*p
= dsa_to_port(ds
, port
)->cpu_dp
->master
;
752 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
753 struct ethtool_wolinfo pwol
= { };
755 /* Get the parent device WoL settings */
756 if (p
->ethtool_ops
->get_wol
)
757 p
->ethtool_ops
->get_wol(p
, &pwol
);
759 /* Advertise the parent device supported settings */
760 wol
->supported
= pwol
.supported
;
761 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
763 if (pwol
.wolopts
& WAKE_MAGICSECURE
)
764 memcpy(&wol
->sopass
, pwol
.sopass
, sizeof(wol
->sopass
));
766 if (priv
->wol_ports_mask
& (1 << port
))
767 wol
->wolopts
= pwol
.wolopts
;
772 static int bcm_sf2_sw_set_wol(struct dsa_switch
*ds
, int port
,
773 struct ethtool_wolinfo
*wol
)
775 struct net_device
*p
= dsa_to_port(ds
, port
)->cpu_dp
->master
;
776 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
777 s8 cpu_port
= dsa_to_port(ds
, port
)->cpu_dp
->index
;
778 struct ethtool_wolinfo pwol
= { };
780 if (p
->ethtool_ops
->get_wol
)
781 p
->ethtool_ops
->get_wol(p
, &pwol
);
782 if (wol
->wolopts
& ~pwol
.supported
)
786 priv
->wol_ports_mask
|= (1 << port
);
788 priv
->wol_ports_mask
&= ~(1 << port
);
790 /* If we have at least one port enabled, make sure the CPU port
791 * is also enabled. If the CPU port is the last one enabled, we disable
792 * it since this configuration does not make sense.
794 if (priv
->wol_ports_mask
&& priv
->wol_ports_mask
!= (1 << cpu_port
))
795 priv
->wol_ports_mask
|= (1 << cpu_port
);
797 priv
->wol_ports_mask
&= ~(1 << cpu_port
);
799 return p
->ethtool_ops
->set_wol(p
, wol
);
802 static int bcm_sf2_sw_setup(struct dsa_switch
*ds
)
804 struct bcm_sf2_priv
*priv
= bcm_sf2_to_priv(ds
);
807 /* Enable all valid ports and disable those unused */
808 for (port
= 0; port
< priv
->hw_params
.num_ports
; port
++) {
809 /* IMP port receives special treatment */
810 if (dsa_is_user_port(ds
, port
))
811 bcm_sf2_port_setup(ds
, port
, NULL
);
812 else if (dsa_is_cpu_port(ds
, port
))
813 bcm_sf2_imp_setup(ds
, port
);
815 bcm_sf2_port_disable(ds
, port
);
818 b53_configure_vlan(ds
);
819 bcm_sf2_enable_acb(ds
);
824 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
825 * register basis so we need to translate that into an address that the
826 * bus-glue understands.
828 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
830 static int bcm_sf2_core_read8(struct b53_device
*dev
, u8 page
, u8 reg
,
833 struct bcm_sf2_priv
*priv
= dev
->priv
;
835 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
840 static int bcm_sf2_core_read16(struct b53_device
*dev
, u8 page
, u8 reg
,
843 struct bcm_sf2_priv
*priv
= dev
->priv
;
845 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
850 static int bcm_sf2_core_read32(struct b53_device
*dev
, u8 page
, u8 reg
,
853 struct bcm_sf2_priv
*priv
= dev
->priv
;
855 *val
= core_readl(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
860 static int bcm_sf2_core_read64(struct b53_device
*dev
, u8 page
, u8 reg
,
863 struct bcm_sf2_priv
*priv
= dev
->priv
;
865 *val
= core_readq(priv
, SF2_PAGE_REG_MKADDR(page
, reg
));
870 static int bcm_sf2_core_write8(struct b53_device
*dev
, u8 page
, u8 reg
,
873 struct bcm_sf2_priv
*priv
= dev
->priv
;
875 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
880 static int bcm_sf2_core_write16(struct b53_device
*dev
, u8 page
, u8 reg
,
883 struct bcm_sf2_priv
*priv
= dev
->priv
;
885 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
890 static int bcm_sf2_core_write32(struct b53_device
*dev
, u8 page
, u8 reg
,
893 struct bcm_sf2_priv
*priv
= dev
->priv
;
895 core_writel(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
900 static int bcm_sf2_core_write64(struct b53_device
*dev
, u8 page
, u8 reg
,
903 struct bcm_sf2_priv
*priv
= dev
->priv
;
905 core_writeq(priv
, value
, SF2_PAGE_REG_MKADDR(page
, reg
));
910 static const struct b53_io_ops bcm_sf2_io_ops
= {
911 .read8
= bcm_sf2_core_read8
,
912 .read16
= bcm_sf2_core_read16
,
913 .read32
= bcm_sf2_core_read32
,
914 .read48
= bcm_sf2_core_read64
,
915 .read64
= bcm_sf2_core_read64
,
916 .write8
= bcm_sf2_core_write8
,
917 .write16
= bcm_sf2_core_write16
,
918 .write32
= bcm_sf2_core_write32
,
919 .write48
= bcm_sf2_core_write64
,
920 .write64
= bcm_sf2_core_write64
,
923 static void bcm_sf2_sw_get_strings(struct dsa_switch
*ds
, int port
,
924 u32 stringset
, uint8_t *data
)
926 int cnt
= b53_get_sset_count(ds
, port
, stringset
);
928 b53_get_strings(ds
, port
, stringset
, data
);
929 bcm_sf2_cfp_get_strings(ds
, port
, stringset
,
930 data
+ cnt
* ETH_GSTRING_LEN
);
933 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
936 int cnt
= b53_get_sset_count(ds
, port
, ETH_SS_STATS
);
938 b53_get_ethtool_stats(ds
, port
, data
);
939 bcm_sf2_cfp_get_ethtool_stats(ds
, port
, data
+ cnt
);
942 static int bcm_sf2_sw_get_sset_count(struct dsa_switch
*ds
, int port
,
945 int cnt
= b53_get_sset_count(ds
, port
, sset
);
950 cnt
+= bcm_sf2_cfp_get_sset_count(ds
, port
, sset
);
955 static const struct dsa_switch_ops bcm_sf2_ops
= {
956 .get_tag_protocol
= b53_get_tag_protocol
,
957 .setup
= bcm_sf2_sw_setup
,
958 .get_strings
= bcm_sf2_sw_get_strings
,
959 .get_ethtool_stats
= bcm_sf2_sw_get_ethtool_stats
,
960 .get_sset_count
= bcm_sf2_sw_get_sset_count
,
961 .get_ethtool_phy_stats
= b53_get_ethtool_phy_stats
,
962 .get_phy_flags
= bcm_sf2_sw_get_phy_flags
,
963 .phylink_validate
= bcm_sf2_sw_validate
,
964 .phylink_mac_config
= bcm_sf2_sw_mac_config
,
965 .phylink_mac_link_down
= bcm_sf2_sw_mac_link_down
,
966 .phylink_mac_link_up
= bcm_sf2_sw_mac_link_up
,
967 .phylink_fixed_state
= bcm_sf2_sw_fixed_state
,
968 .suspend
= bcm_sf2_sw_suspend
,
969 .resume
= bcm_sf2_sw_resume
,
970 .get_wol
= bcm_sf2_sw_get_wol
,
971 .set_wol
= bcm_sf2_sw_set_wol
,
972 .port_enable
= bcm_sf2_port_setup
,
973 .port_disable
= bcm_sf2_port_disable
,
974 .get_mac_eee
= b53_get_mac_eee
,
975 .set_mac_eee
= b53_set_mac_eee
,
976 .port_bridge_join
= b53_br_join
,
977 .port_bridge_leave
= b53_br_leave
,
978 .port_stp_state_set
= b53_br_set_stp_state
,
979 .port_fast_age
= b53_br_fast_age
,
980 .port_vlan_filtering
= b53_vlan_filtering
,
981 .port_vlan_prepare
= b53_vlan_prepare
,
982 .port_vlan_add
= b53_vlan_add
,
983 .port_vlan_del
= b53_vlan_del
,
984 .port_fdb_dump
= b53_fdb_dump
,
985 .port_fdb_add
= b53_fdb_add
,
986 .port_fdb_del
= b53_fdb_del
,
987 .get_rxnfc
= bcm_sf2_get_rxnfc
,
988 .set_rxnfc
= bcm_sf2_set_rxnfc
,
989 .port_mirror_add
= b53_mirror_add
,
990 .port_mirror_del
= b53_mirror_del
,
991 .port_mdb_prepare
= b53_mdb_prepare
,
992 .port_mdb_add
= b53_mdb_add
,
993 .port_mdb_del
= b53_mdb_del
,
996 struct bcm_sf2_of_data
{
998 const u16
*reg_offsets
;
999 unsigned int core_reg_align
;
1000 unsigned int num_cfp_rules
;
1003 /* Register offsets for the SWITCH_REG_* block */
1004 static const u16 bcm_sf2_7445_reg_offsets
[] = {
1005 [REG_SWITCH_CNTRL
] = 0x00,
1006 [REG_SWITCH_STATUS
] = 0x04,
1007 [REG_DIR_DATA_WRITE
] = 0x08,
1008 [REG_DIR_DATA_READ
] = 0x0C,
1009 [REG_SWITCH_REVISION
] = 0x18,
1010 [REG_PHY_REVISION
] = 0x1C,
1011 [REG_SPHY_CNTRL
] = 0x2C,
1012 [REG_RGMII_0_CNTRL
] = 0x34,
1013 [REG_RGMII_1_CNTRL
] = 0x40,
1014 [REG_RGMII_2_CNTRL
] = 0x4c,
1015 [REG_LED_0_CNTRL
] = 0x90,
1016 [REG_LED_1_CNTRL
] = 0x94,
1017 [REG_LED_2_CNTRL
] = 0x98,
1020 static const struct bcm_sf2_of_data bcm_sf2_7445_data
= {
1021 .type
= BCM7445_DEVICE_ID
,
1022 .core_reg_align
= 0,
1023 .reg_offsets
= bcm_sf2_7445_reg_offsets
,
1024 .num_cfp_rules
= 256,
1027 static const u16 bcm_sf2_7278_reg_offsets
[] = {
1028 [REG_SWITCH_CNTRL
] = 0x00,
1029 [REG_SWITCH_STATUS
] = 0x04,
1030 [REG_DIR_DATA_WRITE
] = 0x08,
1031 [REG_DIR_DATA_READ
] = 0x0c,
1032 [REG_SWITCH_REVISION
] = 0x10,
1033 [REG_PHY_REVISION
] = 0x14,
1034 [REG_SPHY_CNTRL
] = 0x24,
1035 [REG_RGMII_0_CNTRL
] = 0xe0,
1036 [REG_RGMII_1_CNTRL
] = 0xec,
1037 [REG_RGMII_2_CNTRL
] = 0xf8,
1038 [REG_LED_0_CNTRL
] = 0x40,
1039 [REG_LED_1_CNTRL
] = 0x4c,
1040 [REG_LED_2_CNTRL
] = 0x58,
1043 static const struct bcm_sf2_of_data bcm_sf2_7278_data
= {
1044 .type
= BCM7278_DEVICE_ID
,
1045 .core_reg_align
= 1,
1046 .reg_offsets
= bcm_sf2_7278_reg_offsets
,
1047 .num_cfp_rules
= 128,
1050 static const struct of_device_id bcm_sf2_of_match
[] = {
1051 { .compatible
= "brcm,bcm7445-switch-v4.0",
1052 .data
= &bcm_sf2_7445_data
1054 { .compatible
= "brcm,bcm7278-switch-v4.0",
1055 .data
= &bcm_sf2_7278_data
1057 { .compatible
= "brcm,bcm7278-switch-v4.8",
1058 .data
= &bcm_sf2_7278_data
1062 MODULE_DEVICE_TABLE(of
, bcm_sf2_of_match
);
1064 static int bcm_sf2_sw_probe(struct platform_device
*pdev
)
1066 const char *reg_names
[BCM_SF2_REGS_NUM
] = BCM_SF2_REGS_NAME
;
1067 struct device_node
*dn
= pdev
->dev
.of_node
;
1068 const struct of_device_id
*of_id
= NULL
;
1069 const struct bcm_sf2_of_data
*data
;
1070 struct b53_platform_data
*pdata
;
1071 struct dsa_switch_ops
*ops
;
1072 struct bcm_sf2_priv
*priv
;
1073 struct b53_device
*dev
;
1074 struct dsa_switch
*ds
;
1075 void __iomem
**base
;
1080 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1084 ops
= devm_kzalloc(&pdev
->dev
, sizeof(*ops
), GFP_KERNEL
);
1088 dev
= b53_switch_alloc(&pdev
->dev
, &bcm_sf2_io_ops
, priv
);
1092 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1096 of_id
= of_match_node(bcm_sf2_of_match
, dn
);
1097 if (!of_id
|| !of_id
->data
)
1102 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1103 priv
->type
= data
->type
;
1104 priv
->reg_offsets
= data
->reg_offsets
;
1105 priv
->core_reg_align
= data
->core_reg_align
;
1106 priv
->num_cfp_rules
= data
->num_cfp_rules
;
1108 priv
->rcdev
= devm_reset_control_get_optional_exclusive(&pdev
->dev
,
1110 if (PTR_ERR(priv
->rcdev
) == -EPROBE_DEFER
)
1111 return PTR_ERR(priv
->rcdev
);
1113 /* Auto-detection using standard registers will not work, so
1114 * provide an indication of what kind of device we are for
1115 * b53_common to work with
1117 pdata
->chip_id
= priv
->type
;
1122 ds
->ops
= &bcm_sf2_ops
;
1124 /* Advertise the 8 egress queues */
1125 ds
->num_tx_queues
= SF2_NUM_EGRESS_QUEUES
;
1127 dev_set_drvdata(&pdev
->dev
, priv
);
1129 spin_lock_init(&priv
->indir_lock
);
1130 mutex_init(&priv
->cfp
.lock
);
1131 INIT_LIST_HEAD(&priv
->cfp
.rules_list
);
1133 /* CFP rule #0 cannot be used for specific classifications, flag it as
1136 set_bit(0, priv
->cfp
.used
);
1137 set_bit(0, priv
->cfp
.unique
);
1139 bcm_sf2_identify_ports(priv
, dn
->child
);
1141 priv
->irq0
= irq_of_parse_and_map(dn
, 0);
1142 priv
->irq1
= irq_of_parse_and_map(dn
, 1);
1145 for (i
= 0; i
< BCM_SF2_REGS_NUM
; i
++) {
1146 *base
= devm_platform_ioremap_resource(pdev
, i
);
1147 if (IS_ERR(*base
)) {
1148 pr_err("unable to find register: %s\n", reg_names
[i
]);
1149 return PTR_ERR(*base
);
1154 ret
= bcm_sf2_sw_rst(priv
);
1156 pr_err("unable to software reset switch: %d\n", ret
);
1160 bcm_sf2_gphy_enable_set(priv
->dev
->ds
, true);
1162 ret
= bcm_sf2_mdio_register(ds
);
1164 pr_err("failed to register MDIO bus\n");
1168 bcm_sf2_gphy_enable_set(priv
->dev
->ds
, false);
1170 ret
= bcm_sf2_cfp_rst(priv
);
1172 pr_err("failed to reset CFP\n");
1176 /* Disable all interrupts and request them */
1177 bcm_sf2_intr_disable(priv
);
1179 ret
= devm_request_irq(&pdev
->dev
, priv
->irq0
, bcm_sf2_switch_0_isr
, 0,
1182 pr_err("failed to request switch_0 IRQ\n");
1186 ret
= devm_request_irq(&pdev
->dev
, priv
->irq1
, bcm_sf2_switch_1_isr
, 0,
1189 pr_err("failed to request switch_1 IRQ\n");
1193 /* Reset the MIB counters */
1194 reg
= core_readl(priv
, CORE_GMNCFGCFG
);
1196 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
1197 reg
&= ~RST_MIB_CNT
;
1198 core_writel(priv
, reg
, CORE_GMNCFGCFG
);
1200 /* Get the maximum number of ports for this switch */
1201 priv
->hw_params
.num_ports
= core_readl(priv
, CORE_IMP0_PRT_ID
) + 1;
1202 if (priv
->hw_params
.num_ports
> DSA_MAX_PORTS
)
1203 priv
->hw_params
.num_ports
= DSA_MAX_PORTS
;
1205 /* Assume a single GPHY setup if we can't read that property */
1206 if (of_property_read_u32(dn
, "brcm,num-gphy",
1207 &priv
->hw_params
.num_gphy
))
1208 priv
->hw_params
.num_gphy
= 1;
1210 rev
= reg_readl(priv
, REG_SWITCH_REVISION
);
1211 priv
->hw_params
.top_rev
= (rev
>> SWITCH_TOP_REV_SHIFT
) &
1212 SWITCH_TOP_REV_MASK
;
1213 priv
->hw_params
.core_rev
= (rev
& SF2_REV_MASK
);
1215 rev
= reg_readl(priv
, REG_PHY_REVISION
);
1216 priv
->hw_params
.gphy_rev
= rev
& PHY_REVISION_MASK
;
1218 ret
= b53_switch_register(dev
);
1222 dev_info(&pdev
->dev
,
1223 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1224 priv
->hw_params
.top_rev
>> 8, priv
->hw_params
.top_rev
& 0xff,
1225 priv
->hw_params
.core_rev
>> 8, priv
->hw_params
.core_rev
& 0xff,
1226 priv
->irq0
, priv
->irq1
);
1231 bcm_sf2_mdio_unregister(priv
);
1235 static int bcm_sf2_sw_remove(struct platform_device
*pdev
)
1237 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1239 priv
->wol_ports_mask
= 0;
1240 /* Disable interrupts */
1241 bcm_sf2_intr_disable(priv
);
1242 dsa_unregister_switch(priv
->dev
->ds
);
1243 bcm_sf2_cfp_exit(priv
->dev
->ds
);
1244 bcm_sf2_mdio_unregister(priv
);
1245 if (priv
->type
== BCM7278_DEVICE_ID
&& !IS_ERR(priv
->rcdev
))
1246 reset_control_assert(priv
->rcdev
);
1251 static void bcm_sf2_sw_shutdown(struct platform_device
*pdev
)
1253 struct bcm_sf2_priv
*priv
= platform_get_drvdata(pdev
);
1255 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1256 * successful MDIO bus scan to occur. If we did turn off the GPHY
1257 * before (e.g: port_disable), this will also power it back on.
1259 * Do not rely on kexec_in_progress, just power the PHY on.
1261 if (priv
->hw_params
.num_gphy
== 1)
1262 bcm_sf2_gphy_enable_set(priv
->dev
->ds
, true);
1265 #ifdef CONFIG_PM_SLEEP
1266 static int bcm_sf2_suspend(struct device
*dev
)
1268 struct bcm_sf2_priv
*priv
= dev_get_drvdata(dev
);
1270 return dsa_switch_suspend(priv
->dev
->ds
);
1273 static int bcm_sf2_resume(struct device
*dev
)
1275 struct bcm_sf2_priv
*priv
= dev_get_drvdata(dev
);
1277 return dsa_switch_resume(priv
->dev
->ds
);
1279 #endif /* CONFIG_PM_SLEEP */
1281 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops
,
1282 bcm_sf2_suspend
, bcm_sf2_resume
);
1285 static struct platform_driver bcm_sf2_driver
= {
1286 .probe
= bcm_sf2_sw_probe
,
1287 .remove
= bcm_sf2_sw_remove
,
1288 .shutdown
= bcm_sf2_sw_shutdown
,
1291 .of_match_table
= bcm_sf2_of_match
,
1292 .pm
= &bcm_sf2_pm_ops
,
1295 module_platform_driver(bcm_sf2_driver
);
1297 MODULE_AUTHOR("Broadcom Corporation");
1298 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1299 MODULE_LICENSE("GPL");
1300 MODULE_ALIAS("platform:brcm-sf2");