1 // SPDX-License-Identifier: GPL-2.0
3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/etherdevice.h>
31 #include <linux/firmware.h>
32 #include <linux/if_bridge.h>
33 #include <linux/if_vlan.h>
34 #include <linux/iopoll.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/module.h>
37 #include <linux/of_mdio.h>
38 #include <linux/of_net.h>
39 #include <linux/of_platform.h>
40 #include <linux/phy.h>
41 #include <linux/phylink.h>
42 #include <linux/platform_device.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
48 #include "lantiq_pce.h"
50 /* GSWIP MDIO Registers */
51 #define GSWIP_MDIO_GLOB 0x00
52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53 #define GSWIP_MDIO_CTRL 0x08
54 #define GSWIP_MDIO_CTRL_BUSY BIT(12)
55 #define GSWIP_MDIO_CTRL_RD BIT(11)
56 #define GSWIP_MDIO_CTRL_WR BIT(10)
57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60 #define GSWIP_MDIO_READ 0x09
61 #define GSWIP_MDIO_WRITE 0x0A
62 #define GSWIP_MDIO_MDC_CFG0 0x0B
63 #define GSWIP_MDIO_MDC_CFG1 0x0C
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000
69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
94 /* GSWIP MII Registers */
95 #define GSWIP_MII_CFGp(p) (0x2 * (p))
96 #define GSWIP_MII_CFG_RESET BIT(15)
97 #define GSWIP_MII_CFG_EN BIT(14)
98 #define GSWIP_MII_CFG_ISOLATE BIT(13)
99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12)
100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8)
101 #define GSWIP_MII_CFG_RMII_CLK BIT(7)
102 #define GSWIP_MII_CFG_MODE_MIIP 0x0
103 #define GSWIP_MII_CFG_MODE_MIIM 0x1
104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2
105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3
106 #define GSWIP_MII_CFG_MODE_RGMII 0x4
107 #define GSWIP_MII_CFG_MODE_GMII 0x9
108 #define GSWIP_MII_CFG_MODE_MASK 0xf
109 #define GSWIP_MII_CFG_RATE_M2P5 0x00
110 #define GSWIP_MII_CFG_RATE_M25 0x10
111 #define GSWIP_MII_CFG_RATE_M125 0x20
112 #define GSWIP_MII_CFG_RATE_M50 0x30
113 #define GSWIP_MII_CFG_RATE_AUTO 0x40
114 #define GSWIP_MII_CFG_RATE_MASK 0x70
115 #define GSWIP_MII_PCDU0 0x01
116 #define GSWIP_MII_PCDU1 0x03
117 #define GSWIP_MII_PCDU5 0x05
118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
121 /* GSWIP Core Registers */
122 #define GSWIP_SWRES 0x000
123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
125 #define GSWIP_VERSION 0x013
126 #define GSWIP_VERSION_REV_SHIFT 0
127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
128 #define GSWIP_VERSION_MOD_SHIFT 8
129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
130 #define GSWIP_VERSION_2_0 0x100
131 #define GSWIP_VERSION_2_1 0x021
132 #define GSWIP_VERSION_2_2 0x122
133 #define GSWIP_VERSION_2_2_ETC 0x022
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
136 #define GSWIP_BM_RAM_ADDR 0x044
137 #define GSWIP_BM_RAM_CTRL 0x045
138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15)
139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
141 #define GSWIP_BM_QUEUE_GCTRL 0x04A
142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
143 /* buffer management Port Configuration Register */
144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
147 /* buffer management Port Control Register */
148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154 #define GSWIP_PCE_TBL_MASK 0x448
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
156 #define GSWIP_PCE_TBL_ADDR 0x44E
157 #define GSWIP_PCE_TBL_CTRL 0x44F
158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
172 #define GSWIP_PCE_GCTRL_0 0x456
173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
176 #define GSWIP_PCE_GCTRL_1 0x457
177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
197 #define GSWIP_MAC_FLEN 0x8C5
198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8)
200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
218 /* Ethernet Switch Fetch DMA Port Control Register */
219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
229 /* Ethernet Switch Store DMA Port Control Register */
230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */
235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01
236 #define GSWIP_TABLE_VLAN_MAPPING 0x02
237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b
238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
240 #define XRX200_GPHY_FW_ALIGN (16 * 1024)
242 struct gswip_hw_info
{
245 const struct dsa_switch_ops
*ops
;
248 struct xway_gphy_match_data
{
249 char *fe_firmware_name
;
250 char *ge_firmware_name
;
253 struct gswip_gphy_fw
{
254 struct clk
*clk_gate
;
255 struct reset_control
*reset
;
261 struct net_device
*bridge
;
270 const struct gswip_hw_info
*hw_info
;
271 const struct xway_gphy_match_data
*gphy_fw_name_cfg
;
272 struct dsa_switch
*ds
;
274 struct regmap
*rcu_regmap
;
275 struct gswip_vlan vlans
[64];
277 struct gswip_gphy_fw
*gphy_fw
;
278 u32 port_vlan_filter
;
281 struct gswip_pce_table_entry
{
282 u16 index
; // PCE_TBL_ADDR.ADDR = pData->table_index
283 u16 table
; // PCE_TBL_CTRL.ADDR = pData->table
293 struct gswip_rmon_cnt_desc
{
299 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
301 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt
[] = {
302 /** Receive Packet Count (only packets that are accepted and not discarded). */
303 MIB_DESC(1, 0x1F, "RxGoodPkts"),
304 MIB_DESC(1, 0x23, "RxUnicastPkts"),
305 MIB_DESC(1, 0x22, "RxMulticastPkts"),
306 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
307 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
308 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
309 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
310 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
311 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
312 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
313 MIB_DESC(1, 0x12, "Rx64BytePkts"),
314 MIB_DESC(1, 0x13, "Rx127BytePkts"),
315 MIB_DESC(1, 0x14, "Rx255BytePkts"),
316 MIB_DESC(1, 0x15, "Rx511BytePkts"),
317 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
318 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
319 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
320 MIB_DESC(1, 0x18, "RxDroppedPkts"),
321 MIB_DESC(1, 0x19, "RxFilteredPkts"),
322 MIB_DESC(2, 0x24, "RxGoodBytes"),
323 MIB_DESC(2, 0x26, "RxBadBytes"),
324 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
325 MIB_DESC(1, 0x0C, "TxGoodPkts"),
326 MIB_DESC(1, 0x06, "TxUnicastPkts"),
327 MIB_DESC(1, 0x07, "TxMulticastPkts"),
328 MIB_DESC(1, 0x00, "Tx64BytePkts"),
329 MIB_DESC(1, 0x01, "Tx127BytePkts"),
330 MIB_DESC(1, 0x02, "Tx255BytePkts"),
331 MIB_DESC(1, 0x03, "Tx511BytePkts"),
332 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
333 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
334 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
335 MIB_DESC(1, 0x08, "TxSingleCollCount"),
336 MIB_DESC(1, 0x09, "TxMultCollCount"),
337 MIB_DESC(1, 0x0A, "TxLateCollCount"),
338 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
339 MIB_DESC(1, 0x0D, "TxPauseCount"),
340 MIB_DESC(1, 0x10, "TxDroppedPkts"),
341 MIB_DESC(2, 0x0E, "TxGoodBytes"),
344 static u32
gswip_switch_r(struct gswip_priv
*priv
, u32 offset
)
346 return __raw_readl(priv
->gswip
+ (offset
* 4));
349 static void gswip_switch_w(struct gswip_priv
*priv
, u32 val
, u32 offset
)
351 __raw_writel(val
, priv
->gswip
+ (offset
* 4));
354 static void gswip_switch_mask(struct gswip_priv
*priv
, u32 clear
, u32 set
,
357 u32 val
= gswip_switch_r(priv
, offset
);
361 gswip_switch_w(priv
, val
, offset
);
364 static u32
gswip_switch_r_timeout(struct gswip_priv
*priv
, u32 offset
,
369 return readx_poll_timeout(__raw_readl
, priv
->gswip
+ (offset
* 4), val
,
370 (val
& cleared
) == 0, 20, 50000);
373 static u32
gswip_mdio_r(struct gswip_priv
*priv
, u32 offset
)
375 return __raw_readl(priv
->mdio
+ (offset
* 4));
378 static void gswip_mdio_w(struct gswip_priv
*priv
, u32 val
, u32 offset
)
380 __raw_writel(val
, priv
->mdio
+ (offset
* 4));
383 static void gswip_mdio_mask(struct gswip_priv
*priv
, u32 clear
, u32 set
,
386 u32 val
= gswip_mdio_r(priv
, offset
);
390 gswip_mdio_w(priv
, val
, offset
);
393 static u32
gswip_mii_r(struct gswip_priv
*priv
, u32 offset
)
395 return __raw_readl(priv
->mii
+ (offset
* 4));
398 static void gswip_mii_w(struct gswip_priv
*priv
, u32 val
, u32 offset
)
400 __raw_writel(val
, priv
->mii
+ (offset
* 4));
403 static void gswip_mii_mask(struct gswip_priv
*priv
, u32 clear
, u32 set
,
406 u32 val
= gswip_mii_r(priv
, offset
);
410 gswip_mii_w(priv
, val
, offset
);
413 static void gswip_mii_mask_cfg(struct gswip_priv
*priv
, u32 clear
, u32 set
,
416 /* There's no MII_CFG register for the CPU port */
417 if (!dsa_is_cpu_port(priv
->ds
, port
))
418 gswip_mii_mask(priv
, clear
, set
, GSWIP_MII_CFGp(port
));
421 static void gswip_mii_mask_pcdu(struct gswip_priv
*priv
, u32 clear
, u32 set
,
426 gswip_mii_mask(priv
, clear
, set
, GSWIP_MII_PCDU0
);
429 gswip_mii_mask(priv
, clear
, set
, GSWIP_MII_PCDU1
);
432 gswip_mii_mask(priv
, clear
, set
, GSWIP_MII_PCDU5
);
437 static int gswip_mdio_poll(struct gswip_priv
*priv
)
441 while (likely(cnt
--)) {
442 u32 ctrl
= gswip_mdio_r(priv
, GSWIP_MDIO_CTRL
);
444 if ((ctrl
& GSWIP_MDIO_CTRL_BUSY
) == 0)
446 usleep_range(20, 40);
452 static int gswip_mdio_wr(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
454 struct gswip_priv
*priv
= bus
->priv
;
457 err
= gswip_mdio_poll(priv
);
459 dev_err(&bus
->dev
, "waiting for MDIO bus busy timed out\n");
463 gswip_mdio_w(priv
, val
, GSWIP_MDIO_WRITE
);
464 gswip_mdio_w(priv
, GSWIP_MDIO_CTRL_BUSY
| GSWIP_MDIO_CTRL_WR
|
465 ((addr
& GSWIP_MDIO_CTRL_PHYAD_MASK
) << GSWIP_MDIO_CTRL_PHYAD_SHIFT
) |
466 (reg
& GSWIP_MDIO_CTRL_REGAD_MASK
),
472 static int gswip_mdio_rd(struct mii_bus
*bus
, int addr
, int reg
)
474 struct gswip_priv
*priv
= bus
->priv
;
477 err
= gswip_mdio_poll(priv
);
479 dev_err(&bus
->dev
, "waiting for MDIO bus busy timed out\n");
483 gswip_mdio_w(priv
, GSWIP_MDIO_CTRL_BUSY
| GSWIP_MDIO_CTRL_RD
|
484 ((addr
& GSWIP_MDIO_CTRL_PHYAD_MASK
) << GSWIP_MDIO_CTRL_PHYAD_SHIFT
) |
485 (reg
& GSWIP_MDIO_CTRL_REGAD_MASK
),
488 err
= gswip_mdio_poll(priv
);
490 dev_err(&bus
->dev
, "waiting for MDIO bus busy timed out\n");
494 return gswip_mdio_r(priv
, GSWIP_MDIO_READ
);
497 static int gswip_mdio(struct gswip_priv
*priv
, struct device_node
*mdio_np
)
499 struct dsa_switch
*ds
= priv
->ds
;
501 ds
->slave_mii_bus
= devm_mdiobus_alloc(priv
->dev
);
502 if (!ds
->slave_mii_bus
)
505 ds
->slave_mii_bus
->priv
= priv
;
506 ds
->slave_mii_bus
->read
= gswip_mdio_rd
;
507 ds
->slave_mii_bus
->write
= gswip_mdio_wr
;
508 ds
->slave_mii_bus
->name
= "lantiq,xrx200-mdio";
509 snprintf(ds
->slave_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-mii",
510 dev_name(priv
->dev
));
511 ds
->slave_mii_bus
->parent
= priv
->dev
;
512 ds
->slave_mii_bus
->phy_mask
= ~ds
->phys_mii_mask
;
514 return of_mdiobus_register(ds
->slave_mii_bus
, mdio_np
);
517 static int gswip_pce_table_entry_read(struct gswip_priv
*priv
,
518 struct gswip_pce_table_entry
*tbl
)
523 u16 addr_mode
= tbl
->key_mode
? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD
:
524 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD
;
526 err
= gswip_switch_r_timeout(priv
, GSWIP_PCE_TBL_CTRL
,
527 GSWIP_PCE_TBL_CTRL_BAS
);
531 gswip_switch_w(priv
, tbl
->index
, GSWIP_PCE_TBL_ADDR
);
532 gswip_switch_mask(priv
, GSWIP_PCE_TBL_CTRL_ADDR_MASK
|
533 GSWIP_PCE_TBL_CTRL_OPMOD_MASK
,
534 tbl
->table
| addr_mode
| GSWIP_PCE_TBL_CTRL_BAS
,
537 err
= gswip_switch_r_timeout(priv
, GSWIP_PCE_TBL_CTRL
,
538 GSWIP_PCE_TBL_CTRL_BAS
);
542 for (i
= 0; i
< ARRAY_SIZE(tbl
->key
); i
++)
543 tbl
->key
[i
] = gswip_switch_r(priv
, GSWIP_PCE_TBL_KEY(i
));
545 for (i
= 0; i
< ARRAY_SIZE(tbl
->val
); i
++)
546 tbl
->val
[i
] = gswip_switch_r(priv
, GSWIP_PCE_TBL_VAL(i
));
548 tbl
->mask
= gswip_switch_r(priv
, GSWIP_PCE_TBL_MASK
);
550 crtl
= gswip_switch_r(priv
, GSWIP_PCE_TBL_CTRL
);
552 tbl
->type
= !!(crtl
& GSWIP_PCE_TBL_CTRL_TYPE
);
553 tbl
->valid
= !!(crtl
& GSWIP_PCE_TBL_CTRL_VLD
);
554 tbl
->gmap
= (crtl
& GSWIP_PCE_TBL_CTRL_GMAP_MASK
) >> 7;
559 static int gswip_pce_table_entry_write(struct gswip_priv
*priv
,
560 struct gswip_pce_table_entry
*tbl
)
565 u16 addr_mode
= tbl
->key_mode
? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR
:
566 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR
;
568 err
= gswip_switch_r_timeout(priv
, GSWIP_PCE_TBL_CTRL
,
569 GSWIP_PCE_TBL_CTRL_BAS
);
573 gswip_switch_w(priv
, tbl
->index
, GSWIP_PCE_TBL_ADDR
);
574 gswip_switch_mask(priv
, GSWIP_PCE_TBL_CTRL_ADDR_MASK
|
575 GSWIP_PCE_TBL_CTRL_OPMOD_MASK
,
576 tbl
->table
| addr_mode
,
579 for (i
= 0; i
< ARRAY_SIZE(tbl
->key
); i
++)
580 gswip_switch_w(priv
, tbl
->key
[i
], GSWIP_PCE_TBL_KEY(i
));
582 for (i
= 0; i
< ARRAY_SIZE(tbl
->val
); i
++)
583 gswip_switch_w(priv
, tbl
->val
[i
], GSWIP_PCE_TBL_VAL(i
));
585 gswip_switch_mask(priv
, GSWIP_PCE_TBL_CTRL_ADDR_MASK
|
586 GSWIP_PCE_TBL_CTRL_OPMOD_MASK
,
587 tbl
->table
| addr_mode
,
590 gswip_switch_w(priv
, tbl
->mask
, GSWIP_PCE_TBL_MASK
);
592 crtl
= gswip_switch_r(priv
, GSWIP_PCE_TBL_CTRL
);
593 crtl
&= ~(GSWIP_PCE_TBL_CTRL_TYPE
| GSWIP_PCE_TBL_CTRL_VLD
|
594 GSWIP_PCE_TBL_CTRL_GMAP_MASK
);
596 crtl
|= GSWIP_PCE_TBL_CTRL_TYPE
;
598 crtl
|= GSWIP_PCE_TBL_CTRL_VLD
;
599 crtl
|= (tbl
->gmap
<< 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK
;
600 crtl
|= GSWIP_PCE_TBL_CTRL_BAS
;
601 gswip_switch_w(priv
, crtl
, GSWIP_PCE_TBL_CTRL
);
603 return gswip_switch_r_timeout(priv
, GSWIP_PCE_TBL_CTRL
,
604 GSWIP_PCE_TBL_CTRL_BAS
);
607 /* Add the LAN port into a bridge with the CPU port by
608 * default. This prevents automatic forwarding of
609 * packages between the LAN ports when no explicit
610 * bridge is configured.
612 static int gswip_add_single_port_br(struct gswip_priv
*priv
, int port
, bool add
)
614 struct gswip_pce_table_entry vlan_active
= {0,};
615 struct gswip_pce_table_entry vlan_mapping
= {0,};
616 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
617 unsigned int max_ports
= priv
->hw_info
->max_ports
;
620 if (port
>= max_ports
) {
621 dev_err(priv
->dev
, "single port for %i supported\n", port
);
625 vlan_active
.index
= port
+ 1;
626 vlan_active
.table
= GSWIP_TABLE_ACTIVE_VLAN
;
627 vlan_active
.key
[0] = 0; /* vid */
628 vlan_active
.val
[0] = port
+ 1 /* fid */;
629 vlan_active
.valid
= add
;
630 err
= gswip_pce_table_entry_write(priv
, &vlan_active
);
632 dev_err(priv
->dev
, "failed to write active VLAN: %d\n", err
);
639 vlan_mapping
.index
= port
+ 1;
640 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
641 vlan_mapping
.val
[0] = 0 /* vid */;
642 vlan_mapping
.val
[1] = BIT(port
) | BIT(cpu_port
);
643 vlan_mapping
.val
[2] = 0;
644 err
= gswip_pce_table_entry_write(priv
, &vlan_mapping
);
646 dev_err(priv
->dev
, "failed to write VLAN mapping: %d\n", err
);
653 static int gswip_port_enable(struct dsa_switch
*ds
, int port
,
654 struct phy_device
*phydev
)
656 struct gswip_priv
*priv
= ds
->priv
;
659 if (!dsa_is_user_port(ds
, port
))
662 if (!dsa_is_cpu_port(ds
, port
)) {
663 err
= gswip_add_single_port_br(priv
, port
, true);
668 /* RMON Counter Enable for port */
669 gswip_switch_w(priv
, GSWIP_BM_PCFG_CNTEN
, GSWIP_BM_PCFGp(port
));
671 /* enable port fetch/store dma & VLAN Modification */
672 gswip_switch_mask(priv
, 0, GSWIP_FDMA_PCTRL_EN
|
673 GSWIP_FDMA_PCTRL_VLANMOD_BOTH
,
674 GSWIP_FDMA_PCTRLp(port
));
675 gswip_switch_mask(priv
, 0, GSWIP_SDMA_PCTRL_EN
,
676 GSWIP_SDMA_PCTRLp(port
));
678 if (!dsa_is_cpu_port(ds
, port
)) {
682 mdio_phy
= phydev
->mdio
.addr
& GSWIP_MDIO_PHY_ADDR_MASK
;
684 gswip_mdio_mask(priv
, GSWIP_MDIO_PHY_ADDR_MASK
, mdio_phy
,
685 GSWIP_MDIO_PHYp(port
));
691 static void gswip_port_disable(struct dsa_switch
*ds
, int port
)
693 struct gswip_priv
*priv
= ds
->priv
;
695 if (!dsa_is_user_port(ds
, port
))
698 gswip_switch_mask(priv
, GSWIP_FDMA_PCTRL_EN
, 0,
699 GSWIP_FDMA_PCTRLp(port
));
700 gswip_switch_mask(priv
, GSWIP_SDMA_PCTRL_EN
, 0,
701 GSWIP_SDMA_PCTRLp(port
));
704 static int gswip_pce_load_microcode(struct gswip_priv
*priv
)
709 gswip_switch_mask(priv
, GSWIP_PCE_TBL_CTRL_ADDR_MASK
|
710 GSWIP_PCE_TBL_CTRL_OPMOD_MASK
,
711 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR
, GSWIP_PCE_TBL_CTRL
);
712 gswip_switch_w(priv
, 0, GSWIP_PCE_TBL_MASK
);
714 for (i
= 0; i
< ARRAY_SIZE(gswip_pce_microcode
); i
++) {
715 gswip_switch_w(priv
, i
, GSWIP_PCE_TBL_ADDR
);
716 gswip_switch_w(priv
, gswip_pce_microcode
[i
].val_0
,
717 GSWIP_PCE_TBL_VAL(0));
718 gswip_switch_w(priv
, gswip_pce_microcode
[i
].val_1
,
719 GSWIP_PCE_TBL_VAL(1));
720 gswip_switch_w(priv
, gswip_pce_microcode
[i
].val_2
,
721 GSWIP_PCE_TBL_VAL(2));
722 gswip_switch_w(priv
, gswip_pce_microcode
[i
].val_3
,
723 GSWIP_PCE_TBL_VAL(3));
725 /* start the table access: */
726 gswip_switch_mask(priv
, 0, GSWIP_PCE_TBL_CTRL_BAS
,
728 err
= gswip_switch_r_timeout(priv
, GSWIP_PCE_TBL_CTRL
,
729 GSWIP_PCE_TBL_CTRL_BAS
);
734 /* tell the switch that the microcode is loaded */
735 gswip_switch_mask(priv
, 0, GSWIP_PCE_GCTRL_0_MC_VALID
,
741 static int gswip_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
743 struct netlink_ext_ack
*extack
)
745 struct net_device
*bridge
= dsa_to_port(ds
, port
)->bridge_dev
;
746 struct gswip_priv
*priv
= ds
->priv
;
748 /* Do not allow changing the VLAN filtering options while in bridge */
749 if (bridge
&& !!(priv
->port_vlan_filter
& BIT(port
)) != vlan_filtering
) {
750 NL_SET_ERR_MSG_MOD(extack
,
751 "Dynamic toggling of vlan_filtering not supported");
755 if (vlan_filtering
) {
756 /* Use port based VLAN tag */
757 gswip_switch_mask(priv
,
759 GSWIP_PCE_VCTRL_UVR
| GSWIP_PCE_VCTRL_VIMR
|
760 GSWIP_PCE_VCTRL_VEMR
,
761 GSWIP_PCE_VCTRL(port
));
762 gswip_switch_mask(priv
, GSWIP_PCE_PCTRL_0_TVM
, 0,
763 GSWIP_PCE_PCTRL_0p(port
));
765 /* Use port based VLAN tag */
766 gswip_switch_mask(priv
,
767 GSWIP_PCE_VCTRL_UVR
| GSWIP_PCE_VCTRL_VIMR
|
768 GSWIP_PCE_VCTRL_VEMR
,
770 GSWIP_PCE_VCTRL(port
));
771 gswip_switch_mask(priv
, 0, GSWIP_PCE_PCTRL_0_TVM
,
772 GSWIP_PCE_PCTRL_0p(port
));
778 static int gswip_setup(struct dsa_switch
*ds
)
780 struct gswip_priv
*priv
= ds
->priv
;
781 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
785 gswip_switch_w(priv
, GSWIP_SWRES_R0
, GSWIP_SWRES
);
786 usleep_range(5000, 10000);
787 gswip_switch_w(priv
, 0, GSWIP_SWRES
);
789 /* disable port fetch/store dma on all ports */
790 for (i
= 0; i
< priv
->hw_info
->max_ports
; i
++) {
791 gswip_port_disable(ds
, i
);
792 gswip_port_vlan_filtering(ds
, i
, false, NULL
);
796 gswip_mdio_mask(priv
, 0, GSWIP_MDIO_GLOB_ENABLE
, GSWIP_MDIO_GLOB
);
798 err
= gswip_pce_load_microcode(priv
);
800 dev_err(priv
->dev
, "writing PCE microcode failed, %i", err
);
804 /* Default unknown Broadcast/Multicast/Unicast port maps */
805 gswip_switch_w(priv
, BIT(cpu_port
), GSWIP_PCE_PMAP1
);
806 gswip_switch_w(priv
, BIT(cpu_port
), GSWIP_PCE_PMAP2
);
807 gswip_switch_w(priv
, BIT(cpu_port
), GSWIP_PCE_PMAP3
);
809 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
810 * interoperability problem with this auto polling mechanism because
811 * their status registers think that the link is in a different state
812 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
813 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
814 * auto polling state machine consider the link being negotiated with
815 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
816 * to the switch port being completely dead (RX and TX are both not
818 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
819 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
820 * it would work fine for a few minutes to hours and then stop, on
821 * other device it would no traffic could be sent or received at all.
822 * Testing shows that when PHY auto polling is disabled these problems
825 gswip_mdio_w(priv
, 0x0, GSWIP_MDIO_MDC_CFG0
);
827 /* Configure the MDIO Clock 2.5 MHz */
828 gswip_mdio_mask(priv
, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1
);
830 /* Disable the xMII interface and clear it's isolation bit */
831 for (i
= 0; i
< priv
->hw_info
->max_ports
; i
++)
832 gswip_mii_mask_cfg(priv
,
833 GSWIP_MII_CFG_EN
| GSWIP_MII_CFG_ISOLATE
,
836 /* enable special tag insertion on cpu port */
837 gswip_switch_mask(priv
, 0, GSWIP_FDMA_PCTRL_STEN
,
838 GSWIP_FDMA_PCTRLp(cpu_port
));
840 /* accept special tag in ingress direction */
841 gswip_switch_mask(priv
, 0, GSWIP_PCE_PCTRL_0_INGRESS
,
842 GSWIP_PCE_PCTRL_0p(cpu_port
));
844 gswip_switch_mask(priv
, 0, GSWIP_MAC_CTRL_2_MLEN
,
845 GSWIP_MAC_CTRL_2p(cpu_port
));
846 gswip_switch_w(priv
, VLAN_ETH_FRAME_LEN
+ 8 + ETH_FCS_LEN
,
848 gswip_switch_mask(priv
, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD
,
849 GSWIP_BM_QUEUE_GCTRL
);
851 /* VLAN aware Switching */
852 gswip_switch_mask(priv
, 0, GSWIP_PCE_GCTRL_0_VLAN
, GSWIP_PCE_GCTRL_0
);
854 /* Flush MAC Table */
855 gswip_switch_mask(priv
, 0, GSWIP_PCE_GCTRL_0_MTFL
, GSWIP_PCE_GCTRL_0
);
857 err
= gswip_switch_r_timeout(priv
, GSWIP_PCE_GCTRL_0
,
858 GSWIP_PCE_GCTRL_0_MTFL
);
860 dev_err(priv
->dev
, "MAC flushing didn't finish\n");
864 gswip_port_enable(ds
, cpu_port
, NULL
);
866 ds
->configure_vlan_while_not_filtering
= false;
871 static enum dsa_tag_protocol
gswip_get_tag_protocol(struct dsa_switch
*ds
,
873 enum dsa_tag_protocol mp
)
875 return DSA_TAG_PROTO_GSWIP
;
878 static int gswip_vlan_active_create(struct gswip_priv
*priv
,
879 struct net_device
*bridge
,
882 struct gswip_pce_table_entry vlan_active
= {0,};
883 unsigned int max_ports
= priv
->hw_info
->max_ports
;
888 /* Look for a free slot */
889 for (i
= max_ports
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
890 if (!priv
->vlans
[i
].bridge
) {
902 vlan_active
.index
= idx
;
903 vlan_active
.table
= GSWIP_TABLE_ACTIVE_VLAN
;
904 vlan_active
.key
[0] = vid
;
905 vlan_active
.val
[0] = fid
;
906 vlan_active
.valid
= true;
908 err
= gswip_pce_table_entry_write(priv
, &vlan_active
);
910 dev_err(priv
->dev
, "failed to write active VLAN: %d\n", err
);
914 priv
->vlans
[idx
].bridge
= bridge
;
915 priv
->vlans
[idx
].vid
= vid
;
916 priv
->vlans
[idx
].fid
= fid
;
921 static int gswip_vlan_active_remove(struct gswip_priv
*priv
, int idx
)
923 struct gswip_pce_table_entry vlan_active
= {0,};
926 vlan_active
.index
= idx
;
927 vlan_active
.table
= GSWIP_TABLE_ACTIVE_VLAN
;
928 vlan_active
.valid
= false;
929 err
= gswip_pce_table_entry_write(priv
, &vlan_active
);
931 dev_err(priv
->dev
, "failed to delete active VLAN: %d\n", err
);
932 priv
->vlans
[idx
].bridge
= NULL
;
937 static int gswip_vlan_add_unaware(struct gswip_priv
*priv
,
938 struct net_device
*bridge
, int port
)
940 struct gswip_pce_table_entry vlan_mapping
= {0,};
941 unsigned int max_ports
= priv
->hw_info
->max_ports
;
942 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
943 bool active_vlan_created
= false;
948 /* Check if there is already a page for this bridge */
949 for (i
= max_ports
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
950 if (priv
->vlans
[i
].bridge
== bridge
) {
956 /* If this bridge is not programmed yet, add a Active VLAN table
957 * entry in a free slot and prepare the VLAN mapping table entry.
960 idx
= gswip_vlan_active_create(priv
, bridge
, -1, 0);
963 active_vlan_created
= true;
965 vlan_mapping
.index
= idx
;
966 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
967 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
968 vlan_mapping
.val
[0] = 0;
970 /* Read the existing VLAN mapping entry from the switch */
971 vlan_mapping
.index
= idx
;
972 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
973 err
= gswip_pce_table_entry_read(priv
, &vlan_mapping
);
975 dev_err(priv
->dev
, "failed to read VLAN mapping: %d\n",
981 /* Update the VLAN mapping entry and write it to the switch */
982 vlan_mapping
.val
[1] |= BIT(cpu_port
);
983 vlan_mapping
.val
[1] |= BIT(port
);
984 err
= gswip_pce_table_entry_write(priv
, &vlan_mapping
);
986 dev_err(priv
->dev
, "failed to write VLAN mapping: %d\n", err
);
987 /* In case an Active VLAN was creaetd delete it again */
988 if (active_vlan_created
)
989 gswip_vlan_active_remove(priv
, idx
);
993 gswip_switch_w(priv
, 0, GSWIP_PCE_DEFPVID(port
));
997 static int gswip_vlan_add_aware(struct gswip_priv
*priv
,
998 struct net_device
*bridge
, int port
,
999 u16 vid
, bool untagged
,
1002 struct gswip_pce_table_entry vlan_mapping
= {0,};
1003 unsigned int max_ports
= priv
->hw_info
->max_ports
;
1004 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
1005 bool active_vlan_created
= false;
1011 /* Check if there is already a page for this bridge */
1012 for (i
= max_ports
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
1013 if (priv
->vlans
[i
].bridge
== bridge
) {
1014 if (fid
!= -1 && fid
!= priv
->vlans
[i
].fid
)
1015 dev_err(priv
->dev
, "one bridge with multiple flow ids\n");
1016 fid
= priv
->vlans
[i
].fid
;
1017 if (priv
->vlans
[i
].vid
== vid
) {
1024 /* If this bridge is not programmed yet, add a Active VLAN table
1025 * entry in a free slot and prepare the VLAN mapping table entry.
1028 idx
= gswip_vlan_active_create(priv
, bridge
, fid
, vid
);
1031 active_vlan_created
= true;
1033 vlan_mapping
.index
= idx
;
1034 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
1035 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1036 vlan_mapping
.val
[0] = vid
;
1038 /* Read the existing VLAN mapping entry from the switch */
1039 vlan_mapping
.index
= idx
;
1040 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
1041 err
= gswip_pce_table_entry_read(priv
, &vlan_mapping
);
1043 dev_err(priv
->dev
, "failed to read VLAN mapping: %d\n",
1049 vlan_mapping
.val
[0] = vid
;
1050 /* Update the VLAN mapping entry and write it to the switch */
1051 vlan_mapping
.val
[1] |= BIT(cpu_port
);
1052 vlan_mapping
.val
[2] |= BIT(cpu_port
);
1053 vlan_mapping
.val
[1] |= BIT(port
);
1055 vlan_mapping
.val
[2] &= ~BIT(port
);
1057 vlan_mapping
.val
[2] |= BIT(port
);
1058 err
= gswip_pce_table_entry_write(priv
, &vlan_mapping
);
1060 dev_err(priv
->dev
, "failed to write VLAN mapping: %d\n", err
);
1061 /* In case an Active VLAN was creaetd delete it again */
1062 if (active_vlan_created
)
1063 gswip_vlan_active_remove(priv
, idx
);
1068 gswip_switch_w(priv
, idx
, GSWIP_PCE_DEFPVID(port
));
1073 static int gswip_vlan_remove(struct gswip_priv
*priv
,
1074 struct net_device
*bridge
, int port
,
1075 u16 vid
, bool pvid
, bool vlan_aware
)
1077 struct gswip_pce_table_entry vlan_mapping
= {0,};
1078 unsigned int max_ports
= priv
->hw_info
->max_ports
;
1079 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
1084 /* Check if there is already a page for this bridge */
1085 for (i
= max_ports
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
1086 if (priv
->vlans
[i
].bridge
== bridge
&&
1087 (!vlan_aware
|| priv
->vlans
[i
].vid
== vid
)) {
1094 dev_err(priv
->dev
, "bridge to leave does not exists\n");
1098 vlan_mapping
.index
= idx
;
1099 vlan_mapping
.table
= GSWIP_TABLE_VLAN_MAPPING
;
1100 err
= gswip_pce_table_entry_read(priv
, &vlan_mapping
);
1102 dev_err(priv
->dev
, "failed to read VLAN mapping: %d\n", err
);
1106 vlan_mapping
.val
[1] &= ~BIT(port
);
1107 vlan_mapping
.val
[2] &= ~BIT(port
);
1108 err
= gswip_pce_table_entry_write(priv
, &vlan_mapping
);
1110 dev_err(priv
->dev
, "failed to write VLAN mapping: %d\n", err
);
1114 /* In case all ports are removed from the bridge, remove the VLAN */
1115 if ((vlan_mapping
.val
[1] & ~BIT(cpu_port
)) == 0) {
1116 err
= gswip_vlan_active_remove(priv
, idx
);
1118 dev_err(priv
->dev
, "failed to write active VLAN: %d\n",
1124 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1126 gswip_switch_w(priv
, 0, GSWIP_PCE_DEFPVID(port
));
1131 static int gswip_port_bridge_join(struct dsa_switch
*ds
, int port
,
1132 struct net_device
*bridge
)
1134 struct gswip_priv
*priv
= ds
->priv
;
1137 /* When the bridge uses VLAN filtering we have to configure VLAN
1138 * specific bridges. No bridge is configured here.
1140 if (!br_vlan_enabled(bridge
)) {
1141 err
= gswip_vlan_add_unaware(priv
, bridge
, port
);
1144 priv
->port_vlan_filter
&= ~BIT(port
);
1146 priv
->port_vlan_filter
|= BIT(port
);
1148 return gswip_add_single_port_br(priv
, port
, false);
1151 static void gswip_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1152 struct net_device
*bridge
)
1154 struct gswip_priv
*priv
= ds
->priv
;
1156 gswip_add_single_port_br(priv
, port
, true);
1158 /* When the bridge uses VLAN filtering we have to configure VLAN
1159 * specific bridges. No bridge is configured here.
1161 if (!br_vlan_enabled(bridge
))
1162 gswip_vlan_remove(priv
, bridge
, port
, 0, true, false);
1165 static int gswip_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1166 const struct switchdev_obj_port_vlan
*vlan
,
1167 struct netlink_ext_ack
*extack
)
1169 struct gswip_priv
*priv
= ds
->priv
;
1170 struct net_device
*bridge
= dsa_to_port(ds
, port
)->bridge_dev
;
1171 unsigned int max_ports
= priv
->hw_info
->max_ports
;
1172 int pos
= max_ports
;
1175 /* We only support VLAN filtering on bridges */
1176 if (!dsa_is_cpu_port(ds
, port
) && !bridge
)
1179 /* Check if there is already a page for this VLAN */
1180 for (i
= max_ports
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
1181 if (priv
->vlans
[i
].bridge
== bridge
&&
1182 priv
->vlans
[i
].vid
== vlan
->vid
) {
1188 /* If this VLAN is not programmed yet, we have to reserve
1189 * one entry in the VLAN table. Make sure we start at the
1190 * next position round.
1193 /* Look for a free slot */
1194 for (; pos
< ARRAY_SIZE(priv
->vlans
); pos
++) {
1195 if (!priv
->vlans
[pos
].bridge
) {
1203 NL_SET_ERR_MSG_MOD(extack
, "No slot in VLAN table");
1211 static int gswip_port_vlan_add(struct dsa_switch
*ds
, int port
,
1212 const struct switchdev_obj_port_vlan
*vlan
,
1213 struct netlink_ext_ack
*extack
)
1215 struct gswip_priv
*priv
= ds
->priv
;
1216 struct net_device
*bridge
= dsa_to_port(ds
, port
)->bridge_dev
;
1217 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1218 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1221 err
= gswip_port_vlan_prepare(ds
, port
, vlan
, extack
);
1225 /* We have to receive all packets on the CPU port and should not
1226 * do any VLAN filtering here. This is also called with bridge
1227 * NULL and then we do not know for which bridge to configure
1230 if (dsa_is_cpu_port(ds
, port
))
1233 return gswip_vlan_add_aware(priv
, bridge
, port
, vlan
->vid
,
1237 static int gswip_port_vlan_del(struct dsa_switch
*ds
, int port
,
1238 const struct switchdev_obj_port_vlan
*vlan
)
1240 struct gswip_priv
*priv
= ds
->priv
;
1241 struct net_device
*bridge
= dsa_to_port(ds
, port
)->bridge_dev
;
1242 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1244 /* We have to receive all packets on the CPU port and should not
1245 * do any VLAN filtering here. This is also called with bridge
1246 * NULL and then we do not know for which bridge to configure
1249 if (dsa_is_cpu_port(ds
, port
))
1252 return gswip_vlan_remove(priv
, bridge
, port
, vlan
->vid
, pvid
, true);
1255 static void gswip_port_fast_age(struct dsa_switch
*ds
, int port
)
1257 struct gswip_priv
*priv
= ds
->priv
;
1258 struct gswip_pce_table_entry mac_bridge
= {0,};
1262 for (i
= 0; i
< 2048; i
++) {
1263 mac_bridge
.table
= GSWIP_TABLE_MAC_BRIDGE
;
1264 mac_bridge
.index
= i
;
1266 err
= gswip_pce_table_entry_read(priv
, &mac_bridge
);
1268 dev_err(priv
->dev
, "failed to read mac bridge: %d\n",
1273 if (!mac_bridge
.valid
)
1276 if (mac_bridge
.val
[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC
)
1279 if (((mac_bridge
.val
[0] & GENMASK(7, 4)) >> 4) != port
)
1282 mac_bridge
.valid
= false;
1283 err
= gswip_pce_table_entry_write(priv
, &mac_bridge
);
1285 dev_err(priv
->dev
, "failed to write mac bridge: %d\n",
1292 static void gswip_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1294 struct gswip_priv
*priv
= ds
->priv
;
1298 case BR_STATE_DISABLED
:
1299 gswip_switch_mask(priv
, GSWIP_SDMA_PCTRL_EN
, 0,
1300 GSWIP_SDMA_PCTRLp(port
));
1302 case BR_STATE_BLOCKING
:
1303 case BR_STATE_LISTENING
:
1304 stp_state
= GSWIP_PCE_PCTRL_0_PSTATE_LISTEN
;
1306 case BR_STATE_LEARNING
:
1307 stp_state
= GSWIP_PCE_PCTRL_0_PSTATE_LEARNING
;
1309 case BR_STATE_FORWARDING
:
1310 stp_state
= GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING
;
1313 dev_err(priv
->dev
, "invalid STP state: %d\n", state
);
1317 gswip_switch_mask(priv
, 0, GSWIP_SDMA_PCTRL_EN
,
1318 GSWIP_SDMA_PCTRLp(port
));
1319 gswip_switch_mask(priv
, GSWIP_PCE_PCTRL_0_PSTATE_MASK
, stp_state
,
1320 GSWIP_PCE_PCTRL_0p(port
));
1323 static int gswip_port_fdb(struct dsa_switch
*ds
, int port
,
1324 const unsigned char *addr
, u16 vid
, bool add
)
1326 struct gswip_priv
*priv
= ds
->priv
;
1327 struct net_device
*bridge
= dsa_to_port(ds
, port
)->bridge_dev
;
1328 struct gswip_pce_table_entry mac_bridge
= {0,};
1329 unsigned int cpu_port
= priv
->hw_info
->cpu_port
;
1337 for (i
= cpu_port
; i
< ARRAY_SIZE(priv
->vlans
); i
++) {
1338 if (priv
->vlans
[i
].bridge
== bridge
) {
1339 fid
= priv
->vlans
[i
].fid
;
1345 dev_err(priv
->dev
, "Port not part of a bridge\n");
1349 mac_bridge
.table
= GSWIP_TABLE_MAC_BRIDGE
;
1350 mac_bridge
.key_mode
= true;
1351 mac_bridge
.key
[0] = addr
[5] | (addr
[4] << 8);
1352 mac_bridge
.key
[1] = addr
[3] | (addr
[2] << 8);
1353 mac_bridge
.key
[2] = addr
[1] | (addr
[0] << 8);
1354 mac_bridge
.key
[3] = fid
;
1355 mac_bridge
.val
[0] = add
? BIT(port
) : 0; /* port map */
1356 mac_bridge
.val
[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC
;
1357 mac_bridge
.valid
= add
;
1359 err
= gswip_pce_table_entry_write(priv
, &mac_bridge
);
1361 dev_err(priv
->dev
, "failed to write mac bridge: %d\n", err
);
1366 static int gswip_port_fdb_add(struct dsa_switch
*ds
, int port
,
1367 const unsigned char *addr
, u16 vid
)
1369 return gswip_port_fdb(ds
, port
, addr
, vid
, true);
1372 static int gswip_port_fdb_del(struct dsa_switch
*ds
, int port
,
1373 const unsigned char *addr
, u16 vid
)
1375 return gswip_port_fdb(ds
, port
, addr
, vid
, false);
1378 static int gswip_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1379 dsa_fdb_dump_cb_t
*cb
, void *data
)
1381 struct gswip_priv
*priv
= ds
->priv
;
1382 struct gswip_pce_table_entry mac_bridge
= {0,};
1383 unsigned char addr
[6];
1387 for (i
= 0; i
< 2048; i
++) {
1388 mac_bridge
.table
= GSWIP_TABLE_MAC_BRIDGE
;
1389 mac_bridge
.index
= i
;
1391 err
= gswip_pce_table_entry_read(priv
, &mac_bridge
);
1393 dev_err(priv
->dev
, "failed to write mac bridge: %d\n",
1398 if (!mac_bridge
.valid
)
1401 addr
[5] = mac_bridge
.key
[0] & 0xff;
1402 addr
[4] = (mac_bridge
.key
[0] >> 8) & 0xff;
1403 addr
[3] = mac_bridge
.key
[1] & 0xff;
1404 addr
[2] = (mac_bridge
.key
[1] >> 8) & 0xff;
1405 addr
[1] = mac_bridge
.key
[2] & 0xff;
1406 addr
[0] = (mac_bridge
.key
[2] >> 8) & 0xff;
1407 if (mac_bridge
.val
[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC
) {
1408 if (mac_bridge
.val
[0] & BIT(port
)) {
1409 err
= cb(addr
, 0, true, data
);
1414 if (((mac_bridge
.val
[0] & GENMASK(7, 4)) >> 4) == port
) {
1415 err
= cb(addr
, 0, false, data
);
1424 static void gswip_phylink_set_capab(unsigned long *supported
,
1425 struct phylink_link_state
*state
)
1427 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1429 /* Allow all the expected bits */
1430 phylink_set(mask
, Autoneg
);
1431 phylink_set_port_modes(mask
);
1432 phylink_set(mask
, Pause
);
1433 phylink_set(mask
, Asym_Pause
);
1435 /* With the exclusion of MII, Reverse MII and Reduced MII, we
1436 * support Gigabit, including Half duplex
1438 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1439 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
1440 state
->interface
!= PHY_INTERFACE_MODE_RMII
) {
1441 phylink_set(mask
, 1000baseT_Full
);
1442 phylink_set(mask
, 1000baseT_Half
);
1445 phylink_set(mask
, 10baseT_Half
);
1446 phylink_set(mask
, 10baseT_Full
);
1447 phylink_set(mask
, 100baseT_Half
);
1448 phylink_set(mask
, 100baseT_Full
);
1450 bitmap_and(supported
, supported
, mask
,
1451 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1452 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1453 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1456 static void gswip_xrx200_phylink_validate(struct dsa_switch
*ds
, int port
,
1457 unsigned long *supported
,
1458 struct phylink_link_state
*state
)
1463 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1464 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1465 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
1466 state
->interface
!= PHY_INTERFACE_MODE_RMII
)
1472 if (state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1476 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1477 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1481 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1482 dev_err(ds
->dev
, "Unsupported port: %i\n", port
);
1486 gswip_phylink_set_capab(supported
, state
);
1491 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1492 dev_err(ds
->dev
, "Unsupported interface '%s' for port %d\n",
1493 phy_modes(state
->interface
), port
);
1496 static void gswip_xrx300_phylink_validate(struct dsa_switch
*ds
, int port
,
1497 unsigned long *supported
,
1498 struct phylink_link_state
*state
)
1502 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1503 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
1504 state
->interface
!= PHY_INTERFACE_MODE_RMII
)
1511 if (state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1515 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1516 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
1517 state
->interface
!= PHY_INTERFACE_MODE_RMII
)
1521 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1522 dev_err(ds
->dev
, "Unsupported port: %i\n", port
);
1526 gswip_phylink_set_capab(supported
, state
);
1531 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1532 dev_err(ds
->dev
, "Unsupported interface '%s' for port %d\n",
1533 phy_modes(state
->interface
), port
);
1536 static void gswip_port_set_link(struct gswip_priv
*priv
, int port
, bool link
)
1541 mdio_phy
= GSWIP_MDIO_PHY_LINK_UP
;
1543 mdio_phy
= GSWIP_MDIO_PHY_LINK_DOWN
;
1545 gswip_mdio_mask(priv
, GSWIP_MDIO_PHY_LINK_MASK
, mdio_phy
,
1546 GSWIP_MDIO_PHYp(port
));
1549 static void gswip_port_set_speed(struct gswip_priv
*priv
, int port
, int speed
,
1550 phy_interface_t interface
)
1552 u32 mdio_phy
= 0, mii_cfg
= 0, mac_ctrl_0
= 0;
1556 mdio_phy
= GSWIP_MDIO_PHY_SPEED_M10
;
1558 if (interface
== PHY_INTERFACE_MODE_RMII
)
1559 mii_cfg
= GSWIP_MII_CFG_RATE_M50
;
1561 mii_cfg
= GSWIP_MII_CFG_RATE_M2P5
;
1563 mac_ctrl_0
= GSWIP_MAC_CTRL_0_GMII_MII
;
1567 mdio_phy
= GSWIP_MDIO_PHY_SPEED_M100
;
1569 if (interface
== PHY_INTERFACE_MODE_RMII
)
1570 mii_cfg
= GSWIP_MII_CFG_RATE_M50
;
1572 mii_cfg
= GSWIP_MII_CFG_RATE_M25
;
1574 mac_ctrl_0
= GSWIP_MAC_CTRL_0_GMII_MII
;
1578 mdio_phy
= GSWIP_MDIO_PHY_SPEED_G1
;
1580 mii_cfg
= GSWIP_MII_CFG_RATE_M125
;
1582 mac_ctrl_0
= GSWIP_MAC_CTRL_0_GMII_RGMII
;
1586 gswip_mdio_mask(priv
, GSWIP_MDIO_PHY_SPEED_MASK
, mdio_phy
,
1587 GSWIP_MDIO_PHYp(port
));
1588 gswip_mii_mask_cfg(priv
, GSWIP_MII_CFG_RATE_MASK
, mii_cfg
, port
);
1589 gswip_switch_mask(priv
, GSWIP_MAC_CTRL_0_GMII_MASK
, mac_ctrl_0
,
1590 GSWIP_MAC_CTRL_0p(port
));
1593 static void gswip_port_set_duplex(struct gswip_priv
*priv
, int port
, int duplex
)
1595 u32 mac_ctrl_0
, mdio_phy
;
1597 if (duplex
== DUPLEX_FULL
) {
1598 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FDUP_EN
;
1599 mdio_phy
= GSWIP_MDIO_PHY_FDUP_EN
;
1601 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FDUP_DIS
;
1602 mdio_phy
= GSWIP_MDIO_PHY_FDUP_DIS
;
1605 gswip_switch_mask(priv
, GSWIP_MAC_CTRL_0_FDUP_MASK
, mac_ctrl_0
,
1606 GSWIP_MAC_CTRL_0p(port
));
1607 gswip_mdio_mask(priv
, GSWIP_MDIO_PHY_FDUP_MASK
, mdio_phy
,
1608 GSWIP_MDIO_PHYp(port
));
1611 static void gswip_port_set_pause(struct gswip_priv
*priv
, int port
,
1612 bool tx_pause
, bool rx_pause
)
1614 u32 mac_ctrl_0
, mdio_phy
;
1616 if (tx_pause
&& rx_pause
) {
1617 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FCON_RXTX
;
1618 mdio_phy
= GSWIP_MDIO_PHY_FCONTX_EN
|
1619 GSWIP_MDIO_PHY_FCONRX_EN
;
1620 } else if (tx_pause
) {
1621 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FCON_TX
;
1622 mdio_phy
= GSWIP_MDIO_PHY_FCONTX_EN
|
1623 GSWIP_MDIO_PHY_FCONRX_DIS
;
1624 } else if (rx_pause
) {
1625 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FCON_RX
;
1626 mdio_phy
= GSWIP_MDIO_PHY_FCONTX_DIS
|
1627 GSWIP_MDIO_PHY_FCONRX_EN
;
1629 mac_ctrl_0
= GSWIP_MAC_CTRL_0_FCON_NONE
;
1630 mdio_phy
= GSWIP_MDIO_PHY_FCONTX_DIS
|
1631 GSWIP_MDIO_PHY_FCONRX_DIS
;
1634 gswip_switch_mask(priv
, GSWIP_MAC_CTRL_0_FCON_MASK
,
1635 mac_ctrl_0
, GSWIP_MAC_CTRL_0p(port
));
1636 gswip_mdio_mask(priv
,
1637 GSWIP_MDIO_PHY_FCONTX_MASK
|
1638 GSWIP_MDIO_PHY_FCONRX_MASK
,
1639 mdio_phy
, GSWIP_MDIO_PHYp(port
));
1642 static void gswip_phylink_mac_config(struct dsa_switch
*ds
, int port
,
1644 const struct phylink_link_state
*state
)
1646 struct gswip_priv
*priv
= ds
->priv
;
1649 miicfg
|= GSWIP_MII_CFG_LDCLKDIS
;
1651 switch (state
->interface
) {
1652 case PHY_INTERFACE_MODE_MII
:
1653 case PHY_INTERFACE_MODE_INTERNAL
:
1654 miicfg
|= GSWIP_MII_CFG_MODE_MIIM
;
1656 case PHY_INTERFACE_MODE_REVMII
:
1657 miicfg
|= GSWIP_MII_CFG_MODE_MIIP
;
1659 case PHY_INTERFACE_MODE_RMII
:
1660 miicfg
|= GSWIP_MII_CFG_MODE_RMIIM
;
1662 /* Configure the RMII clock as output: */
1663 miicfg
|= GSWIP_MII_CFG_RMII_CLK
;
1665 case PHY_INTERFACE_MODE_RGMII
:
1666 case PHY_INTERFACE_MODE_RGMII_ID
:
1667 case PHY_INTERFACE_MODE_RGMII_RXID
:
1668 case PHY_INTERFACE_MODE_RGMII_TXID
:
1669 miicfg
|= GSWIP_MII_CFG_MODE_RGMII
;
1671 case PHY_INTERFACE_MODE_GMII
:
1672 miicfg
|= GSWIP_MII_CFG_MODE_GMII
;
1676 "Unsupported interface: %d\n", state
->interface
);
1680 gswip_mii_mask_cfg(priv
,
1681 GSWIP_MII_CFG_MODE_MASK
| GSWIP_MII_CFG_RMII_CLK
|
1682 GSWIP_MII_CFG_RGMII_IBS
| GSWIP_MII_CFG_LDCLKDIS
,
1685 switch (state
->interface
) {
1686 case PHY_INTERFACE_MODE_RGMII_ID
:
1687 gswip_mii_mask_pcdu(priv
, GSWIP_MII_PCDU_TXDLY_MASK
|
1688 GSWIP_MII_PCDU_RXDLY_MASK
, 0, port
);
1690 case PHY_INTERFACE_MODE_RGMII_RXID
:
1691 gswip_mii_mask_pcdu(priv
, GSWIP_MII_PCDU_RXDLY_MASK
, 0, port
);
1693 case PHY_INTERFACE_MODE_RGMII_TXID
:
1694 gswip_mii_mask_pcdu(priv
, GSWIP_MII_PCDU_TXDLY_MASK
, 0, port
);
1701 static void gswip_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
1703 phy_interface_t interface
)
1705 struct gswip_priv
*priv
= ds
->priv
;
1707 gswip_mii_mask_cfg(priv
, GSWIP_MII_CFG_EN
, 0, port
);
1709 if (!dsa_is_cpu_port(ds
, port
))
1710 gswip_port_set_link(priv
, port
, false);
1713 static void gswip_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
1715 phy_interface_t interface
,
1716 struct phy_device
*phydev
,
1717 int speed
, int duplex
,
1718 bool tx_pause
, bool rx_pause
)
1720 struct gswip_priv
*priv
= ds
->priv
;
1722 if (!dsa_is_cpu_port(ds
, port
)) {
1723 gswip_port_set_link(priv
, port
, true);
1724 gswip_port_set_speed(priv
, port
, speed
, interface
);
1725 gswip_port_set_duplex(priv
, port
, duplex
);
1726 gswip_port_set_pause(priv
, port
, tx_pause
, rx_pause
);
1729 gswip_mii_mask_cfg(priv
, 0, GSWIP_MII_CFG_EN
, port
);
1732 static void gswip_get_strings(struct dsa_switch
*ds
, int port
, u32 stringset
,
1737 if (stringset
!= ETH_SS_STATS
)
1740 for (i
= 0; i
< ARRAY_SIZE(gswip_rmon_cnt
); i
++)
1741 strncpy(data
+ i
* ETH_GSTRING_LEN
, gswip_rmon_cnt
[i
].name
,
1745 static u32
gswip_bcm_ram_entry_read(struct gswip_priv
*priv
, u32 table
,
1751 gswip_switch_w(priv
, index
, GSWIP_BM_RAM_ADDR
);
1752 gswip_switch_mask(priv
, GSWIP_BM_RAM_CTRL_ADDR_MASK
|
1753 GSWIP_BM_RAM_CTRL_OPMOD
,
1754 table
| GSWIP_BM_RAM_CTRL_BAS
,
1757 err
= gswip_switch_r_timeout(priv
, GSWIP_BM_RAM_CTRL
,
1758 GSWIP_BM_RAM_CTRL_BAS
);
1760 dev_err(priv
->dev
, "timeout while reading table: %u, index: %u",
1765 result
= gswip_switch_r(priv
, GSWIP_BM_RAM_VAL(0));
1766 result
|= gswip_switch_r(priv
, GSWIP_BM_RAM_VAL(1)) << 16;
1771 static void gswip_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
1774 struct gswip_priv
*priv
= ds
->priv
;
1775 const struct gswip_rmon_cnt_desc
*rmon_cnt
;
1779 for (i
= 0; i
< ARRAY_SIZE(gswip_rmon_cnt
); i
++) {
1780 rmon_cnt
= &gswip_rmon_cnt
[i
];
1782 data
[i
] = gswip_bcm_ram_entry_read(priv
, port
,
1784 if (rmon_cnt
->size
== 2) {
1785 high
= gswip_bcm_ram_entry_read(priv
, port
,
1786 rmon_cnt
->offset
+ 1);
1787 data
[i
] |= high
<< 32;
1792 static int gswip_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
1794 if (sset
!= ETH_SS_STATS
)
1797 return ARRAY_SIZE(gswip_rmon_cnt
);
1800 static const struct dsa_switch_ops gswip_xrx200_switch_ops
= {
1801 .get_tag_protocol
= gswip_get_tag_protocol
,
1802 .setup
= gswip_setup
,
1803 .port_enable
= gswip_port_enable
,
1804 .port_disable
= gswip_port_disable
,
1805 .port_bridge_join
= gswip_port_bridge_join
,
1806 .port_bridge_leave
= gswip_port_bridge_leave
,
1807 .port_fast_age
= gswip_port_fast_age
,
1808 .port_vlan_filtering
= gswip_port_vlan_filtering
,
1809 .port_vlan_add
= gswip_port_vlan_add
,
1810 .port_vlan_del
= gswip_port_vlan_del
,
1811 .port_stp_state_set
= gswip_port_stp_state_set
,
1812 .port_fdb_add
= gswip_port_fdb_add
,
1813 .port_fdb_del
= gswip_port_fdb_del
,
1814 .port_fdb_dump
= gswip_port_fdb_dump
,
1815 .phylink_validate
= gswip_xrx200_phylink_validate
,
1816 .phylink_mac_config
= gswip_phylink_mac_config
,
1817 .phylink_mac_link_down
= gswip_phylink_mac_link_down
,
1818 .phylink_mac_link_up
= gswip_phylink_mac_link_up
,
1819 .get_strings
= gswip_get_strings
,
1820 .get_ethtool_stats
= gswip_get_ethtool_stats
,
1821 .get_sset_count
= gswip_get_sset_count
,
1824 static const struct dsa_switch_ops gswip_xrx300_switch_ops
= {
1825 .get_tag_protocol
= gswip_get_tag_protocol
,
1826 .setup
= gswip_setup
,
1827 .port_enable
= gswip_port_enable
,
1828 .port_disable
= gswip_port_disable
,
1829 .port_bridge_join
= gswip_port_bridge_join
,
1830 .port_bridge_leave
= gswip_port_bridge_leave
,
1831 .port_fast_age
= gswip_port_fast_age
,
1832 .port_vlan_filtering
= gswip_port_vlan_filtering
,
1833 .port_vlan_add
= gswip_port_vlan_add
,
1834 .port_vlan_del
= gswip_port_vlan_del
,
1835 .port_stp_state_set
= gswip_port_stp_state_set
,
1836 .port_fdb_add
= gswip_port_fdb_add
,
1837 .port_fdb_del
= gswip_port_fdb_del
,
1838 .port_fdb_dump
= gswip_port_fdb_dump
,
1839 .phylink_validate
= gswip_xrx300_phylink_validate
,
1840 .phylink_mac_config
= gswip_phylink_mac_config
,
1841 .phylink_mac_link_down
= gswip_phylink_mac_link_down
,
1842 .phylink_mac_link_up
= gswip_phylink_mac_link_up
,
1843 .get_strings
= gswip_get_strings
,
1844 .get_ethtool_stats
= gswip_get_ethtool_stats
,
1845 .get_sset_count
= gswip_get_sset_count
,
1848 static const struct xway_gphy_match_data xrx200a1x_gphy_data
= {
1849 .fe_firmware_name
= "lantiq/xrx200_phy22f_a14.bin",
1850 .ge_firmware_name
= "lantiq/xrx200_phy11g_a14.bin",
1853 static const struct xway_gphy_match_data xrx200a2x_gphy_data
= {
1854 .fe_firmware_name
= "lantiq/xrx200_phy22f_a22.bin",
1855 .ge_firmware_name
= "lantiq/xrx200_phy11g_a22.bin",
1858 static const struct xway_gphy_match_data xrx300_gphy_data
= {
1859 .fe_firmware_name
= "lantiq/xrx300_phy22f_a21.bin",
1860 .ge_firmware_name
= "lantiq/xrx300_phy11g_a21.bin",
1863 static const struct of_device_id xway_gphy_match
[] = {
1864 { .compatible
= "lantiq,xrx200-gphy-fw", .data
= NULL
},
1865 { .compatible
= "lantiq,xrx200a1x-gphy-fw", .data
= &xrx200a1x_gphy_data
},
1866 { .compatible
= "lantiq,xrx200a2x-gphy-fw", .data
= &xrx200a2x_gphy_data
},
1867 { .compatible
= "lantiq,xrx300-gphy-fw", .data
= &xrx300_gphy_data
},
1868 { .compatible
= "lantiq,xrx330-gphy-fw", .data
= &xrx300_gphy_data
},
1872 static int gswip_gphy_fw_load(struct gswip_priv
*priv
, struct gswip_gphy_fw
*gphy_fw
)
1874 struct device
*dev
= priv
->dev
;
1875 const struct firmware
*fw
;
1877 dma_addr_t dma_addr
;
1878 dma_addr_t dev_addr
;
1882 ret
= clk_prepare_enable(gphy_fw
->clk_gate
);
1886 reset_control_assert(gphy_fw
->reset
);
1888 /* The vendor BSP uses a 200ms delay after asserting the reset line.
1889 * Without this some users are observing that the PHY is not coming up
1894 ret
= request_firmware(&fw
, gphy_fw
->fw_name
, dev
);
1896 dev_err(dev
, "failed to load firmware: %s, error: %i\n",
1897 gphy_fw
->fw_name
, ret
);
1901 /* GPHY cores need the firmware code in a persistent and contiguous
1902 * memory area with a 16 kB boundary aligned start address.
1904 size
= fw
->size
+ XRX200_GPHY_FW_ALIGN
;
1906 fw_addr
= dmam_alloc_coherent(dev
, size
, &dma_addr
, GFP_KERNEL
);
1908 fw_addr
= PTR_ALIGN(fw_addr
, XRX200_GPHY_FW_ALIGN
);
1909 dev_addr
= ALIGN(dma_addr
, XRX200_GPHY_FW_ALIGN
);
1910 memcpy(fw_addr
, fw
->data
, fw
->size
);
1912 dev_err(dev
, "failed to alloc firmware memory\n");
1913 release_firmware(fw
);
1917 release_firmware(fw
);
1919 ret
= regmap_write(priv
->rcu_regmap
, gphy_fw
->fw_addr_offset
, dev_addr
);
1923 reset_control_deassert(gphy_fw
->reset
);
1928 static int gswip_gphy_fw_probe(struct gswip_priv
*priv
,
1929 struct gswip_gphy_fw
*gphy_fw
,
1930 struct device_node
*gphy_fw_np
, int i
)
1932 struct device
*dev
= priv
->dev
;
1937 snprintf(gphyname
, sizeof(gphyname
), "gphy%d", i
);
1939 gphy_fw
->clk_gate
= devm_clk_get(dev
, gphyname
);
1940 if (IS_ERR(gphy_fw
->clk_gate
)) {
1941 dev_err(dev
, "Failed to lookup gate clock\n");
1942 return PTR_ERR(gphy_fw
->clk_gate
);
1945 ret
= of_property_read_u32(gphy_fw_np
, "reg", &gphy_fw
->fw_addr_offset
);
1949 ret
= of_property_read_u32(gphy_fw_np
, "lantiq,gphy-mode", &gphy_mode
);
1950 /* Default to GE mode */
1952 gphy_mode
= GPHY_MODE_GE
;
1954 switch (gphy_mode
) {
1956 gphy_fw
->fw_name
= priv
->gphy_fw_name_cfg
->fe_firmware_name
;
1959 gphy_fw
->fw_name
= priv
->gphy_fw_name_cfg
->ge_firmware_name
;
1962 dev_err(dev
, "Unknown GPHY mode %d\n", gphy_mode
);
1966 gphy_fw
->reset
= of_reset_control_array_get_exclusive(gphy_fw_np
);
1967 if (IS_ERR(gphy_fw
->reset
)) {
1968 if (PTR_ERR(gphy_fw
->reset
) != -EPROBE_DEFER
)
1969 dev_err(dev
, "Failed to lookup gphy reset\n");
1970 return PTR_ERR(gphy_fw
->reset
);
1973 return gswip_gphy_fw_load(priv
, gphy_fw
);
1976 static void gswip_gphy_fw_remove(struct gswip_priv
*priv
,
1977 struct gswip_gphy_fw
*gphy_fw
)
1981 /* check if the device was fully probed */
1982 if (!gphy_fw
->fw_name
)
1985 ret
= regmap_write(priv
->rcu_regmap
, gphy_fw
->fw_addr_offset
, 0);
1987 dev_err(priv
->dev
, "can not reset GPHY FW pointer");
1989 clk_disable_unprepare(gphy_fw
->clk_gate
);
1991 reset_control_put(gphy_fw
->reset
);
1994 static int gswip_gphy_fw_list(struct gswip_priv
*priv
,
1995 struct device_node
*gphy_fw_list_np
, u32 version
)
1997 struct device
*dev
= priv
->dev
;
1998 struct device_node
*gphy_fw_np
;
1999 const struct of_device_id
*match
;
2003 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
2004 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
2005 * needs a different GPHY firmware.
2007 if (of_device_is_compatible(gphy_fw_list_np
, "lantiq,xrx200-gphy-fw")) {
2009 case GSWIP_VERSION_2_0
:
2010 priv
->gphy_fw_name_cfg
= &xrx200a1x_gphy_data
;
2012 case GSWIP_VERSION_2_1
:
2013 priv
->gphy_fw_name_cfg
= &xrx200a2x_gphy_data
;
2016 dev_err(dev
, "unknown GSWIP version: 0x%x", version
);
2021 match
= of_match_node(xway_gphy_match
, gphy_fw_list_np
);
2022 if (match
&& match
->data
)
2023 priv
->gphy_fw_name_cfg
= match
->data
;
2025 if (!priv
->gphy_fw_name_cfg
) {
2026 dev_err(dev
, "GPHY compatible type not supported");
2030 priv
->num_gphy_fw
= of_get_available_child_count(gphy_fw_list_np
);
2031 if (!priv
->num_gphy_fw
)
2034 priv
->rcu_regmap
= syscon_regmap_lookup_by_phandle(gphy_fw_list_np
,
2036 if (IS_ERR(priv
->rcu_regmap
))
2037 return PTR_ERR(priv
->rcu_regmap
);
2039 priv
->gphy_fw
= devm_kmalloc_array(dev
, priv
->num_gphy_fw
,
2040 sizeof(*priv
->gphy_fw
),
2041 GFP_KERNEL
| __GFP_ZERO
);
2045 for_each_available_child_of_node(gphy_fw_list_np
, gphy_fw_np
) {
2046 err
= gswip_gphy_fw_probe(priv
, &priv
->gphy_fw
[i
],
2053 /* The standalone PHY11G requires 300ms to be fully
2054 * initialized and ready for any MDIO communication after being
2055 * taken out of reset. For the SoC-internal GPHY variant there
2056 * is no (known) documentation for the minimum time after a
2057 * reset. Use the same value as for the standalone variant as
2058 * some users have reported internal PHYs not being detected
2059 * without any delay.
2066 for (i
= 0; i
< priv
->num_gphy_fw
; i
++)
2067 gswip_gphy_fw_remove(priv
, &priv
->gphy_fw
[i
]);
2071 static int gswip_probe(struct platform_device
*pdev
)
2073 struct gswip_priv
*priv
;
2074 struct device_node
*np
, *mdio_np
, *gphy_fw_np
;
2075 struct device
*dev
= &pdev
->dev
;
2080 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
2084 priv
->gswip
= devm_platform_ioremap_resource(pdev
, 0);
2085 if (IS_ERR(priv
->gswip
))
2086 return PTR_ERR(priv
->gswip
);
2088 priv
->mdio
= devm_platform_ioremap_resource(pdev
, 1);
2089 if (IS_ERR(priv
->mdio
))
2090 return PTR_ERR(priv
->mdio
);
2092 priv
->mii
= devm_platform_ioremap_resource(pdev
, 2);
2093 if (IS_ERR(priv
->mii
))
2094 return PTR_ERR(priv
->mii
);
2096 priv
->hw_info
= of_device_get_match_data(dev
);
2100 priv
->ds
= devm_kzalloc(dev
, sizeof(*priv
->ds
), GFP_KERNEL
);
2104 priv
->ds
->dev
= dev
;
2105 priv
->ds
->num_ports
= priv
->hw_info
->max_ports
;
2106 priv
->ds
->priv
= priv
;
2107 priv
->ds
->ops
= priv
->hw_info
->ops
;
2109 version
= gswip_switch_r(priv
, GSWIP_VERSION
);
2113 case GSWIP_VERSION_2_0
:
2114 case GSWIP_VERSION_2_1
:
2115 if (!of_device_is_compatible(np
, "lantiq,xrx200-gswip"))
2118 case GSWIP_VERSION_2_2
:
2119 case GSWIP_VERSION_2_2_ETC
:
2120 if (!of_device_is_compatible(np
, "lantiq,xrx300-gswip") &&
2121 !of_device_is_compatible(np
, "lantiq,xrx330-gswip"))
2125 dev_err(dev
, "unknown GSWIP version: 0x%x", version
);
2129 /* bring up the mdio bus */
2130 gphy_fw_np
= of_get_compatible_child(dev
->of_node
, "lantiq,gphy-fw");
2132 err
= gswip_gphy_fw_list(priv
, gphy_fw_np
, version
);
2133 of_node_put(gphy_fw_np
);
2135 dev_err(dev
, "gphy fw probe failed\n");
2140 /* bring up the mdio bus */
2141 mdio_np
= of_get_compatible_child(dev
->of_node
, "lantiq,xrx200-mdio");
2143 err
= gswip_mdio(priv
, mdio_np
);
2145 dev_err(dev
, "mdio probe failed\n");
2150 err
= dsa_register_switch(priv
->ds
);
2152 dev_err(dev
, "dsa switch register failed: %i\n", err
);
2155 if (!dsa_is_cpu_port(priv
->ds
, priv
->hw_info
->cpu_port
)) {
2156 dev_err(dev
, "wrong CPU port defined, HW only supports port: %i",
2157 priv
->hw_info
->cpu_port
);
2159 goto disable_switch
;
2162 platform_set_drvdata(pdev
, priv
);
2164 dev_info(dev
, "probed GSWIP version %lx mod %lx\n",
2165 (version
& GSWIP_VERSION_REV_MASK
) >> GSWIP_VERSION_REV_SHIFT
,
2166 (version
& GSWIP_VERSION_MOD_MASK
) >> GSWIP_VERSION_MOD_SHIFT
);
2170 gswip_mdio_mask(priv
, GSWIP_MDIO_GLOB_ENABLE
, 0, GSWIP_MDIO_GLOB
);
2171 dsa_unregister_switch(priv
->ds
);
2174 mdiobus_unregister(priv
->ds
->slave_mii_bus
);
2176 of_node_put(mdio_np
);
2177 for (i
= 0; i
< priv
->num_gphy_fw
; i
++)
2178 gswip_gphy_fw_remove(priv
, &priv
->gphy_fw
[i
]);
2182 static int gswip_remove(struct platform_device
*pdev
)
2184 struct gswip_priv
*priv
= platform_get_drvdata(pdev
);
2187 /* disable the switch */
2188 gswip_mdio_mask(priv
, GSWIP_MDIO_GLOB_ENABLE
, 0, GSWIP_MDIO_GLOB
);
2190 dsa_unregister_switch(priv
->ds
);
2192 if (priv
->ds
->slave_mii_bus
) {
2193 mdiobus_unregister(priv
->ds
->slave_mii_bus
);
2194 of_node_put(priv
->ds
->slave_mii_bus
->dev
.of_node
);
2197 for (i
= 0; i
< priv
->num_gphy_fw
; i
++)
2198 gswip_gphy_fw_remove(priv
, &priv
->gphy_fw
[i
]);
2203 static const struct gswip_hw_info gswip_xrx200
= {
2206 .ops
= &gswip_xrx200_switch_ops
,
2209 static const struct gswip_hw_info gswip_xrx300
= {
2212 .ops
= &gswip_xrx300_switch_ops
,
2215 static const struct of_device_id gswip_of_match
[] = {
2216 { .compatible
= "lantiq,xrx200-gswip", .data
= &gswip_xrx200
},
2217 { .compatible
= "lantiq,xrx300-gswip", .data
= &gswip_xrx300
},
2218 { .compatible
= "lantiq,xrx330-gswip", .data
= &gswip_xrx300
},
2221 MODULE_DEVICE_TABLE(of
, gswip_of_match
);
2223 static struct platform_driver gswip_driver
= {
2224 .probe
= gswip_probe
,
2225 .remove
= gswip_remove
,
2228 .of_match_table
= gswip_of_match
,
2232 module_platform_driver(gswip_driver
);
2234 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
2235 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
2236 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
2237 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
2238 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2239 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2240 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2241 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2242 MODULE_LICENSE("GPL v2");