2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/gpio/consumer.h>
34 /* String, offset, and register size in bytes if different from 4 bytes */
35 static const struct mt7530_mib_desc mt7530_mib
[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
79 mt7623_trgmii_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
83 ret
= regmap_write(priv
->ethernet
, TRGMII_BASE(reg
), val
);
86 "failed to priv write register\n");
91 mt7623_trgmii_read(struct mt7530_priv
*priv
, u32 reg
)
96 ret
= regmap_read(priv
->ethernet
, TRGMII_BASE(reg
), &val
);
99 "failed to priv read register\n");
107 mt7623_trgmii_rmw(struct mt7530_priv
*priv
, u32 reg
,
112 val
= mt7623_trgmii_read(priv
, reg
);
115 mt7623_trgmii_write(priv
, reg
, val
);
119 mt7623_trgmii_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
121 mt7623_trgmii_rmw(priv
, reg
, 0, val
);
125 mt7623_trgmii_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
127 mt7623_trgmii_rmw(priv
, reg
, val
, 0);
131 core_read_mmd_indirect(struct mt7530_priv
*priv
, int prtad
, int devad
)
133 struct mii_bus
*bus
= priv
->bus
;
136 /* Write the desired MMD Devad */
137 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, devad
);
141 /* Write the desired MMD register address */
142 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, prtad
);
146 /* Select the Function : DATA with no post increment */
147 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, (devad
| MII_MMD_CTRL_NOINCR
));
151 /* Read the content of the MMD's selected register */
152 value
= bus
->read(bus
, 0, MII_MMD_DATA
);
156 dev_err(&bus
->dev
, "failed to read mmd register\n");
162 core_write_mmd_indirect(struct mt7530_priv
*priv
, int prtad
,
165 struct mii_bus
*bus
= priv
->bus
;
168 /* Write the desired MMD Devad */
169 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, devad
);
173 /* Write the desired MMD register address */
174 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, prtad
);
178 /* Select the Function : DATA with no post increment */
179 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, (devad
| MII_MMD_CTRL_NOINCR
));
183 /* Write the data into MMD's selected register */
184 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, data
);
188 "failed to write mmd register\n");
193 core_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
195 struct mii_bus
*bus
= priv
->bus
;
197 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
199 core_write_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
, val
);
201 mutex_unlock(&bus
->mdio_lock
);
205 core_rmw(struct mt7530_priv
*priv
, u32 reg
, u32 mask
, u32 set
)
207 struct mii_bus
*bus
= priv
->bus
;
210 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
212 val
= core_read_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
);
215 core_write_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
, val
);
217 mutex_unlock(&bus
->mdio_lock
);
221 core_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
223 core_rmw(priv
, reg
, 0, val
);
227 core_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
229 core_rmw(priv
, reg
, val
, 0);
233 mt7530_mii_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
235 struct mii_bus
*bus
= priv
->bus
;
239 page
= (reg
>> 6) & 0x3ff;
240 r
= (reg
>> 2) & 0xf;
244 /* MT7530 uses 31 as the pseudo port */
245 ret
= bus
->write(bus
, 0x1f, 0x1f, page
);
249 ret
= bus
->write(bus
, 0x1f, r
, lo
);
253 ret
= bus
->write(bus
, 0x1f, 0x10, hi
);
257 "failed to write mt7530 register\n");
262 mt7530_mii_read(struct mt7530_priv
*priv
, u32 reg
)
264 struct mii_bus
*bus
= priv
->bus
;
268 page
= (reg
>> 6) & 0x3ff;
269 r
= (reg
>> 2) & 0xf;
271 /* MT7530 uses 31 as the pseudo port */
272 ret
= bus
->write(bus
, 0x1f, 0x1f, page
);
275 "failed to read mt7530 register\n");
279 lo
= bus
->read(bus
, 0x1f, r
);
280 hi
= bus
->read(bus
, 0x1f, 0x10);
282 return (hi
<< 16) | (lo
& 0xffff);
286 mt7530_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
288 struct mii_bus
*bus
= priv
->bus
;
290 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
292 mt7530_mii_write(priv
, reg
, val
);
294 mutex_unlock(&bus
->mdio_lock
);
298 _mt7530_read(struct mt7530_dummy_poll
*p
)
300 struct mii_bus
*bus
= p
->priv
->bus
;
303 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
305 val
= mt7530_mii_read(p
->priv
, p
->reg
);
307 mutex_unlock(&bus
->mdio_lock
);
313 mt7530_read(struct mt7530_priv
*priv
, u32 reg
)
315 struct mt7530_dummy_poll p
;
317 INIT_MT7530_DUMMY_POLL(&p
, priv
, reg
);
318 return _mt7530_read(&p
);
322 mt7530_rmw(struct mt7530_priv
*priv
, u32 reg
,
325 struct mii_bus
*bus
= priv
->bus
;
328 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
330 val
= mt7530_mii_read(priv
, reg
);
333 mt7530_mii_write(priv
, reg
, val
);
335 mutex_unlock(&bus
->mdio_lock
);
339 mt7530_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
341 mt7530_rmw(priv
, reg
, 0, val
);
345 mt7530_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
347 mt7530_rmw(priv
, reg
, val
, 0);
351 mt7530_fdb_cmd(struct mt7530_priv
*priv
, enum mt7530_fdb_cmd cmd
, u32
*rsp
)
355 struct mt7530_dummy_poll p
;
357 /* Set the command operating upon the MAC address entries */
358 val
= ATC_BUSY
| ATC_MAT(0) | cmd
;
359 mt7530_write(priv
, MT7530_ATC
, val
);
361 INIT_MT7530_DUMMY_POLL(&p
, priv
, MT7530_ATC
);
362 ret
= readx_poll_timeout(_mt7530_read
, &p
, val
,
363 !(val
& ATC_BUSY
), 20, 20000);
365 dev_err(priv
->dev
, "reset timeout\n");
369 /* Additional sanity for read command if the specified
372 val
= mt7530_read(priv
, MT7530_ATC
);
373 if ((cmd
== MT7530_FDB_READ
) && (val
& ATC_INVALID
))
383 mt7530_fdb_read(struct mt7530_priv
*priv
, struct mt7530_fdb
*fdb
)
388 /* Read from ARL table into an array */
389 for (i
= 0; i
< 3; i
++) {
390 reg
[i
] = mt7530_read(priv
, MT7530_TSRA1
+ (i
* 4));
392 dev_dbg(priv
->dev
, "%s(%d) reg[%d]=0x%x\n",
393 __func__
, __LINE__
, i
, reg
[i
]);
396 fdb
->vid
= (reg
[1] >> CVID
) & CVID_MASK
;
397 fdb
->aging
= (reg
[2] >> AGE_TIMER
) & AGE_TIMER_MASK
;
398 fdb
->port_mask
= (reg
[2] >> PORT_MAP
) & PORT_MAP_MASK
;
399 fdb
->mac
[0] = (reg
[0] >> MAC_BYTE_0
) & MAC_BYTE_MASK
;
400 fdb
->mac
[1] = (reg
[0] >> MAC_BYTE_1
) & MAC_BYTE_MASK
;
401 fdb
->mac
[2] = (reg
[0] >> MAC_BYTE_2
) & MAC_BYTE_MASK
;
402 fdb
->mac
[3] = (reg
[0] >> MAC_BYTE_3
) & MAC_BYTE_MASK
;
403 fdb
->mac
[4] = (reg
[1] >> MAC_BYTE_4
) & MAC_BYTE_MASK
;
404 fdb
->mac
[5] = (reg
[1] >> MAC_BYTE_5
) & MAC_BYTE_MASK
;
405 fdb
->noarp
= ((reg
[2] >> ENT_STATUS
) & ENT_STATUS_MASK
) == STATIC_ENT
;
409 mt7530_fdb_write(struct mt7530_priv
*priv
, u16 vid
,
410 u8 port_mask
, const u8
*mac
,
416 reg
[1] |= vid
& CVID_MASK
;
417 reg
[2] |= (aging
& AGE_TIMER_MASK
) << AGE_TIMER
;
418 reg
[2] |= (port_mask
& PORT_MAP_MASK
) << PORT_MAP
;
419 /* STATIC_ENT indicate that entry is static wouldn't
420 * be aged out and STATIC_EMP specified as erasing an
423 reg
[2] |= (type
& ENT_STATUS_MASK
) << ENT_STATUS
;
424 reg
[1] |= mac
[5] << MAC_BYTE_5
;
425 reg
[1] |= mac
[4] << MAC_BYTE_4
;
426 reg
[0] |= mac
[3] << MAC_BYTE_3
;
427 reg
[0] |= mac
[2] << MAC_BYTE_2
;
428 reg
[0] |= mac
[1] << MAC_BYTE_1
;
429 reg
[0] |= mac
[0] << MAC_BYTE_0
;
431 /* Write array into the ARL table */
432 for (i
= 0; i
< 3; i
++)
433 mt7530_write(priv
, MT7530_ATA1
+ (i
* 4), reg
[i
]);
437 mt7530_pad_clk_setup(struct dsa_switch
*ds
, int mode
)
439 struct mt7530_priv
*priv
= ds
->priv
;
440 u32 ncpo1
, ssc_delta
, trgint
, i
;
443 case PHY_INTERFACE_MODE_RGMII
:
448 case PHY_INTERFACE_MODE_TRGMII
:
454 dev_err(priv
->dev
, "xMII mode %d not supported\n", mode
);
458 mt7530_rmw(priv
, MT7530_P6ECR
, P6_INTF_MODE_MASK
,
459 P6_INTF_MODE(trgint
));
461 /* Lower Tx Driving for TRGMII path */
462 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
463 mt7530_write(priv
, MT7530_TRGMII_TD_ODT(i
),
464 TD_DM_DRVP(8) | TD_DM_DRVN(8));
466 /* Setup core clock for MT7530 */
468 /* Disable MT7530 core clock */
469 core_clear(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
471 /* Disable PLL, since phy_device has not yet been created
472 * provided for phy_[read,write]_mmd_indirect is called, we
473 * provide our own core_write_mmd_indirect to complete this
476 core_write_mmd_indirect(priv
,
481 /* Set core clock into 500Mhz */
482 core_write(priv
, CORE_GSWPLL_GRP2
,
483 RG_GSWPLL_POSDIV_500M(1) |
484 RG_GSWPLL_FBKDIV_500M(25));
487 core_write(priv
, CORE_GSWPLL_GRP1
,
489 RG_GSWPLL_POSDIV_200M(2) |
490 RG_GSWPLL_FBKDIV_200M(32));
492 /* Enable MT7530 core clock */
493 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
496 /* Setup the MT7530 TRGMII Tx Clock */
497 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
498 core_write(priv
, CORE_PLL_GROUP5
, RG_LCDDS_PCW_NCPO1(ncpo1
));
499 core_write(priv
, CORE_PLL_GROUP6
, RG_LCDDS_PCW_NCPO0(0));
500 core_write(priv
, CORE_PLL_GROUP10
, RG_LCDDS_SSC_DELTA(ssc_delta
));
501 core_write(priv
, CORE_PLL_GROUP11
, RG_LCDDS_SSC_DELTA1(ssc_delta
));
502 core_write(priv
, CORE_PLL_GROUP4
,
503 RG_SYSPLL_DDSFBK_EN
| RG_SYSPLL_BIAS_EN
|
504 RG_SYSPLL_BIAS_LPF_EN
);
505 core_write(priv
, CORE_PLL_GROUP2
,
506 RG_SYSPLL_EN_NORMAL
| RG_SYSPLL_VODEN
|
507 RG_SYSPLL_POSDIV(1));
508 core_write(priv
, CORE_PLL_GROUP7
,
509 RG_LCDDS_PCW_NCPO_CHG
| RG_LCCDS_C(3) |
510 RG_LCDDS_PWDB
| RG_LCDDS_ISO_EN
);
511 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
,
512 REG_GSWCK_EN
| REG_TRGMIICK_EN
);
515 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
516 mt7530_rmw(priv
, MT7530_TRGMII_RD(i
),
517 RD_TAP_MASK
, RD_TAP(16));
519 mt7623_trgmii_set(priv
, GSW_INTF_MODE
, INTF_MODE_TRGMII
);
525 mt7623_pad_clk_setup(struct dsa_switch
*ds
)
527 struct mt7530_priv
*priv
= ds
->priv
;
530 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
531 mt7623_trgmii_write(priv
, GSW_TRGMII_TD_ODT(i
),
532 TD_DM_DRVP(8) | TD_DM_DRVN(8));
534 mt7623_trgmii_set(priv
, GSW_TRGMII_RCK_CTRL
, RX_RST
| RXC_DQSISEL
);
535 mt7623_trgmii_clear(priv
, GSW_TRGMII_RCK_CTRL
, RX_RST
);
541 mt7530_mib_reset(struct dsa_switch
*ds
)
543 struct mt7530_priv
*priv
= ds
->priv
;
545 mt7530_write(priv
, MT7530_MIB_CCR
, CCR_MIB_FLUSH
);
546 mt7530_write(priv
, MT7530_MIB_CCR
, CCR_MIB_ACTIVATE
);
550 mt7530_port_set_status(struct mt7530_priv
*priv
, int port
, int enable
)
552 u32 mask
= PMCR_TX_EN
| PMCR_RX_EN
;
555 mt7530_set(priv
, MT7530_PMCR_P(port
), mask
);
557 mt7530_clear(priv
, MT7530_PMCR_P(port
), mask
);
560 static int mt7530_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
562 struct mt7530_priv
*priv
= ds
->priv
;
564 return mdiobus_read_nested(priv
->bus
, port
, regnum
);
567 static int mt7530_phy_write(struct dsa_switch
*ds
, int port
, int regnum
,
570 struct mt7530_priv
*priv
= ds
->priv
;
572 return mdiobus_write_nested(priv
->bus
, port
, regnum
, val
);
576 mt7530_get_strings(struct dsa_switch
*ds
, int port
, u32 stringset
,
581 if (stringset
!= ETH_SS_STATS
)
584 for (i
= 0; i
< ARRAY_SIZE(mt7530_mib
); i
++)
585 strncpy(data
+ i
* ETH_GSTRING_LEN
, mt7530_mib
[i
].name
,
590 mt7530_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
593 struct mt7530_priv
*priv
= ds
->priv
;
594 const struct mt7530_mib_desc
*mib
;
598 for (i
= 0; i
< ARRAY_SIZE(mt7530_mib
); i
++) {
599 mib
= &mt7530_mib
[i
];
600 reg
= MT7530_PORT_MIB_COUNTER(port
) + mib
->offset
;
602 data
[i
] = mt7530_read(priv
, reg
);
603 if (mib
->size
== 2) {
604 hi
= mt7530_read(priv
, reg
+ 4);
611 mt7530_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
613 if (sset
!= ETH_SS_STATS
)
616 return ARRAY_SIZE(mt7530_mib
);
619 static void mt7530_adjust_link(struct dsa_switch
*ds
, int port
,
620 struct phy_device
*phydev
)
622 struct mt7530_priv
*priv
= ds
->priv
;
624 if (phy_is_pseudo_fixed_link(phydev
)) {
625 dev_dbg(priv
->dev
, "phy-mode for master device = %x\n",
628 /* Setup TX circuit incluing relevant PAD and driving */
629 mt7530_pad_clk_setup(ds
, phydev
->interface
);
631 /* Setup RX circuit, relevant PAD and driving on the host
632 * which must be placed after the setup on the device side is
635 mt7623_pad_clk_setup(ds
);
637 u16 lcl_adv
= 0, rmt_adv
= 0;
639 u32 mcr
= PMCR_USERP_LINK
| PMCR_FORCE_MODE
;
641 switch (phydev
->speed
) {
643 mcr
|= PMCR_FORCE_SPEED_1000
;
646 mcr
|= PMCR_FORCE_SPEED_100
;
651 mcr
|= PMCR_FORCE_LNK
;
653 if (phydev
->duplex
) {
654 mcr
|= PMCR_FORCE_FDX
;
657 rmt_adv
= LPA_PAUSE_CAP
;
658 if (phydev
->asym_pause
)
659 rmt_adv
|= LPA_PAUSE_ASYM
;
661 lcl_adv
= linkmode_adv_to_lcl_adv_t(
662 phydev
->advertising
);
663 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
665 if (flowctrl
& FLOW_CTRL_TX
)
666 mcr
|= PMCR_TX_FC_EN
;
667 if (flowctrl
& FLOW_CTRL_RX
)
668 mcr
|= PMCR_RX_FC_EN
;
670 mt7530_write(priv
, MT7530_PMCR_P(port
), mcr
);
675 mt7530_cpu_port_enable(struct mt7530_priv
*priv
,
678 /* Enable Mediatek header mode on the cpu port */
679 mt7530_write(priv
, MT7530_PVC_P(port
),
682 /* Setup the MAC by default for the cpu port */
683 mt7530_write(priv
, MT7530_PMCR_P(port
), PMCR_CPUP_LINK
);
685 /* Disable auto learning on the cpu port */
686 mt7530_set(priv
, MT7530_PSC_P(port
), SA_DIS
);
688 /* Unknown unicast frame fordwarding to the cpu port */
689 mt7530_set(priv
, MT7530_MFC
, UNU_FFP(BIT(port
)));
691 /* CPU port gets connected to all user ports of
694 mt7530_write(priv
, MT7530_PCR_P(port
),
695 PCR_MATRIX(dsa_user_ports(priv
->ds
)));
701 mt7530_port_enable(struct dsa_switch
*ds
, int port
,
702 struct phy_device
*phy
)
704 struct mt7530_priv
*priv
= ds
->priv
;
706 mutex_lock(&priv
->reg_mutex
);
708 /* Setup the MAC for the user port */
709 mt7530_write(priv
, MT7530_PMCR_P(port
), PMCR_USERP_LINK
);
711 /* Allow the user port gets connected to the cpu port and also
712 * restore the port matrix if the port is the member of a certain
715 priv
->ports
[port
].pm
|= PCR_MATRIX(BIT(MT7530_CPU_PORT
));
716 priv
->ports
[port
].enable
= true;
717 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
718 priv
->ports
[port
].pm
);
719 mt7530_port_set_status(priv
, port
, 1);
721 mutex_unlock(&priv
->reg_mutex
);
727 mt7530_port_disable(struct dsa_switch
*ds
, int port
,
728 struct phy_device
*phy
)
730 struct mt7530_priv
*priv
= ds
->priv
;
732 mutex_lock(&priv
->reg_mutex
);
734 /* Clear up all port matrix which could be restored in the next
735 * enablement for the port.
737 priv
->ports
[port
].enable
= false;
738 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
740 mt7530_port_set_status(priv
, port
, 0);
742 mutex_unlock(&priv
->reg_mutex
);
746 mt7530_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
748 struct mt7530_priv
*priv
= ds
->priv
;
752 case BR_STATE_DISABLED
:
753 stp_state
= MT7530_STP_DISABLED
;
755 case BR_STATE_BLOCKING
:
756 stp_state
= MT7530_STP_BLOCKING
;
758 case BR_STATE_LISTENING
:
759 stp_state
= MT7530_STP_LISTENING
;
761 case BR_STATE_LEARNING
:
762 stp_state
= MT7530_STP_LEARNING
;
764 case BR_STATE_FORWARDING
:
766 stp_state
= MT7530_STP_FORWARDING
;
770 mt7530_rmw(priv
, MT7530_SSP_P(port
), FID_PST_MASK
, stp_state
);
774 mt7530_port_bridge_join(struct dsa_switch
*ds
, int port
,
775 struct net_device
*bridge
)
777 struct mt7530_priv
*priv
= ds
->priv
;
778 u32 port_bitmap
= BIT(MT7530_CPU_PORT
);
781 mutex_lock(&priv
->reg_mutex
);
783 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
784 /* Add this port to the port matrix of the other ports in the
785 * same bridge. If the port is disabled, port matrix is kept
786 * and not being setup until the port becomes enabled.
788 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
789 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
791 if (priv
->ports
[i
].enable
)
792 mt7530_set(priv
, MT7530_PCR_P(i
),
793 PCR_MATRIX(BIT(port
)));
794 priv
->ports
[i
].pm
|= PCR_MATRIX(BIT(port
));
796 port_bitmap
|= BIT(i
);
800 /* Add the all other ports to this port matrix. */
801 if (priv
->ports
[port
].enable
)
802 mt7530_rmw(priv
, MT7530_PCR_P(port
),
803 PCR_MATRIX_MASK
, PCR_MATRIX(port_bitmap
));
804 priv
->ports
[port
].pm
|= PCR_MATRIX(port_bitmap
);
806 mutex_unlock(&priv
->reg_mutex
);
812 mt7530_port_set_vlan_unaware(struct dsa_switch
*ds
, int port
)
814 struct mt7530_priv
*priv
= ds
->priv
;
815 bool all_user_ports_removed
= true;
818 /* When a port is removed from the bridge, the port would be set up
819 * back to the default as is at initial boot which is a VLAN-unaware
822 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_PORT_VLAN_MASK
,
823 MT7530_PORT_MATRIX_MODE
);
824 mt7530_rmw(priv
, MT7530_PVC_P(port
), VLAN_ATTR_MASK
,
825 VLAN_ATTR(MT7530_VLAN_TRANSPARENT
));
827 priv
->ports
[port
].vlan_filtering
= false;
829 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
830 if (dsa_is_user_port(ds
, i
) &&
831 priv
->ports
[i
].vlan_filtering
) {
832 all_user_ports_removed
= false;
837 /* CPU port also does the same thing until all user ports belonging to
838 * the CPU port get out of VLAN filtering mode.
840 if (all_user_ports_removed
) {
841 mt7530_write(priv
, MT7530_PCR_P(MT7530_CPU_PORT
),
842 PCR_MATRIX(dsa_user_ports(priv
->ds
)));
843 mt7530_write(priv
, MT7530_PVC_P(MT7530_CPU_PORT
),
849 mt7530_port_set_vlan_aware(struct dsa_switch
*ds
, int port
)
851 struct mt7530_priv
*priv
= ds
->priv
;
853 /* The real fabric path would be decided on the membership in the
854 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
855 * means potential VLAN can be consisting of certain subset of all
858 mt7530_rmw(priv
, MT7530_PCR_P(port
),
859 PCR_MATRIX_MASK
, PCR_MATRIX(MT7530_ALL_MEMBERS
));
861 /* Trapped into security mode allows packet forwarding through VLAN
864 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_PORT_VLAN_MASK
,
865 MT7530_PORT_SECURITY_MODE
);
867 /* Set the port as a user port which is to be able to recognize VID
868 * from incoming packets before fetching entry within the VLAN table.
870 mt7530_rmw(priv
, MT7530_PVC_P(port
), VLAN_ATTR_MASK
,
871 VLAN_ATTR(MT7530_VLAN_USER
));
875 mt7530_port_bridge_leave(struct dsa_switch
*ds
, int port
,
876 struct net_device
*bridge
)
878 struct mt7530_priv
*priv
= ds
->priv
;
881 mutex_lock(&priv
->reg_mutex
);
883 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
884 /* Remove this port from the port matrix of the other ports
885 * in the same bridge. If the port is disabled, port matrix
886 * is kept and not being setup until the port becomes enabled.
887 * And the other port's port matrix cannot be broken when the
888 * other port is still a VLAN-aware port.
890 if (!priv
->ports
[i
].vlan_filtering
&&
891 dsa_is_user_port(ds
, i
) && i
!= port
) {
892 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
894 if (priv
->ports
[i
].enable
)
895 mt7530_clear(priv
, MT7530_PCR_P(i
),
896 PCR_MATRIX(BIT(port
)));
897 priv
->ports
[i
].pm
&= ~PCR_MATRIX(BIT(port
));
901 /* Set the cpu port to be the only one in the port matrix of
904 if (priv
->ports
[port
].enable
)
905 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
906 PCR_MATRIX(BIT(MT7530_CPU_PORT
)));
907 priv
->ports
[port
].pm
= PCR_MATRIX(BIT(MT7530_CPU_PORT
));
909 mt7530_port_set_vlan_unaware(ds
, port
);
911 mutex_unlock(&priv
->reg_mutex
);
915 mt7530_port_fdb_add(struct dsa_switch
*ds
, int port
,
916 const unsigned char *addr
, u16 vid
)
918 struct mt7530_priv
*priv
= ds
->priv
;
920 u8 port_mask
= BIT(port
);
922 mutex_lock(&priv
->reg_mutex
);
923 mt7530_fdb_write(priv
, vid
, port_mask
, addr
, -1, STATIC_ENT
);
924 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_WRITE
, NULL
);
925 mutex_unlock(&priv
->reg_mutex
);
931 mt7530_port_fdb_del(struct dsa_switch
*ds
, int port
,
932 const unsigned char *addr
, u16 vid
)
934 struct mt7530_priv
*priv
= ds
->priv
;
936 u8 port_mask
= BIT(port
);
938 mutex_lock(&priv
->reg_mutex
);
939 mt7530_fdb_write(priv
, vid
, port_mask
, addr
, -1, STATIC_EMP
);
940 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_WRITE
, NULL
);
941 mutex_unlock(&priv
->reg_mutex
);
947 mt7530_port_fdb_dump(struct dsa_switch
*ds
, int port
,
948 dsa_fdb_dump_cb_t
*cb
, void *data
)
950 struct mt7530_priv
*priv
= ds
->priv
;
951 struct mt7530_fdb _fdb
= { 0 };
952 int cnt
= MT7530_NUM_FDB_RECORDS
;
956 mutex_lock(&priv
->reg_mutex
);
958 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_START
, &rsp
);
963 if (rsp
& ATC_SRCH_HIT
) {
964 mt7530_fdb_read(priv
, &_fdb
);
965 if (_fdb
.port_mask
& BIT(port
)) {
966 ret
= cb(_fdb
.mac
, _fdb
.vid
, _fdb
.noarp
,
973 !(rsp
& ATC_SRCH_END
) &&
974 !mt7530_fdb_cmd(priv
, MT7530_FDB_NEXT
, &rsp
));
976 mutex_unlock(&priv
->reg_mutex
);
982 mt7530_vlan_cmd(struct mt7530_priv
*priv
, enum mt7530_vlan_cmd cmd
, u16 vid
)
984 struct mt7530_dummy_poll p
;
988 val
= VTCR_BUSY
| VTCR_FUNC(cmd
) | vid
;
989 mt7530_write(priv
, MT7530_VTCR
, val
);
991 INIT_MT7530_DUMMY_POLL(&p
, priv
, MT7530_VTCR
);
992 ret
= readx_poll_timeout(_mt7530_read
, &p
, val
,
993 !(val
& VTCR_BUSY
), 20, 20000);
995 dev_err(priv
->dev
, "poll timeout\n");
999 val
= mt7530_read(priv
, MT7530_VTCR
);
1000 if (val
& VTCR_INVALID
) {
1001 dev_err(priv
->dev
, "read VTCR invalid\n");
1009 mt7530_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1010 bool vlan_filtering
)
1012 struct mt7530_priv
*priv
= ds
->priv
;
1014 priv
->ports
[port
].vlan_filtering
= vlan_filtering
;
1016 if (vlan_filtering
) {
1017 /* The port is being kept as VLAN-unaware port when bridge is
1018 * set up with vlan_filtering not being set, Otherwise, the
1019 * port and the corresponding CPU port is required the setup
1020 * for becoming a VLAN-aware port.
1022 mt7530_port_set_vlan_aware(ds
, port
);
1023 mt7530_port_set_vlan_aware(ds
, MT7530_CPU_PORT
);
1030 mt7530_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1031 const struct switchdev_obj_port_vlan
*vlan
)
1033 /* nothing needed */
1039 mt7530_hw_vlan_add(struct mt7530_priv
*priv
,
1040 struct mt7530_hw_vlan_entry
*entry
)
1045 new_members
= entry
->old_members
| BIT(entry
->port
) |
1046 BIT(MT7530_CPU_PORT
);
1048 /* Validate the entry with independent learning, create egress tag per
1049 * VLAN and joining the port as one of the port members.
1051 val
= IVL_MAC
| VTAG_EN
| PORT_MEM(new_members
) | VLAN_VALID
;
1052 mt7530_write(priv
, MT7530_VAWD1
, val
);
1054 /* Decide whether adding tag or not for those outgoing packets from the
1055 * port inside the VLAN.
1057 val
= entry
->untagged
? MT7530_VLAN_EGRESS_UNTAG
:
1058 MT7530_VLAN_EGRESS_TAG
;
1059 mt7530_rmw(priv
, MT7530_VAWD2
,
1060 ETAG_CTRL_P_MASK(entry
->port
),
1061 ETAG_CTRL_P(entry
->port
, val
));
1063 /* CPU port is always taken as a tagged port for serving more than one
1064 * VLANs across and also being applied with egress type stack mode for
1065 * that VLAN tags would be appended after hardware special tag used as
1068 mt7530_rmw(priv
, MT7530_VAWD2
,
1069 ETAG_CTRL_P_MASK(MT7530_CPU_PORT
),
1070 ETAG_CTRL_P(MT7530_CPU_PORT
,
1071 MT7530_VLAN_EGRESS_STACK
));
1075 mt7530_hw_vlan_del(struct mt7530_priv
*priv
,
1076 struct mt7530_hw_vlan_entry
*entry
)
1081 new_members
= entry
->old_members
& ~BIT(entry
->port
);
1083 val
= mt7530_read(priv
, MT7530_VAWD1
);
1084 if (!(val
& VLAN_VALID
)) {
1086 "Cannot be deleted due to invalid entry\n");
1090 /* If certain member apart from CPU port is still alive in the VLAN,
1091 * the entry would be kept valid. Otherwise, the entry is got to be
1094 if (new_members
&& new_members
!= BIT(MT7530_CPU_PORT
)) {
1095 val
= IVL_MAC
| VTAG_EN
| PORT_MEM(new_members
) |
1097 mt7530_write(priv
, MT7530_VAWD1
, val
);
1099 mt7530_write(priv
, MT7530_VAWD1
, 0);
1100 mt7530_write(priv
, MT7530_VAWD2
, 0);
1105 mt7530_hw_vlan_update(struct mt7530_priv
*priv
, u16 vid
,
1106 struct mt7530_hw_vlan_entry
*entry
,
1107 mt7530_vlan_op vlan_op
)
1112 mt7530_vlan_cmd(priv
, MT7530_VTCR_RD_VID
, vid
);
1114 val
= mt7530_read(priv
, MT7530_VAWD1
);
1116 entry
->old_members
= (val
>> PORT_MEM_SHFT
) & PORT_MEM_MASK
;
1118 /* Manipulate entry */
1119 vlan_op(priv
, entry
);
1121 /* Flush result to hardware */
1122 mt7530_vlan_cmd(priv
, MT7530_VTCR_WR_VID
, vid
);
1126 mt7530_port_vlan_add(struct dsa_switch
*ds
, int port
,
1127 const struct switchdev_obj_port_vlan
*vlan
)
1129 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1130 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1131 struct mt7530_hw_vlan_entry new_entry
;
1132 struct mt7530_priv
*priv
= ds
->priv
;
1135 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1138 if (!priv
->ports
[port
].vlan_filtering
)
1141 mutex_lock(&priv
->reg_mutex
);
1143 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1144 mt7530_hw_vlan_entry_init(&new_entry
, port
, untagged
);
1145 mt7530_hw_vlan_update(priv
, vid
, &new_entry
,
1146 mt7530_hw_vlan_add
);
1150 mt7530_rmw(priv
, MT7530_PPBV1_P(port
), G0_PORT_VID_MASK
,
1151 G0_PORT_VID(vlan
->vid_end
));
1152 priv
->ports
[port
].pvid
= vlan
->vid_end
;
1155 mutex_unlock(&priv
->reg_mutex
);
1159 mt7530_port_vlan_del(struct dsa_switch
*ds
, int port
,
1160 const struct switchdev_obj_port_vlan
*vlan
)
1162 struct mt7530_hw_vlan_entry target_entry
;
1163 struct mt7530_priv
*priv
= ds
->priv
;
1166 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1169 if (!priv
->ports
[port
].vlan_filtering
)
1172 mutex_lock(&priv
->reg_mutex
);
1174 pvid
= priv
->ports
[port
].pvid
;
1175 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1176 mt7530_hw_vlan_entry_init(&target_entry
, port
, 0);
1177 mt7530_hw_vlan_update(priv
, vid
, &target_entry
,
1178 mt7530_hw_vlan_del
);
1180 /* PVID is being restored to the default whenever the PVID port
1181 * is being removed from the VLAN.
1184 pvid
= G0_PORT_VID_DEF
;
1187 mt7530_rmw(priv
, MT7530_PPBV1_P(port
), G0_PORT_VID_MASK
, pvid
);
1188 priv
->ports
[port
].pvid
= pvid
;
1190 mutex_unlock(&priv
->reg_mutex
);
1195 static enum dsa_tag_protocol
1196 mtk_get_tag_protocol(struct dsa_switch
*ds
, int port
)
1198 struct mt7530_priv
*priv
= ds
->priv
;
1200 if (port
!= MT7530_CPU_PORT
) {
1202 "port not matched with tagging CPU port\n");
1203 return DSA_TAG_PROTO_NONE
;
1205 return DSA_TAG_PROTO_MTK
;
1210 mt7530_setup(struct dsa_switch
*ds
)
1212 struct mt7530_priv
*priv
= ds
->priv
;
1215 struct device_node
*dn
;
1216 struct mt7530_dummy_poll p
;
1218 /* The parent node of master netdev which holds the common system
1219 * controller also is the container for two GMACs nodes representing
1220 * as two netdev instances.
1222 dn
= ds
->ports
[MT7530_CPU_PORT
].master
->dev
.of_node
->parent
;
1223 priv
->ethernet
= syscon_node_to_regmap(dn
);
1224 if (IS_ERR(priv
->ethernet
))
1225 return PTR_ERR(priv
->ethernet
);
1227 regulator_set_voltage(priv
->core_pwr
, 1000000, 1000000);
1228 ret
= regulator_enable(priv
->core_pwr
);
1231 "Failed to enable core power: %d\n", ret
);
1235 regulator_set_voltage(priv
->io_pwr
, 3300000, 3300000);
1236 ret
= regulator_enable(priv
->io_pwr
);
1238 dev_err(priv
->dev
, "Failed to enable io pwr: %d\n",
1243 /* Reset whole chip through gpio pin or memory-mapped registers for
1244 * different type of hardware
1247 reset_control_assert(priv
->rstc
);
1248 usleep_range(1000, 1100);
1249 reset_control_deassert(priv
->rstc
);
1251 gpiod_set_value_cansleep(priv
->reset
, 0);
1252 usleep_range(1000, 1100);
1253 gpiod_set_value_cansleep(priv
->reset
, 1);
1256 /* Waiting for MT7530 got to stable */
1257 INIT_MT7530_DUMMY_POLL(&p
, priv
, MT7530_HWTRAP
);
1258 ret
= readx_poll_timeout(_mt7530_read
, &p
, val
, val
!= 0,
1261 dev_err(priv
->dev
, "reset timeout\n");
1265 id
= mt7530_read(priv
, MT7530_CREV
);
1266 id
>>= CHIP_NAME_SHIFT
;
1267 if (id
!= MT7530_ID
) {
1268 dev_err(priv
->dev
, "chip %x can't be supported\n", id
);
1272 /* Reset the switch through internal reset */
1273 mt7530_write(priv
, MT7530_SYS_CTRL
,
1274 SYS_CTRL_PHY_RST
| SYS_CTRL_SW_RST
|
1277 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1278 val
= mt7530_read(priv
, MT7530_MHWTRAP
);
1279 val
&= ~MHWTRAP_P6_DIS
& ~MHWTRAP_PHY_ACCESS
;
1280 val
|= MHWTRAP_MANUAL
;
1281 mt7530_write(priv
, MT7530_MHWTRAP
, val
);
1283 /* Enable and reset MIB counters */
1284 mt7530_mib_reset(ds
);
1286 mt7530_clear(priv
, MT7530_MFC
, UNU_FFP_MASK
);
1288 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
1289 /* Disable forwarding by default on all ports */
1290 mt7530_rmw(priv
, MT7530_PCR_P(i
), PCR_MATRIX_MASK
,
1293 if (dsa_is_cpu_port(ds
, i
))
1294 mt7530_cpu_port_enable(priv
, i
);
1296 mt7530_port_disable(ds
, i
, NULL
);
1299 /* Flush the FDB table */
1300 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_FLUSH
, NULL
);
1307 static const struct dsa_switch_ops mt7530_switch_ops
= {
1308 .get_tag_protocol
= mtk_get_tag_protocol
,
1309 .setup
= mt7530_setup
,
1310 .get_strings
= mt7530_get_strings
,
1311 .phy_read
= mt7530_phy_read
,
1312 .phy_write
= mt7530_phy_write
,
1313 .get_ethtool_stats
= mt7530_get_ethtool_stats
,
1314 .get_sset_count
= mt7530_get_sset_count
,
1315 .adjust_link
= mt7530_adjust_link
,
1316 .port_enable
= mt7530_port_enable
,
1317 .port_disable
= mt7530_port_disable
,
1318 .port_stp_state_set
= mt7530_stp_state_set
,
1319 .port_bridge_join
= mt7530_port_bridge_join
,
1320 .port_bridge_leave
= mt7530_port_bridge_leave
,
1321 .port_fdb_add
= mt7530_port_fdb_add
,
1322 .port_fdb_del
= mt7530_port_fdb_del
,
1323 .port_fdb_dump
= mt7530_port_fdb_dump
,
1324 .port_vlan_filtering
= mt7530_port_vlan_filtering
,
1325 .port_vlan_prepare
= mt7530_port_vlan_prepare
,
1326 .port_vlan_add
= mt7530_port_vlan_add
,
1327 .port_vlan_del
= mt7530_port_vlan_del
,
1331 mt7530_probe(struct mdio_device
*mdiodev
)
1333 struct mt7530_priv
*priv
;
1334 struct device_node
*dn
;
1336 dn
= mdiodev
->dev
.of_node
;
1338 priv
= devm_kzalloc(&mdiodev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1342 priv
->ds
= dsa_switch_alloc(&mdiodev
->dev
, DSA_MAX_PORTS
);
1346 /* Use medatek,mcm property to distinguish hardware type that would
1347 * casues a little bit differences on power-on sequence.
1349 priv
->mcm
= of_property_read_bool(dn
, "mediatek,mcm");
1351 dev_info(&mdiodev
->dev
, "MT7530 adapts as multi-chip module\n");
1353 priv
->rstc
= devm_reset_control_get(&mdiodev
->dev
, "mcm");
1354 if (IS_ERR(priv
->rstc
)) {
1355 dev_err(&mdiodev
->dev
, "Couldn't get our reset line\n");
1356 return PTR_ERR(priv
->rstc
);
1360 priv
->core_pwr
= devm_regulator_get(&mdiodev
->dev
, "core");
1361 if (IS_ERR(priv
->core_pwr
))
1362 return PTR_ERR(priv
->core_pwr
);
1364 priv
->io_pwr
= devm_regulator_get(&mdiodev
->dev
, "io");
1365 if (IS_ERR(priv
->io_pwr
))
1366 return PTR_ERR(priv
->io_pwr
);
1368 /* Not MCM that indicates switch works as the remote standalone
1369 * integrated circuit so the GPIO pin would be used to complete
1370 * the reset, otherwise memory-mapped register accessing used
1371 * through syscon provides in the case of MCM.
1374 priv
->reset
= devm_gpiod_get_optional(&mdiodev
->dev
, "reset",
1376 if (IS_ERR(priv
->reset
)) {
1377 dev_err(&mdiodev
->dev
, "Couldn't get our reset line\n");
1378 return PTR_ERR(priv
->reset
);
1382 priv
->bus
= mdiodev
->bus
;
1383 priv
->dev
= &mdiodev
->dev
;
1384 priv
->ds
->priv
= priv
;
1385 priv
->ds
->ops
= &mt7530_switch_ops
;
1386 mutex_init(&priv
->reg_mutex
);
1387 dev_set_drvdata(&mdiodev
->dev
, priv
);
1389 return dsa_register_switch(priv
->ds
);
1393 mt7530_remove(struct mdio_device
*mdiodev
)
1395 struct mt7530_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
1398 ret
= regulator_disable(priv
->core_pwr
);
1401 "Failed to disable core power: %d\n", ret
);
1403 ret
= regulator_disable(priv
->io_pwr
);
1405 dev_err(priv
->dev
, "Failed to disable io pwr: %d\n",
1408 dsa_unregister_switch(priv
->ds
);
1409 mutex_destroy(&priv
->reg_mutex
);
1412 static const struct of_device_id mt7530_of_match
[] = {
1413 { .compatible
= "mediatek,mt7530" },
1416 MODULE_DEVICE_TABLE(of
, mt7530_of_match
);
1418 static struct mdio_driver mt7530_mdio_driver
= {
1419 .probe
= mt7530_probe
,
1420 .remove
= mt7530_remove
,
1423 .of_match_table
= mt7530_of_match
,
1427 mdio_module_driver(mt7530_mdio_driver
);
1429 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1430 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1431 MODULE_LICENSE("GPL");