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Merge tag 'integrity-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/zohar...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / dsa / mt7530.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 */
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_net.h>
16 #include <linux/of_platform.h>
17 #include <linux/phylink.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/reset.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/gpio/driver.h>
23 #include <net/dsa.h>
24
25 #include "mt7530.h"
26
27 /* String, offset, and register size in bytes if different from 4 bytes */
28 static const struct mt7530_mib_desc mt7530_mib[] = {
29 MIB_DESC(1, 0x00, "TxDrop"),
30 MIB_DESC(1, 0x04, "TxCrcErr"),
31 MIB_DESC(1, 0x08, "TxUnicast"),
32 MIB_DESC(1, 0x0c, "TxMulticast"),
33 MIB_DESC(1, 0x10, "TxBroadcast"),
34 MIB_DESC(1, 0x14, "TxCollision"),
35 MIB_DESC(1, 0x18, "TxSingleCollision"),
36 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
37 MIB_DESC(1, 0x20, "TxDeferred"),
38 MIB_DESC(1, 0x24, "TxLateCollision"),
39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
40 MIB_DESC(1, 0x2c, "TxPause"),
41 MIB_DESC(1, 0x30, "TxPktSz64"),
42 MIB_DESC(1, 0x34, "TxPktSz65To127"),
43 MIB_DESC(1, 0x38, "TxPktSz128To255"),
44 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
45 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
46 MIB_DESC(1, 0x44, "Tx1024ToMax"),
47 MIB_DESC(2, 0x48, "TxBytes"),
48 MIB_DESC(1, 0x60, "RxDrop"),
49 MIB_DESC(1, 0x64, "RxFiltering"),
50 MIB_DESC(1, 0x68, "RxUnicast"),
51 MIB_DESC(1, 0x6c, "RxMulticast"),
52 MIB_DESC(1, 0x70, "RxBroadcast"),
53 MIB_DESC(1, 0x74, "RxAlignErr"),
54 MIB_DESC(1, 0x78, "RxCrcErr"),
55 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
56 MIB_DESC(1, 0x80, "RxFragErr"),
57 MIB_DESC(1, 0x84, "RxOverSzErr"),
58 MIB_DESC(1, 0x88, "RxJabberErr"),
59 MIB_DESC(1, 0x8c, "RxPause"),
60 MIB_DESC(1, 0x90, "RxPktSz64"),
61 MIB_DESC(1, 0x94, "RxPktSz65To127"),
62 MIB_DESC(1, 0x98, "RxPktSz128To255"),
63 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
64 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
65 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
66 MIB_DESC(2, 0xa8, "RxBytes"),
67 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
68 MIB_DESC(1, 0xb4, "RxIngressDrop"),
69 MIB_DESC(1, 0xb8, "RxArlDrop"),
70 };
71
72 /* Since phy_device has not yet been created and
73 * phy_{read,write}_mmd_indirect is not available, we provide our own
74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
75 * to complete this function.
76 */
77 static int
78 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
79 {
80 struct mii_bus *bus = priv->bus;
81 int value, ret;
82
83 /* Write the desired MMD Devad */
84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
85 if (ret < 0)
86 goto err;
87
88 /* Write the desired MMD register address */
89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
90 if (ret < 0)
91 goto err;
92
93 /* Select the Function : DATA with no post increment */
94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
95 if (ret < 0)
96 goto err;
97
98 /* Read the content of the MMD's selected register */
99 value = bus->read(bus, 0, MII_MMD_DATA);
100
101 return value;
102 err:
103 dev_err(&bus->dev, "failed to read mmd register\n");
104
105 return ret;
106 }
107
108 static int
109 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
110 int devad, u32 data)
111 {
112 struct mii_bus *bus = priv->bus;
113 int ret;
114
115 /* Write the desired MMD Devad */
116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
117 if (ret < 0)
118 goto err;
119
120 /* Write the desired MMD register address */
121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
122 if (ret < 0)
123 goto err;
124
125 /* Select the Function : DATA with no post increment */
126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
127 if (ret < 0)
128 goto err;
129
130 /* Write the data into MMD's selected register */
131 ret = bus->write(bus, 0, MII_MMD_DATA, data);
132 err:
133 if (ret < 0)
134 dev_err(&bus->dev,
135 "failed to write mmd register\n");
136 return ret;
137 }
138
139 static void
140 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
141 {
142 struct mii_bus *bus = priv->bus;
143
144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
145
146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
147
148 mutex_unlock(&bus->mdio_lock);
149 }
150
151 static void
152 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
153 {
154 struct mii_bus *bus = priv->bus;
155 u32 val;
156
157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
158
159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
160 val &= ~mask;
161 val |= set;
162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
163
164 mutex_unlock(&bus->mdio_lock);
165 }
166
167 static void
168 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
169 {
170 core_rmw(priv, reg, 0, val);
171 }
172
173 static void
174 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
175 {
176 core_rmw(priv, reg, val, 0);
177 }
178
179 static int
180 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
181 {
182 struct mii_bus *bus = priv->bus;
183 u16 page, r, lo, hi;
184 int ret;
185
186 page = (reg >> 6) & 0x3ff;
187 r = (reg >> 2) & 0xf;
188 lo = val & 0xffff;
189 hi = val >> 16;
190
191 /* MT7530 uses 31 as the pseudo port */
192 ret = bus->write(bus, 0x1f, 0x1f, page);
193 if (ret < 0)
194 goto err;
195
196 ret = bus->write(bus, 0x1f, r, lo);
197 if (ret < 0)
198 goto err;
199
200 ret = bus->write(bus, 0x1f, 0x10, hi);
201 err:
202 if (ret < 0)
203 dev_err(&bus->dev,
204 "failed to write mt7530 register\n");
205 return ret;
206 }
207
208 static u32
209 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
210 {
211 struct mii_bus *bus = priv->bus;
212 u16 page, r, lo, hi;
213 int ret;
214
215 page = (reg >> 6) & 0x3ff;
216 r = (reg >> 2) & 0xf;
217
218 /* MT7530 uses 31 as the pseudo port */
219 ret = bus->write(bus, 0x1f, 0x1f, page);
220 if (ret < 0) {
221 dev_err(&bus->dev,
222 "failed to read mt7530 register\n");
223 return ret;
224 }
225
226 lo = bus->read(bus, 0x1f, r);
227 hi = bus->read(bus, 0x1f, 0x10);
228
229 return (hi << 16) | (lo & 0xffff);
230 }
231
232 static void
233 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
234 {
235 struct mii_bus *bus = priv->bus;
236
237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
238
239 mt7530_mii_write(priv, reg, val);
240
241 mutex_unlock(&bus->mdio_lock);
242 }
243
244 static u32
245 _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
246 {
247 return mt7530_mii_read(p->priv, p->reg);
248 }
249
250 static u32
251 _mt7530_read(struct mt7530_dummy_poll *p)
252 {
253 struct mii_bus *bus = p->priv->bus;
254 u32 val;
255
256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
257
258 val = mt7530_mii_read(p->priv, p->reg);
259
260 mutex_unlock(&bus->mdio_lock);
261
262 return val;
263 }
264
265 static u32
266 mt7530_read(struct mt7530_priv *priv, u32 reg)
267 {
268 struct mt7530_dummy_poll p;
269
270 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
271 return _mt7530_read(&p);
272 }
273
274 static void
275 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
276 u32 mask, u32 set)
277 {
278 struct mii_bus *bus = priv->bus;
279 u32 val;
280
281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
282
283 val = mt7530_mii_read(priv, reg);
284 val &= ~mask;
285 val |= set;
286 mt7530_mii_write(priv, reg, val);
287
288 mutex_unlock(&bus->mdio_lock);
289 }
290
291 static void
292 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
293 {
294 mt7530_rmw(priv, reg, 0, val);
295 }
296
297 static void
298 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
299 {
300 mt7530_rmw(priv, reg, val, 0);
301 }
302
303 static int
304 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
305 {
306 u32 val;
307 int ret;
308 struct mt7530_dummy_poll p;
309
310 /* Set the command operating upon the MAC address entries */
311 val = ATC_BUSY | ATC_MAT(0) | cmd;
312 mt7530_write(priv, MT7530_ATC, val);
313
314 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
315 ret = readx_poll_timeout(_mt7530_read, &p, val,
316 !(val & ATC_BUSY), 20, 20000);
317 if (ret < 0) {
318 dev_err(priv->dev, "reset timeout\n");
319 return ret;
320 }
321
322 /* Additional sanity for read command if the specified
323 * entry is invalid
324 */
325 val = mt7530_read(priv, MT7530_ATC);
326 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
327 return -EINVAL;
328
329 if (rsp)
330 *rsp = val;
331
332 return 0;
333 }
334
335 static void
336 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
337 {
338 u32 reg[3];
339 int i;
340
341 /* Read from ARL table into an array */
342 for (i = 0; i < 3; i++) {
343 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
344
345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
346 __func__, __LINE__, i, reg[i]);
347 }
348
349 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
359 }
360
361 static void
362 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
363 u8 port_mask, const u8 *mac,
364 u8 aging, u8 type)
365 {
366 u32 reg[3] = { 0 };
367 int i;
368
369 reg[1] |= vid & CVID_MASK;
370 reg[1] |= ATA2_IVL;
371 reg[1] |= ATA2_FID(FID_BRIDGED);
372 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
373 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
374 /* STATIC_ENT indicate that entry is static wouldn't
375 * be aged out and STATIC_EMP specified as erasing an
376 * entry
377 */
378 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
379 reg[1] |= mac[5] << MAC_BYTE_5;
380 reg[1] |= mac[4] << MAC_BYTE_4;
381 reg[0] |= mac[3] << MAC_BYTE_3;
382 reg[0] |= mac[2] << MAC_BYTE_2;
383 reg[0] |= mac[1] << MAC_BYTE_1;
384 reg[0] |= mac[0] << MAC_BYTE_0;
385
386 /* Write array into the ARL table */
387 for (i = 0; i < 3; i++)
388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
389 }
390
391 /* Setup TX circuit including relevant PAD and driving */
392 static int
393 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
394 {
395 struct mt7530_priv *priv = ds->priv;
396 u32 ncpo1, ssc_delta, trgint, i, xtal;
397
398 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
399
400 if (xtal == HWTRAP_XTAL_20MHZ) {
401 dev_err(priv->dev,
402 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
403 __func__);
404 return -EINVAL;
405 }
406
407 switch (interface) {
408 case PHY_INTERFACE_MODE_RGMII:
409 trgint = 0;
410 /* PLL frequency: 125MHz */
411 ncpo1 = 0x0c80;
412 break;
413 case PHY_INTERFACE_MODE_TRGMII:
414 trgint = 1;
415 if (priv->id == ID_MT7621) {
416 /* PLL frequency: 150MHz: 1.2GBit */
417 if (xtal == HWTRAP_XTAL_40MHZ)
418 ncpo1 = 0x0780;
419 if (xtal == HWTRAP_XTAL_25MHZ)
420 ncpo1 = 0x0a00;
421 } else { /* PLL frequency: 250MHz: 2.0Gbit */
422 if (xtal == HWTRAP_XTAL_40MHZ)
423 ncpo1 = 0x0c80;
424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ncpo1 = 0x1400;
426 }
427 break;
428 default:
429 dev_err(priv->dev, "xMII interface %d not supported\n",
430 interface);
431 return -EINVAL;
432 }
433
434 if (xtal == HWTRAP_XTAL_25MHZ)
435 ssc_delta = 0x57;
436 else
437 ssc_delta = 0x87;
438
439 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
440 P6_INTF_MODE(trgint));
441
442 /* Lower Tx Driving for TRGMII path */
443 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
445 TD_DM_DRVP(8) | TD_DM_DRVN(8));
446
447 /* Disable MT7530 core and TRGMII Tx clocks */
448 core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
449 REG_GSWCK_EN | REG_TRGMIICK_EN);
450
451 /* Setup core clock for MT7530 */
452 /* Disable PLL */
453 core_write(priv, CORE_GSWPLL_GRP1, 0);
454
455 /* Set core clock into 500Mhz */
456 core_write(priv, CORE_GSWPLL_GRP2,
457 RG_GSWPLL_POSDIV_500M(1) |
458 RG_GSWPLL_FBKDIV_500M(25));
459
460 /* Enable PLL */
461 core_write(priv, CORE_GSWPLL_GRP1,
462 RG_GSWPLL_EN_PRE |
463 RG_GSWPLL_POSDIV_200M(2) |
464 RG_GSWPLL_FBKDIV_200M(32));
465
466 /* Setup the MT7530 TRGMII Tx Clock */
467 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
468 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
469 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
470 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
471 core_write(priv, CORE_PLL_GROUP4,
472 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
473 RG_SYSPLL_BIAS_LPF_EN);
474 core_write(priv, CORE_PLL_GROUP2,
475 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
476 RG_SYSPLL_POSDIV(1));
477 core_write(priv, CORE_PLL_GROUP7,
478 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
479 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
480
481 /* Enable MT7530 core and TRGMII Tx clocks */
482 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
483 REG_GSWCK_EN | REG_TRGMIICK_EN);
484
485 if (!trgint)
486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
487 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
488 RD_TAP_MASK, RD_TAP(16));
489 return 0;
490 }
491
492 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
493 {
494 u32 val;
495
496 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
497
498 return (val & PAD_DUAL_SGMII_EN) != 0;
499 }
500
501 static int
502 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
503 {
504 struct mt7530_priv *priv = ds->priv;
505 u32 top_sig;
506 u32 hwstrap;
507 u32 xtal;
508 u32 val;
509
510 if (mt7531_dual_sgmii_supported(priv))
511 return 0;
512
513 val = mt7530_read(priv, MT7531_CREV);
514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
515 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
516 if ((val & CHIP_REV_M) > 0)
517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
518 HWTRAP_XTAL_FSEL_25MHZ;
519 else
520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
521
522 /* Step 1 : Disable MT7531 COREPLL */
523 val = mt7530_read(priv, MT7531_PLLGP_EN);
524 val &= ~EN_COREPLL;
525 mt7530_write(priv, MT7531_PLLGP_EN, val);
526
527 /* Step 2: switch to XTAL output */
528 val = mt7530_read(priv, MT7531_PLLGP_EN);
529 val |= SW_CLKSW;
530 mt7530_write(priv, MT7531_PLLGP_EN, val);
531
532 val = mt7530_read(priv, MT7531_PLLGP_CR0);
533 val &= ~RG_COREPLL_EN;
534 mt7530_write(priv, MT7531_PLLGP_CR0, val);
535
536 /* Step 3: disable PLLGP and enable program PLLGP */
537 val = mt7530_read(priv, MT7531_PLLGP_EN);
538 val |= SW_PLLGP;
539 mt7530_write(priv, MT7531_PLLGP_EN, val);
540
541 /* Step 4: program COREPLL output frequency to 500MHz */
542 val = mt7530_read(priv, MT7531_PLLGP_CR0);
543 val &= ~RG_COREPLL_POSDIV_M;
544 val |= 2 << RG_COREPLL_POSDIV_S;
545 mt7530_write(priv, MT7531_PLLGP_CR0, val);
546 usleep_range(25, 35);
547
548 switch (xtal) {
549 case HWTRAP_XTAL_FSEL_25MHZ:
550 val = mt7530_read(priv, MT7531_PLLGP_CR0);
551 val &= ~RG_COREPLL_SDM_PCW_M;
552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
553 mt7530_write(priv, MT7531_PLLGP_CR0, val);
554 break;
555 case HWTRAP_XTAL_FSEL_40MHZ:
556 val = mt7530_read(priv, MT7531_PLLGP_CR0);
557 val &= ~RG_COREPLL_SDM_PCW_M;
558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
559 mt7530_write(priv, MT7531_PLLGP_CR0, val);
560 break;
561 }
562
563 /* Set feedback divide ratio update signal to high */
564 val = mt7530_read(priv, MT7531_PLLGP_CR0);
565 val |= RG_COREPLL_SDM_PCW_CHG;
566 mt7530_write(priv, MT7531_PLLGP_CR0, val);
567 /* Wait for at least 16 XTAL clocks */
568 usleep_range(10, 20);
569
570 /* Step 5: set feedback divide ratio update signal to low */
571 val = mt7530_read(priv, MT7531_PLLGP_CR0);
572 val &= ~RG_COREPLL_SDM_PCW_CHG;
573 mt7530_write(priv, MT7531_PLLGP_CR0, val);
574
575 /* Enable 325M clock for SGMII */
576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
577
578 /* Enable 250SSC clock for RGMII */
579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
580
581 /* Step 6: Enable MT7531 PLL */
582 val = mt7530_read(priv, MT7531_PLLGP_CR0);
583 val |= RG_COREPLL_EN;
584 mt7530_write(priv, MT7531_PLLGP_CR0, val);
585
586 val = mt7530_read(priv, MT7531_PLLGP_EN);
587 val |= EN_COREPLL;
588 mt7530_write(priv, MT7531_PLLGP_EN, val);
589 usleep_range(25, 35);
590
591 return 0;
592 }
593
594 static void
595 mt7530_mib_reset(struct dsa_switch *ds)
596 {
597 struct mt7530_priv *priv = ds->priv;
598
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
601 }
602
603 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
604 {
605 return mdiobus_read_nested(priv->bus, port, regnum);
606 }
607
608 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
609 u16 val)
610 {
611 return mdiobus_write_nested(priv->bus, port, regnum, val);
612 }
613
614 static int
615 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
616 int regnum)
617 {
618 struct mii_bus *bus = priv->bus;
619 struct mt7530_dummy_poll p;
620 u32 reg, val;
621 int ret;
622
623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
624
625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
626
627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
628 !(val & MT7531_PHY_ACS_ST), 20, 100000);
629 if (ret < 0) {
630 dev_err(priv->dev, "poll timeout\n");
631 goto out;
632 }
633
634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
635 MT7531_MDIO_DEV_ADDR(devad) | regnum;
636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
637
638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
639 !(val & MT7531_PHY_ACS_ST), 20, 100000);
640 if (ret < 0) {
641 dev_err(priv->dev, "poll timeout\n");
642 goto out;
643 }
644
645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
646 MT7531_MDIO_DEV_ADDR(devad);
647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
648
649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
650 !(val & MT7531_PHY_ACS_ST), 20, 100000);
651 if (ret < 0) {
652 dev_err(priv->dev, "poll timeout\n");
653 goto out;
654 }
655
656 ret = val & MT7531_MDIO_RW_DATA_MASK;
657 out:
658 mutex_unlock(&bus->mdio_lock);
659
660 return ret;
661 }
662
663 static int
664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
665 int regnum, u32 data)
666 {
667 struct mii_bus *bus = priv->bus;
668 struct mt7530_dummy_poll p;
669 u32 val, reg;
670 int ret;
671
672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
673
674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
675
676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
677 !(val & MT7531_PHY_ACS_ST), 20, 100000);
678 if (ret < 0) {
679 dev_err(priv->dev, "poll timeout\n");
680 goto out;
681 }
682
683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
684 MT7531_MDIO_DEV_ADDR(devad) | regnum;
685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
686
687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
688 !(val & MT7531_PHY_ACS_ST), 20, 100000);
689 if (ret < 0) {
690 dev_err(priv->dev, "poll timeout\n");
691 goto out;
692 }
693
694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
695 MT7531_MDIO_DEV_ADDR(devad) | data;
696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
697
698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
699 !(val & MT7531_PHY_ACS_ST), 20, 100000);
700 if (ret < 0) {
701 dev_err(priv->dev, "poll timeout\n");
702 goto out;
703 }
704
705 out:
706 mutex_unlock(&bus->mdio_lock);
707
708 return ret;
709 }
710
711 static int
712 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
713 {
714 struct mii_bus *bus = priv->bus;
715 struct mt7530_dummy_poll p;
716 int ret;
717 u32 val;
718
719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
720
721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
722
723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
724 !(val & MT7531_PHY_ACS_ST), 20, 100000);
725 if (ret < 0) {
726 dev_err(priv->dev, "poll timeout\n");
727 goto out;
728 }
729
730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
731 MT7531_MDIO_REG_ADDR(regnum);
732
733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
734
735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
736 !(val & MT7531_PHY_ACS_ST), 20, 100000);
737 if (ret < 0) {
738 dev_err(priv->dev, "poll timeout\n");
739 goto out;
740 }
741
742 ret = val & MT7531_MDIO_RW_DATA_MASK;
743 out:
744 mutex_unlock(&bus->mdio_lock);
745
746 return ret;
747 }
748
749 static int
750 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
751 u16 data)
752 {
753 struct mii_bus *bus = priv->bus;
754 struct mt7530_dummy_poll p;
755 int ret;
756 u32 reg;
757
758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
759
760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
761
762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
763 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
764 if (ret < 0) {
765 dev_err(priv->dev, "poll timeout\n");
766 goto out;
767 }
768
769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
770 MT7531_MDIO_REG_ADDR(regnum) | data;
771
772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
773
774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
775 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
776 if (ret < 0) {
777 dev_err(priv->dev, "poll timeout\n");
778 goto out;
779 }
780
781 out:
782 mutex_unlock(&bus->mdio_lock);
783
784 return ret;
785 }
786
787 static int
788 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
789 {
790 int devad;
791 int ret;
792
793 if (regnum & MII_ADDR_C45) {
794 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
795 ret = mt7531_ind_c45_phy_read(priv, port, devad,
796 regnum & MII_REGADDR_C45_MASK);
797 } else {
798 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
799 }
800
801 return ret;
802 }
803
804 static int
805 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
806 u16 data)
807 {
808 int devad;
809 int ret;
810
811 if (regnum & MII_ADDR_C45) {
812 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
813 ret = mt7531_ind_c45_phy_write(priv, port, devad,
814 regnum & MII_REGADDR_C45_MASK,
815 data);
816 } else {
817 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
818 }
819
820 return ret;
821 }
822
823 static int
824 mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
825 {
826 struct mt7530_priv *priv = bus->priv;
827
828 return priv->info->phy_read(priv, port, regnum);
829 }
830
831 static int
832 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
833 {
834 struct mt7530_priv *priv = bus->priv;
835
836 return priv->info->phy_write(priv, port, regnum, val);
837 }
838
839 static void
840 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
841 uint8_t *data)
842 {
843 int i;
844
845 if (stringset != ETH_SS_STATS)
846 return;
847
848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
850 ETH_GSTRING_LEN);
851 }
852
853 static void
854 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
855 uint64_t *data)
856 {
857 struct mt7530_priv *priv = ds->priv;
858 const struct mt7530_mib_desc *mib;
859 u32 reg, i;
860 u64 hi;
861
862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
863 mib = &mt7530_mib[i];
864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
865
866 data[i] = mt7530_read(priv, reg);
867 if (mib->size == 2) {
868 hi = mt7530_read(priv, reg + 4);
869 data[i] |= hi << 32;
870 }
871 }
872 }
873
874 static int
875 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
876 {
877 if (sset != ETH_SS_STATS)
878 return 0;
879
880 return ARRAY_SIZE(mt7530_mib);
881 }
882
883 static int
884 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
885 {
886 struct mt7530_priv *priv = ds->priv;
887 unsigned int secs = msecs / 1000;
888 unsigned int tmp_age_count;
889 unsigned int error = -1;
890 unsigned int age_count;
891 unsigned int age_unit;
892
893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
895 return -ERANGE;
896
897 /* iterate through all possible age_count to find the closest pair */
898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
900
901 if (tmp_age_unit <= AGE_UNIT_MAX) {
902 unsigned int tmp_error = secs -
903 (tmp_age_count + 1) * (tmp_age_unit + 1);
904
905 /* found a closer pair */
906 if (error > tmp_error) {
907 error = tmp_error;
908 age_count = tmp_age_count;
909 age_unit = tmp_age_unit;
910 }
911
912 /* found the exact match, so break the loop */
913 if (!error)
914 break;
915 }
916 }
917
918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
919
920 return 0;
921 }
922
923 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
924 {
925 struct mt7530_priv *priv = ds->priv;
926 u8 tx_delay = 0;
927 int val;
928
929 mutex_lock(&priv->reg_mutex);
930
931 val = mt7530_read(priv, MT7530_MHWTRAP);
932
933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
935
936 switch (priv->p5_intf_sel) {
937 case P5_INTF_SEL_PHY_P0:
938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
939 val |= MHWTRAP_PHY0_SEL;
940 fallthrough;
941 case P5_INTF_SEL_PHY_P4:
942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
944
945 /* Setup the MAC by default for the cpu port */
946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
947 break;
948 case P5_INTF_SEL_GMAC5:
949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
950 val &= ~MHWTRAP_P5_DIS;
951 break;
952 case P5_DISABLED:
953 interface = PHY_INTERFACE_MODE_NA;
954 break;
955 default:
956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
957 priv->p5_intf_sel);
958 goto unlock_exit;
959 }
960
961 /* Setup RGMII settings */
962 if (phy_interface_mode_is_rgmii(interface)) {
963 val |= MHWTRAP_P5_RGMII_MODE;
964
965 /* P5 RGMII RX Clock Control: delay setting for 1000M */
966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
967
968 /* Don't set delay in DSA mode */
969 if (!dsa_is_dsa_port(priv->ds, 5) &&
970 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
971 interface == PHY_INTERFACE_MODE_RGMII_ID))
972 tx_delay = 4; /* n * 0.5 ns */
973
974 /* P5 RGMII TX Clock Control: delay x */
975 mt7530_write(priv, MT7530_P5RGMIITXCR,
976 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
977
978 /* reduce P5 RGMII Tx driving, 8mA */
979 mt7530_write(priv, MT7530_IO_DRV_CR,
980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
981 }
982
983 mt7530_write(priv, MT7530_MHWTRAP, val);
984
985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
987
988 priv->p5_interface = interface;
989
990 unlock_exit:
991 mutex_unlock(&priv->reg_mutex);
992 }
993
994 static int
995 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
996 {
997 struct mt7530_priv *priv = ds->priv;
998 int ret;
999
1000 /* Setup max capability of CPU port at first */
1001 if (priv->info->cpu_port_config) {
1002 ret = priv->info->cpu_port_config(ds, port);
1003 if (ret)
1004 return ret;
1005 }
1006
1007 /* Enable Mediatek header mode on the cpu port */
1008 mt7530_write(priv, MT7530_PVC_P(port),
1009 PORT_SPEC_TAG);
1010
1011 /* Disable flooding by default */
1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
1014
1015 /* Set CPU port number */
1016 if (priv->id == ID_MT7621)
1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1018
1019 /* CPU port gets connected to all user ports of
1020 * the switch.
1021 */
1022 mt7530_write(priv, MT7530_PCR_P(port),
1023 PCR_MATRIX(dsa_user_ports(priv->ds)));
1024
1025 /* Set to fallback mode for independent VLAN learning */
1026 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1027 MT7530_PORT_FALLBACK_MODE);
1028
1029 return 0;
1030 }
1031
1032 static int
1033 mt7530_port_enable(struct dsa_switch *ds, int port,
1034 struct phy_device *phy)
1035 {
1036 struct mt7530_priv *priv = ds->priv;
1037
1038 if (!dsa_is_user_port(ds, port))
1039 return 0;
1040
1041 mutex_lock(&priv->reg_mutex);
1042
1043 /* Allow the user port gets connected to the cpu port and also
1044 * restore the port matrix if the port is the member of a certain
1045 * bridge.
1046 */
1047 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1048 priv->ports[port].enable = true;
1049 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1050 priv->ports[port].pm);
1051 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1052
1053 mutex_unlock(&priv->reg_mutex);
1054
1055 return 0;
1056 }
1057
1058 static void
1059 mt7530_port_disable(struct dsa_switch *ds, int port)
1060 {
1061 struct mt7530_priv *priv = ds->priv;
1062
1063 if (!dsa_is_user_port(ds, port))
1064 return;
1065
1066 mutex_lock(&priv->reg_mutex);
1067
1068 /* Clear up all port matrix which could be restored in the next
1069 * enablement for the port.
1070 */
1071 priv->ports[port].enable = false;
1072 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1073 PCR_MATRIX_CLR);
1074 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1075
1076 mutex_unlock(&priv->reg_mutex);
1077 }
1078
1079 static int
1080 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1081 {
1082 struct mt7530_priv *priv = ds->priv;
1083 struct mii_bus *bus = priv->bus;
1084 int length;
1085 u32 val;
1086
1087 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1088 * largest MTU of the slave ports. Because the switch only has a global
1089 * RX length register, only allowing CPU port here is enough.
1090 */
1091 if (!dsa_is_cpu_port(ds, port))
1092 return 0;
1093
1094 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1095
1096 val = mt7530_mii_read(priv, MT7530_GMACCR);
1097 val &= ~MAX_RX_PKT_LEN_MASK;
1098
1099 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1100 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1101 if (length <= 1522) {
1102 val |= MAX_RX_PKT_LEN_1522;
1103 } else if (length <= 1536) {
1104 val |= MAX_RX_PKT_LEN_1536;
1105 } else if (length <= 1552) {
1106 val |= MAX_RX_PKT_LEN_1552;
1107 } else {
1108 val &= ~MAX_RX_JUMBO_MASK;
1109 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1110 val |= MAX_RX_PKT_LEN_JUMBO;
1111 }
1112
1113 mt7530_mii_write(priv, MT7530_GMACCR, val);
1114
1115 mutex_unlock(&bus->mdio_lock);
1116
1117 return 0;
1118 }
1119
1120 static int
1121 mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1122 {
1123 return MT7530_MAX_MTU;
1124 }
1125
1126 static void
1127 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1128 {
1129 struct mt7530_priv *priv = ds->priv;
1130 u32 stp_state;
1131
1132 switch (state) {
1133 case BR_STATE_DISABLED:
1134 stp_state = MT7530_STP_DISABLED;
1135 break;
1136 case BR_STATE_BLOCKING:
1137 stp_state = MT7530_STP_BLOCKING;
1138 break;
1139 case BR_STATE_LISTENING:
1140 stp_state = MT7530_STP_LISTENING;
1141 break;
1142 case BR_STATE_LEARNING:
1143 stp_state = MT7530_STP_LEARNING;
1144 break;
1145 case BR_STATE_FORWARDING:
1146 default:
1147 stp_state = MT7530_STP_FORWARDING;
1148 break;
1149 }
1150
1151 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1152 FID_PST(FID_BRIDGED, stp_state));
1153 }
1154
1155 static int
1156 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1157 struct switchdev_brport_flags flags,
1158 struct netlink_ext_ack *extack)
1159 {
1160 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1161 BR_BCAST_FLOOD))
1162 return -EINVAL;
1163
1164 return 0;
1165 }
1166
1167 static int
1168 mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1169 struct switchdev_brport_flags flags,
1170 struct netlink_ext_ack *extack)
1171 {
1172 struct mt7530_priv *priv = ds->priv;
1173
1174 if (flags.mask & BR_LEARNING)
1175 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1176 flags.val & BR_LEARNING ? 0 : SA_DIS);
1177
1178 if (flags.mask & BR_FLOOD)
1179 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1180 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1181
1182 if (flags.mask & BR_MCAST_FLOOD)
1183 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1184 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1185
1186 if (flags.mask & BR_BCAST_FLOOD)
1187 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1188 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1189
1190 return 0;
1191 }
1192
1193 static int
1194 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1195 struct net_device *bridge)
1196 {
1197 struct mt7530_priv *priv = ds->priv;
1198 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1199 int i;
1200
1201 mutex_lock(&priv->reg_mutex);
1202
1203 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1204 /* Add this port to the port matrix of the other ports in the
1205 * same bridge. If the port is disabled, port matrix is kept
1206 * and not being setup until the port becomes enabled.
1207 */
1208 if (dsa_is_user_port(ds, i) && i != port) {
1209 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1210 continue;
1211 if (priv->ports[i].enable)
1212 mt7530_set(priv, MT7530_PCR_P(i),
1213 PCR_MATRIX(BIT(port)));
1214 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1215
1216 port_bitmap |= BIT(i);
1217 }
1218 }
1219
1220 /* Add the all other ports to this port matrix. */
1221 if (priv->ports[port].enable)
1222 mt7530_rmw(priv, MT7530_PCR_P(port),
1223 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1224 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1225
1226 /* Set to fallback mode for independent VLAN learning */
1227 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1228 MT7530_PORT_FALLBACK_MODE);
1229
1230 mutex_unlock(&priv->reg_mutex);
1231
1232 return 0;
1233 }
1234
1235 static void
1236 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1237 {
1238 struct mt7530_priv *priv = ds->priv;
1239 bool all_user_ports_removed = true;
1240 int i;
1241
1242 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1243 * bridge. Don't set standalone ports to fallback mode.
1244 */
1245 if (dsa_to_port(ds, port)->bridge_dev)
1246 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1247 MT7530_PORT_FALLBACK_MODE);
1248
1249 mt7530_rmw(priv, MT7530_PVC_P(port),
1250 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
1251 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1252 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1253 MT7530_VLAN_ACC_ALL);
1254
1255 /* Set PVID to 0 */
1256 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1257 G0_PORT_VID_DEF);
1258
1259 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1260 if (dsa_is_user_port(ds, i) &&
1261 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1262 all_user_ports_removed = false;
1263 break;
1264 }
1265 }
1266
1267 /* CPU port also does the same thing until all user ports belonging to
1268 * the CPU port get out of VLAN filtering mode.
1269 */
1270 if (all_user_ports_removed) {
1271 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1272 PCR_MATRIX(dsa_user_ports(priv->ds)));
1273 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1274 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1275 }
1276 }
1277
1278 static void
1279 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1280 {
1281 struct mt7530_priv *priv = ds->priv;
1282
1283 /* Trapped into security mode allows packet forwarding through VLAN
1284 * table lookup.
1285 */
1286 if (dsa_is_user_port(ds, port)) {
1287 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1288 MT7530_PORT_SECURITY_MODE);
1289 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1290 G0_PORT_VID(priv->ports[port].pvid));
1291
1292 /* Only accept tagged frames if PVID is not set */
1293 if (!priv->ports[port].pvid)
1294 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1295 MT7530_VLAN_ACC_TAGGED);
1296 }
1297
1298 /* Set the port as a user port which is to be able to recognize VID
1299 * from incoming packets before fetching entry within the VLAN table.
1300 */
1301 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1302 VLAN_ATTR(MT7530_VLAN_USER) |
1303 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1304 }
1305
1306 static void
1307 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1308 struct net_device *bridge)
1309 {
1310 struct mt7530_priv *priv = ds->priv;
1311 int i;
1312
1313 mutex_lock(&priv->reg_mutex);
1314
1315 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1316 /* Remove this port from the port matrix of the other ports
1317 * in the same bridge. If the port is disabled, port matrix
1318 * is kept and not being setup until the port becomes enabled.
1319 */
1320 if (dsa_is_user_port(ds, i) && i != port) {
1321 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1322 continue;
1323 if (priv->ports[i].enable)
1324 mt7530_clear(priv, MT7530_PCR_P(i),
1325 PCR_MATRIX(BIT(port)));
1326 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1327 }
1328 }
1329
1330 /* Set the cpu port to be the only one in the port matrix of
1331 * this port.
1332 */
1333 if (priv->ports[port].enable)
1334 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1335 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1336 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1337
1338 /* When a port is removed from the bridge, the port would be set up
1339 * back to the default as is at initial boot which is a VLAN-unaware
1340 * port.
1341 */
1342 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1343 MT7530_PORT_MATRIX_MODE);
1344
1345 mutex_unlock(&priv->reg_mutex);
1346 }
1347
1348 static int
1349 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1350 const unsigned char *addr, u16 vid)
1351 {
1352 struct mt7530_priv *priv = ds->priv;
1353 int ret;
1354 u8 port_mask = BIT(port);
1355
1356 mutex_lock(&priv->reg_mutex);
1357 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1358 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1359 mutex_unlock(&priv->reg_mutex);
1360
1361 return ret;
1362 }
1363
1364 static int
1365 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1366 const unsigned char *addr, u16 vid)
1367 {
1368 struct mt7530_priv *priv = ds->priv;
1369 int ret;
1370 u8 port_mask = BIT(port);
1371
1372 mutex_lock(&priv->reg_mutex);
1373 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1374 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1375 mutex_unlock(&priv->reg_mutex);
1376
1377 return ret;
1378 }
1379
1380 static int
1381 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1382 dsa_fdb_dump_cb_t *cb, void *data)
1383 {
1384 struct mt7530_priv *priv = ds->priv;
1385 struct mt7530_fdb _fdb = { 0 };
1386 int cnt = MT7530_NUM_FDB_RECORDS;
1387 int ret = 0;
1388 u32 rsp = 0;
1389
1390 mutex_lock(&priv->reg_mutex);
1391
1392 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1393 if (ret < 0)
1394 goto err;
1395
1396 do {
1397 if (rsp & ATC_SRCH_HIT) {
1398 mt7530_fdb_read(priv, &_fdb);
1399 if (_fdb.port_mask & BIT(port)) {
1400 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1401 data);
1402 if (ret < 0)
1403 break;
1404 }
1405 }
1406 } while (--cnt &&
1407 !(rsp & ATC_SRCH_END) &&
1408 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1409 err:
1410 mutex_unlock(&priv->reg_mutex);
1411
1412 return 0;
1413 }
1414
1415 static int
1416 mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1417 const struct switchdev_obj_port_mdb *mdb)
1418 {
1419 struct mt7530_priv *priv = ds->priv;
1420 const u8 *addr = mdb->addr;
1421 u16 vid = mdb->vid;
1422 u8 port_mask = 0;
1423 int ret;
1424
1425 mutex_lock(&priv->reg_mutex);
1426
1427 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1428 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1429 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1430 & PORT_MAP_MASK;
1431
1432 port_mask |= BIT(port);
1433 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1434 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1435
1436 mutex_unlock(&priv->reg_mutex);
1437
1438 return ret;
1439 }
1440
1441 static int
1442 mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1443 const struct switchdev_obj_port_mdb *mdb)
1444 {
1445 struct mt7530_priv *priv = ds->priv;
1446 const u8 *addr = mdb->addr;
1447 u16 vid = mdb->vid;
1448 u8 port_mask = 0;
1449 int ret;
1450
1451 mutex_lock(&priv->reg_mutex);
1452
1453 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1454 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1455 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1456 & PORT_MAP_MASK;
1457
1458 port_mask &= ~BIT(port);
1459 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1460 port_mask ? STATIC_ENT : STATIC_EMP);
1461 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1462
1463 mutex_unlock(&priv->reg_mutex);
1464
1465 return ret;
1466 }
1467
1468 static int
1469 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1470 {
1471 struct mt7530_dummy_poll p;
1472 u32 val;
1473 int ret;
1474
1475 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1476 mt7530_write(priv, MT7530_VTCR, val);
1477
1478 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1479 ret = readx_poll_timeout(_mt7530_read, &p, val,
1480 !(val & VTCR_BUSY), 20, 20000);
1481 if (ret < 0) {
1482 dev_err(priv->dev, "poll timeout\n");
1483 return ret;
1484 }
1485
1486 val = mt7530_read(priv, MT7530_VTCR);
1487 if (val & VTCR_INVALID) {
1488 dev_err(priv->dev, "read VTCR invalid\n");
1489 return -EINVAL;
1490 }
1491
1492 return 0;
1493 }
1494
1495 static int
1496 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1497 struct netlink_ext_ack *extack)
1498 {
1499 if (vlan_filtering) {
1500 /* The port is being kept as VLAN-unaware port when bridge is
1501 * set up with vlan_filtering not being set, Otherwise, the
1502 * port and the corresponding CPU port is required the setup
1503 * for becoming a VLAN-aware port.
1504 */
1505 mt7530_port_set_vlan_aware(ds, port);
1506 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1507 } else {
1508 mt7530_port_set_vlan_unaware(ds, port);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static void
1515 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1516 struct mt7530_hw_vlan_entry *entry)
1517 {
1518 u8 new_members;
1519 u32 val;
1520
1521 new_members = entry->old_members | BIT(entry->port) |
1522 BIT(MT7530_CPU_PORT);
1523
1524 /* Validate the entry with independent learning, create egress tag per
1525 * VLAN and joining the port as one of the port members.
1526 */
1527 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1528 VLAN_VALID;
1529 mt7530_write(priv, MT7530_VAWD1, val);
1530
1531 /* Decide whether adding tag or not for those outgoing packets from the
1532 * port inside the VLAN.
1533 */
1534 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1535 MT7530_VLAN_EGRESS_TAG;
1536 mt7530_rmw(priv, MT7530_VAWD2,
1537 ETAG_CTRL_P_MASK(entry->port),
1538 ETAG_CTRL_P(entry->port, val));
1539
1540 /* CPU port is always taken as a tagged port for serving more than one
1541 * VLANs across and also being applied with egress type stack mode for
1542 * that VLAN tags would be appended after hardware special tag used as
1543 * DSA tag.
1544 */
1545 mt7530_rmw(priv, MT7530_VAWD2,
1546 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1547 ETAG_CTRL_P(MT7530_CPU_PORT,
1548 MT7530_VLAN_EGRESS_STACK));
1549 }
1550
1551 static void
1552 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1553 struct mt7530_hw_vlan_entry *entry)
1554 {
1555 u8 new_members;
1556 u32 val;
1557
1558 new_members = entry->old_members & ~BIT(entry->port);
1559
1560 val = mt7530_read(priv, MT7530_VAWD1);
1561 if (!(val & VLAN_VALID)) {
1562 dev_err(priv->dev,
1563 "Cannot be deleted due to invalid entry\n");
1564 return;
1565 }
1566
1567 /* If certain member apart from CPU port is still alive in the VLAN,
1568 * the entry would be kept valid. Otherwise, the entry is got to be
1569 * disabled.
1570 */
1571 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1572 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1573 VLAN_VALID;
1574 mt7530_write(priv, MT7530_VAWD1, val);
1575 } else {
1576 mt7530_write(priv, MT7530_VAWD1, 0);
1577 mt7530_write(priv, MT7530_VAWD2, 0);
1578 }
1579 }
1580
1581 static void
1582 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1583 struct mt7530_hw_vlan_entry *entry,
1584 mt7530_vlan_op vlan_op)
1585 {
1586 u32 val;
1587
1588 /* Fetch entry */
1589 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1590
1591 val = mt7530_read(priv, MT7530_VAWD1);
1592
1593 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1594
1595 /* Manipulate entry */
1596 vlan_op(priv, entry);
1597
1598 /* Flush result to hardware */
1599 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1600 }
1601
1602 static int
1603 mt7530_setup_vlan0(struct mt7530_priv *priv)
1604 {
1605 u32 val;
1606
1607 /* Validate the entry with independent learning, keep the original
1608 * ingress tag attribute.
1609 */
1610 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1611 VLAN_VALID;
1612 mt7530_write(priv, MT7530_VAWD1, val);
1613
1614 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1615 }
1616
1617 static int
1618 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1619 const struct switchdev_obj_port_vlan *vlan,
1620 struct netlink_ext_ack *extack)
1621 {
1622 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1623 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1624 struct mt7530_hw_vlan_entry new_entry;
1625 struct mt7530_priv *priv = ds->priv;
1626
1627 mutex_lock(&priv->reg_mutex);
1628
1629 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1630 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
1631
1632 if (pvid) {
1633 priv->ports[port].pvid = vlan->vid;
1634
1635 /* Accept all frames if PVID is set */
1636 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1637 MT7530_VLAN_ACC_ALL);
1638
1639 /* Only configure PVID if VLAN filtering is enabled */
1640 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1641 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1642 G0_PORT_VID_MASK,
1643 G0_PORT_VID(vlan->vid));
1644 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1645 /* This VLAN is overwritten without PVID, so unset it */
1646 priv->ports[port].pvid = G0_PORT_VID_DEF;
1647
1648 /* Only accept tagged frames if the port is VLAN-aware */
1649 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1650 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1651 MT7530_VLAN_ACC_TAGGED);
1652
1653 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1654 G0_PORT_VID_DEF);
1655 }
1656
1657 mutex_unlock(&priv->reg_mutex);
1658
1659 return 0;
1660 }
1661
1662 static int
1663 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1664 const struct switchdev_obj_port_vlan *vlan)
1665 {
1666 struct mt7530_hw_vlan_entry target_entry;
1667 struct mt7530_priv *priv = ds->priv;
1668
1669 mutex_lock(&priv->reg_mutex);
1670
1671 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1672 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1673 mt7530_hw_vlan_del);
1674
1675 /* PVID is being restored to the default whenever the PVID port
1676 * is being removed from the VLAN.
1677 */
1678 if (priv->ports[port].pvid == vlan->vid) {
1679 priv->ports[port].pvid = G0_PORT_VID_DEF;
1680
1681 /* Only accept tagged frames if the port is VLAN-aware */
1682 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1683 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1684 MT7530_VLAN_ACC_TAGGED);
1685
1686 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1687 G0_PORT_VID_DEF);
1688 }
1689
1690
1691 mutex_unlock(&priv->reg_mutex);
1692
1693 return 0;
1694 }
1695
1696 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1697 {
1698 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1699 MIRROR_PORT(val);
1700 }
1701
1702 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1703 {
1704 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1705 MIRROR_PORT(val);
1706 }
1707
1708 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1709 struct dsa_mall_mirror_tc_entry *mirror,
1710 bool ingress)
1711 {
1712 struct mt7530_priv *priv = ds->priv;
1713 int monitor_port;
1714 u32 val;
1715
1716 /* Check for existent entry */
1717 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1718 return -EEXIST;
1719
1720 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1721
1722 /* MT7530 only supports one monitor port */
1723 monitor_port = mt753x_mirror_port_get(priv->id, val);
1724 if (val & MT753X_MIRROR_EN(priv->id) &&
1725 monitor_port != mirror->to_local_port)
1726 return -EEXIST;
1727
1728 val |= MT753X_MIRROR_EN(priv->id);
1729 val &= ~MT753X_MIRROR_MASK(priv->id);
1730 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1731 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1732
1733 val = mt7530_read(priv, MT7530_PCR_P(port));
1734 if (ingress) {
1735 val |= PORT_RX_MIR;
1736 priv->mirror_rx |= BIT(port);
1737 } else {
1738 val |= PORT_TX_MIR;
1739 priv->mirror_tx |= BIT(port);
1740 }
1741 mt7530_write(priv, MT7530_PCR_P(port), val);
1742
1743 return 0;
1744 }
1745
1746 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1747 struct dsa_mall_mirror_tc_entry *mirror)
1748 {
1749 struct mt7530_priv *priv = ds->priv;
1750 u32 val;
1751
1752 val = mt7530_read(priv, MT7530_PCR_P(port));
1753 if (mirror->ingress) {
1754 val &= ~PORT_RX_MIR;
1755 priv->mirror_rx &= ~BIT(port);
1756 } else {
1757 val &= ~PORT_TX_MIR;
1758 priv->mirror_tx &= ~BIT(port);
1759 }
1760 mt7530_write(priv, MT7530_PCR_P(port), val);
1761
1762 if (!priv->mirror_rx && !priv->mirror_tx) {
1763 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1764 val &= ~MT753X_MIRROR_EN(priv->id);
1765 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1766 }
1767 }
1768
1769 static enum dsa_tag_protocol
1770 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1771 enum dsa_tag_protocol mp)
1772 {
1773 return DSA_TAG_PROTO_MTK;
1774 }
1775
1776 #ifdef CONFIG_GPIOLIB
1777 static inline u32
1778 mt7530_gpio_to_bit(unsigned int offset)
1779 {
1780 /* Map GPIO offset to register bit
1781 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1782 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1783 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1784 * [14:12] port 3 LED 0..2 as GPIO 9..11
1785 * [18:16] port 4 LED 0..2 as GPIO 12..14
1786 */
1787 return BIT(offset + offset / 3);
1788 }
1789
1790 static int
1791 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1792 {
1793 struct mt7530_priv *priv = gpiochip_get_data(gc);
1794 u32 bit = mt7530_gpio_to_bit(offset);
1795
1796 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1797 }
1798
1799 static void
1800 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1801 {
1802 struct mt7530_priv *priv = gpiochip_get_data(gc);
1803 u32 bit = mt7530_gpio_to_bit(offset);
1804
1805 if (value)
1806 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1807 else
1808 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1809 }
1810
1811 static int
1812 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1813 {
1814 struct mt7530_priv *priv = gpiochip_get_data(gc);
1815 u32 bit = mt7530_gpio_to_bit(offset);
1816
1817 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1818 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1819 }
1820
1821 static int
1822 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1823 {
1824 struct mt7530_priv *priv = gpiochip_get_data(gc);
1825 u32 bit = mt7530_gpio_to_bit(offset);
1826
1827 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1828 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1829
1830 return 0;
1831 }
1832
1833 static int
1834 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1835 {
1836 struct mt7530_priv *priv = gpiochip_get_data(gc);
1837 u32 bit = mt7530_gpio_to_bit(offset);
1838
1839 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1840
1841 if (value)
1842 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1843 else
1844 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1845
1846 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1847
1848 return 0;
1849 }
1850
1851 static int
1852 mt7530_setup_gpio(struct mt7530_priv *priv)
1853 {
1854 struct device *dev = priv->dev;
1855 struct gpio_chip *gc;
1856
1857 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1858 if (!gc)
1859 return -ENOMEM;
1860
1861 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1862 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1863 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1864
1865 gc->label = "mt7530";
1866 gc->parent = dev;
1867 gc->owner = THIS_MODULE;
1868 gc->get_direction = mt7530_gpio_get_direction;
1869 gc->direction_input = mt7530_gpio_direction_input;
1870 gc->direction_output = mt7530_gpio_direction_output;
1871 gc->get = mt7530_gpio_get;
1872 gc->set = mt7530_gpio_set;
1873 gc->base = -1;
1874 gc->ngpio = 15;
1875 gc->can_sleep = true;
1876
1877 return devm_gpiochip_add_data(dev, gc, priv);
1878 }
1879 #endif /* CONFIG_GPIOLIB */
1880
1881 static irqreturn_t
1882 mt7530_irq_thread_fn(int irq, void *dev_id)
1883 {
1884 struct mt7530_priv *priv = dev_id;
1885 bool handled = false;
1886 u32 val;
1887 int p;
1888
1889 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1890 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1891 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1892 mutex_unlock(&priv->bus->mdio_lock);
1893
1894 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1895 if (BIT(p) & val) {
1896 unsigned int irq;
1897
1898 irq = irq_find_mapping(priv->irq_domain, p);
1899 handle_nested_irq(irq);
1900 handled = true;
1901 }
1902 }
1903
1904 return IRQ_RETVAL(handled);
1905 }
1906
1907 static void
1908 mt7530_irq_mask(struct irq_data *d)
1909 {
1910 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1911
1912 priv->irq_enable &= ~BIT(d->hwirq);
1913 }
1914
1915 static void
1916 mt7530_irq_unmask(struct irq_data *d)
1917 {
1918 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1919
1920 priv->irq_enable |= BIT(d->hwirq);
1921 }
1922
1923 static void
1924 mt7530_irq_bus_lock(struct irq_data *d)
1925 {
1926 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1927
1928 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1929 }
1930
1931 static void
1932 mt7530_irq_bus_sync_unlock(struct irq_data *d)
1933 {
1934 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1935
1936 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1937 mutex_unlock(&priv->bus->mdio_lock);
1938 }
1939
1940 static struct irq_chip mt7530_irq_chip = {
1941 .name = KBUILD_MODNAME,
1942 .irq_mask = mt7530_irq_mask,
1943 .irq_unmask = mt7530_irq_unmask,
1944 .irq_bus_lock = mt7530_irq_bus_lock,
1945 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1946 };
1947
1948 static int
1949 mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1950 irq_hw_number_t hwirq)
1951 {
1952 irq_set_chip_data(irq, domain->host_data);
1953 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1954 irq_set_nested_thread(irq, true);
1955 irq_set_noprobe(irq);
1956
1957 return 0;
1958 }
1959
1960 static const struct irq_domain_ops mt7530_irq_domain_ops = {
1961 .map = mt7530_irq_map,
1962 .xlate = irq_domain_xlate_onecell,
1963 };
1964
1965 static void
1966 mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1967 {
1968 struct dsa_switch *ds = priv->ds;
1969 int p;
1970
1971 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1972 if (BIT(p) & ds->phys_mii_mask) {
1973 unsigned int irq;
1974
1975 irq = irq_create_mapping(priv->irq_domain, p);
1976 ds->slave_mii_bus->irq[p] = irq;
1977 }
1978 }
1979 }
1980
1981 static int
1982 mt7530_setup_irq(struct mt7530_priv *priv)
1983 {
1984 struct device *dev = priv->dev;
1985 struct device_node *np = dev->of_node;
1986 int ret;
1987
1988 if (!of_property_read_bool(np, "interrupt-controller")) {
1989 dev_info(dev, "no interrupt support\n");
1990 return 0;
1991 }
1992
1993 priv->irq = of_irq_get(np, 0);
1994 if (priv->irq <= 0) {
1995 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
1996 return priv->irq ? : -EINVAL;
1997 }
1998
1999 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2000 &mt7530_irq_domain_ops, priv);
2001 if (!priv->irq_domain) {
2002 dev_err(dev, "failed to create IRQ domain\n");
2003 return -ENOMEM;
2004 }
2005
2006 /* This register must be set for MT7530 to properly fire interrupts */
2007 if (priv->id != ID_MT7531)
2008 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2009
2010 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2011 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2012 if (ret) {
2013 irq_domain_remove(priv->irq_domain);
2014 dev_err(dev, "failed to request IRQ: %d\n", ret);
2015 return ret;
2016 }
2017
2018 return 0;
2019 }
2020
2021 static void
2022 mt7530_free_mdio_irq(struct mt7530_priv *priv)
2023 {
2024 int p;
2025
2026 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2027 if (BIT(p) & priv->ds->phys_mii_mask) {
2028 unsigned int irq;
2029
2030 irq = irq_find_mapping(priv->irq_domain, p);
2031 irq_dispose_mapping(irq);
2032 }
2033 }
2034 }
2035
2036 static void
2037 mt7530_free_irq_common(struct mt7530_priv *priv)
2038 {
2039 free_irq(priv->irq, priv);
2040 irq_domain_remove(priv->irq_domain);
2041 }
2042
2043 static void
2044 mt7530_free_irq(struct mt7530_priv *priv)
2045 {
2046 mt7530_free_mdio_irq(priv);
2047 mt7530_free_irq_common(priv);
2048 }
2049
2050 static int
2051 mt7530_setup_mdio(struct mt7530_priv *priv)
2052 {
2053 struct dsa_switch *ds = priv->ds;
2054 struct device *dev = priv->dev;
2055 struct mii_bus *bus;
2056 static int idx;
2057 int ret;
2058
2059 bus = devm_mdiobus_alloc(dev);
2060 if (!bus)
2061 return -ENOMEM;
2062
2063 ds->slave_mii_bus = bus;
2064 bus->priv = priv;
2065 bus->name = KBUILD_MODNAME "-mii";
2066 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2067 bus->read = mt753x_phy_read;
2068 bus->write = mt753x_phy_write;
2069 bus->parent = dev;
2070 bus->phy_mask = ~ds->phys_mii_mask;
2071
2072 if (priv->irq)
2073 mt7530_setup_mdio_irq(priv);
2074
2075 ret = mdiobus_register(bus);
2076 if (ret) {
2077 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2078 if (priv->irq)
2079 mt7530_free_mdio_irq(priv);
2080 }
2081
2082 return ret;
2083 }
2084
2085 static int
2086 mt7530_setup(struct dsa_switch *ds)
2087 {
2088 struct mt7530_priv *priv = ds->priv;
2089 struct device_node *phy_node;
2090 struct device_node *mac_np;
2091 struct mt7530_dummy_poll p;
2092 phy_interface_t interface;
2093 struct device_node *dn;
2094 u32 id, val;
2095 int ret, i;
2096
2097 /* The parent node of master netdev which holds the common system
2098 * controller also is the container for two GMACs nodes representing
2099 * as two netdev instances.
2100 */
2101 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
2102 ds->assisted_learning_on_cpu_port = true;
2103 ds->mtu_enforcement_ingress = true;
2104
2105 if (priv->id == ID_MT7530) {
2106 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2107 ret = regulator_enable(priv->core_pwr);
2108 if (ret < 0) {
2109 dev_err(priv->dev,
2110 "Failed to enable core power: %d\n", ret);
2111 return ret;
2112 }
2113
2114 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2115 ret = regulator_enable(priv->io_pwr);
2116 if (ret < 0) {
2117 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2118 ret);
2119 return ret;
2120 }
2121 }
2122
2123 /* Reset whole chip through gpio pin or memory-mapped registers for
2124 * different type of hardware
2125 */
2126 if (priv->mcm) {
2127 reset_control_assert(priv->rstc);
2128 usleep_range(1000, 1100);
2129 reset_control_deassert(priv->rstc);
2130 } else {
2131 gpiod_set_value_cansleep(priv->reset, 0);
2132 usleep_range(1000, 1100);
2133 gpiod_set_value_cansleep(priv->reset, 1);
2134 }
2135
2136 /* Waiting for MT7530 got to stable */
2137 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2138 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2139 20, 1000000);
2140 if (ret < 0) {
2141 dev_err(priv->dev, "reset timeout\n");
2142 return ret;
2143 }
2144
2145 id = mt7530_read(priv, MT7530_CREV);
2146 id >>= CHIP_NAME_SHIFT;
2147 if (id != MT7530_ID) {
2148 dev_err(priv->dev, "chip %x can't be supported\n", id);
2149 return -ENODEV;
2150 }
2151
2152 /* Reset the switch through internal reset */
2153 mt7530_write(priv, MT7530_SYS_CTRL,
2154 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2155 SYS_CTRL_REG_RST);
2156
2157 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2158 val = mt7530_read(priv, MT7530_MHWTRAP);
2159 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2160 val |= MHWTRAP_MANUAL;
2161 mt7530_write(priv, MT7530_MHWTRAP, val);
2162
2163 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2164
2165 /* Enable and reset MIB counters */
2166 mt7530_mib_reset(ds);
2167
2168 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2169 /* Disable forwarding by default on all ports */
2170 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2171 PCR_MATRIX_CLR);
2172
2173 /* Disable learning by default on all ports */
2174 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2175
2176 if (dsa_is_cpu_port(ds, i)) {
2177 ret = mt753x_cpu_port_enable(ds, i);
2178 if (ret)
2179 return ret;
2180 } else {
2181 mt7530_port_disable(ds, i);
2182
2183 /* Set default PVID to 0 on all user ports */
2184 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2185 G0_PORT_VID_DEF);
2186 }
2187 /* Enable consistent egress tag */
2188 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2189 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2190 }
2191
2192 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2193 ret = mt7530_setup_vlan0(priv);
2194 if (ret)
2195 return ret;
2196
2197 /* Setup port 5 */
2198 priv->p5_intf_sel = P5_DISABLED;
2199 interface = PHY_INTERFACE_MODE_NA;
2200
2201 if (!dsa_is_unused_port(ds, 5)) {
2202 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2203 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2204 if (ret && ret != -ENODEV)
2205 return ret;
2206 } else {
2207 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2208 for_each_child_of_node(dn, mac_np) {
2209 if (!of_device_is_compatible(mac_np,
2210 "mediatek,eth-mac"))
2211 continue;
2212
2213 ret = of_property_read_u32(mac_np, "reg", &id);
2214 if (ret < 0 || id != 1)
2215 continue;
2216
2217 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
2218 if (!phy_node)
2219 continue;
2220
2221 if (phy_node->parent == priv->dev->of_node->parent) {
2222 ret = of_get_phy_mode(mac_np, &interface);
2223 if (ret && ret != -ENODEV) {
2224 of_node_put(mac_np);
2225 return ret;
2226 }
2227 id = of_mdio_parse_addr(ds->dev, phy_node);
2228 if (id == 0)
2229 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2230 if (id == 4)
2231 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2232 }
2233 of_node_put(mac_np);
2234 of_node_put(phy_node);
2235 break;
2236 }
2237 }
2238
2239 #ifdef CONFIG_GPIOLIB
2240 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2241 ret = mt7530_setup_gpio(priv);
2242 if (ret)
2243 return ret;
2244 }
2245 #endif /* CONFIG_GPIOLIB */
2246
2247 mt7530_setup_port5(ds, interface);
2248
2249 /* Flush the FDB table */
2250 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2251 if (ret < 0)
2252 return ret;
2253
2254 return 0;
2255 }
2256
2257 static int
2258 mt7531_setup(struct dsa_switch *ds)
2259 {
2260 struct mt7530_priv *priv = ds->priv;
2261 struct mt7530_dummy_poll p;
2262 u32 val, id;
2263 int ret, i;
2264
2265 /* Reset whole chip through gpio pin or memory-mapped registers for
2266 * different type of hardware
2267 */
2268 if (priv->mcm) {
2269 reset_control_assert(priv->rstc);
2270 usleep_range(1000, 1100);
2271 reset_control_deassert(priv->rstc);
2272 } else {
2273 gpiod_set_value_cansleep(priv->reset, 0);
2274 usleep_range(1000, 1100);
2275 gpiod_set_value_cansleep(priv->reset, 1);
2276 }
2277
2278 /* Waiting for MT7530 got to stable */
2279 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2280 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2281 20, 1000000);
2282 if (ret < 0) {
2283 dev_err(priv->dev, "reset timeout\n");
2284 return ret;
2285 }
2286
2287 id = mt7530_read(priv, MT7531_CREV);
2288 id >>= CHIP_NAME_SHIFT;
2289
2290 if (id != MT7531_ID) {
2291 dev_err(priv->dev, "chip %x can't be supported\n", id);
2292 return -ENODEV;
2293 }
2294
2295 /* Reset the switch through internal reset */
2296 mt7530_write(priv, MT7530_SYS_CTRL,
2297 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2298 SYS_CTRL_REG_RST);
2299
2300 if (mt7531_dual_sgmii_supported(priv)) {
2301 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2302
2303 /* Let ds->slave_mii_bus be able to access external phy. */
2304 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2305 MT7531_EXT_P_MDC_11);
2306 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2307 MT7531_EXT_P_MDIO_12);
2308 } else {
2309 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2310 }
2311 dev_dbg(ds->dev, "P5 support %s interface\n",
2312 p5_intf_modes(priv->p5_intf_sel));
2313
2314 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2315 MT7531_GPIO0_INTERRUPT);
2316
2317 /* Let phylink decide the interface later. */
2318 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2319 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2320
2321 /* Enable PHY core PLL, since phy_device has not yet been created
2322 * provided for phy_[read,write]_mmd_indirect is called, we provide
2323 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2324 * function.
2325 */
2326 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2327 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2328 val |= MT7531_PHY_PLL_BYPASS_MODE;
2329 val &= ~MT7531_PHY_PLL_OFF;
2330 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2331 CORE_PLL_GROUP4, val);
2332
2333 /* BPDU to CPU port */
2334 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2335 BIT(MT7530_CPU_PORT));
2336 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2337 MT753X_BPDU_CPU_ONLY);
2338
2339 /* Enable and reset MIB counters */
2340 mt7530_mib_reset(ds);
2341
2342 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2343 /* Disable forwarding by default on all ports */
2344 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2345 PCR_MATRIX_CLR);
2346
2347 /* Disable learning by default on all ports */
2348 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2349
2350 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2351
2352 if (dsa_is_cpu_port(ds, i)) {
2353 ret = mt753x_cpu_port_enable(ds, i);
2354 if (ret)
2355 return ret;
2356 } else {
2357 mt7530_port_disable(ds, i);
2358
2359 /* Set default PVID to 0 on all user ports */
2360 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2361 G0_PORT_VID_DEF);
2362 }
2363
2364 /* Enable consistent egress tag */
2365 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2366 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2367 }
2368
2369 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2370 ret = mt7530_setup_vlan0(priv);
2371 if (ret)
2372 return ret;
2373
2374 ds->assisted_learning_on_cpu_port = true;
2375 ds->mtu_enforcement_ingress = true;
2376
2377 /* Flush the FDB table */
2378 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2379 if (ret < 0)
2380 return ret;
2381
2382 return 0;
2383 }
2384
2385 static bool
2386 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2387 const struct phylink_link_state *state)
2388 {
2389 struct mt7530_priv *priv = ds->priv;
2390
2391 switch (port) {
2392 case 0 ... 4: /* Internal phy */
2393 if (state->interface != PHY_INTERFACE_MODE_GMII)
2394 return false;
2395 break;
2396 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2397 if (!phy_interface_mode_is_rgmii(state->interface) &&
2398 state->interface != PHY_INTERFACE_MODE_MII &&
2399 state->interface != PHY_INTERFACE_MODE_GMII)
2400 return false;
2401 break;
2402 case 6: /* 1st cpu port */
2403 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2404 state->interface != PHY_INTERFACE_MODE_TRGMII)
2405 return false;
2406 break;
2407 default:
2408 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2409 port);
2410 return false;
2411 }
2412
2413 return true;
2414 }
2415
2416 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2417 {
2418 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2419 }
2420
2421 static bool
2422 mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2423 const struct phylink_link_state *state)
2424 {
2425 struct mt7530_priv *priv = ds->priv;
2426
2427 switch (port) {
2428 case 0 ... 4: /* Internal phy */
2429 if (state->interface != PHY_INTERFACE_MODE_GMII)
2430 return false;
2431 break;
2432 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2433 if (mt7531_is_rgmii_port(priv, port))
2434 return phy_interface_mode_is_rgmii(state->interface);
2435 fallthrough;
2436 case 6: /* 1st cpu port supports sgmii/8023z only */
2437 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2438 !phy_interface_mode_is_8023z(state->interface))
2439 return false;
2440 break;
2441 default:
2442 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2443 port);
2444 return false;
2445 }
2446
2447 return true;
2448 }
2449
2450 static bool
2451 mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2452 const struct phylink_link_state *state)
2453 {
2454 struct mt7530_priv *priv = ds->priv;
2455
2456 return priv->info->phy_mode_supported(ds, port, state);
2457 }
2458
2459 static int
2460 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2461 {
2462 struct mt7530_priv *priv = ds->priv;
2463
2464 return priv->info->pad_setup(ds, state->interface);
2465 }
2466
2467 static int
2468 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2469 phy_interface_t interface)
2470 {
2471 struct mt7530_priv *priv = ds->priv;
2472
2473 /* Only need to setup port5. */
2474 if (port != 5)
2475 return 0;
2476
2477 mt7530_setup_port5(priv->ds, interface);
2478
2479 return 0;
2480 }
2481
2482 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2483 phy_interface_t interface,
2484 struct phy_device *phydev)
2485 {
2486 u32 val;
2487
2488 if (!mt7531_is_rgmii_port(priv, port)) {
2489 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2490 port);
2491 return -EINVAL;
2492 }
2493
2494 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2495 val |= GP_CLK_EN;
2496 val &= ~GP_MODE_MASK;
2497 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2498 val &= ~CLK_SKEW_IN_MASK;
2499 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2500 val &= ~CLK_SKEW_OUT_MASK;
2501 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2502 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2503
2504 /* Do not adjust rgmii delay when vendor phy driver presents. */
2505 if (!phydev || phy_driver_is_genphy(phydev)) {
2506 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2507 switch (interface) {
2508 case PHY_INTERFACE_MODE_RGMII:
2509 val |= TXCLK_NO_REVERSE;
2510 val |= RXCLK_NO_DELAY;
2511 break;
2512 case PHY_INTERFACE_MODE_RGMII_RXID:
2513 val |= TXCLK_NO_REVERSE;
2514 break;
2515 case PHY_INTERFACE_MODE_RGMII_TXID:
2516 val |= RXCLK_NO_DELAY;
2517 break;
2518 case PHY_INTERFACE_MODE_RGMII_ID:
2519 break;
2520 default:
2521 return -EINVAL;
2522 }
2523 }
2524 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2525
2526 return 0;
2527 }
2528
2529 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2530 unsigned long *supported)
2531 {
2532 /* Port5 supports ethier RGMII or SGMII.
2533 * Port6 supports SGMII only.
2534 */
2535 switch (port) {
2536 case 5:
2537 if (mt7531_is_rgmii_port(priv, port))
2538 break;
2539 fallthrough;
2540 case 6:
2541 phylink_set(supported, 1000baseX_Full);
2542 phylink_set(supported, 2500baseX_Full);
2543 phylink_set(supported, 2500baseT_Full);
2544 }
2545 }
2546
2547 static void
2548 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2549 unsigned int mode, phy_interface_t interface,
2550 int speed, int duplex)
2551 {
2552 struct mt7530_priv *priv = ds->priv;
2553 unsigned int val;
2554
2555 /* For adjusting speed and duplex of SGMII force mode. */
2556 if (interface != PHY_INTERFACE_MODE_SGMII ||
2557 phylink_autoneg_inband(mode))
2558 return;
2559
2560 /* SGMII force mode setting */
2561 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2562 val &= ~MT7531_SGMII_IF_MODE_MASK;
2563
2564 switch (speed) {
2565 case SPEED_10:
2566 val |= MT7531_SGMII_FORCE_SPEED_10;
2567 break;
2568 case SPEED_100:
2569 val |= MT7531_SGMII_FORCE_SPEED_100;
2570 break;
2571 case SPEED_1000:
2572 val |= MT7531_SGMII_FORCE_SPEED_1000;
2573 break;
2574 }
2575
2576 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2577 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2578 */
2579 if ((speed == SPEED_10 || speed == SPEED_100) &&
2580 duplex != DUPLEX_FULL)
2581 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2582
2583 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2584 }
2585
2586 static bool mt753x_is_mac_port(u32 port)
2587 {
2588 return (port == 5 || port == 6);
2589 }
2590
2591 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2592 phy_interface_t interface)
2593 {
2594 u32 val;
2595
2596 if (!mt753x_is_mac_port(port))
2597 return -EINVAL;
2598
2599 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2600 MT7531_SGMII_PHYA_PWD);
2601
2602 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2603 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2604 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2605 * encoding.
2606 */
2607 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2608 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2609 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2610
2611 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2612
2613 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2614 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2615 */
2616 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2617 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2618 MT7531_SGMII_FORCE_SPEED_1000);
2619
2620 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2621
2622 return 0;
2623 }
2624
2625 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2626 phy_interface_t interface)
2627 {
2628 if (!mt753x_is_mac_port(port))
2629 return -EINVAL;
2630
2631 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2632 MT7531_SGMII_PHYA_PWD);
2633
2634 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2635 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2636
2637 mt7530_set(priv, MT7531_SGMII_MODE(port),
2638 MT7531_SGMII_REMOTE_FAULT_DIS |
2639 MT7531_SGMII_SPEED_DUPLEX_AN);
2640
2641 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2642 MT7531_SGMII_TX_CONFIG_MASK, 1);
2643
2644 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2645
2646 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2647
2648 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2649
2650 return 0;
2651 }
2652
2653 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2654 {
2655 struct mt7530_priv *priv = ds->priv;
2656 u32 val;
2657
2658 /* Only restart AN when AN is enabled */
2659 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2660 if (val & MT7531_SGMII_AN_ENABLE) {
2661 val |= MT7531_SGMII_AN_RESTART;
2662 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2663 }
2664 }
2665
2666 static int
2667 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2668 phy_interface_t interface)
2669 {
2670 struct mt7530_priv *priv = ds->priv;
2671 struct phy_device *phydev;
2672 struct dsa_port *dp;
2673
2674 if (!mt753x_is_mac_port(port)) {
2675 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2676 return -EINVAL;
2677 }
2678
2679 switch (interface) {
2680 case PHY_INTERFACE_MODE_RGMII:
2681 case PHY_INTERFACE_MODE_RGMII_ID:
2682 case PHY_INTERFACE_MODE_RGMII_RXID:
2683 case PHY_INTERFACE_MODE_RGMII_TXID:
2684 dp = dsa_to_port(ds, port);
2685 phydev = dp->slave->phydev;
2686 return mt7531_rgmii_setup(priv, port, interface, phydev);
2687 case PHY_INTERFACE_MODE_SGMII:
2688 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2689 case PHY_INTERFACE_MODE_NA:
2690 case PHY_INTERFACE_MODE_1000BASEX:
2691 case PHY_INTERFACE_MODE_2500BASEX:
2692 if (phylink_autoneg_inband(mode))
2693 return -EINVAL;
2694
2695 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2696 default:
2697 return -EINVAL;
2698 }
2699
2700 return -EINVAL;
2701 }
2702
2703 static int
2704 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2705 const struct phylink_link_state *state)
2706 {
2707 struct mt7530_priv *priv = ds->priv;
2708
2709 return priv->info->mac_port_config(ds, port, mode, state->interface);
2710 }
2711
2712 static void
2713 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2714 const struct phylink_link_state *state)
2715 {
2716 struct mt7530_priv *priv = ds->priv;
2717 u32 mcr_cur, mcr_new;
2718
2719 if (!mt753x_phy_mode_supported(ds, port, state))
2720 goto unsupported;
2721
2722 switch (port) {
2723 case 0 ... 4: /* Internal phy */
2724 if (state->interface != PHY_INTERFACE_MODE_GMII)
2725 goto unsupported;
2726 break;
2727 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2728 if (priv->p5_interface == state->interface)
2729 break;
2730
2731 if (mt753x_mac_config(ds, port, mode, state) < 0)
2732 goto unsupported;
2733
2734 if (priv->p5_intf_sel != P5_DISABLED)
2735 priv->p5_interface = state->interface;
2736 break;
2737 case 6: /* 1st cpu port */
2738 if (priv->p6_interface == state->interface)
2739 break;
2740
2741 mt753x_pad_setup(ds, state);
2742
2743 if (mt753x_mac_config(ds, port, mode, state) < 0)
2744 goto unsupported;
2745
2746 priv->p6_interface = state->interface;
2747 break;
2748 default:
2749 unsupported:
2750 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2751 __func__, phy_modes(state->interface), port);
2752 return;
2753 }
2754
2755 if (phylink_autoneg_inband(mode) &&
2756 state->interface != PHY_INTERFACE_MODE_SGMII) {
2757 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2758 __func__);
2759 return;
2760 }
2761
2762 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2763 mcr_new = mcr_cur;
2764 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2765 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2766 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2767
2768 /* Are we connected to external phy */
2769 if (port == 5 && dsa_is_user_port(ds, 5))
2770 mcr_new |= PMCR_EXT_PHY;
2771
2772 if (mcr_new != mcr_cur)
2773 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2774 }
2775
2776 static void
2777 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2778 {
2779 struct mt7530_priv *priv = ds->priv;
2780
2781 if (!priv->info->mac_pcs_an_restart)
2782 return;
2783
2784 priv->info->mac_pcs_an_restart(ds, port);
2785 }
2786
2787 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2788 unsigned int mode,
2789 phy_interface_t interface)
2790 {
2791 struct mt7530_priv *priv = ds->priv;
2792
2793 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2794 }
2795
2796 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2797 unsigned int mode, phy_interface_t interface,
2798 int speed, int duplex)
2799 {
2800 struct mt7530_priv *priv = ds->priv;
2801
2802 if (!priv->info->mac_pcs_link_up)
2803 return;
2804
2805 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2806 }
2807
2808 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2809 unsigned int mode,
2810 phy_interface_t interface,
2811 struct phy_device *phydev,
2812 int speed, int duplex,
2813 bool tx_pause, bool rx_pause)
2814 {
2815 struct mt7530_priv *priv = ds->priv;
2816 u32 mcr;
2817
2818 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2819
2820 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2821
2822 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2823 * variants.
2824 */
2825 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2826 (phy_interface_mode_is_8023z(interface))) {
2827 speed = SPEED_1000;
2828 duplex = DUPLEX_FULL;
2829 }
2830
2831 switch (speed) {
2832 case SPEED_1000:
2833 mcr |= PMCR_FORCE_SPEED_1000;
2834 break;
2835 case SPEED_100:
2836 mcr |= PMCR_FORCE_SPEED_100;
2837 break;
2838 }
2839 if (duplex == DUPLEX_FULL) {
2840 mcr |= PMCR_FORCE_FDX;
2841 if (tx_pause)
2842 mcr |= PMCR_TX_FC_EN;
2843 if (rx_pause)
2844 mcr |= PMCR_RX_FC_EN;
2845 }
2846
2847 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
2848 switch (speed) {
2849 case SPEED_1000:
2850 mcr |= PMCR_FORCE_EEE1G;
2851 break;
2852 case SPEED_100:
2853 mcr |= PMCR_FORCE_EEE100;
2854 break;
2855 }
2856 }
2857
2858 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2859 }
2860
2861 static int
2862 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2863 {
2864 struct mt7530_priv *priv = ds->priv;
2865 phy_interface_t interface;
2866 int speed;
2867 int ret;
2868
2869 switch (port) {
2870 case 5:
2871 if (mt7531_is_rgmii_port(priv, port))
2872 interface = PHY_INTERFACE_MODE_RGMII;
2873 else
2874 interface = PHY_INTERFACE_MODE_2500BASEX;
2875
2876 priv->p5_interface = interface;
2877 break;
2878 case 6:
2879 interface = PHY_INTERFACE_MODE_2500BASEX;
2880
2881 mt7531_pad_setup(ds, interface);
2882
2883 priv->p6_interface = interface;
2884 break;
2885 default:
2886 return -EINVAL;
2887 }
2888
2889 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2890 speed = SPEED_2500;
2891 else
2892 speed = SPEED_1000;
2893
2894 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2895 if (ret)
2896 return ret;
2897 mt7530_write(priv, MT7530_PMCR_P(port),
2898 PMCR_CPU_PORT_SETTING(priv->id));
2899 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2900 speed, DUPLEX_FULL, true, true);
2901
2902 return 0;
2903 }
2904
2905 static void
2906 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2907 unsigned long *supported)
2908 {
2909 if (port == 5)
2910 phylink_set(supported, 1000baseX_Full);
2911 }
2912
2913 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2914 unsigned long *supported)
2915 {
2916 struct mt7530_priv *priv = ds->priv;
2917
2918 mt7531_sgmii_validate(priv, port, supported);
2919 }
2920
2921 static void
2922 mt753x_phylink_validate(struct dsa_switch *ds, int port,
2923 unsigned long *supported,
2924 struct phylink_link_state *state)
2925 {
2926 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2927 struct mt7530_priv *priv = ds->priv;
2928
2929 if (state->interface != PHY_INTERFACE_MODE_NA &&
2930 !mt753x_phy_mode_supported(ds, port, state)) {
2931 linkmode_zero(supported);
2932 return;
2933 }
2934
2935 phylink_set_port_modes(mask);
2936
2937 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2938 !phy_interface_mode_is_8023z(state->interface)) {
2939 phylink_set(mask, 10baseT_Half);
2940 phylink_set(mask, 10baseT_Full);
2941 phylink_set(mask, 100baseT_Half);
2942 phylink_set(mask, 100baseT_Full);
2943 phylink_set(mask, Autoneg);
2944 }
2945
2946 /* This switch only supports 1G full-duplex. */
2947 if (state->interface != PHY_INTERFACE_MODE_MII)
2948 phylink_set(mask, 1000baseT_Full);
2949
2950 priv->info->mac_port_validate(ds, port, mask);
2951
2952 phylink_set(mask, Pause);
2953 phylink_set(mask, Asym_Pause);
2954
2955 linkmode_and(supported, supported, mask);
2956 linkmode_and(state->advertising, state->advertising, mask);
2957
2958 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2959 * to advertise both, only report advertising at 2500BaseX.
2960 */
2961 phylink_helper_basex_speed(state);
2962 }
2963
2964 static int
2965 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2966 struct phylink_link_state *state)
2967 {
2968 struct mt7530_priv *priv = ds->priv;
2969 u32 pmsr;
2970
2971 if (port < 0 || port >= MT7530_NUM_PORTS)
2972 return -EINVAL;
2973
2974 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2975
2976 state->link = (pmsr & PMSR_LINK);
2977 state->an_complete = state->link;
2978 state->duplex = !!(pmsr & PMSR_DPX);
2979
2980 switch (pmsr & PMSR_SPEED_MASK) {
2981 case PMSR_SPEED_10:
2982 state->speed = SPEED_10;
2983 break;
2984 case PMSR_SPEED_100:
2985 state->speed = SPEED_100;
2986 break;
2987 case PMSR_SPEED_1000:
2988 state->speed = SPEED_1000;
2989 break;
2990 default:
2991 state->speed = SPEED_UNKNOWN;
2992 break;
2993 }
2994
2995 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2996 if (pmsr & PMSR_RX_FC)
2997 state->pause |= MLO_PAUSE_RX;
2998 if (pmsr & PMSR_TX_FC)
2999 state->pause |= MLO_PAUSE_TX;
3000
3001 return 1;
3002 }
3003
3004 static int
3005 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
3006 struct phylink_link_state *state)
3007 {
3008 u32 status, val;
3009 u16 config_reg;
3010
3011 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
3012 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
3013 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
3014 (status & MT7531_SGMII_AN_ENABLE)) {
3015 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
3016 config_reg = val >> 16;
3017
3018 switch (config_reg & LPA_SGMII_SPD_MASK) {
3019 case LPA_SGMII_1000:
3020 state->speed = SPEED_1000;
3021 break;
3022 case LPA_SGMII_100:
3023 state->speed = SPEED_100;
3024 break;
3025 case LPA_SGMII_10:
3026 state->speed = SPEED_10;
3027 break;
3028 default:
3029 dev_err(priv->dev, "invalid sgmii PHY speed\n");
3030 state->link = false;
3031 return -EINVAL;
3032 }
3033
3034 if (config_reg & LPA_SGMII_FULL_DUPLEX)
3035 state->duplex = DUPLEX_FULL;
3036 else
3037 state->duplex = DUPLEX_HALF;
3038 }
3039
3040 return 0;
3041 }
3042
3043 static int
3044 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
3045 struct phylink_link_state *state)
3046 {
3047 struct mt7530_priv *priv = ds->priv;
3048
3049 if (state->interface == PHY_INTERFACE_MODE_SGMII)
3050 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
3051
3052 return -EOPNOTSUPP;
3053 }
3054
3055 static int
3056 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
3057 struct phylink_link_state *state)
3058 {
3059 struct mt7530_priv *priv = ds->priv;
3060
3061 return priv->info->mac_port_get_state(ds, port, state);
3062 }
3063
3064 static int
3065 mt753x_setup(struct dsa_switch *ds)
3066 {
3067 struct mt7530_priv *priv = ds->priv;
3068 int ret = priv->info->sw_setup(ds);
3069
3070 if (ret)
3071 return ret;
3072
3073 ret = mt7530_setup_irq(priv);
3074 if (ret)
3075 return ret;
3076
3077 ret = mt7530_setup_mdio(priv);
3078 if (ret && priv->irq)
3079 mt7530_free_irq_common(priv);
3080
3081 return ret;
3082 }
3083
3084 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3085 struct ethtool_eee *e)
3086 {
3087 struct mt7530_priv *priv = ds->priv;
3088 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3089
3090 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3091 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3092
3093 return 0;
3094 }
3095
3096 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3097 struct ethtool_eee *e)
3098 {
3099 struct mt7530_priv *priv = ds->priv;
3100 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3101
3102 if (e->tx_lpi_timer > 0xFFF)
3103 return -EINVAL;
3104
3105 set = SET_LPI_THRESH(e->tx_lpi_timer);
3106 if (!e->tx_lpi_enabled)
3107 /* Force LPI Mode without a delay */
3108 set |= LPI_MODE_EN;
3109 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3110
3111 return 0;
3112 }
3113
3114 static const struct dsa_switch_ops mt7530_switch_ops = {
3115 .get_tag_protocol = mtk_get_tag_protocol,
3116 .setup = mt753x_setup,
3117 .get_strings = mt7530_get_strings,
3118 .get_ethtool_stats = mt7530_get_ethtool_stats,
3119 .get_sset_count = mt7530_get_sset_count,
3120 .set_ageing_time = mt7530_set_ageing_time,
3121 .port_enable = mt7530_port_enable,
3122 .port_disable = mt7530_port_disable,
3123 .port_change_mtu = mt7530_port_change_mtu,
3124 .port_max_mtu = mt7530_port_max_mtu,
3125 .port_stp_state_set = mt7530_stp_state_set,
3126 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3127 .port_bridge_flags = mt7530_port_bridge_flags,
3128 .port_bridge_join = mt7530_port_bridge_join,
3129 .port_bridge_leave = mt7530_port_bridge_leave,
3130 .port_fdb_add = mt7530_port_fdb_add,
3131 .port_fdb_del = mt7530_port_fdb_del,
3132 .port_fdb_dump = mt7530_port_fdb_dump,
3133 .port_mdb_add = mt7530_port_mdb_add,
3134 .port_mdb_del = mt7530_port_mdb_del,
3135 .port_vlan_filtering = mt7530_port_vlan_filtering,
3136 .port_vlan_add = mt7530_port_vlan_add,
3137 .port_vlan_del = mt7530_port_vlan_del,
3138 .port_mirror_add = mt753x_port_mirror_add,
3139 .port_mirror_del = mt753x_port_mirror_del,
3140 .phylink_validate = mt753x_phylink_validate,
3141 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
3142 .phylink_mac_config = mt753x_phylink_mac_config,
3143 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
3144 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3145 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
3146 .get_mac_eee = mt753x_get_mac_eee,
3147 .set_mac_eee = mt753x_set_mac_eee,
3148 };
3149
3150 static const struct mt753x_info mt753x_table[] = {
3151 [ID_MT7621] = {
3152 .id = ID_MT7621,
3153 .sw_setup = mt7530_setup,
3154 .phy_read = mt7530_phy_read,
3155 .phy_write = mt7530_phy_write,
3156 .pad_setup = mt7530_pad_clk_setup,
3157 .phy_mode_supported = mt7530_phy_mode_supported,
3158 .mac_port_validate = mt7530_mac_port_validate,
3159 .mac_port_get_state = mt7530_phylink_mac_link_state,
3160 .mac_port_config = mt7530_mac_config,
3161 },
3162 [ID_MT7530] = {
3163 .id = ID_MT7530,
3164 .sw_setup = mt7530_setup,
3165 .phy_read = mt7530_phy_read,
3166 .phy_write = mt7530_phy_write,
3167 .pad_setup = mt7530_pad_clk_setup,
3168 .phy_mode_supported = mt7530_phy_mode_supported,
3169 .mac_port_validate = mt7530_mac_port_validate,
3170 .mac_port_get_state = mt7530_phylink_mac_link_state,
3171 .mac_port_config = mt7530_mac_config,
3172 },
3173 [ID_MT7531] = {
3174 .id = ID_MT7531,
3175 .sw_setup = mt7531_setup,
3176 .phy_read = mt7531_ind_phy_read,
3177 .phy_write = mt7531_ind_phy_write,
3178 .pad_setup = mt7531_pad_setup,
3179 .cpu_port_config = mt7531_cpu_port_config,
3180 .phy_mode_supported = mt7531_phy_mode_supported,
3181 .mac_port_validate = mt7531_mac_port_validate,
3182 .mac_port_get_state = mt7531_phylink_mac_link_state,
3183 .mac_port_config = mt7531_mac_config,
3184 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
3185 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
3186 },
3187 };
3188
3189 static const struct of_device_id mt7530_of_match[] = {
3190 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3191 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
3192 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
3193 { /* sentinel */ },
3194 };
3195 MODULE_DEVICE_TABLE(of, mt7530_of_match);
3196
3197 static int
3198 mt7530_probe(struct mdio_device *mdiodev)
3199 {
3200 struct mt7530_priv *priv;
3201 struct device_node *dn;
3202
3203 dn = mdiodev->dev.of_node;
3204
3205 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3206 if (!priv)
3207 return -ENOMEM;
3208
3209 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
3210 if (!priv->ds)
3211 return -ENOMEM;
3212
3213 priv->ds->dev = &mdiodev->dev;
3214 priv->ds->num_ports = DSA_MAX_PORTS;
3215
3216 /* Use medatek,mcm property to distinguish hardware type that would
3217 * casues a little bit differences on power-on sequence.
3218 */
3219 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3220 if (priv->mcm) {
3221 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3222
3223 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3224 if (IS_ERR(priv->rstc)) {
3225 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3226 return PTR_ERR(priv->rstc);
3227 }
3228 }
3229
3230 /* Get the hardware identifier from the devicetree node.
3231 * We will need it for some of the clock and regulator setup.
3232 */
3233 priv->info = of_device_get_match_data(&mdiodev->dev);
3234 if (!priv->info)
3235 return -EINVAL;
3236
3237 /* Sanity check if these required device operations are filled
3238 * properly.
3239 */
3240 if (!priv->info->sw_setup || !priv->info->pad_setup ||
3241 !priv->info->phy_read || !priv->info->phy_write ||
3242 !priv->info->phy_mode_supported ||
3243 !priv->info->mac_port_validate ||
3244 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
3245 return -EINVAL;
3246
3247 priv->id = priv->info->id;
3248
3249 if (priv->id == ID_MT7530) {
3250 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3251 if (IS_ERR(priv->core_pwr))
3252 return PTR_ERR(priv->core_pwr);
3253
3254 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3255 if (IS_ERR(priv->io_pwr))
3256 return PTR_ERR(priv->io_pwr);
3257 }
3258
3259 /* Not MCM that indicates switch works as the remote standalone
3260 * integrated circuit so the GPIO pin would be used to complete
3261 * the reset, otherwise memory-mapped register accessing used
3262 * through syscon provides in the case of MCM.
3263 */
3264 if (!priv->mcm) {
3265 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3266 GPIOD_OUT_LOW);
3267 if (IS_ERR(priv->reset)) {
3268 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3269 return PTR_ERR(priv->reset);
3270 }
3271 }
3272
3273 priv->bus = mdiodev->bus;
3274 priv->dev = &mdiodev->dev;
3275 priv->ds->priv = priv;
3276 priv->ds->ops = &mt7530_switch_ops;
3277 mutex_init(&priv->reg_mutex);
3278 dev_set_drvdata(&mdiodev->dev, priv);
3279
3280 return dsa_register_switch(priv->ds);
3281 }
3282
3283 static void
3284 mt7530_remove(struct mdio_device *mdiodev)
3285 {
3286 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3287 int ret = 0;
3288
3289 ret = regulator_disable(priv->core_pwr);
3290 if (ret < 0)
3291 dev_err(priv->dev,
3292 "Failed to disable core power: %d\n", ret);
3293
3294 ret = regulator_disable(priv->io_pwr);
3295 if (ret < 0)
3296 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3297 ret);
3298
3299 if (priv->irq)
3300 mt7530_free_irq(priv);
3301
3302 dsa_unregister_switch(priv->ds);
3303 mutex_destroy(&priv->reg_mutex);
3304 }
3305
3306 static struct mdio_driver mt7530_mdio_driver = {
3307 .probe = mt7530_probe,
3308 .remove = mt7530_remove,
3309 .mdiodrv.driver = {
3310 .name = "mt7530",
3311 .of_match_table = mt7530_of_match,
3312 },
3313 };
3314
3315 mdio_module_driver(mt7530_mdio_driver);
3316
3317 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3318 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3319 MODULE_LICENSE("GPL");
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