2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/gpio/consumer.h>
34 /* String, offset, and register size in bytes if different from 4 bytes */
35 static const struct mt7530_mib_desc mt7530_mib
[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
79 mt7623_trgmii_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
83 ret
= regmap_write(priv
->ethernet
, TRGMII_BASE(reg
), val
);
86 "failed to priv write register\n");
91 mt7623_trgmii_read(struct mt7530_priv
*priv
, u32 reg
)
96 ret
= regmap_read(priv
->ethernet
, TRGMII_BASE(reg
), &val
);
99 "failed to priv read register\n");
107 mt7623_trgmii_rmw(struct mt7530_priv
*priv
, u32 reg
,
112 val
= mt7623_trgmii_read(priv
, reg
);
115 mt7623_trgmii_write(priv
, reg
, val
);
119 mt7623_trgmii_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
121 mt7623_trgmii_rmw(priv
, reg
, 0, val
);
125 mt7623_trgmii_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
127 mt7623_trgmii_rmw(priv
, reg
, val
, 0);
131 core_read_mmd_indirect(struct mt7530_priv
*priv
, int prtad
, int devad
)
133 struct mii_bus
*bus
= priv
->bus
;
136 /* Write the desired MMD Devad */
137 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, devad
);
141 /* Write the desired MMD register address */
142 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, prtad
);
146 /* Select the Function : DATA with no post increment */
147 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, (devad
| MII_MMD_CTRL_NOINCR
));
151 /* Read the content of the MMD's selected register */
152 value
= bus
->read(bus
, 0, MII_MMD_DATA
);
156 dev_err(&bus
->dev
, "failed to read mmd register\n");
162 core_write_mmd_indirect(struct mt7530_priv
*priv
, int prtad
,
165 struct mii_bus
*bus
= priv
->bus
;
168 /* Write the desired MMD Devad */
169 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, devad
);
173 /* Write the desired MMD register address */
174 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, prtad
);
178 /* Select the Function : DATA with no post increment */
179 ret
= bus
->write(bus
, 0, MII_MMD_CTRL
, (devad
| MII_MMD_CTRL_NOINCR
));
183 /* Write the data into MMD's selected register */
184 ret
= bus
->write(bus
, 0, MII_MMD_DATA
, data
);
188 "failed to write mmd register\n");
193 core_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
195 struct mii_bus
*bus
= priv
->bus
;
197 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
199 core_write_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
, val
);
201 mutex_unlock(&bus
->mdio_lock
);
205 core_rmw(struct mt7530_priv
*priv
, u32 reg
, u32 mask
, u32 set
)
207 struct mii_bus
*bus
= priv
->bus
;
210 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
212 val
= core_read_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
);
215 core_write_mmd_indirect(priv
, reg
, MDIO_MMD_VEND2
, val
);
217 mutex_unlock(&bus
->mdio_lock
);
221 core_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
223 core_rmw(priv
, reg
, 0, val
);
227 core_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
229 core_rmw(priv
, reg
, val
, 0);
233 mt7530_mii_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
235 struct mii_bus
*bus
= priv
->bus
;
239 page
= (reg
>> 6) & 0x3ff;
240 r
= (reg
>> 2) & 0xf;
244 /* MT7530 uses 31 as the pseudo port */
245 ret
= bus
->write(bus
, 0x1f, 0x1f, page
);
249 ret
= bus
->write(bus
, 0x1f, r
, lo
);
253 ret
= bus
->write(bus
, 0x1f, 0x10, hi
);
257 "failed to write mt7530 register\n");
262 mt7530_mii_read(struct mt7530_priv
*priv
, u32 reg
)
264 struct mii_bus
*bus
= priv
->bus
;
268 page
= (reg
>> 6) & 0x3ff;
269 r
= (reg
>> 2) & 0xf;
271 /* MT7530 uses 31 as the pseudo port */
272 ret
= bus
->write(bus
, 0x1f, 0x1f, page
);
275 "failed to read mt7530 register\n");
279 lo
= bus
->read(bus
, 0x1f, r
);
280 hi
= bus
->read(bus
, 0x1f, 0x10);
282 return (hi
<< 16) | (lo
& 0xffff);
286 mt7530_write(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
288 struct mii_bus
*bus
= priv
->bus
;
290 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
292 mt7530_mii_write(priv
, reg
, val
);
294 mutex_unlock(&bus
->mdio_lock
);
298 _mt7530_read(struct mt7530_dummy_poll
*p
)
300 struct mii_bus
*bus
= p
->priv
->bus
;
303 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
305 val
= mt7530_mii_read(p
->priv
, p
->reg
);
307 mutex_unlock(&bus
->mdio_lock
);
313 mt7530_read(struct mt7530_priv
*priv
, u32 reg
)
315 struct mt7530_dummy_poll p
;
317 INIT_MT7530_DUMMY_POLL(&p
, priv
, reg
);
318 return _mt7530_read(&p
);
322 mt7530_rmw(struct mt7530_priv
*priv
, u32 reg
,
325 struct mii_bus
*bus
= priv
->bus
;
328 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
330 val
= mt7530_mii_read(priv
, reg
);
333 mt7530_mii_write(priv
, reg
, val
);
335 mutex_unlock(&bus
->mdio_lock
);
339 mt7530_set(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
341 mt7530_rmw(priv
, reg
, 0, val
);
345 mt7530_clear(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
347 mt7530_rmw(priv
, reg
, val
, 0);
351 mt7530_fdb_cmd(struct mt7530_priv
*priv
, enum mt7530_fdb_cmd cmd
, u32
*rsp
)
355 struct mt7530_dummy_poll p
;
357 /* Set the command operating upon the MAC address entries */
358 val
= ATC_BUSY
| ATC_MAT(0) | cmd
;
359 mt7530_write(priv
, MT7530_ATC
, val
);
361 INIT_MT7530_DUMMY_POLL(&p
, priv
, MT7530_ATC
);
362 ret
= readx_poll_timeout(_mt7530_read
, &p
, val
,
363 !(val
& ATC_BUSY
), 20, 20000);
365 dev_err(priv
->dev
, "reset timeout\n");
369 /* Additional sanity for read command if the specified
372 val
= mt7530_read(priv
, MT7530_ATC
);
373 if ((cmd
== MT7530_FDB_READ
) && (val
& ATC_INVALID
))
383 mt7530_fdb_read(struct mt7530_priv
*priv
, struct mt7530_fdb
*fdb
)
388 /* Read from ARL table into an array */
389 for (i
= 0; i
< 3; i
++) {
390 reg
[i
] = mt7530_read(priv
, MT7530_TSRA1
+ (i
* 4));
392 dev_dbg(priv
->dev
, "%s(%d) reg[%d]=0x%x\n",
393 __func__
, __LINE__
, i
, reg
[i
]);
396 fdb
->vid
= (reg
[1] >> CVID
) & CVID_MASK
;
397 fdb
->aging
= (reg
[2] >> AGE_TIMER
) & AGE_TIMER_MASK
;
398 fdb
->port_mask
= (reg
[2] >> PORT_MAP
) & PORT_MAP_MASK
;
399 fdb
->mac
[0] = (reg
[0] >> MAC_BYTE_0
) & MAC_BYTE_MASK
;
400 fdb
->mac
[1] = (reg
[0] >> MAC_BYTE_1
) & MAC_BYTE_MASK
;
401 fdb
->mac
[2] = (reg
[0] >> MAC_BYTE_2
) & MAC_BYTE_MASK
;
402 fdb
->mac
[3] = (reg
[0] >> MAC_BYTE_3
) & MAC_BYTE_MASK
;
403 fdb
->mac
[4] = (reg
[1] >> MAC_BYTE_4
) & MAC_BYTE_MASK
;
404 fdb
->mac
[5] = (reg
[1] >> MAC_BYTE_5
) & MAC_BYTE_MASK
;
405 fdb
->noarp
= ((reg
[2] >> ENT_STATUS
) & ENT_STATUS_MASK
) == STATIC_ENT
;
409 mt7530_fdb_write(struct mt7530_priv
*priv
, u16 vid
,
410 u8 port_mask
, const u8
*mac
,
416 reg
[1] |= vid
& CVID_MASK
;
417 reg
[2] |= (aging
& AGE_TIMER_MASK
) << AGE_TIMER
;
418 reg
[2] |= (port_mask
& PORT_MAP_MASK
) << PORT_MAP
;
419 /* STATIC_ENT indicate that entry is static wouldn't
420 * be aged out and STATIC_EMP specified as erasing an
423 reg
[2] |= (type
& ENT_STATUS_MASK
) << ENT_STATUS
;
424 reg
[1] |= mac
[5] << MAC_BYTE_5
;
425 reg
[1] |= mac
[4] << MAC_BYTE_4
;
426 reg
[0] |= mac
[3] << MAC_BYTE_3
;
427 reg
[0] |= mac
[2] << MAC_BYTE_2
;
428 reg
[0] |= mac
[1] << MAC_BYTE_1
;
429 reg
[0] |= mac
[0] << MAC_BYTE_0
;
431 /* Write array into the ARL table */
432 for (i
= 0; i
< 3; i
++)
433 mt7530_write(priv
, MT7530_ATA1
+ (i
* 4), reg
[i
]);
437 mt7530_pad_clk_setup(struct dsa_switch
*ds
, int mode
)
439 struct mt7530_priv
*priv
= ds
->priv
;
440 u32 ncpo1
, ssc_delta
, trgint
, i
;
443 case PHY_INTERFACE_MODE_RGMII
:
448 case PHY_INTERFACE_MODE_TRGMII
:
454 dev_err(priv
->dev
, "xMII mode %d not supported\n", mode
);
458 mt7530_rmw(priv
, MT7530_P6ECR
, P6_INTF_MODE_MASK
,
459 P6_INTF_MODE(trgint
));
461 /* Lower Tx Driving for TRGMII path */
462 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
463 mt7530_write(priv
, MT7530_TRGMII_TD_ODT(i
),
464 TD_DM_DRVP(8) | TD_DM_DRVN(8));
466 /* Setup core clock for MT7530 */
468 /* Disable MT7530 core clock */
469 core_clear(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
471 /* Disable PLL, since phy_device has not yet been created
472 * provided for phy_[read,write]_mmd_indirect is called, we
473 * provide our own core_write_mmd_indirect to complete this
476 core_write_mmd_indirect(priv
,
481 /* Set core clock into 500Mhz */
482 core_write(priv
, CORE_GSWPLL_GRP2
,
483 RG_GSWPLL_POSDIV_500M(1) |
484 RG_GSWPLL_FBKDIV_500M(25));
487 core_write(priv
, CORE_GSWPLL_GRP1
,
489 RG_GSWPLL_POSDIV_200M(2) |
490 RG_GSWPLL_FBKDIV_200M(32));
492 /* Enable MT7530 core clock */
493 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
496 /* Setup the MT7530 TRGMII Tx Clock */
497 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
, REG_GSWCK_EN
);
498 core_write(priv
, CORE_PLL_GROUP5
, RG_LCDDS_PCW_NCPO1(ncpo1
));
499 core_write(priv
, CORE_PLL_GROUP6
, RG_LCDDS_PCW_NCPO0(0));
500 core_write(priv
, CORE_PLL_GROUP10
, RG_LCDDS_SSC_DELTA(ssc_delta
));
501 core_write(priv
, CORE_PLL_GROUP11
, RG_LCDDS_SSC_DELTA1(ssc_delta
));
502 core_write(priv
, CORE_PLL_GROUP4
,
503 RG_SYSPLL_DDSFBK_EN
| RG_SYSPLL_BIAS_EN
|
504 RG_SYSPLL_BIAS_LPF_EN
);
505 core_write(priv
, CORE_PLL_GROUP2
,
506 RG_SYSPLL_EN_NORMAL
| RG_SYSPLL_VODEN
|
507 RG_SYSPLL_POSDIV(1));
508 core_write(priv
, CORE_PLL_GROUP7
,
509 RG_LCDDS_PCW_NCPO_CHG
| RG_LCCDS_C(3) |
510 RG_LCDDS_PWDB
| RG_LCDDS_ISO_EN
);
511 core_set(priv
, CORE_TRGMII_GSW_CLK_CG
,
512 REG_GSWCK_EN
| REG_TRGMIICK_EN
);
515 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
516 mt7530_rmw(priv
, MT7530_TRGMII_RD(i
),
517 RD_TAP_MASK
, RD_TAP(16));
519 mt7623_trgmii_set(priv
, GSW_INTF_MODE
, INTF_MODE_TRGMII
);
525 mt7623_pad_clk_setup(struct dsa_switch
*ds
)
527 struct mt7530_priv
*priv
= ds
->priv
;
530 for (i
= 0 ; i
< NUM_TRGMII_CTRL
; i
++)
531 mt7623_trgmii_write(priv
, GSW_TRGMII_TD_ODT(i
),
532 TD_DM_DRVP(8) | TD_DM_DRVN(8));
534 mt7623_trgmii_set(priv
, GSW_TRGMII_RCK_CTRL
, RX_RST
| RXC_DQSISEL
);
535 mt7623_trgmii_clear(priv
, GSW_TRGMII_RCK_CTRL
, RX_RST
);
541 mt7530_mib_reset(struct dsa_switch
*ds
)
543 struct mt7530_priv
*priv
= ds
->priv
;
545 mt7530_write(priv
, MT7530_MIB_CCR
, CCR_MIB_FLUSH
);
546 mt7530_write(priv
, MT7530_MIB_CCR
, CCR_MIB_ACTIVATE
);
550 mt7530_port_set_status(struct mt7530_priv
*priv
, int port
, int enable
)
552 u32 mask
= PMCR_TX_EN
| PMCR_RX_EN
;
555 mt7530_set(priv
, MT7530_PMCR_P(port
), mask
);
557 mt7530_clear(priv
, MT7530_PMCR_P(port
), mask
);
560 static int mt7530_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
562 struct mt7530_priv
*priv
= ds
->priv
;
564 return mdiobus_read_nested(priv
->bus
, port
, regnum
);
567 int mt7530_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
569 struct mt7530_priv
*priv
= ds
->priv
;
571 return mdiobus_write_nested(priv
->bus
, port
, regnum
, val
);
575 mt7530_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
579 for (i
= 0; i
< ARRAY_SIZE(mt7530_mib
); i
++)
580 strncpy(data
+ i
* ETH_GSTRING_LEN
, mt7530_mib
[i
].name
,
585 mt7530_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
588 struct mt7530_priv
*priv
= ds
->priv
;
589 const struct mt7530_mib_desc
*mib
;
593 for (i
= 0; i
< ARRAY_SIZE(mt7530_mib
); i
++) {
594 mib
= &mt7530_mib
[i
];
595 reg
= MT7530_PORT_MIB_COUNTER(port
) + mib
->offset
;
597 data
[i
] = mt7530_read(priv
, reg
);
598 if (mib
->size
== 2) {
599 hi
= mt7530_read(priv
, reg
+ 4);
606 mt7530_get_sset_count(struct dsa_switch
*ds
)
608 return ARRAY_SIZE(mt7530_mib
);
611 static void mt7530_adjust_link(struct dsa_switch
*ds
, int port
,
612 struct phy_device
*phydev
)
614 struct mt7530_priv
*priv
= ds
->priv
;
616 if (phy_is_pseudo_fixed_link(phydev
)) {
617 dev_dbg(priv
->dev
, "phy-mode for master device = %x\n",
620 /* Setup TX circuit incluing relevant PAD and driving */
621 mt7530_pad_clk_setup(ds
, phydev
->interface
);
623 /* Setup RX circuit, relevant PAD and driving on the host
624 * which must be placed after the setup on the device side is
627 mt7623_pad_clk_setup(ds
);
629 u16 lcl_adv
= 0, rmt_adv
= 0;
631 u32 mcr
= PMCR_USERP_LINK
| PMCR_FORCE_MODE
;
633 switch (phydev
->speed
) {
635 mcr
|= PMCR_FORCE_SPEED_1000
;
638 mcr
|= PMCR_FORCE_SPEED_100
;
643 mcr
|= PMCR_FORCE_LNK
;
645 if (phydev
->duplex
) {
646 mcr
|= PMCR_FORCE_FDX
;
649 rmt_adv
= LPA_PAUSE_CAP
;
650 if (phydev
->asym_pause
)
651 rmt_adv
|= LPA_PAUSE_ASYM
;
653 if (phydev
->advertising
& ADVERTISED_Pause
)
654 lcl_adv
|= ADVERTISE_PAUSE_CAP
;
655 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
656 lcl_adv
|= ADVERTISE_PAUSE_ASYM
;
658 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
660 if (flowctrl
& FLOW_CTRL_TX
)
661 mcr
|= PMCR_TX_FC_EN
;
662 if (flowctrl
& FLOW_CTRL_RX
)
663 mcr
|= PMCR_RX_FC_EN
;
665 mt7530_write(priv
, MT7530_PMCR_P(port
), mcr
);
670 mt7530_cpu_port_enable(struct mt7530_priv
*priv
,
673 /* Enable Mediatek header mode on the cpu port */
674 mt7530_write(priv
, MT7530_PVC_P(port
),
677 /* Setup the MAC by default for the cpu port */
678 mt7530_write(priv
, MT7530_PMCR_P(port
), PMCR_CPUP_LINK
);
680 /* Disable auto learning on the cpu port */
681 mt7530_set(priv
, MT7530_PSC_P(port
), SA_DIS
);
683 /* Unknown unicast frame fordwarding to the cpu port */
684 mt7530_set(priv
, MT7530_MFC
, UNU_FFP(BIT(port
)));
686 /* CPU port gets connected to all user ports of
689 mt7530_write(priv
, MT7530_PCR_P(port
),
690 PCR_MATRIX(priv
->ds
->enabled_port_mask
));
696 mt7530_port_enable(struct dsa_switch
*ds
, int port
,
697 struct phy_device
*phy
)
699 struct mt7530_priv
*priv
= ds
->priv
;
701 mutex_lock(&priv
->reg_mutex
);
703 /* Setup the MAC for the user port */
704 mt7530_write(priv
, MT7530_PMCR_P(port
), PMCR_USERP_LINK
);
706 /* Allow the user port gets connected to the cpu port and also
707 * restore the port matrix if the port is the member of a certain
710 priv
->ports
[port
].pm
|= PCR_MATRIX(BIT(MT7530_CPU_PORT
));
711 priv
->ports
[port
].enable
= true;
712 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
713 priv
->ports
[port
].pm
);
714 mt7530_port_set_status(priv
, port
, 1);
716 mutex_unlock(&priv
->reg_mutex
);
722 mt7530_port_disable(struct dsa_switch
*ds
, int port
,
723 struct phy_device
*phy
)
725 struct mt7530_priv
*priv
= ds
->priv
;
727 mutex_lock(&priv
->reg_mutex
);
729 /* Clear up all port matrix which could be restored in the next
730 * enablement for the port.
732 priv
->ports
[port
].enable
= false;
733 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
735 mt7530_port_set_status(priv
, port
, 0);
737 mutex_unlock(&priv
->reg_mutex
);
741 mt7530_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
743 struct mt7530_priv
*priv
= ds
->priv
;
747 case BR_STATE_DISABLED
:
748 stp_state
= MT7530_STP_DISABLED
;
750 case BR_STATE_BLOCKING
:
751 stp_state
= MT7530_STP_BLOCKING
;
753 case BR_STATE_LISTENING
:
754 stp_state
= MT7530_STP_LISTENING
;
756 case BR_STATE_LEARNING
:
757 stp_state
= MT7530_STP_LEARNING
;
759 case BR_STATE_FORWARDING
:
761 stp_state
= MT7530_STP_FORWARDING
;
765 mt7530_rmw(priv
, MT7530_SSP_P(port
), FID_PST_MASK
, stp_state
);
769 mt7530_port_bridge_join(struct dsa_switch
*ds
, int port
,
770 struct net_device
*bridge
)
772 struct mt7530_priv
*priv
= ds
->priv
;
773 u32 port_bitmap
= BIT(MT7530_CPU_PORT
);
776 mutex_lock(&priv
->reg_mutex
);
778 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
779 /* Add this port to the port matrix of the other ports in the
780 * same bridge. If the port is disabled, port matrix is kept
781 * and not being setup until the port becomes enabled.
783 if (ds
->enabled_port_mask
& BIT(i
) && i
!= port
) {
784 if (ds
->ports
[i
].bridge_dev
!= bridge
)
786 if (priv
->ports
[i
].enable
)
787 mt7530_set(priv
, MT7530_PCR_P(i
),
788 PCR_MATRIX(BIT(port
)));
789 priv
->ports
[i
].pm
|= PCR_MATRIX(BIT(port
));
791 port_bitmap
|= BIT(i
);
795 /* Add the all other ports to this port matrix. */
796 if (priv
->ports
[port
].enable
)
797 mt7530_rmw(priv
, MT7530_PCR_P(port
),
798 PCR_MATRIX_MASK
, PCR_MATRIX(port_bitmap
));
799 priv
->ports
[port
].pm
|= PCR_MATRIX(port_bitmap
);
801 mutex_unlock(&priv
->reg_mutex
);
807 mt7530_port_bridge_leave(struct dsa_switch
*ds
, int port
,
808 struct net_device
*bridge
)
810 struct mt7530_priv
*priv
= ds
->priv
;
813 mutex_lock(&priv
->reg_mutex
);
815 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
816 /* Remove this port from the port matrix of the other ports
817 * in the same bridge. If the port is disabled, port matrix
818 * is kept and not being setup until the port becomes enabled.
820 if (ds
->enabled_port_mask
& BIT(i
) && i
!= port
) {
821 if (ds
->ports
[i
].bridge_dev
!= bridge
)
823 if (priv
->ports
[i
].enable
)
824 mt7530_clear(priv
, MT7530_PCR_P(i
),
825 PCR_MATRIX(BIT(port
)));
826 priv
->ports
[i
].pm
&= ~PCR_MATRIX(BIT(port
));
830 /* Set the cpu port to be the only one in the port matrix of
833 if (priv
->ports
[port
].enable
)
834 mt7530_rmw(priv
, MT7530_PCR_P(port
), PCR_MATRIX_MASK
,
835 PCR_MATRIX(BIT(MT7530_CPU_PORT
)));
836 priv
->ports
[port
].pm
= PCR_MATRIX(BIT(MT7530_CPU_PORT
));
838 mutex_unlock(&priv
->reg_mutex
);
842 mt7530_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
843 const struct switchdev_obj_port_fdb
*fdb
,
844 struct switchdev_trans
*trans
)
846 struct mt7530_priv
*priv
= ds
->priv
;
849 /* Because auto-learned entrie shares the same FDB table.
850 * an entry is reserved with no port_mask to make sure fdb_add
851 * is called while the entry is still available.
853 mutex_lock(&priv
->reg_mutex
);
854 mt7530_fdb_write(priv
, fdb
->vid
, 0, fdb
->addr
, -1, STATIC_ENT
);
855 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_WRITE
, 0);
856 mutex_unlock(&priv
->reg_mutex
);
862 mt7530_port_fdb_add(struct dsa_switch
*ds
, int port
,
863 const struct switchdev_obj_port_fdb
*fdb
,
864 struct switchdev_trans
*trans
)
866 struct mt7530_priv
*priv
= ds
->priv
;
867 u8 port_mask
= BIT(port
);
869 mutex_lock(&priv
->reg_mutex
);
870 mt7530_fdb_write(priv
, fdb
->vid
, port_mask
, fdb
->addr
, -1, STATIC_ENT
);
871 mt7530_fdb_cmd(priv
, MT7530_FDB_WRITE
, 0);
872 mutex_unlock(&priv
->reg_mutex
);
876 mt7530_port_fdb_del(struct dsa_switch
*ds
, int port
,
877 const struct switchdev_obj_port_fdb
*fdb
)
879 struct mt7530_priv
*priv
= ds
->priv
;
881 u8 port_mask
= BIT(port
);
883 mutex_lock(&priv
->reg_mutex
);
884 mt7530_fdb_write(priv
, fdb
->vid
, port_mask
, fdb
->addr
, -1, STATIC_EMP
);
885 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_WRITE
, 0);
886 mutex_unlock(&priv
->reg_mutex
);
892 mt7530_port_fdb_dump(struct dsa_switch
*ds
, int port
,
893 struct switchdev_obj_port_fdb
*fdb
,
894 switchdev_obj_dump_cb_t
*cb
)
896 struct mt7530_priv
*priv
= ds
->priv
;
897 struct mt7530_fdb _fdb
= { 0 };
898 int cnt
= MT7530_NUM_FDB_RECORDS
;
902 mutex_lock(&priv
->reg_mutex
);
904 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_START
, &rsp
);
909 if (rsp
& ATC_SRCH_HIT
) {
910 mt7530_fdb_read(priv
, &_fdb
);
911 if (_fdb
.port_mask
& BIT(port
)) {
912 ether_addr_copy(fdb
->addr
, _fdb
.mac
);
914 fdb
->ndm_state
= _fdb
.noarp
?
915 NUD_NOARP
: NUD_REACHABLE
;
922 !(rsp
& ATC_SRCH_END
) &&
923 !mt7530_fdb_cmd(priv
, MT7530_FDB_NEXT
, &rsp
));
925 mutex_unlock(&priv
->reg_mutex
);
930 static enum dsa_tag_protocol
931 mtk_get_tag_protocol(struct dsa_switch
*ds
)
933 struct mt7530_priv
*priv
= ds
->priv
;
935 if (!dsa_is_cpu_port(ds
, MT7530_CPU_PORT
)) {
937 "port not matched with tagging CPU port\n");
938 return DSA_TAG_PROTO_NONE
;
940 return DSA_TAG_PROTO_MTK
;
945 mt7530_setup(struct dsa_switch
*ds
)
947 struct mt7530_priv
*priv
= ds
->priv
;
950 struct device_node
*dn
;
951 struct mt7530_dummy_poll p
;
953 /* The parent node of cpu_dp->netdev which holds the common system
954 * controller also is the container for two GMACs nodes representing
955 * as two netdev instances.
957 dn
= ds
->dst
->cpu_dp
->netdev
->dev
.of_node
->parent
;
958 priv
->ethernet
= syscon_node_to_regmap(dn
);
959 if (IS_ERR(priv
->ethernet
))
960 return PTR_ERR(priv
->ethernet
);
962 regulator_set_voltage(priv
->core_pwr
, 1000000, 1000000);
963 ret
= regulator_enable(priv
->core_pwr
);
966 "Failed to enable core power: %d\n", ret
);
970 regulator_set_voltage(priv
->io_pwr
, 3300000, 3300000);
971 ret
= regulator_enable(priv
->io_pwr
);
973 dev_err(priv
->dev
, "Failed to enable io pwr: %d\n",
978 /* Reset whole chip through gpio pin or memory-mapped registers for
979 * different type of hardware
982 reset_control_assert(priv
->rstc
);
983 usleep_range(1000, 1100);
984 reset_control_deassert(priv
->rstc
);
986 gpiod_set_value_cansleep(priv
->reset
, 0);
987 usleep_range(1000, 1100);
988 gpiod_set_value_cansleep(priv
->reset
, 1);
991 /* Waiting for MT7530 got to stable */
992 INIT_MT7530_DUMMY_POLL(&p
, priv
, MT7530_HWTRAP
);
993 ret
= readx_poll_timeout(_mt7530_read
, &p
, val
, val
!= 0,
996 dev_err(priv
->dev
, "reset timeout\n");
1000 id
= mt7530_read(priv
, MT7530_CREV
);
1001 id
>>= CHIP_NAME_SHIFT
;
1002 if (id
!= MT7530_ID
) {
1003 dev_err(priv
->dev
, "chip %x can't be supported\n", id
);
1007 /* Reset the switch through internal reset */
1008 mt7530_write(priv
, MT7530_SYS_CTRL
,
1009 SYS_CTRL_PHY_RST
| SYS_CTRL_SW_RST
|
1012 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1013 val
= mt7530_read(priv
, MT7530_MHWTRAP
);
1014 val
&= ~MHWTRAP_P6_DIS
& ~MHWTRAP_PHY_ACCESS
;
1015 val
|= MHWTRAP_MANUAL
;
1016 mt7530_write(priv
, MT7530_MHWTRAP
, val
);
1018 /* Enable and reset MIB counters */
1019 mt7530_mib_reset(ds
);
1021 mt7530_clear(priv
, MT7530_MFC
, UNU_FFP_MASK
);
1023 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
1024 /* Disable forwarding by default on all ports */
1025 mt7530_rmw(priv
, MT7530_PCR_P(i
), PCR_MATRIX_MASK
,
1028 if (dsa_is_cpu_port(ds
, i
))
1029 mt7530_cpu_port_enable(priv
, i
);
1031 mt7530_port_disable(ds
, i
, NULL
);
1034 /* Flush the FDB table */
1035 ret
= mt7530_fdb_cmd(priv
, MT7530_FDB_FLUSH
, 0);
1042 static struct dsa_switch_ops mt7530_switch_ops
= {
1043 .get_tag_protocol
= mtk_get_tag_protocol
,
1044 .setup
= mt7530_setup
,
1045 .get_strings
= mt7530_get_strings
,
1046 .phy_read
= mt7530_phy_read
,
1047 .phy_write
= mt7530_phy_write
,
1048 .get_ethtool_stats
= mt7530_get_ethtool_stats
,
1049 .get_sset_count
= mt7530_get_sset_count
,
1050 .adjust_link
= mt7530_adjust_link
,
1051 .port_enable
= mt7530_port_enable
,
1052 .port_disable
= mt7530_port_disable
,
1053 .port_stp_state_set
= mt7530_stp_state_set
,
1054 .port_bridge_join
= mt7530_port_bridge_join
,
1055 .port_bridge_leave
= mt7530_port_bridge_leave
,
1056 .port_fdb_prepare
= mt7530_port_fdb_prepare
,
1057 .port_fdb_add
= mt7530_port_fdb_add
,
1058 .port_fdb_del
= mt7530_port_fdb_del
,
1059 .port_fdb_dump
= mt7530_port_fdb_dump
,
1063 mt7530_probe(struct mdio_device
*mdiodev
)
1065 struct mt7530_priv
*priv
;
1066 struct device_node
*dn
;
1068 dn
= mdiodev
->dev
.of_node
;
1070 priv
= devm_kzalloc(&mdiodev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1074 priv
->ds
= dsa_switch_alloc(&mdiodev
->dev
, DSA_MAX_PORTS
);
1078 /* Use medatek,mcm property to distinguish hardware type that would
1079 * casues a little bit differences on power-on sequence.
1081 priv
->mcm
= of_property_read_bool(dn
, "mediatek,mcm");
1083 dev_info(&mdiodev
->dev
, "MT7530 adapts as multi-chip module\n");
1085 priv
->rstc
= devm_reset_control_get(&mdiodev
->dev
, "mcm");
1086 if (IS_ERR(priv
->rstc
)) {
1087 dev_err(&mdiodev
->dev
, "Couldn't get our reset line\n");
1088 return PTR_ERR(priv
->rstc
);
1092 priv
->core_pwr
= devm_regulator_get(&mdiodev
->dev
, "core");
1093 if (IS_ERR(priv
->core_pwr
))
1094 return PTR_ERR(priv
->core_pwr
);
1096 priv
->io_pwr
= devm_regulator_get(&mdiodev
->dev
, "io");
1097 if (IS_ERR(priv
->io_pwr
))
1098 return PTR_ERR(priv
->io_pwr
);
1100 /* Not MCM that indicates switch works as the remote standalone
1101 * integrated circuit so the GPIO pin would be used to complete
1102 * the reset, otherwise memory-mapped register accessing used
1103 * through syscon provides in the case of MCM.
1106 priv
->reset
= devm_gpiod_get_optional(&mdiodev
->dev
, "reset",
1108 if (IS_ERR(priv
->reset
)) {
1109 dev_err(&mdiodev
->dev
, "Couldn't get our reset line\n");
1110 return PTR_ERR(priv
->reset
);
1114 priv
->bus
= mdiodev
->bus
;
1115 priv
->dev
= &mdiodev
->dev
;
1116 priv
->ds
->priv
= priv
;
1117 priv
->ds
->ops
= &mt7530_switch_ops
;
1118 mutex_init(&priv
->reg_mutex
);
1119 dev_set_drvdata(&mdiodev
->dev
, priv
);
1121 return dsa_register_switch(priv
->ds
);
1125 mt7530_remove(struct mdio_device
*mdiodev
)
1127 struct mt7530_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
1130 ret
= regulator_disable(priv
->core_pwr
);
1133 "Failed to disable core power: %d\n", ret
);
1135 ret
= regulator_disable(priv
->io_pwr
);
1137 dev_err(priv
->dev
, "Failed to disable io pwr: %d\n",
1140 dsa_unregister_switch(priv
->ds
);
1141 mutex_destroy(&priv
->reg_mutex
);
1144 static const struct of_device_id mt7530_of_match
[] = {
1145 { .compatible
= "mediatek,mt7530" },
1149 static struct mdio_driver mt7530_mdio_driver
= {
1150 .probe
= mt7530_probe
,
1151 .remove
= mt7530_remove
,
1154 .of_match_table
= mt7530_of_match
,
1158 mdio_module_driver(mt7530_mdio_driver
);
1160 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1161 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1162 MODULE_LICENSE("GPL");
1163 MODULE_ALIAS("platform:mediatek-mt7530");