drivers/net/dsa/mt7530.h

   1 /*
   2  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef __MT7530_H
  15 #define __MT7530_H
  16
  17 #define MT7530_NUM_PORTS                7
  18 #define MT7530_CPU_PORT                 6
  19 #define MT7530_NUM_FDB_RECORDS          2048
  20 #define MT7530_ALL_MEMBERS              0xff
  21
  22 enum {
  23         ID_MT7530 = 0,
  24         ID_MT7621 = 1,
  25 };
  26
  27 #define NUM_TRGMII_CTRL                 5
  28
  29 #define TRGMII_BASE(x)                  (0x10000 + (x))
  30
  31 /* Registers to ethsys access */
  32 #define ETHSYS_CLKCFG0                  0x2c
  33 #define  ETHSYS_TRGMII_CLK_SEL362_5     BIT(11)
  34
  35 #define SYSC_REG_RSTCTRL                0x34
  36 #define  RESET_MCM                      BIT(2)
  37
  38 /* Registers to mac forward control for unknown frames */
  39 #define MT7530_MFC                      0x10
  40 #define  BC_FFP(x)                      (((x) & 0xff) << 24)
  41 #define  UNM_FFP(x)                     (((x) & 0xff) << 16)
  42 #define  UNU_FFP(x)                     (((x) & 0xff) << 8)
  43 #define  UNU_FFP_MASK                   UNU_FFP(~0)
  44 #define  CPU_EN                         BIT(7)
  45 #define  CPU_PORT(x)                    ((x) << 4)
  46 #define  CPU_MASK                       (0xf << 4)
  47
  48 /* Registers for address table access */
  49 #define MT7530_ATA1                     0x74
  50 #define  STATIC_EMP                     0
  51 #define  STATIC_ENT                     3
  52 #define MT7530_ATA2                     0x78
  53
  54 /* Register for address table write data */
  55 #define MT7530_ATWD                     0x7c
  56
  57 /* Register for address table control */
  58 #define MT7530_ATC                      0x80
  59 #define  ATC_HASH                       (((x) & 0xfff) << 16)
  60 #define  ATC_BUSY                       BIT(15)
  61 #define  ATC_SRCH_END                   BIT(14)
  62 #define  ATC_SRCH_HIT                   BIT(13)
  63 #define  ATC_INVALID                    BIT(12)
  64 #define  ATC_MAT(x)                     (((x) & 0xf) << 8)
  65 #define  ATC_MAT_MACTAB                 ATC_MAT(0)
  66
  67 enum mt7530_fdb_cmd {
  68         MT7530_FDB_READ = 0,
  69         MT7530_FDB_WRITE = 1,
  70         MT7530_FDB_FLUSH = 2,
  71         MT7530_FDB_START = 4,
  72         MT7530_FDB_NEXT = 5,
  73 };
  74
  75 /* Registers for table search read address */
  76 #define MT7530_TSRA1                    0x84
  77 #define  MAC_BYTE_0                     24
  78 #define  MAC_BYTE_1                     16
  79 #define  MAC_BYTE_2                     8
  80 #define  MAC_BYTE_3                     0
  81 #define  MAC_BYTE_MASK                  0xff
  82
  83 #define MT7530_TSRA2                    0x88
  84 #define  MAC_BYTE_4                     24
  85 #define  MAC_BYTE_5                     16
  86 #define  CVID                           0
  87 #define  CVID_MASK                      0xfff
  88
  89 #define MT7530_ATRD                     0x8C
  90 #define  AGE_TIMER                      24
  91 #define  AGE_TIMER_MASK                 0xff
  92 #define  PORT_MAP                       4
  93 #define  PORT_MAP_MASK                  0xff
  94 #define  ENT_STATUS                     2
  95 #define  ENT_STATUS_MASK                0x3
  96
  97 /* Register for vlan table control */
  98 #define MT7530_VTCR                     0x90
  99 #define  VTCR_BUSY                      BIT(31)
 100 #define  VTCR_INVALID                   BIT(16)
 101 #define  VTCR_FUNC(x)                   (((x) & 0xf) << 12)
 102 #define  VTCR_VID                       ((x) & 0xfff)
 103
 104 enum mt7530_vlan_cmd {
 105         /* Read/Write the specified VID entry from VAWD register based
 106          * on VID.
 107          */
 108         MT7530_VTCR_RD_VID = 0,
 109         MT7530_VTCR_WR_VID = 1,
 110 };
 111
 112 /* Register for setup vlan and acl write data */
 113 #define MT7530_VAWD1                    0x94
 114 #define  PORT_STAG                      BIT(31)
 115 /* Independent VLAN Learning */
 116 #define  IVL_MAC                        BIT(30)
 117 /* Per VLAN Egress Tag Control */
 118 #define  VTAG_EN                        BIT(28)
 119 /* VLAN Member Control */
 120 #define  PORT_MEM(x)                    (((x) & 0xff) << 16)
 121 /* VLAN Entry Valid */
 122 #define  VLAN_VALID                     BIT(0)
 123 #define  PORT_MEM_SHFT                  16
 124 #define  PORT_MEM_MASK                  0xff
 125
 126 #define MT7530_VAWD2                    0x98
 127 /* Egress Tag Control */
 128 #define  ETAG_CTRL_P(p, x)              (((x) & 0x3) << ((p) << 1))
 129 #define  ETAG_CTRL_P_MASK(p)            ETAG_CTRL_P(p, 3)
 130
 131 enum mt7530_vlan_egress_attr {
 132         MT7530_VLAN_EGRESS_UNTAG = 0,
 133         MT7530_VLAN_EGRESS_TAG = 2,
 134         MT7530_VLAN_EGRESS_STACK = 3,
 135 };
 136
 137 /* Register for port STP state control */
 138 #define MT7530_SSP_P(x)                 (0x2000 + ((x) * 0x100))
 139 #define  FID_PST(x)                     ((x) & 0x3)
 140 #define  FID_PST_MASK                   FID_PST(0x3)
 141
 142 enum mt7530_stp_state {
 143         MT7530_STP_DISABLED = 0,
 144         MT7530_STP_BLOCKING = 1,
 145         MT7530_STP_LISTENING = 1,
 146         MT7530_STP_LEARNING = 2,
 147         MT7530_STP_FORWARDING  = 3
 148 };
 149
 150 /* Register for port control */
 151 #define MT7530_PCR_P(x)                 (0x2004 + ((x) * 0x100))
 152 #define  PORT_VLAN(x)                   ((x) & 0x3)
 153
 154 enum mt7530_port_mode {
 155         /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
 156         MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
 157
 158         /* Security Mode: Discard any frame due to ingress membership
 159          * violation or VID missed on the VLAN table.
 160          */
 161         MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
 162 };
 163
 164 #define  PCR_MATRIX(x)                  (((x) & 0xff) << 16)
 165 #define  PORT_PRI(x)                    (((x) & 0x7) << 24)
 166 #define  EG_TAG(x)                      (((x) & 0x3) << 28)
 167 #define  PCR_MATRIX_MASK                PCR_MATRIX(0xff)
 168 #define  PCR_MATRIX_CLR                 PCR_MATRIX(0)
 169 #define  PCR_PORT_VLAN_MASK             PORT_VLAN(3)
 170
 171 /* Register for port security control */
 172 #define MT7530_PSC_P(x)                 (0x200c + ((x) * 0x100))
 173 #define  SA_DIS                         BIT(4)
 174
 175 /* Register for port vlan control */
 176 #define MT7530_PVC_P(x)                 (0x2010 + ((x) * 0x100))
 177 #define  PORT_SPEC_TAG                  BIT(5)
 178 #define  VLAN_ATTR(x)                   (((x) & 0x3) << 6)
 179 #define  VLAN_ATTR_MASK                 VLAN_ATTR(3)
 180
 181 enum mt7530_vlan_port_attr {
 182         MT7530_VLAN_USER = 0,
 183         MT7530_VLAN_TRANSPARENT = 3,
 184 };
 185
 186 #define  STAG_VPID                      (((x) & 0xffff) << 16)
 187
 188 /* Register for port port-and-protocol based vlan 1 control */
 189 #define MT7530_PPBV1_P(x)               (0x2014 + ((x) * 0x100))
 190 #define  G0_PORT_VID(x)                 (((x) & 0xfff) << 0)
 191 #define  G0_PORT_VID_MASK               G0_PORT_VID(0xfff)
 192 #define  G0_PORT_VID_DEF                G0_PORT_VID(1)
 193
 194 /* Register for port MAC control register */
 195 #define MT7530_PMCR_P(x)                (0x3000 + ((x) * 0x100))
 196 #define  PMCR_IFG_XMIT(x)               (((x) & 0x3) << 18)
 197 #define  PMCR_MAC_MODE                  BIT(16)
 198 #define  PMCR_FORCE_MODE                BIT(15)
 199 #define  PMCR_TX_EN                     BIT(14)
 200 #define  PMCR_RX_EN                     BIT(13)
 201 #define  PMCR_BACKOFF_EN                BIT(9)
 202 #define  PMCR_BACKPR_EN                 BIT(8)
 203 #define  PMCR_TX_FC_EN                  BIT(5)
 204 #define  PMCR_RX_FC_EN                  BIT(4)
 205 #define  PMCR_FORCE_SPEED_1000          BIT(3)
 206 #define  PMCR_FORCE_SPEED_100           BIT(2)
 207 #define  PMCR_FORCE_FDX                 BIT(1)
 208 #define  PMCR_FORCE_LNK                 BIT(0)
 209 #define  PMCR_COMMON_LINK               (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
 210                                          PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
 211                                          PMCR_TX_EN | PMCR_RX_EN | \
 212                                          PMCR_TX_FC_EN | PMCR_RX_FC_EN)
 213 #define  PMCR_CPUP_LINK                 (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \
 214                                          PMCR_FORCE_SPEED_1000 | \
 215                                          PMCR_FORCE_FDX | \
 216                                          PMCR_FORCE_LNK)
 217 #define  PMCR_USERP_LINK                PMCR_COMMON_LINK
 218 #define  PMCR_FIXED_LINK                (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
 219                                          PMCR_FORCE_MODE | PMCR_TX_EN | \
 220                                          PMCR_RX_EN | PMCR_BACKPR_EN | \
 221                                          PMCR_BACKOFF_EN | \
 222                                          PMCR_FORCE_SPEED_1000 | \
 223                                          PMCR_FORCE_FDX | \
 224                                          PMCR_FORCE_LNK)
 225 #define PMCR_FIXED_LINK_FC              (PMCR_FIXED_LINK | \
 226                                          PMCR_TX_FC_EN | PMCR_RX_FC_EN)
 227
 228 #define MT7530_PMSR_P(x)                (0x3008 + (x) * 0x100)
 229
 230 /* Register for MIB */
 231 #define MT7530_PORT_MIB_COUNTER(x)      (0x4000 + (x) * 0x100)
 232 #define MT7530_MIB_CCR                  0x4fe0
 233 #define  CCR_MIB_ENABLE                 BIT(31)
 234 #define  CCR_RX_OCT_CNT_GOOD            BIT(7)
 235 #define  CCR_RX_OCT_CNT_BAD             BIT(6)
 236 #define  CCR_TX_OCT_CNT_GOOD            BIT(5)
 237 #define  CCR_TX_OCT_CNT_BAD             BIT(4)
 238 #define  CCR_MIB_FLUSH                  (CCR_RX_OCT_CNT_GOOD | \
 239                                          CCR_RX_OCT_CNT_BAD | \
 240                                          CCR_TX_OCT_CNT_GOOD | \
 241                                          CCR_TX_OCT_CNT_BAD)
 242 #define  CCR_MIB_ACTIVATE               (CCR_MIB_ENABLE | \
 243                                          CCR_RX_OCT_CNT_GOOD | \
 244                                          CCR_RX_OCT_CNT_BAD | \
 245                                          CCR_TX_OCT_CNT_GOOD | \
 246                                          CCR_TX_OCT_CNT_BAD)
 247 /* Register for system reset */
 248 #define MT7530_SYS_CTRL                 0x7000
 249 #define  SYS_CTRL_PHY_RST               BIT(2)
 250 #define  SYS_CTRL_SW_RST                BIT(1)
 251 #define  SYS_CTRL_REG_RST               BIT(0)
 252
 253 /* Register for hw trap status */
 254 #define MT7530_HWTRAP                   0x7800
 255
 256 /* Register for hw trap modification */
 257 #define MT7530_MHWTRAP                  0x7804
 258 #define  MHWTRAP_MANUAL                 BIT(16)
 259 #define  MHWTRAP_P5_MAC_SEL             BIT(13)
 260 #define  MHWTRAP_P6_DIS                 BIT(8)
 261 #define  MHWTRAP_P5_RGMII_MODE          BIT(7)
 262 #define  MHWTRAP_P5_DIS                 BIT(6)
 263 #define  MHWTRAP_PHY_ACCESS             BIT(5)
 264
 265 /* Register for TOP signal control */
 266 #define MT7530_TOP_SIG_CTRL             0x7808
 267 #define  TOP_SIG_CTRL_NORMAL            (BIT(17) | BIT(16))
 268
 269 #define MT7530_IO_DRV_CR                0x7810
 270 #define  P5_IO_CLK_DRV(x)               ((x) & 0x3)
 271 #define  P5_IO_DATA_DRV(x)              (((x) & 0x3) << 4)
 272
 273 #define MT7530_P6ECR                    0x7830
 274 #define  P6_INTF_MODE_MASK              0x3
 275 #define  P6_INTF_MODE(x)                ((x) & 0x3)
 276
 277 /* Registers for TRGMII on the both side */
 278 #define MT7530_TRGMII_RCK_CTRL          0x7a00
 279 #define GSW_TRGMII_RCK_CTRL             0x300
 280 #define  RX_RST                         BIT(31)
 281 #define  RXC_DQSISEL                    BIT(30)
 282 #define  DQSI1_TAP_MASK                 (0x7f << 8)
 283 #define  DQSI0_TAP_MASK                 0x7f
 284 #define  DQSI1_TAP(x)                   (((x) & 0x7f) << 8)
 285 #define  DQSI0_TAP(x)                   ((x) & 0x7f)
 286
 287 #define MT7530_TRGMII_RCK_RTT           0x7a04
 288 #define GSW_TRGMII_RCK_RTT              0x304
 289 #define  DQS1_GATE                      BIT(31)
 290 #define  DQS0_GATE                      BIT(30)
 291
 292 #define MT7530_TRGMII_RD(x)             (0x7a10 + (x) * 8)
 293 #define GSW_TRGMII_RD(x)                (0x310 + (x) * 8)
 294 #define  BSLIP_EN                       BIT(31)
 295 #define  EDGE_CHK                       BIT(30)
 296 #define  RD_TAP_MASK                    0x7f
 297 #define  RD_TAP(x)                      ((x) & 0x7f)
 298
 299 #define GSW_TRGMII_TXCTRL               0x340
 300 #define MT7530_TRGMII_TXCTRL            0x7a40
 301 #define  TRAIN_TXEN                     BIT(31)
 302 #define  TXC_INV                        BIT(30)
 303 #define  TX_RST                         BIT(28)
 304
 305 #define MT7530_TRGMII_TD_ODT(i)         (0x7a54 + 8 * (i))
 306 #define GSW_TRGMII_TD_ODT(i)            (0x354 + 8 * (i))
 307 #define  TD_DM_DRVP(x)                  ((x) & 0xf)
 308 #define  TD_DM_DRVN(x)                  (((x) & 0xf) << 4)
 309
 310 #define GSW_INTF_MODE                   0x390
 311 #define  INTF_MODE_TRGMII               BIT(1)
 312
 313 #define MT7530_TRGMII_TCK_CTRL          0x7a78
 314 #define  TCK_TAP(x)                     (((x) & 0xf) << 8)
 315
 316 #define MT7530_P5RGMIIRXCR              0x7b00
 317 #define  CSR_RGMII_EDGE_ALIGN           BIT(8)
 318 #define  CSR_RGMII_RXC_0DEG_CFG(x)      ((x) & 0xf)
 319
 320 #define MT7530_P5RGMIITXCR              0x7b04
 321 #define  CSR_RGMII_TXC_CFG(x)           ((x) & 0x1f)
 322
 323 #define MT7530_CREV                     0x7ffc
 324 #define  CHIP_NAME_SHIFT                16
 325 #define  MT7530_ID                      0x7530
 326
 327 /* Registers for core PLL access through mmd indirect */
 328 #define CORE_PLL_GROUP2                 0x401
 329 #define  RG_SYSPLL_EN_NORMAL            BIT(15)
 330 #define  RG_SYSPLL_VODEN                BIT(14)
 331 #define  RG_SYSPLL_LF                   BIT(13)
 332 #define  RG_SYSPLL_RST_DLY(x)           (((x) & 0x3) << 12)
 333 #define  RG_SYSPLL_LVROD_EN             BIT(10)
 334 #define  RG_SYSPLL_PREDIV(x)            (((x) & 0x3) << 8)
 335 #define  RG_SYSPLL_POSDIV(x)            (((x) & 0x3) << 5)
 336 #define  RG_SYSPLL_FBKSEL               BIT(4)
 337 #define  RT_SYSPLL_EN_AFE_OLT           BIT(0)
 338
 339 #define CORE_PLL_GROUP4                 0x403
 340 #define  RG_SYSPLL_DDSFBK_EN            BIT(12)
 341 #define  RG_SYSPLL_BIAS_EN              BIT(11)
 342 #define  RG_SYSPLL_BIAS_LPF_EN          BIT(10)
 343
 344 #define CORE_PLL_GROUP5                 0x404
 345 #define  RG_LCDDS_PCW_NCPO1(x)          ((x) & 0xffff)
 346
 347 #define CORE_PLL_GROUP6                 0x405
 348 #define  RG_LCDDS_PCW_NCPO0(x)          ((x) & 0xffff)
 349
 350 #define CORE_PLL_GROUP7                 0x406
 351 #define  RG_LCDDS_PWDB                  BIT(15)
 352 #define  RG_LCDDS_ISO_EN                BIT(13)
 353 #define  RG_LCCDS_C(x)                  (((x) & 0x7) << 4)
 354 #define  RG_LCDDS_PCW_NCPO_CHG          BIT(3)
 355
 356 #define CORE_PLL_GROUP10                0x409
 357 #define  RG_LCDDS_SSC_DELTA(x)          ((x) & 0xfff)
 358
 359 #define CORE_PLL_GROUP11                0x40a
 360 #define  RG_LCDDS_SSC_DELTA1(x)         ((x) & 0xfff)
 361
 362 #define CORE_GSWPLL_GRP1                0x40d
 363 #define  RG_GSWPLL_PREDIV(x)            (((x) & 0x3) << 14)
 364 #define  RG_GSWPLL_POSDIV_200M(x)       (((x) & 0x3) << 12)
 365 #define  RG_GSWPLL_EN_PRE               BIT(11)
 366 #define  RG_GSWPLL_FBKSEL               BIT(10)
 367 #define  RG_GSWPLL_BP                   BIT(9)
 368 #define  RG_GSWPLL_BR                   BIT(8)
 369 #define  RG_GSWPLL_FBKDIV_200M(x)       ((x) & 0xff)
 370
 371 #define CORE_GSWPLL_GRP2                0x40e
 372 #define  RG_GSWPLL_POSDIV_500M(x)       (((x) & 0x3) << 8)
 373 #define  RG_GSWPLL_FBKDIV_500M(x)       ((x) & 0xff)
 374
 375 #define CORE_TRGMII_GSW_CLK_CG          0x410
 376 #define  REG_GSWCK_EN                   BIT(0)
 377 #define  REG_TRGMIICK_EN                BIT(1)
 378
 379 #define MIB_DESC(_s, _o, _n)    \
 380         {                       \
 381                 .size = (_s),   \
 382                 .offset = (_o), \
 383                 .name = (_n),   \
 384         }
 385
 386 struct mt7530_mib_desc {
 387         unsigned int size;
 388         unsigned int offset;
 389         const char *name;
 390 };
 391
 392 struct mt7530_fdb {
 393         u16 vid;
 394         u8 port_mask;
 395         u8 aging;
 396         u8 mac[6];
 397         bool noarp;
 398 };
 399
 400 /* struct mt7530_port - This is the main data structure for holding the state
 401  *                      of the port.
 402  * @enable:     The status used for show port is enabled or not.
 403  * @pm:         The matrix used to show all connections with the port.
 404  * @pvid:       The VLAN specified is to be considered a PVID at ingress.  Any
 405  *              untagged frames will be assigned to the related VLAN.
 406  * @vlan_filtering: The flags indicating whether the port that can recognize
 407  *                  VLAN-tagged frames.
 408  */
 409 struct mt7530_port {
 410         bool enable;
 411         u32 pm;
 412         u16 pvid;
 413 };
 414
 415 /* struct mt7530_priv - This is the main data structure for holding the state
 416  *                      of the driver
 417  * @dev:                The device pointer
 418  * @ds:                 The pointer to the dsa core structure
 419  * @bus:                The bus used for the device and built-in PHY
 420  * @rstc:               The pointer to reset control used by MCM
 421  * @ethernet:           The regmap used for access TRGMII-based registers
 422  * @core_pwr:           The power supplied into the core
 423  * @io_pwr:             The power supplied into the I/O
 424  * @reset:              The descriptor for GPIO line tied to its reset pin
 425  * @mcm:                Flag for distinguishing if standalone IC or module
 426  *                      coupling
 427  * @ports:              Holding the state among ports
 428  * @reg_mutex:          The lock for protecting among process accessing
 429  *                      registers
 430  */
 431 struct mt7530_priv {
 432         struct device           *dev;
 433         struct dsa_switch       *ds;
 434         struct mii_bus          *bus;
 435         struct reset_control    *rstc;
 436         struct regmap           *ethernet;
 437         struct regulator        *core_pwr;
 438         struct regulator        *io_pwr;
 439         struct gpio_desc        *reset;
 440         unsigned int            id;
 441         bool                    mcm;
 442
 443         struct mt7530_port      ports[MT7530_NUM_PORTS];
 444         /* protect among processes for registers access*/
 445         struct mutex reg_mutex;
 446 };
 447
 448 struct mt7530_hw_vlan_entry {
 449         int port;
 450         u8  old_members;
 451         bool untagged;
 452 };
 453
 454 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
 455                                              int port, bool untagged)
 456 {
 457         e->port = port;
 458         e->untagged = untagged;
 459 }
 460
 461 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
 462                                struct mt7530_hw_vlan_entry *);
 463
 464 struct mt7530_hw_stats {
 465         const char      *string;
 466         u16             reg;
 467         u8              sizeof_stat;
 468 };
 469
 470 struct mt7530_dummy_poll {
 471         struct mt7530_priv *priv;
 472         u32 reg;
 473 };
 474
 475 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
 476                                           struct mt7530_priv *priv, u32 reg)
 477 {
 478         p->priv = priv;
 479         p->reg = reg;
 480 }
 481
 482 #endif /* __MT7530_H */