drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static char *mv88e6131_probe(struct device *host_dev, int sw_addr)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  23         int ret;
  24
  25         if (bus == NULL)
  26                 return NULL;
  27
  28         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
  29         if (ret >= 0) {
  30                 int ret_masked = ret & 0xfff0;
  31
  32                 if (ret_masked == PORT_SWITCH_ID_6085)
  33                         return "Marvell 88E6085";
  34                 if (ret_masked == PORT_SWITCH_ID_6095)
  35                         return "Marvell 88E6095/88E6095F";
  36                 if (ret == PORT_SWITCH_ID_6131_B2)
  37                         return "Marvell 88E6131 (B2)";
  38                 if (ret_masked == PORT_SWITCH_ID_6131)
  39                         return "Marvell 88E6131";
  40                 if (ret_masked == PORT_SWITCH_ID_6185)
  41                         return "Marvell 88E6185";
  42         }
  43
  44         return NULL;
  45 }
  46
  47 static int mv88e6131_setup_global(struct dsa_switch *ds)
  48 {
  49         u32 upstream_port = dsa_upstream_port(ds);
  50         int ret;
  51         u32 reg;
  52
  53         ret = mv88e6xxx_setup_global(ds);
  54         if (ret)
  55                 return ret;
  56
  57         /* Enable the PHY polling unit, don't discard packets with
  58          * excessive collisions, use a weighted fair queueing scheme
  59          * to arbitrate between packet queues, set the maximum frame
  60          * size to 1632, and mask all interrupt sources.
  61          */
  62         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
  63                   GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632);
  64
  65         /* Set the VLAN ethertype to 0x8100. */
  66         REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
  67
  68         /* Disable ARP mirroring, and configure the upstream port as
  69          * the port to which ingress and egress monitor frames are to
  70          * be sent.
  71          */
  72         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
  73                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
  74                 GLOBAL_MONITOR_CONTROL_ARP_DISABLED;
  75         REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
  76
  77         /* Disable cascade port functionality unless this device
  78          * is used in a cascade configuration, and set the switch's
  79          * DSA device number.
  80          */
  81         if (ds->dst->pd->nr_chips > 1)
  82                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  83                           GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
  84                           (ds->index & 0x1f));
  85         else
  86                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  87                           GLOBAL_CONTROL_2_NO_CASCADE |
  88                           (ds->index & 0x1f));
  89
  90         /* Force the priority of IGMP/MLD snoop frames and ARP frames
  91          * to the highest setting.
  92          */
  93         REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
  94                   GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
  95                   7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
  96                   GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
  97                   7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
  98
  99         return 0;
 100 }
 101
 102 static int mv88e6131_setup(struct dsa_switch *ds)
 103 {
 104         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 105         int ret;
 106
 107         ret = mv88e6xxx_setup_common(ds);
 108         if (ret < 0)
 109                 return ret;
 110
 111         mv88e6xxx_ppu_state_init(ds);
 112
 113         switch (ps->id) {
 114         case PORT_SWITCH_ID_6085:
 115         case PORT_SWITCH_ID_6185:
 116                 ps->num_ports = 10;
 117                 break;
 118         case PORT_SWITCH_ID_6095:
 119                 ps->num_ports = 11;
 120                 break;
 121         case PORT_SWITCH_ID_6131:
 122         case PORT_SWITCH_ID_6131_B2:
 123                 ps->num_ports = 8;
 124                 break;
 125         default:
 126                 return -ENODEV;
 127         }
 128
 129         ret = mv88e6xxx_switch_reset(ds, false);
 130         if (ret < 0)
 131                 return ret;
 132
 133         ret = mv88e6131_setup_global(ds);
 134         if (ret < 0)
 135                 return ret;
 136
 137         return mv88e6xxx_setup_ports(ds);
 138 }
 139
 140 static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port)
 141 {
 142         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 143
 144         if (port >= 0 && port < ps->num_ports)
 145                 return port;
 146
 147         return -EINVAL;
 148 }
 149
 150 static int
 151 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 152 {
 153         int addr = mv88e6131_port_to_phy_addr(ds, port);
 154
 155         if (addr < 0)
 156                 return addr;
 157
 158         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 159 }
 160
 161 static int
 162 mv88e6131_phy_write(struct dsa_switch *ds,
 163                               int port, int regnum, u16 val)
 164 {
 165         int addr = mv88e6131_port_to_phy_addr(ds, port);
 166
 167         if (addr < 0)
 168                 return addr;
 169
 170         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 171 }
 172
 173 struct dsa_switch_driver mv88e6131_switch_driver = {
 174         .tag_protocol           = DSA_TAG_PROTO_DSA,
 175         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 176         .probe                  = mv88e6131_probe,
 177         .setup                  = mv88e6131_setup,
 178         .set_addr               = mv88e6xxx_set_addr_direct,
 179         .phy_read               = mv88e6131_phy_read,
 180         .phy_write              = mv88e6131_phy_write,
 181         .poll_link              = mv88e6xxx_poll_link,
 182         .get_strings            = mv88e6xxx_get_strings,
 183         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
 184         .get_sset_count         = mv88e6xxx_get_sset_count,
 185 };
 186
 187 MODULE_ALIAS("platform:mv88e6085");
 188 MODULE_ALIAS("platform:mv88e6095");
 189 MODULE_ALIAS("platform:mv88e6095f");
 190 MODULE_ALIAS("platform:mv88e6131");