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net: dsa: mv88e6131: add registers access
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1 /*
2 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
3 * Copyright (c) 2008-2009 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <net/dsa.h>
18 #include "mv88e6xxx.h"
19
20 static const struct mv88e6xxx_info mv88e6131_table[] = {
21 {
22 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
23 .family = MV88E6XXX_FAMILY_6095,
24 .name = "Marvell 88E6095/88E6095F",
25 .num_databases = 256,
26 .num_ports = 11,
27 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
28 }, {
29 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
30 .family = MV88E6XXX_FAMILY_6097,
31 .name = "Marvell 88E6085",
32 .num_databases = 4096,
33 .num_ports = 10,
34 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
35 }, {
36 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
37 .family = MV88E6XXX_FAMILY_6185,
38 .name = "Marvell 88E6131",
39 .num_databases = 256,
40 .num_ports = 8,
41 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
42 }, {
43 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
44 .family = MV88E6XXX_FAMILY_6185,
45 .name = "Marvell 88E6185",
46 .num_databases = 256,
47 .num_ports = 10,
48 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
49 }
50 };
51
52 static const char *mv88e6131_drv_probe(struct device *dsa_dev,
53 struct device *host_dev, int sw_addr,
54 void **priv)
55 {
56 return mv88e6xxx_drv_probe(dsa_dev, host_dev, sw_addr, priv,
57 mv88e6131_table,
58 ARRAY_SIZE(mv88e6131_table));
59 }
60
61 static int mv88e6131_setup_global(struct dsa_switch *ds)
62 {
63 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
64 u32 upstream_port = dsa_upstream_port(ds);
65 int ret;
66 u32 reg;
67
68 ret = mv88e6xxx_setup_global(ds);
69 if (ret)
70 return ret;
71
72 /* Enable the PHY polling unit, don't discard packets with
73 * excessive collisions, use a weighted fair queueing scheme
74 * to arbitrate between packet queues, set the maximum frame
75 * size to 1632, and mask all interrupt sources.
76 */
77 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
78 GLOBAL_CONTROL_PPU_ENABLE |
79 GLOBAL_CONTROL_MAX_FRAME_1632);
80 if (ret)
81 return ret;
82
83 /* Set the VLAN ethertype to 0x8100. */
84 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
85 if (ret)
86 return ret;
87
88 /* Disable ARP mirroring, and configure the upstream port as
89 * the port to which ingress and egress monitor frames are to
90 * be sent.
91 */
92 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
93 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
94 GLOBAL_MONITOR_CONTROL_ARP_DISABLED;
95 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
96 if (ret)
97 return ret;
98
99 /* Disable cascade port functionality unless this device
100 * is used in a cascade configuration, and set the switch's
101 * DSA device number.
102 */
103 if (ds->dst->pd->nr_chips > 1)
104 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
105 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
106 (ds->index & 0x1f));
107 else
108 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
109 GLOBAL_CONTROL_2_NO_CASCADE |
110 (ds->index & 0x1f));
111 if (ret)
112 return ret;
113
114 /* Force the priority of IGMP/MLD snoop frames and ARP frames
115 * to the highest setting.
116 */
117 return mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
118 GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
119 7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
120 GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
121 7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
122 }
123
124 static int mv88e6131_setup(struct dsa_switch *ds)
125 {
126 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
127 int ret;
128
129 ps->ds = ds;
130
131 ret = mv88e6xxx_setup_common(ps);
132 if (ret < 0)
133 return ret;
134
135 ret = mv88e6xxx_switch_reset(ps, false);
136 if (ret < 0)
137 return ret;
138
139 ret = mv88e6131_setup_global(ds);
140 if (ret < 0)
141 return ret;
142
143 return mv88e6xxx_setup_ports(ds);
144 }
145
146 struct dsa_switch_driver mv88e6131_switch_driver = {
147 .tag_protocol = DSA_TAG_PROTO_DSA,
148 .probe = mv88e6131_drv_probe,
149 .setup = mv88e6131_setup,
150 .set_addr = mv88e6xxx_set_addr,
151 .phy_read = mv88e6xxx_phy_read,
152 .phy_write = mv88e6xxx_phy_write,
153 .set_eee = mv88e6xxx_set_eee,
154 .get_eee = mv88e6xxx_get_eee,
155 .get_strings = mv88e6xxx_get_strings,
156 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
157 .get_sset_count = mv88e6xxx_get_sset_count,
158 .get_eeprom = mv88e6xxx_get_eeprom,
159 .set_eeprom = mv88e6xxx_set_eeprom,
160 .get_regs_len = mv88e6xxx_get_regs_len,
161 .get_regs = mv88e6xxx_get_regs,
162 #ifdef CONFIG_NET_DSA_HWMON
163 .get_temp = mv88e6xxx_get_temp,
164 .get_temp_limit = mv88e6xxx_get_temp_limit,
165 .set_temp_limit = mv88e6xxx_set_temp_limit,
166 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
167 #endif
168 .adjust_link = mv88e6xxx_adjust_link,
169 .port_bridge_join = mv88e6xxx_port_bridge_join,
170 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
171 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
172 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
173 .port_vlan_add = mv88e6xxx_port_vlan_add,
174 .port_vlan_del = mv88e6xxx_port_vlan_del,
175 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
176 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
177 .port_fdb_add = mv88e6xxx_port_fdb_add,
178 .port_fdb_del = mv88e6xxx_port_fdb_del,
179 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
180 };
181
182 MODULE_ALIAS("platform:mv88e6085");
183 MODULE_ALIAS("platform:mv88e6095");
184 MODULE_ALIAS("platform:mv88e6095f");
185 MODULE_ALIAS("platform:mv88e6131");