drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static char *mv88e6131_probe(struct device *host_dev, int sw_addr)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  23         int ret;
  24
  25         if (bus == NULL)
  26                 return NULL;
  27
  28         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
  29         if (ret >= 0) {
  30                 int ret_masked = ret & 0xfff0;
  31
  32                 if (ret_masked == ID_6085)
  33                         return "Marvell 88E6085";
  34                 if (ret_masked == ID_6095)
  35                         return "Marvell 88E6095/88E6095F";
  36                 if (ret == ID_6131_B2)
  37                         return "Marvell 88E6131 (B2)";
  38                 if (ret_masked == ID_6131)
  39                         return "Marvell 88E6131";
  40         }
  41
  42         return NULL;
  43 }
  44
  45 static int mv88e6131_switch_reset(struct dsa_switch *ds)
  46 {
  47         int i;
  48         int ret;
  49         unsigned long timeout;
  50
  51         /* Set all ports to the disabled state. */
  52         for (i = 0; i < 11; i++) {
  53                 ret = REG_READ(REG_PORT(i), 0x04);
  54                 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  55         }
  56
  57         /* Wait for transmit queues to drain. */
  58         usleep_range(2000, 4000);
  59
  60         /* Reset the switch. */
  61         REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
  62
  63         /* Wait up to one second for reset to complete. */
  64         timeout = jiffies + 1 * HZ;
  65         while (time_before(jiffies, timeout)) {
  66                 ret = REG_READ(REG_GLOBAL, 0x00);
  67                 if ((ret & 0xc800) == 0xc800)
  68                         break;
  69
  70                 usleep_range(1000, 2000);
  71         }
  72         if (time_after(jiffies, timeout))
  73                 return -ETIMEDOUT;
  74
  75         return 0;
  76 }
  77
  78 static int mv88e6131_setup_global(struct dsa_switch *ds)
  79 {
  80         int ret;
  81         int i;
  82
  83         /* Enable the PHY polling unit, don't discard packets with
  84          * excessive collisions, use a weighted fair queueing scheme
  85          * to arbitrate between packet queues, set the maximum frame
  86          * size to 1632, and mask all interrupt sources.
  87          */
  88         REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
  89
  90         /* Set the default address aging time to 5 minutes, and
  91          * enable address learn messages to be sent to all message
  92          * ports.
  93          */
  94         REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
  95
  96         /* Configure the priority mapping registers. */
  97         ret = mv88e6xxx_config_prio(ds);
  98         if (ret < 0)
  99                 return ret;
 100
 101         /* Set the VLAN ethertype to 0x8100. */
 102         REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
 103
 104         /* Disable ARP mirroring, and configure the upstream port as
 105          * the port to which ingress and egress monitor frames are to
 106          * be sent.
 107          */
 108         REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
 109
 110         /* Disable cascade port functionality unless this device
 111          * is used in a cascade configuration, and set the switch's
 112          * DSA device number.
 113          */
 114         if (ds->dst->pd->nr_chips > 1)
 115                 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
 116         else
 117                 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
 118
 119         /* Send all frames with destination addresses matching
 120          * 01:80:c2:00:00:0x to the CPU port.
 121          */
 122         REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
 123
 124         /* Ignore removed tag data on doubly tagged packets, disable
 125          * flow control messages, force flow control priority to the
 126          * highest, and send all special multicast frames to the CPU
 127          * port at the highest priority.
 128          */
 129         REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
 130
 131         /* Program the DSA routing table. */
 132         for (i = 0; i < 32; i++) {
 133                 int nexthop;
 134
 135                 nexthop = 0x1f;
 136                 if (ds->pd->rtable &&
 137                     i != ds->index && i < ds->dst->pd->nr_chips)
 138                         nexthop = ds->pd->rtable[i] & 0x1f;
 139
 140                 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
 141         }
 142
 143         /* Clear all trunk masks. */
 144         for (i = 0; i < 8; i++)
 145                 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
 146
 147         /* Clear all trunk mappings. */
 148         for (i = 0; i < 16; i++)
 149                 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
 150
 151         /* Force the priority of IGMP/MLD snoop frames and ARP frames
 152          * to the highest setting.
 153          */
 154         REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
 155
 156         return 0;
 157 }
 158
 159 static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
 160 {
 161         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 162         int addr = REG_PORT(p);
 163         u16 val;
 164
 165         /* MAC Forcing register: don't force link, speed, duplex
 166          * or flow control state to any particular values on physical
 167          * ports, but force the CPU port and all DSA ports to 1000 Mb/s
 168          * (100 Mb/s on 6085) full duplex.
 169          */
 170         if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
 171                 if (ps->id == ID_6085)
 172                         REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
 173                 else
 174                         REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
 175         else
 176                 REG_WRITE(addr, 0x01, 0x0003);
 177
 178         /* Port Control: disable Core Tag, disable Drop-on-Lock,
 179          * transmit frames unmodified, disable Header mode,
 180          * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
 181          * tunneling, determine priority by looking at 802.1p and
 182          * IP priority fields (IP prio has precedence), and set STP
 183          * state to Forwarding.
 184          *
 185          * If this is the upstream port for this switch, enable
 186          * forwarding of unknown unicasts, and enable DSA tagging
 187          * mode.
 188          *
 189          * If this is the link to another switch, use DSA tagging
 190          * mode, but do not enable forwarding of unknown unicasts.
 191          */
 192         val = 0x0433;
 193         if (p == dsa_upstream_port(ds)) {
 194                 val |= 0x0104;
 195                 /* On 6085, unknown multicast forward is controlled
 196                  * here rather than in Port Control 2 register.
 197                  */
 198                 if (ps->id == ID_6085)
 199                         val |= 0x0008;
 200         }
 201         if (ds->dsa_port_mask & (1 << p))
 202                 val |= 0x0100;
 203         REG_WRITE(addr, 0x04, val);
 204
 205         /* Port Control 2: don't force a good FCS, don't use
 206          * VLAN-based, source address-based or destination
 207          * address-based priority overrides, don't let the switch
 208          * add or strip 802.1q tags, don't discard tagged or
 209          * untagged frames on this port, do a destination address
 210          * lookup on received packets as usual, don't send a copy
 211          * of all transmitted/received frames on this port to the
 212          * CPU, and configure the upstream port number.
 213          *
 214          * If this is the upstream port for this switch, enable
 215          * forwarding of unknown multicast addresses.
 216          */
 217         if (ps->id == ID_6085)
 218                 /* on 6085, bits 3:0 are reserved, bit 6 control ARP
 219                  * mirroring, and multicast forward is handled in
 220                  * Port Control register.
 221                  */
 222                 REG_WRITE(addr, 0x08, 0x0080);
 223         else {
 224                 val = 0x0080 | dsa_upstream_port(ds);
 225                 if (p == dsa_upstream_port(ds))
 226                         val |= 0x0040;
 227                 REG_WRITE(addr, 0x08, val);
 228         }
 229
 230         /* Rate Control: disable ingress rate limiting. */
 231         REG_WRITE(addr, 0x09, 0x0000);
 232
 233         /* Rate Control 2: disable egress rate limiting. */
 234         REG_WRITE(addr, 0x0a, 0x0000);
 235
 236         /* Port Association Vector: when learning source addresses
 237          * of packets, add the address to the address database using
 238          * a port bitmap that has only the bit for this port set and
 239          * the other bits clear.
 240          */
 241         REG_WRITE(addr, 0x0b, 1 << p);
 242
 243         /* Tag Remap: use an identity 802.1p prio -> switch prio
 244          * mapping.
 245          */
 246         REG_WRITE(addr, 0x18, 0x3210);
 247
 248         /* Tag Remap 2: use an identity 802.1p prio -> switch prio
 249          * mapping.
 250          */
 251         REG_WRITE(addr, 0x19, 0x7654);
 252
 253         return mv88e6xxx_setup_port_common(ds, p);
 254 }
 255
 256 static int mv88e6131_setup(struct dsa_switch *ds)
 257 {
 258         int i;
 259         int ret;
 260
 261         ret = mv88e6xxx_setup_common(ds);
 262         if (ret < 0)
 263                 return ret;
 264
 265         mv88e6xxx_ppu_state_init(ds);
 266
 267         ret = mv88e6131_switch_reset(ds);
 268         if (ret < 0)
 269                 return ret;
 270
 271         /* @@@ initialise vtu and atu */
 272
 273         ret = mv88e6131_setup_global(ds);
 274         if (ret < 0)
 275                 return ret;
 276
 277         for (i = 0; i < 11; i++) {
 278                 ret = mv88e6131_setup_port(ds, i);
 279                 if (ret < 0)
 280                         return ret;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int mv88e6131_port_to_phy_addr(int port)
 287 {
 288         if (port >= 0 && port <= 11)
 289                 return port;
 290         return -1;
 291 }
 292
 293 static int
 294 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 295 {
 296         int addr = mv88e6131_port_to_phy_addr(port);
 297         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 298 }
 299
 300 static int
 301 mv88e6131_phy_write(struct dsa_switch *ds,
 302                               int port, int regnum, u16 val)
 303 {
 304         int addr = mv88e6131_port_to_phy_addr(port);
 305         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 306 }
 307
 308 static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
 309         { "in_good_octets", 8, 0x00, },
 310         { "in_bad_octets", 4, 0x02, },
 311         { "in_unicast", 4, 0x04, },
 312         { "in_broadcasts", 4, 0x06, },
 313         { "in_multicasts", 4, 0x07, },
 314         { "in_pause", 4, 0x16, },
 315         { "in_undersize", 4, 0x18, },
 316         { "in_fragments", 4, 0x19, },
 317         { "in_oversize", 4, 0x1a, },
 318         { "in_jabber", 4, 0x1b, },
 319         { "in_rx_error", 4, 0x1c, },
 320         { "in_fcs_error", 4, 0x1d, },
 321         { "out_octets", 8, 0x0e, },
 322         { "out_unicast", 4, 0x10, },
 323         { "out_broadcasts", 4, 0x13, },
 324         { "out_multicasts", 4, 0x12, },
 325         { "out_pause", 4, 0x15, },
 326         { "excessive", 4, 0x11, },
 327         { "collisions", 4, 0x1e, },
 328         { "deferred", 4, 0x05, },
 329         { "single", 4, 0x14, },
 330         { "multiple", 4, 0x17, },
 331         { "out_fcs_error", 4, 0x03, },
 332         { "late", 4, 0x1f, },
 333         { "hist_64bytes", 4, 0x08, },
 334         { "hist_65_127bytes", 4, 0x09, },
 335         { "hist_128_255bytes", 4, 0x0a, },
 336         { "hist_256_511bytes", 4, 0x0b, },
 337         { "hist_512_1023bytes", 4, 0x0c, },
 338         { "hist_1024_max_bytes", 4, 0x0d, },
 339 };
 340
 341 static void
 342 mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 343 {
 344         mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
 345                               mv88e6131_hw_stats, port, data);
 346 }
 347
 348 static void
 349 mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
 350                                   int port, uint64_t *data)
 351 {
 352         mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
 353                                     mv88e6131_hw_stats, port, data);
 354 }
 355
 356 static int mv88e6131_get_sset_count(struct dsa_switch *ds)
 357 {
 358         return ARRAY_SIZE(mv88e6131_hw_stats);
 359 }
 360
 361 struct dsa_switch_driver mv88e6131_switch_driver = {
 362         .tag_protocol           = DSA_TAG_PROTO_DSA,
 363         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 364         .probe                  = mv88e6131_probe,
 365         .setup                  = mv88e6131_setup,
 366         .set_addr               = mv88e6xxx_set_addr_direct,
 367         .phy_read               = mv88e6131_phy_read,
 368         .phy_write              = mv88e6131_phy_write,
 369         .poll_link              = mv88e6xxx_poll_link,
 370         .get_strings            = mv88e6131_get_strings,
 371         .get_ethtool_stats      = mv88e6131_get_ethtool_stats,
 372         .get_sset_count         = mv88e6131_get_sset_count,
 373 };
 374
 375 MODULE_ALIAS("platform:mv88e6085");
 376 MODULE_ALIAS("platform:mv88e6095");
 377 MODULE_ALIAS("platform:mv88e6095f");
 378 MODULE_ALIAS("platform:mv88e6131");