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net: dsa: mv88e6xxx: add VTU Load/Purge operation
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 /*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
34 #include <net/dsa.h>
35 #include <net/switchdev.h>
36
37 #include "mv88e6xxx.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "port.h"
41
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
43 {
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
46 dump_stack();
47 }
48 }
49
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
60 */
61
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
64 {
65 if (!chip->smi_ops)
66 return -EOPNOTSUPP;
67
68 return chip->smi_ops->read(chip, addr, reg, val);
69 }
70
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
73 {
74 if (!chip->smi_ops)
75 return -EOPNOTSUPP;
76
77 return chip->smi_ops->write(chip, addr, reg, val);
78 }
79
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
82 {
83 int ret;
84
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92 }
93
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
96 {
97 int ret;
98
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
100 if (ret < 0)
101 return ret;
102
103 return 0;
104 }
105
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109 };
110
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
112 {
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
118 if (ret < 0)
119 return ret;
120
121 if ((ret & SMI_CMD_BUSY) == 0)
122 return 0;
123 }
124
125 return -ETIMEDOUT;
126 }
127
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
130 {
131 int ret;
132
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
135 if (ret < 0)
136 return ret;
137
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
141 if (ret < 0)
142 return ret;
143
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
146 if (ret < 0)
147 return ret;
148
149 /* Read the data. */
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
151 if (ret < 0)
152 return ret;
153
154 *val = ret & 0xffff;
155
156 return 0;
157 }
158
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
161 {
162 int ret;
163
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
182 if (ret < 0)
183 return ret;
184
185 return 0;
186 }
187
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191 };
192
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
194 {
195 int err;
196
197 assert_reg_lock(chip);
198
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
200 if (err)
201 return err;
202
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
204 addr, reg, *val);
205
206 return 0;
207 }
208
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
210 {
211 int err;
212
213 assert_reg_lock(chip);
214
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
216 if (err)
217 return err;
218
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
220 addr, reg, val);
221
222 return 0;
223 }
224
225 static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
228 {
229 return mv88e6xxx_read(chip, addr, reg, val);
230 }
231
232 static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
235 {
236 return mv88e6xxx_write(chip, addr, reg, val);
237 }
238
239 static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240 {
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249 }
250
251 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253 {
254 int addr = phy; /* PHY devices addresses start at 0x0 */
255 struct mii_bus *bus;
256
257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
259 return -EOPNOTSUPP;
260
261 if (!chip->info->ops->phy_read)
262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
265 }
266
267 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269 {
270 int addr = phy; /* PHY devices addresses start at 0x0 */
271 struct mii_bus *bus;
272
273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
275 return -EOPNOTSUPP;
276
277 if (!chip->info->ops->phy_write)
278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
281 }
282
283 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284 {
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289 }
290
291 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292 {
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301 }
302
303 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305 {
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319 }
320
321 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323 {
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337 }
338
339 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340 {
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343 }
344
345 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346 {
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349 }
350
351 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352 {
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357 }
358
359 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360 {
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365 }
366
367 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368 {
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390 out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392 }
393
394 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395 {
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399 }
400
401 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402 {
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419 out:
420 mutex_unlock(&chip->reg_lock);
421 }
422
423 static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429 };
430
431 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434 {
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442 }
443
444 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447 };
448
449 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450 {
451 int irq, virq;
452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
459
460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
462 irq_dispose_mapping(virq);
463 }
464
465 irq_domain_remove(chip->g1_irq.domain);
466 }
467
468 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469 {
470 int err, irq, virq;
471 u16 reg, mask;
472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
487 if (err)
488 goto out_mapping;
489
490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
491
492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
493 if (err)
494 goto out_disable;
495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
499 goto out_disable;
500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
506 goto out_disable;
507
508 return 0;
509
510 out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514 out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
521
522 return err;
523 }
524
525 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
526 {
527 int i;
528
529 for (i = 0; i < 16; i++) {
530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
543 dev_err(chip->dev, "Timeout while waiting for switch\n");
544 return -ETIMEDOUT;
545 }
546
547 /* Indirect write to single pointer-data register with an Update bit */
548 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
549 {
550 u16 val;
551 int err;
552
553 /* Wait until the previous operation is completed */
554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562 }
563
564 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
565 {
566 if (!chip->info->ops->ppu_disable)
567 return 0;
568
569 return chip->info->ops->ppu_disable(chip);
570 }
571
572 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
573 {
574 if (!chip->info->ops->ppu_enable)
575 return 0;
576
577 return chip->info->ops->ppu_enable(chip);
578 }
579
580 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581 {
582 struct mv88e6xxx_chip *chip;
583
584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
585
586 mutex_lock(&chip->reg_lock);
587
588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
592 }
593
594 mutex_unlock(&chip->reg_lock);
595 }
596
597 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598 {
599 struct mv88e6xxx_chip *chip = (void *)_ps;
600
601 schedule_work(&chip->ppu_work);
602 }
603
604 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
605 {
606 int ret;
607
608 mutex_lock(&chip->ppu_mutex);
609
610 /* If the PHY polling unit is enabled, disable it so that
611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
617 if (ret < 0) {
618 mutex_unlock(&chip->ppu_mutex);
619 return ret;
620 }
621 chip->ppu_disabled = 1;
622 } else {
623 del_timer(&chip->ppu_timer);
624 ret = 0;
625 }
626
627 return ret;
628 }
629
630 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
631 {
632 /* Schedule a timer to re-enable the PHY polling unit. */
633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
635 }
636
637 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
638 {
639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
643 }
644
645 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646 {
647 del_timer_sync(&chip->ppu_timer);
648 }
649
650 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
653 {
654 int err;
655
656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
659 mv88e6xxx_ppu_access_put(chip);
660 }
661
662 return err;
663 }
664
665 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
668 {
669 int err;
670
671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
674 mv88e6xxx_ppu_access_put(chip);
675 }
676
677 return err;
678 }
679
680 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
681 int link, int speed, int duplex,
682 phy_interface_t mode)
683 {
684 int err;
685
686 if (!chip->info->ops->port_set_link)
687 return 0;
688
689 /* Port's MAC control must not be changed unless the link is down */
690 err = chip->info->ops->port_set_link(chip, port, 0);
691 if (err)
692 return err;
693
694 if (chip->info->ops->port_set_speed) {
695 err = chip->info->ops->port_set_speed(chip, port, speed);
696 if (err && err != -EOPNOTSUPP)
697 goto restore_link;
698 }
699
700 if (chip->info->ops->port_set_duplex) {
701 err = chip->info->ops->port_set_duplex(chip, port, duplex);
702 if (err && err != -EOPNOTSUPP)
703 goto restore_link;
704 }
705
706 if (chip->info->ops->port_set_rgmii_delay) {
707 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
708 if (err && err != -EOPNOTSUPP)
709 goto restore_link;
710 }
711
712 if (chip->info->ops->port_set_cmode) {
713 err = chip->info->ops->port_set_cmode(chip, port, mode);
714 if (err && err != -EOPNOTSUPP)
715 goto restore_link;
716 }
717
718 err = 0;
719 restore_link:
720 if (chip->info->ops->port_set_link(chip, port, link))
721 netdev_err(chip->ds->ports[port].netdev,
722 "failed to restore MAC's link\n");
723
724 return err;
725 }
726
727 /* We expect the switch to perform auto negotiation if there is a real
728 * phy. However, in the case of a fixed link phy, we force the port
729 * settings from the fixed link settings.
730 */
731 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
732 struct phy_device *phydev)
733 {
734 struct mv88e6xxx_chip *chip = ds->priv;
735 int err;
736
737 if (!phy_is_pseudo_fixed_link(phydev))
738 return;
739
740 mutex_lock(&chip->reg_lock);
741 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
742 phydev->duplex, phydev->interface);
743 mutex_unlock(&chip->reg_lock);
744
745 if (err && err != -EOPNOTSUPP)
746 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
747 }
748
749 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
750 {
751 if (!chip->info->ops->stats_snapshot)
752 return -EOPNOTSUPP;
753
754 return chip->info->ops->stats_snapshot(chip, port);
755 }
756
757 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
758 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
759 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
760 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
761 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
762 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
763 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
764 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
765 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
766 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
767 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
768 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
769 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
770 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
771 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
772 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
773 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
774 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
775 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
776 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
777 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
778 { "single", 4, 0x14, STATS_TYPE_BANK0, },
779 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
780 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
781 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
782 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
783 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
784 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
785 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
786 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
787 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
788 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
789 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
790 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
791 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
792 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
793 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
794 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
795 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
796 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
797 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
798 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
799 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
800 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
801 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
802 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
803 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
804 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
805 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
806 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
807 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
808 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
809 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
810 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
811 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
812 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
813 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
814 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
815 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
816 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
817 };
818
819 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
820 struct mv88e6xxx_hw_stat *s,
821 int port, u16 bank1_select,
822 u16 histogram)
823 {
824 u32 low;
825 u32 high = 0;
826 u16 reg = 0;
827 int err;
828 u64 value;
829
830 switch (s->type) {
831 case STATS_TYPE_PORT:
832 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
833 if (err)
834 return UINT64_MAX;
835
836 low = reg;
837 if (s->sizeof_stat == 4) {
838 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
839 if (err)
840 return UINT64_MAX;
841 high = reg;
842 }
843 break;
844 case STATS_TYPE_BANK1:
845 reg = bank1_select;
846 /* fall through */
847 case STATS_TYPE_BANK0:
848 reg |= s->reg | histogram;
849 mv88e6xxx_g1_stats_read(chip, reg, &low);
850 if (s->sizeof_stat == 8)
851 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
852 }
853 value = (((u64)high) << 16) | low;
854 return value;
855 }
856
857 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
858 uint8_t *data, int types)
859 {
860 struct mv88e6xxx_hw_stat *stat;
861 int i, j;
862
863 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
864 stat = &mv88e6xxx_hw_stats[i];
865 if (stat->type & types) {
866 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
867 ETH_GSTRING_LEN);
868 j++;
869 }
870 }
871 }
872
873 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
874 uint8_t *data)
875 {
876 mv88e6xxx_stats_get_strings(chip, data,
877 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
878 }
879
880 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
881 uint8_t *data)
882 {
883 mv88e6xxx_stats_get_strings(chip, data,
884 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
885 }
886
887 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
888 uint8_t *data)
889 {
890 struct mv88e6xxx_chip *chip = ds->priv;
891
892 if (chip->info->ops->stats_get_strings)
893 chip->info->ops->stats_get_strings(chip, data);
894 }
895
896 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
897 int types)
898 {
899 struct mv88e6xxx_hw_stat *stat;
900 int i, j;
901
902 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
903 stat = &mv88e6xxx_hw_stats[i];
904 if (stat->type & types)
905 j++;
906 }
907 return j;
908 }
909
910 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
911 {
912 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
913 STATS_TYPE_PORT);
914 }
915
916 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
917 {
918 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
919 STATS_TYPE_BANK1);
920 }
921
922 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
923 {
924 struct mv88e6xxx_chip *chip = ds->priv;
925
926 if (chip->info->ops->stats_get_sset_count)
927 return chip->info->ops->stats_get_sset_count(chip);
928
929 return 0;
930 }
931
932 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
933 uint64_t *data, int types,
934 u16 bank1_select, u16 histogram)
935 {
936 struct mv88e6xxx_hw_stat *stat;
937 int i, j;
938
939 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
940 stat = &mv88e6xxx_hw_stats[i];
941 if (stat->type & types) {
942 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
943 bank1_select,
944 histogram);
945 j++;
946 }
947 }
948 }
949
950 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
951 uint64_t *data)
952 {
953 return mv88e6xxx_stats_get_stats(chip, port, data,
954 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
955 0, GLOBAL_STATS_OP_HIST_RX_TX);
956 }
957
958 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
959 uint64_t *data)
960 {
961 return mv88e6xxx_stats_get_stats(chip, port, data,
962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
963 GLOBAL_STATS_OP_BANK_1_BIT_9,
964 GLOBAL_STATS_OP_HIST_RX_TX);
965 }
966
967 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
968 uint64_t *data)
969 {
970 return mv88e6xxx_stats_get_stats(chip, port, data,
971 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
972 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
973 }
974
975 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
976 uint64_t *data)
977 {
978 if (chip->info->ops->stats_get_stats)
979 chip->info->ops->stats_get_stats(chip, port, data);
980 }
981
982 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
983 uint64_t *data)
984 {
985 struct mv88e6xxx_chip *chip = ds->priv;
986 int ret;
987
988 mutex_lock(&chip->reg_lock);
989
990 ret = mv88e6xxx_stats_snapshot(chip, port);
991 if (ret < 0) {
992 mutex_unlock(&chip->reg_lock);
993 return;
994 }
995
996 mv88e6xxx_get_stats(chip, port, data);
997
998 mutex_unlock(&chip->reg_lock);
999 }
1000
1001 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1002 {
1003 if (chip->info->ops->stats_set_histogram)
1004 return chip->info->ops->stats_set_histogram(chip);
1005
1006 return 0;
1007 }
1008
1009 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1010 {
1011 return 32 * sizeof(u16);
1012 }
1013
1014 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1015 struct ethtool_regs *regs, void *_p)
1016 {
1017 struct mv88e6xxx_chip *chip = ds->priv;
1018 int err;
1019 u16 reg;
1020 u16 *p = _p;
1021 int i;
1022
1023 regs->version = 0;
1024
1025 memset(p, 0xff, 32 * sizeof(u16));
1026
1027 mutex_lock(&chip->reg_lock);
1028
1029 for (i = 0; i < 32; i++) {
1030
1031 err = mv88e6xxx_port_read(chip, port, i, &reg);
1032 if (!err)
1033 p[i] = reg;
1034 }
1035
1036 mutex_unlock(&chip->reg_lock);
1037 }
1038
1039 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1040 struct ethtool_eee *e)
1041 {
1042 struct mv88e6xxx_chip *chip = ds->priv;
1043 u16 reg;
1044 int err;
1045
1046 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1047 return -EOPNOTSUPP;
1048
1049 mutex_lock(&chip->reg_lock);
1050
1051 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1052 if (err)
1053 goto out;
1054
1055 e->eee_enabled = !!(reg & 0x0200);
1056 e->tx_lpi_enabled = !!(reg & 0x0100);
1057
1058 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
1059 if (err)
1060 goto out;
1061
1062 e->eee_active = !!(reg & PORT_STATUS_EEE);
1063 out:
1064 mutex_unlock(&chip->reg_lock);
1065
1066 return err;
1067 }
1068
1069 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1070 struct phy_device *phydev, struct ethtool_eee *e)
1071 {
1072 struct mv88e6xxx_chip *chip = ds->priv;
1073 u16 reg;
1074 int err;
1075
1076 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1077 return -EOPNOTSUPP;
1078
1079 mutex_lock(&chip->reg_lock);
1080
1081 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1082 if (err)
1083 goto out;
1084
1085 reg &= ~0x0300;
1086 if (e->eee_enabled)
1087 reg |= 0x0200;
1088 if (e->tx_lpi_enabled)
1089 reg |= 0x0100;
1090
1091 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1092 out:
1093 mutex_unlock(&chip->reg_lock);
1094
1095 return err;
1096 }
1097
1098 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1099 {
1100 struct dsa_switch *ds = NULL;
1101 struct net_device *br;
1102 u16 pvlan;
1103 int i;
1104
1105 if (dev < DSA_MAX_SWITCHES)
1106 ds = chip->ds->dst->ds[dev];
1107
1108 /* Prevent frames from unknown switch or port */
1109 if (!ds || port >= ds->num_ports)
1110 return 0;
1111
1112 /* Frames from DSA links and CPU ports can egress any local port */
1113 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1114 return mv88e6xxx_port_mask(chip);
1115
1116 br = ds->ports[port].bridge_dev;
1117 pvlan = 0;
1118
1119 /* Frames from user ports can egress any local DSA links and CPU ports,
1120 * as well as any local member of their bridge group.
1121 */
1122 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1123 if (dsa_is_cpu_port(chip->ds, i) ||
1124 dsa_is_dsa_port(chip->ds, i) ||
1125 (br && chip->ds->ports[i].bridge_dev == br))
1126 pvlan |= BIT(i);
1127
1128 return pvlan;
1129 }
1130
1131 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1132 {
1133 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1134
1135 /* prevent frames from going back out of the port they came in on */
1136 output_ports &= ~BIT(port);
1137
1138 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1139 }
1140
1141 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1142 u8 state)
1143 {
1144 struct mv88e6xxx_chip *chip = ds->priv;
1145 int stp_state;
1146 int err;
1147
1148 switch (state) {
1149 case BR_STATE_DISABLED:
1150 stp_state = PORT_CONTROL_STATE_DISABLED;
1151 break;
1152 case BR_STATE_BLOCKING:
1153 case BR_STATE_LISTENING:
1154 stp_state = PORT_CONTROL_STATE_BLOCKING;
1155 break;
1156 case BR_STATE_LEARNING:
1157 stp_state = PORT_CONTROL_STATE_LEARNING;
1158 break;
1159 case BR_STATE_FORWARDING:
1160 default:
1161 stp_state = PORT_CONTROL_STATE_FORWARDING;
1162 break;
1163 }
1164
1165 mutex_lock(&chip->reg_lock);
1166 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1167 mutex_unlock(&chip->reg_lock);
1168
1169 if (err)
1170 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1171 }
1172
1173 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1174 {
1175 int err;
1176
1177 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1178 if (err)
1179 return err;
1180
1181 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1182 if (err)
1183 return err;
1184
1185 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1186 }
1187
1188 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1189 {
1190 u16 pvlan = 0;
1191
1192 if (!mv88e6xxx_has_pvt(chip))
1193 return -EOPNOTSUPP;
1194
1195 /* Skip the local source device, which uses in-chip port VLAN */
1196 if (dev != chip->ds->index)
1197 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1198
1199 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1200 }
1201
1202 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1203 {
1204 int dev, port;
1205 int err;
1206
1207 if (!mv88e6xxx_has_pvt(chip))
1208 return 0;
1209
1210 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1211 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1212 */
1213 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1214 if (err)
1215 return err;
1216
1217 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1218 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1219 err = mv88e6xxx_pvt_map(chip, dev, port);
1220 if (err)
1221 return err;
1222 }
1223 }
1224
1225 return 0;
1226 }
1227
1228 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1229 {
1230 struct mv88e6xxx_chip *chip = ds->priv;
1231 int err;
1232
1233 mutex_lock(&chip->reg_lock);
1234 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1235 mutex_unlock(&chip->reg_lock);
1236
1237 if (err)
1238 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1239 }
1240
1241 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1242 {
1243 if (!chip->info->max_vid)
1244 return 0;
1245
1246 return mv88e6xxx_g1_vtu_flush(chip);
1247 }
1248
1249 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1250 struct mv88e6xxx_vtu_entry *entry)
1251 {
1252 if (!chip->info->ops->vtu_getnext)
1253 return -EOPNOTSUPP;
1254
1255 return chip->info->ops->vtu_getnext(chip, entry);
1256 }
1257
1258 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1259 struct mv88e6xxx_vtu_entry *entry)
1260 {
1261 if (!chip->info->ops->vtu_loadpurge)
1262 return -EOPNOTSUPP;
1263
1264 return chip->info->ops->vtu_loadpurge(chip, entry);
1265 }
1266
1267 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1268 struct switchdev_obj_port_vlan *vlan,
1269 int (*cb)(struct switchdev_obj *obj))
1270 {
1271 struct mv88e6xxx_chip *chip = ds->priv;
1272 struct mv88e6xxx_vtu_entry next = {
1273 .vid = chip->info->max_vid,
1274 };
1275 u16 pvid;
1276 int err;
1277
1278 if (!chip->info->max_vid)
1279 return -EOPNOTSUPP;
1280
1281 mutex_lock(&chip->reg_lock);
1282
1283 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1284 if (err)
1285 goto unlock;
1286
1287 do {
1288 err = mv88e6xxx_vtu_getnext(chip, &next);
1289 if (err)
1290 break;
1291
1292 if (!next.valid)
1293 break;
1294
1295 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1296 continue;
1297
1298 /* reinit and dump this VLAN obj */
1299 vlan->vid_begin = next.vid;
1300 vlan->vid_end = next.vid;
1301 vlan->flags = 0;
1302
1303 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1304 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1305
1306 if (next.vid == pvid)
1307 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1308
1309 err = cb(&vlan->obj);
1310 if (err)
1311 break;
1312 } while (next.vid < chip->info->max_vid);
1313
1314 unlock:
1315 mutex_unlock(&chip->reg_lock);
1316
1317 return err;
1318 }
1319
1320 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1321 {
1322 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1323 struct mv88e6xxx_vtu_entry vlan = {
1324 .vid = chip->info->max_vid,
1325 };
1326 int i, err;
1327
1328 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1329
1330 /* Set every FID bit used by the (un)bridged ports */
1331 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1332 err = mv88e6xxx_port_get_fid(chip, i, fid);
1333 if (err)
1334 return err;
1335
1336 set_bit(*fid, fid_bitmap);
1337 }
1338
1339 /* Set every FID bit used by the VLAN entries */
1340 do {
1341 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1342 if (err)
1343 return err;
1344
1345 if (!vlan.valid)
1346 break;
1347
1348 set_bit(vlan.fid, fid_bitmap);
1349 } while (vlan.vid < chip->info->max_vid);
1350
1351 /* The reset value 0x000 is used to indicate that multiple address
1352 * databases are not needed. Return the next positive available.
1353 */
1354 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1355 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1356 return -ENOSPC;
1357
1358 /* Clear the database */
1359 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1360 }
1361
1362 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1363 struct mv88e6xxx_vtu_entry *entry)
1364 {
1365 struct dsa_switch *ds = chip->ds;
1366 struct mv88e6xxx_vtu_entry vlan = {
1367 .valid = true,
1368 .vid = vid,
1369 };
1370 int i, err;
1371
1372 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1373 if (err)
1374 return err;
1375
1376 /* exclude all ports except the CPU and DSA ports */
1377 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1378 vlan.member[i] = dsa_is_cpu_port(ds, i) ||
1379 dsa_is_dsa_port(ds, i)
1380 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1381 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1382
1383 *entry = vlan;
1384 return 0;
1385 }
1386
1387 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1388 struct mv88e6xxx_vtu_entry *entry, bool creat)
1389 {
1390 int err;
1391
1392 if (!vid)
1393 return -EINVAL;
1394
1395 entry->vid = vid - 1;
1396 entry->valid = false;
1397
1398 err = mv88e6xxx_vtu_getnext(chip, entry);
1399 if (err)
1400 return err;
1401
1402 if (entry->vid != vid || !entry->valid) {
1403 if (!creat)
1404 return -EOPNOTSUPP;
1405 /* -ENOENT would've been more appropriate, but switchdev expects
1406 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1407 */
1408
1409 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1410 }
1411
1412 return err;
1413 }
1414
1415 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1416 u16 vid_begin, u16 vid_end)
1417 {
1418 struct mv88e6xxx_chip *chip = ds->priv;
1419 struct mv88e6xxx_vtu_entry vlan = {
1420 .vid = vid_begin - 1,
1421 };
1422 int i, err;
1423
1424 if (!vid_begin)
1425 return -EOPNOTSUPP;
1426
1427 mutex_lock(&chip->reg_lock);
1428
1429 do {
1430 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1431 if (err)
1432 goto unlock;
1433
1434 if (!vlan.valid)
1435 break;
1436
1437 if (vlan.vid > vid_end)
1438 break;
1439
1440 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1441 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1442 continue;
1443
1444 if (!ds->ports[port].netdev)
1445 continue;
1446
1447 if (vlan.member[i] ==
1448 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1449 continue;
1450
1451 if (ds->ports[i].bridge_dev ==
1452 ds->ports[port].bridge_dev)
1453 break; /* same bridge, check next VLAN */
1454
1455 if (!ds->ports[i].bridge_dev)
1456 continue;
1457
1458 netdev_warn(ds->ports[port].netdev,
1459 "hardware VLAN %d already used by %s\n",
1460 vlan.vid,
1461 netdev_name(ds->ports[i].bridge_dev));
1462 err = -EOPNOTSUPP;
1463 goto unlock;
1464 }
1465 } while (vlan.vid < vid_end);
1466
1467 unlock:
1468 mutex_unlock(&chip->reg_lock);
1469
1470 return err;
1471 }
1472
1473 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1474 bool vlan_filtering)
1475 {
1476 struct mv88e6xxx_chip *chip = ds->priv;
1477 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1478 PORT_CONTROL_2_8021Q_DISABLED;
1479 int err;
1480
1481 if (!chip->info->max_vid)
1482 return -EOPNOTSUPP;
1483
1484 mutex_lock(&chip->reg_lock);
1485 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1486 mutex_unlock(&chip->reg_lock);
1487
1488 return err;
1489 }
1490
1491 static int
1492 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1493 const struct switchdev_obj_port_vlan *vlan,
1494 struct switchdev_trans *trans)
1495 {
1496 struct mv88e6xxx_chip *chip = ds->priv;
1497 int err;
1498
1499 if (!chip->info->max_vid)
1500 return -EOPNOTSUPP;
1501
1502 /* If the requested port doesn't belong to the same bridge as the VLAN
1503 * members, do not support it (yet) and fallback to software VLAN.
1504 */
1505 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1506 vlan->vid_end);
1507 if (err)
1508 return err;
1509
1510 /* We don't need any dynamic resource from the kernel (yet),
1511 * so skip the prepare phase.
1512 */
1513 return 0;
1514 }
1515
1516 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1517 u16 vid, bool untagged)
1518 {
1519 struct mv88e6xxx_vtu_entry vlan;
1520 int err;
1521
1522 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1523 if (err)
1524 return err;
1525
1526 vlan.member[port] = untagged ?
1527 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1528 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1529
1530 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1531 }
1532
1533 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1534 const struct switchdev_obj_port_vlan *vlan,
1535 struct switchdev_trans *trans)
1536 {
1537 struct mv88e6xxx_chip *chip = ds->priv;
1538 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1539 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1540 u16 vid;
1541
1542 if (!chip->info->max_vid)
1543 return;
1544
1545 mutex_lock(&chip->reg_lock);
1546
1547 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1548 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1549 netdev_err(ds->ports[port].netdev,
1550 "failed to add VLAN %d%c\n",
1551 vid, untagged ? 'u' : 't');
1552
1553 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1554 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1555 vlan->vid_end);
1556
1557 mutex_unlock(&chip->reg_lock);
1558 }
1559
1560 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1561 int port, u16 vid)
1562 {
1563 struct dsa_switch *ds = chip->ds;
1564 struct mv88e6xxx_vtu_entry vlan;
1565 int i, err;
1566
1567 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1568 if (err)
1569 return err;
1570
1571 /* Tell switchdev if this VLAN is handled in software */
1572 if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1573 return -EOPNOTSUPP;
1574
1575 vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1576
1577 /* keep the VLAN unless all ports are excluded */
1578 vlan.valid = false;
1579 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1580 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1581 continue;
1582
1583 if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1584 vlan.valid = true;
1585 break;
1586 }
1587 }
1588
1589 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1590 if (err)
1591 return err;
1592
1593 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1594 }
1595
1596 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1597 const struct switchdev_obj_port_vlan *vlan)
1598 {
1599 struct mv88e6xxx_chip *chip = ds->priv;
1600 u16 pvid, vid;
1601 int err = 0;
1602
1603 if (!chip->info->max_vid)
1604 return -EOPNOTSUPP;
1605
1606 mutex_lock(&chip->reg_lock);
1607
1608 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1609 if (err)
1610 goto unlock;
1611
1612 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1613 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1614 if (err)
1615 goto unlock;
1616
1617 if (vid == pvid) {
1618 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1619 if (err)
1620 goto unlock;
1621 }
1622 }
1623
1624 unlock:
1625 mutex_unlock(&chip->reg_lock);
1626
1627 return err;
1628 }
1629
1630 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1631 const unsigned char *addr, u16 vid,
1632 u8 state)
1633 {
1634 struct mv88e6xxx_vtu_entry vlan;
1635 struct mv88e6xxx_atu_entry entry;
1636 int err;
1637
1638 /* Null VLAN ID corresponds to the port private database */
1639 if (vid == 0)
1640 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1641 else
1642 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1643 if (err)
1644 return err;
1645
1646 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1647 ether_addr_copy(entry.mac, addr);
1648 eth_addr_dec(entry.mac);
1649
1650 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1651 if (err)
1652 return err;
1653
1654 /* Initialize a fresh ATU entry if it isn't found */
1655 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1656 !ether_addr_equal(entry.mac, addr)) {
1657 memset(&entry, 0, sizeof(entry));
1658 ether_addr_copy(entry.mac, addr);
1659 }
1660
1661 /* Purge the ATU entry only if no port is using it anymore */
1662 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
1663 entry.portvec &= ~BIT(port);
1664 if (!entry.portvec)
1665 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1666 } else {
1667 entry.portvec |= BIT(port);
1668 entry.state = state;
1669 }
1670
1671 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1672 }
1673
1674 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1675 const struct switchdev_obj_port_fdb *fdb,
1676 struct switchdev_trans *trans)
1677 {
1678 /* We don't need any dynamic resource from the kernel (yet),
1679 * so skip the prepare phase.
1680 */
1681 return 0;
1682 }
1683
1684 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1685 const struct switchdev_obj_port_fdb *fdb,
1686 struct switchdev_trans *trans)
1687 {
1688 struct mv88e6xxx_chip *chip = ds->priv;
1689
1690 mutex_lock(&chip->reg_lock);
1691 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1692 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1693 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
1694 mutex_unlock(&chip->reg_lock);
1695 }
1696
1697 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1698 const struct switchdev_obj_port_fdb *fdb)
1699 {
1700 struct mv88e6xxx_chip *chip = ds->priv;
1701 int err;
1702
1703 mutex_lock(&chip->reg_lock);
1704 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1705 GLOBAL_ATU_DATA_STATE_UNUSED);
1706 mutex_unlock(&chip->reg_lock);
1707
1708 return err;
1709 }
1710
1711 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1712 u16 fid, u16 vid, int port,
1713 struct switchdev_obj *obj,
1714 int (*cb)(struct switchdev_obj *obj))
1715 {
1716 struct mv88e6xxx_atu_entry addr;
1717 int err;
1718
1719 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1720 eth_broadcast_addr(addr.mac);
1721
1722 do {
1723 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1724 if (err)
1725 return err;
1726
1727 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1728 break;
1729
1730 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1731 continue;
1732
1733 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1734 struct switchdev_obj_port_fdb *fdb;
1735
1736 if (!is_unicast_ether_addr(addr.mac))
1737 continue;
1738
1739 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
1740 fdb->vid = vid;
1741 ether_addr_copy(fdb->addr, addr.mac);
1742 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
1743 fdb->ndm_state = NUD_NOARP;
1744 else
1745 fdb->ndm_state = NUD_REACHABLE;
1746 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1747 struct switchdev_obj_port_mdb *mdb;
1748
1749 if (!is_multicast_ether_addr(addr.mac))
1750 continue;
1751
1752 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1753 mdb->vid = vid;
1754 ether_addr_copy(mdb->addr, addr.mac);
1755 } else {
1756 return -EOPNOTSUPP;
1757 }
1758
1759 err = cb(obj);
1760 if (err)
1761 return err;
1762 } while (!is_broadcast_ether_addr(addr.mac));
1763
1764 return err;
1765 }
1766
1767 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1768 struct switchdev_obj *obj,
1769 int (*cb)(struct switchdev_obj *obj))
1770 {
1771 struct mv88e6xxx_vtu_entry vlan = {
1772 .vid = chip->info->max_vid,
1773 };
1774 u16 fid;
1775 int err;
1776
1777 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1778 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1779 if (err)
1780 return err;
1781
1782 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1783 if (err)
1784 return err;
1785
1786 /* Dump VLANs' Filtering Information Databases */
1787 do {
1788 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1789 if (err)
1790 return err;
1791
1792 if (!vlan.valid)
1793 break;
1794
1795 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1796 obj, cb);
1797 if (err)
1798 return err;
1799 } while (vlan.vid < chip->info->max_vid);
1800
1801 return err;
1802 }
1803
1804 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1805 struct switchdev_obj_port_fdb *fdb,
1806 int (*cb)(struct switchdev_obj *obj))
1807 {
1808 struct mv88e6xxx_chip *chip = ds->priv;
1809 int err;
1810
1811 mutex_lock(&chip->reg_lock);
1812 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
1813 mutex_unlock(&chip->reg_lock);
1814
1815 return err;
1816 }
1817
1818 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1819 struct net_device *br)
1820 {
1821 struct dsa_switch *ds;
1822 int port;
1823 int dev;
1824 int err;
1825
1826 /* Remap the Port VLAN of each local bridge group member */
1827 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1828 if (chip->ds->ports[port].bridge_dev == br) {
1829 err = mv88e6xxx_port_vlan_map(chip, port);
1830 if (err)
1831 return err;
1832 }
1833 }
1834
1835 if (!mv88e6xxx_has_pvt(chip))
1836 return 0;
1837
1838 /* Remap the Port VLAN of each cross-chip bridge group member */
1839 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1840 ds = chip->ds->dst->ds[dev];
1841 if (!ds)
1842 break;
1843
1844 for (port = 0; port < ds->num_ports; ++port) {
1845 if (ds->ports[port].bridge_dev == br) {
1846 err = mv88e6xxx_pvt_map(chip, dev, port);
1847 if (err)
1848 return err;
1849 }
1850 }
1851 }
1852
1853 return 0;
1854 }
1855
1856 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1857 struct net_device *br)
1858 {
1859 struct mv88e6xxx_chip *chip = ds->priv;
1860 int err;
1861
1862 mutex_lock(&chip->reg_lock);
1863 err = mv88e6xxx_bridge_map(chip, br);
1864 mutex_unlock(&chip->reg_lock);
1865
1866 return err;
1867 }
1868
1869 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1870 struct net_device *br)
1871 {
1872 struct mv88e6xxx_chip *chip = ds->priv;
1873
1874 mutex_lock(&chip->reg_lock);
1875 if (mv88e6xxx_bridge_map(chip, br) ||
1876 mv88e6xxx_port_vlan_map(chip, port))
1877 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1878 mutex_unlock(&chip->reg_lock);
1879 }
1880
1881 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1882 int port, struct net_device *br)
1883 {
1884 struct mv88e6xxx_chip *chip = ds->priv;
1885 int err;
1886
1887 if (!mv88e6xxx_has_pvt(chip))
1888 return 0;
1889
1890 mutex_lock(&chip->reg_lock);
1891 err = mv88e6xxx_pvt_map(chip, dev, port);
1892 mutex_unlock(&chip->reg_lock);
1893
1894 return err;
1895 }
1896
1897 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1898 int port, struct net_device *br)
1899 {
1900 struct mv88e6xxx_chip *chip = ds->priv;
1901
1902 if (!mv88e6xxx_has_pvt(chip))
1903 return;
1904
1905 mutex_lock(&chip->reg_lock);
1906 if (mv88e6xxx_pvt_map(chip, dev, port))
1907 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1908 mutex_unlock(&chip->reg_lock);
1909 }
1910
1911 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1912 {
1913 if (chip->info->ops->reset)
1914 return chip->info->ops->reset(chip);
1915
1916 return 0;
1917 }
1918
1919 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1920 {
1921 struct gpio_desc *gpiod = chip->reset;
1922
1923 /* If there is a GPIO connected to the reset pin, toggle it */
1924 if (gpiod) {
1925 gpiod_set_value_cansleep(gpiod, 1);
1926 usleep_range(10000, 20000);
1927 gpiod_set_value_cansleep(gpiod, 0);
1928 usleep_range(10000, 20000);
1929 }
1930 }
1931
1932 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1933 {
1934 int i, err;
1935
1936 /* Set all ports to the Disabled state */
1937 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1938 err = mv88e6xxx_port_set_state(chip, i,
1939 PORT_CONTROL_STATE_DISABLED);
1940 if (err)
1941 return err;
1942 }
1943
1944 /* Wait for transmit queues to drain,
1945 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1946 */
1947 usleep_range(2000, 4000);
1948
1949 return 0;
1950 }
1951
1952 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1953 {
1954 int err;
1955
1956 err = mv88e6xxx_disable_ports(chip);
1957 if (err)
1958 return err;
1959
1960 mv88e6xxx_hardware_reset(chip);
1961
1962 return mv88e6xxx_software_reset(chip);
1963 }
1964
1965 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
1966 {
1967 u16 val;
1968 int err;
1969
1970 /* Clear Power Down bit */
1971 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
1972 if (err)
1973 return err;
1974
1975 if (val & BMCR_PDOWN) {
1976 val &= ~BMCR_PDOWN;
1977 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
1978 }
1979
1980 return err;
1981 }
1982
1983 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1984 enum mv88e6xxx_frame_mode frame, u16 egress,
1985 u16 etype)
1986 {
1987 int err;
1988
1989 if (!chip->info->ops->port_set_frame_mode)
1990 return -EOPNOTSUPP;
1991
1992 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1993 if (err)
1994 return err;
1995
1996 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1997 if (err)
1998 return err;
1999
2000 if (chip->info->ops->port_set_ether_type)
2001 return chip->info->ops->port_set_ether_type(chip, port, etype);
2002
2003 return 0;
2004 }
2005
2006 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2007 {
2008 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2009 PORT_CONTROL_EGRESS_UNMODIFIED,
2010 PORT_ETH_TYPE_DEFAULT);
2011 }
2012
2013 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2014 {
2015 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2016 PORT_CONTROL_EGRESS_UNMODIFIED,
2017 PORT_ETH_TYPE_DEFAULT);
2018 }
2019
2020 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2021 {
2022 return mv88e6xxx_set_port_mode(chip, port,
2023 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2024 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2025 }
2026
2027 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2028 {
2029 if (dsa_is_dsa_port(chip->ds, port))
2030 return mv88e6xxx_set_port_mode_dsa(chip, port);
2031
2032 if (dsa_is_normal_port(chip->ds, port))
2033 return mv88e6xxx_set_port_mode_normal(chip, port);
2034
2035 /* Setup CPU port mode depending on its supported tag format */
2036 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2037 return mv88e6xxx_set_port_mode_dsa(chip, port);
2038
2039 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2040 return mv88e6xxx_set_port_mode_edsa(chip, port);
2041
2042 return -EINVAL;
2043 }
2044
2045 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2046 {
2047 bool message = dsa_is_dsa_port(chip->ds, port);
2048
2049 return mv88e6xxx_port_set_message_port(chip, port, message);
2050 }
2051
2052 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2053 {
2054 bool flood = port == dsa_upstream_port(chip->ds);
2055
2056 /* Upstream ports flood frames with unknown unicast or multicast DA */
2057 if (chip->info->ops->port_set_egress_floods)
2058 return chip->info->ops->port_set_egress_floods(chip, port,
2059 flood, flood);
2060
2061 return 0;
2062 }
2063
2064 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2065 {
2066 struct dsa_switch *ds = chip->ds;
2067 int err;
2068 u16 reg;
2069
2070 /* MAC Forcing register: don't force link, speed, duplex or flow control
2071 * state to any particular values on physical ports, but force the CPU
2072 * port and all DSA ports to their maximum bandwidth and full duplex.
2073 */
2074 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2075 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2076 SPEED_MAX, DUPLEX_FULL,
2077 PHY_INTERFACE_MODE_NA);
2078 else
2079 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2080 SPEED_UNFORCED, DUPLEX_UNFORCED,
2081 PHY_INTERFACE_MODE_NA);
2082 if (err)
2083 return err;
2084
2085 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2086 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2087 * tunneling, determine priority by looking at 802.1p and IP
2088 * priority fields (IP prio has precedence), and set STP state
2089 * to Forwarding.
2090 *
2091 * If this is the CPU link, use DSA or EDSA tagging depending
2092 * on which tagging mode was configured.
2093 *
2094 * If this is a link to another switch, use DSA tagging mode.
2095 *
2096 * If this is the upstream port for this switch, enable
2097 * forwarding of unknown unicasts and multicasts.
2098 */
2099 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2100 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2101 PORT_CONTROL_STATE_FORWARDING;
2102 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2103 if (err)
2104 return err;
2105
2106 err = mv88e6xxx_setup_port_mode(chip, port);
2107 if (err)
2108 return err;
2109
2110 err = mv88e6xxx_setup_egress_floods(chip, port);
2111 if (err)
2112 return err;
2113
2114 /* If this port is connected to a SerDes, make sure the SerDes is not
2115 * powered down.
2116 */
2117 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2118 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2119 if (err)
2120 return err;
2121 reg &= PORT_STATUS_CMODE_MASK;
2122 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2123 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2124 (reg == PORT_STATUS_CMODE_SGMII)) {
2125 err = mv88e6xxx_serdes_power_on(chip);
2126 if (err < 0)
2127 return err;
2128 }
2129 }
2130
2131 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2132 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2133 * untagged frames on this port, do a destination address lookup on all
2134 * received packets as usual, disable ARP mirroring and don't send a
2135 * copy of all transmitted/received frames on this port to the CPU.
2136 */
2137 err = mv88e6xxx_port_set_map_da(chip, port);
2138 if (err)
2139 return err;
2140
2141 reg = 0;
2142 if (chip->info->ops->port_set_upstream_port) {
2143 err = chip->info->ops->port_set_upstream_port(
2144 chip, port, dsa_upstream_port(ds));
2145 if (err)
2146 return err;
2147 }
2148
2149 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2150 PORT_CONTROL_2_8021Q_DISABLED);
2151 if (err)
2152 return err;
2153
2154 if (chip->info->ops->port_jumbo_config) {
2155 err = chip->info->ops->port_jumbo_config(chip, port);
2156 if (err)
2157 return err;
2158 }
2159
2160 /* Port Association Vector: when learning source addresses
2161 * of packets, add the address to the address database using
2162 * a port bitmap that has only the bit for this port set and
2163 * the other bits clear.
2164 */
2165 reg = 1 << port;
2166 /* Disable learning for CPU port */
2167 if (dsa_is_cpu_port(ds, port))
2168 reg = 0;
2169
2170 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2171 if (err)
2172 return err;
2173
2174 /* Egress rate control 2: disable egress rate control. */
2175 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2176 if (err)
2177 return err;
2178
2179 if (chip->info->ops->port_pause_config) {
2180 err = chip->info->ops->port_pause_config(chip, port);
2181 if (err)
2182 return err;
2183 }
2184
2185 if (chip->info->ops->port_disable_learn_limit) {
2186 err = chip->info->ops->port_disable_learn_limit(chip, port);
2187 if (err)
2188 return err;
2189 }
2190
2191 if (chip->info->ops->port_disable_pri_override) {
2192 err = chip->info->ops->port_disable_pri_override(chip, port);
2193 if (err)
2194 return err;
2195 }
2196
2197 if (chip->info->ops->port_tag_remap) {
2198 err = chip->info->ops->port_tag_remap(chip, port);
2199 if (err)
2200 return err;
2201 }
2202
2203 if (chip->info->ops->port_egress_rate_limiting) {
2204 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2205 if (err)
2206 return err;
2207 }
2208
2209 err = mv88e6xxx_setup_message_port(chip, port);
2210 if (err)
2211 return err;
2212
2213 /* Port based VLAN map: give each port the same default address
2214 * database, and allow bidirectional communication between the
2215 * CPU and DSA port(s), and the other ports.
2216 */
2217 err = mv88e6xxx_port_set_fid(chip, port, 0);
2218 if (err)
2219 return err;
2220
2221 err = mv88e6xxx_port_vlan_map(chip, port);
2222 if (err)
2223 return err;
2224
2225 /* Default VLAN ID and priority: don't set a default VLAN
2226 * ID, and set the default packet priority to zero.
2227 */
2228 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2229 }
2230
2231 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2232 {
2233 int err;
2234
2235 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2236 if (err)
2237 return err;
2238
2239 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2240 if (err)
2241 return err;
2242
2243 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2244 if (err)
2245 return err;
2246
2247 return 0;
2248 }
2249
2250 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2251 unsigned int ageing_time)
2252 {
2253 struct mv88e6xxx_chip *chip = ds->priv;
2254 int err;
2255
2256 mutex_lock(&chip->reg_lock);
2257 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2258 mutex_unlock(&chip->reg_lock);
2259
2260 return err;
2261 }
2262
2263 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2264 {
2265 struct dsa_switch *ds = chip->ds;
2266 u32 upstream_port = dsa_upstream_port(ds);
2267 int err;
2268
2269 /* Enable the PHY Polling Unit if present, don't discard any packets,
2270 * and mask all interrupt sources.
2271 */
2272 err = mv88e6xxx_ppu_enable(chip);
2273 if (err)
2274 return err;
2275
2276 if (chip->info->ops->g1_set_cpu_port) {
2277 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2278 if (err)
2279 return err;
2280 }
2281
2282 if (chip->info->ops->g1_set_egress_port) {
2283 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2284 if (err)
2285 return err;
2286 }
2287
2288 /* Disable remote management, and set the switch's DSA device number. */
2289 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2290 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2291 (ds->index & 0x1f));
2292 if (err)
2293 return err;
2294
2295 /* Configure the IP ToS mapping registers. */
2296 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2297 if (err)
2298 return err;
2299 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2300 if (err)
2301 return err;
2302 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2303 if (err)
2304 return err;
2305 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2306 if (err)
2307 return err;
2308 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2309 if (err)
2310 return err;
2311 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2312 if (err)
2313 return err;
2314 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2315 if (err)
2316 return err;
2317 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2318 if (err)
2319 return err;
2320
2321 /* Configure the IEEE 802.1p priority mapping register. */
2322 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2323 if (err)
2324 return err;
2325
2326 /* Initialize the statistics unit */
2327 err = mv88e6xxx_stats_set_histogram(chip);
2328 if (err)
2329 return err;
2330
2331 /* Clear the statistics counters for all ports */
2332 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2333 GLOBAL_STATS_OP_FLUSH_ALL);
2334 if (err)
2335 return err;
2336
2337 /* Wait for the flush to complete. */
2338 err = mv88e6xxx_g1_stats_wait(chip);
2339 if (err)
2340 return err;
2341
2342 return 0;
2343 }
2344
2345 static int mv88e6xxx_setup(struct dsa_switch *ds)
2346 {
2347 struct mv88e6xxx_chip *chip = ds->priv;
2348 int err;
2349 int i;
2350
2351 chip->ds = ds;
2352 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2353
2354 mutex_lock(&chip->reg_lock);
2355
2356 /* Setup Switch Port Registers */
2357 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2358 err = mv88e6xxx_setup_port(chip, i);
2359 if (err)
2360 goto unlock;
2361 }
2362
2363 /* Setup Switch Global 1 Registers */
2364 err = mv88e6xxx_g1_setup(chip);
2365 if (err)
2366 goto unlock;
2367
2368 /* Setup Switch Global 2 Registers */
2369 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2370 err = mv88e6xxx_g2_setup(chip);
2371 if (err)
2372 goto unlock;
2373 }
2374
2375 err = mv88e6xxx_vtu_setup(chip);
2376 if (err)
2377 goto unlock;
2378
2379 err = mv88e6xxx_pvt_setup(chip);
2380 if (err)
2381 goto unlock;
2382
2383 err = mv88e6xxx_atu_setup(chip);
2384 if (err)
2385 goto unlock;
2386
2387 /* Some generations have the configuration of sending reserved
2388 * management frames to the CPU in global2, others in
2389 * global1. Hence it does not fit the two setup functions
2390 * above.
2391 */
2392 if (chip->info->ops->mgmt_rsvd2cpu) {
2393 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2394 if (err)
2395 goto unlock;
2396 }
2397
2398 unlock:
2399 mutex_unlock(&chip->reg_lock);
2400
2401 return err;
2402 }
2403
2404 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2405 {
2406 struct mv88e6xxx_chip *chip = ds->priv;
2407 int err;
2408
2409 if (!chip->info->ops->set_switch_mac)
2410 return -EOPNOTSUPP;
2411
2412 mutex_lock(&chip->reg_lock);
2413 err = chip->info->ops->set_switch_mac(chip, addr);
2414 mutex_unlock(&chip->reg_lock);
2415
2416 return err;
2417 }
2418
2419 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2420 {
2421 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2422 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2423 u16 val;
2424 int err;
2425
2426 if (!chip->info->ops->phy_read)
2427 return -EOPNOTSUPP;
2428
2429 mutex_lock(&chip->reg_lock);
2430 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2431 mutex_unlock(&chip->reg_lock);
2432
2433 if (reg == MII_PHYSID2) {
2434 /* Some internal PHYS don't have a model number. Use
2435 * the mv88e6390 family model number instead.
2436 */
2437 if (!(val & 0x3f0))
2438 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2439 }
2440
2441 return err ? err : val;
2442 }
2443
2444 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2445 {
2446 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2447 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2448 int err;
2449
2450 if (!chip->info->ops->phy_write)
2451 return -EOPNOTSUPP;
2452
2453 mutex_lock(&chip->reg_lock);
2454 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2455 mutex_unlock(&chip->reg_lock);
2456
2457 return err;
2458 }
2459
2460 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2461 struct device_node *np,
2462 bool external)
2463 {
2464 static int index;
2465 struct mv88e6xxx_mdio_bus *mdio_bus;
2466 struct mii_bus *bus;
2467 int err;
2468
2469 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2470 if (!bus)
2471 return -ENOMEM;
2472
2473 mdio_bus = bus->priv;
2474 mdio_bus->bus = bus;
2475 mdio_bus->chip = chip;
2476 INIT_LIST_HEAD(&mdio_bus->list);
2477 mdio_bus->external = external;
2478
2479 if (np) {
2480 bus->name = np->full_name;
2481 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2482 } else {
2483 bus->name = "mv88e6xxx SMI";
2484 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2485 }
2486
2487 bus->read = mv88e6xxx_mdio_read;
2488 bus->write = mv88e6xxx_mdio_write;
2489 bus->parent = chip->dev;
2490
2491 if (np)
2492 err = of_mdiobus_register(bus, np);
2493 else
2494 err = mdiobus_register(bus);
2495 if (err) {
2496 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2497 return err;
2498 }
2499
2500 if (external)
2501 list_add_tail(&mdio_bus->list, &chip->mdios);
2502 else
2503 list_add(&mdio_bus->list, &chip->mdios);
2504
2505 return 0;
2506 }
2507
2508 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2509 { .compatible = "marvell,mv88e6xxx-mdio-external",
2510 .data = (void *)true },
2511 { },
2512 };
2513
2514 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2515 struct device_node *np)
2516 {
2517 const struct of_device_id *match;
2518 struct device_node *child;
2519 int err;
2520
2521 /* Always register one mdio bus for the internal/default mdio
2522 * bus. This maybe represented in the device tree, but is
2523 * optional.
2524 */
2525 child = of_get_child_by_name(np, "mdio");
2526 err = mv88e6xxx_mdio_register(chip, child, false);
2527 if (err)
2528 return err;
2529
2530 /* Walk the device tree, and see if there are any other nodes
2531 * which say they are compatible with the external mdio
2532 * bus.
2533 */
2534 for_each_available_child_of_node(np, child) {
2535 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2536 if (match) {
2537 err = mv88e6xxx_mdio_register(chip, child, true);
2538 if (err)
2539 return err;
2540 }
2541 }
2542
2543 return 0;
2544 }
2545
2546 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2547
2548 {
2549 struct mv88e6xxx_mdio_bus *mdio_bus;
2550 struct mii_bus *bus;
2551
2552 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2553 bus = mdio_bus->bus;
2554
2555 mdiobus_unregister(bus);
2556 }
2557 }
2558
2559 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2560 {
2561 struct mv88e6xxx_chip *chip = ds->priv;
2562
2563 return chip->eeprom_len;
2564 }
2565
2566 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2567 struct ethtool_eeprom *eeprom, u8 *data)
2568 {
2569 struct mv88e6xxx_chip *chip = ds->priv;
2570 int err;
2571
2572 if (!chip->info->ops->get_eeprom)
2573 return -EOPNOTSUPP;
2574
2575 mutex_lock(&chip->reg_lock);
2576 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2577 mutex_unlock(&chip->reg_lock);
2578
2579 if (err)
2580 return err;
2581
2582 eeprom->magic = 0xc3ec4951;
2583
2584 return 0;
2585 }
2586
2587 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2588 struct ethtool_eeprom *eeprom, u8 *data)
2589 {
2590 struct mv88e6xxx_chip *chip = ds->priv;
2591 int err;
2592
2593 if (!chip->info->ops->set_eeprom)
2594 return -EOPNOTSUPP;
2595
2596 if (eeprom->magic != 0xc3ec4951)
2597 return -EINVAL;
2598
2599 mutex_lock(&chip->reg_lock);
2600 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2601 mutex_unlock(&chip->reg_lock);
2602
2603 return err;
2604 }
2605
2606 static const struct mv88e6xxx_ops mv88e6085_ops = {
2607 /* MV88E6XXX_FAMILY_6097 */
2608 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2609 .phy_read = mv88e6xxx_phy_ppu_read,
2610 .phy_write = mv88e6xxx_phy_ppu_write,
2611 .port_set_link = mv88e6xxx_port_set_link,
2612 .port_set_duplex = mv88e6xxx_port_set_duplex,
2613 .port_set_speed = mv88e6185_port_set_speed,
2614 .port_tag_remap = mv88e6095_port_tag_remap,
2615 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2616 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2617 .port_set_ether_type = mv88e6351_port_set_ether_type,
2618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2619 .port_pause_config = mv88e6097_port_pause_config,
2620 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2621 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2622 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2623 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2624 .stats_get_strings = mv88e6095_stats_get_strings,
2625 .stats_get_stats = mv88e6095_stats_get_stats,
2626 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2627 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2628 .watchdog_ops = &mv88e6097_watchdog_ops,
2629 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2630 .ppu_enable = mv88e6185_g1_ppu_enable,
2631 .ppu_disable = mv88e6185_g1_ppu_disable,
2632 .reset = mv88e6185_g1_reset,
2633 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2634 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2635 };
2636
2637 static const struct mv88e6xxx_ops mv88e6095_ops = {
2638 /* MV88E6XXX_FAMILY_6095 */
2639 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2640 .phy_read = mv88e6xxx_phy_ppu_read,
2641 .phy_write = mv88e6xxx_phy_ppu_write,
2642 .port_set_link = mv88e6xxx_port_set_link,
2643 .port_set_duplex = mv88e6xxx_port_set_duplex,
2644 .port_set_speed = mv88e6185_port_set_speed,
2645 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2646 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2647 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2648 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2649 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2650 .stats_get_strings = mv88e6095_stats_get_strings,
2651 .stats_get_stats = mv88e6095_stats_get_stats,
2652 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2653 .ppu_enable = mv88e6185_g1_ppu_enable,
2654 .ppu_disable = mv88e6185_g1_ppu_disable,
2655 .reset = mv88e6185_g1_reset,
2656 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2657 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2658 };
2659
2660 static const struct mv88e6xxx_ops mv88e6097_ops = {
2661 /* MV88E6XXX_FAMILY_6097 */
2662 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2663 .phy_read = mv88e6xxx_g2_smi_phy_read,
2664 .phy_write = mv88e6xxx_g2_smi_phy_write,
2665 .port_set_link = mv88e6xxx_port_set_link,
2666 .port_set_duplex = mv88e6xxx_port_set_duplex,
2667 .port_set_speed = mv88e6185_port_set_speed,
2668 .port_tag_remap = mv88e6095_port_tag_remap,
2669 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2670 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2671 .port_set_ether_type = mv88e6351_port_set_ether_type,
2672 .port_jumbo_config = mv88e6165_port_jumbo_config,
2673 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2674 .port_pause_config = mv88e6097_port_pause_config,
2675 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2676 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2677 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2678 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2679 .stats_get_strings = mv88e6095_stats_get_strings,
2680 .stats_get_stats = mv88e6095_stats_get_stats,
2681 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2682 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2683 .watchdog_ops = &mv88e6097_watchdog_ops,
2684 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2685 .reset = mv88e6352_g1_reset,
2686 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2687 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2688 };
2689
2690 static const struct mv88e6xxx_ops mv88e6123_ops = {
2691 /* MV88E6XXX_FAMILY_6165 */
2692 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2693 .phy_read = mv88e6165_phy_read,
2694 .phy_write = mv88e6165_phy_write,
2695 .port_set_link = mv88e6xxx_port_set_link,
2696 .port_set_duplex = mv88e6xxx_port_set_duplex,
2697 .port_set_speed = mv88e6185_port_set_speed,
2698 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2699 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2700 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2701 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2702 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2703 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2704 .stats_get_strings = mv88e6095_stats_get_strings,
2705 .stats_get_stats = mv88e6095_stats_get_stats,
2706 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2707 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2708 .watchdog_ops = &mv88e6097_watchdog_ops,
2709 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2710 .reset = mv88e6352_g1_reset,
2711 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2713 };
2714
2715 static const struct mv88e6xxx_ops mv88e6131_ops = {
2716 /* MV88E6XXX_FAMILY_6185 */
2717 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2718 .phy_read = mv88e6xxx_phy_ppu_read,
2719 .phy_write = mv88e6xxx_phy_ppu_write,
2720 .port_set_link = mv88e6xxx_port_set_link,
2721 .port_set_duplex = mv88e6xxx_port_set_duplex,
2722 .port_set_speed = mv88e6185_port_set_speed,
2723 .port_tag_remap = mv88e6095_port_tag_remap,
2724 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2725 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2726 .port_set_ether_type = mv88e6351_port_set_ether_type,
2727 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2728 .port_jumbo_config = mv88e6165_port_jumbo_config,
2729 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2730 .port_pause_config = mv88e6097_port_pause_config,
2731 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2732 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2733 .stats_get_strings = mv88e6095_stats_get_strings,
2734 .stats_get_stats = mv88e6095_stats_get_stats,
2735 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2736 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2737 .watchdog_ops = &mv88e6097_watchdog_ops,
2738 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2739 .ppu_enable = mv88e6185_g1_ppu_enable,
2740 .ppu_disable = mv88e6185_g1_ppu_disable,
2741 .reset = mv88e6185_g1_reset,
2742 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2743 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2744 };
2745
2746 static const struct mv88e6xxx_ops mv88e6141_ops = {
2747 /* MV88E6XXX_FAMILY_6341 */
2748 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2749 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2750 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2751 .phy_read = mv88e6xxx_g2_smi_phy_read,
2752 .phy_write = mv88e6xxx_g2_smi_phy_write,
2753 .port_set_link = mv88e6xxx_port_set_link,
2754 .port_set_duplex = mv88e6xxx_port_set_duplex,
2755 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2756 .port_set_speed = mv88e6390_port_set_speed,
2757 .port_tag_remap = mv88e6095_port_tag_remap,
2758 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2759 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2760 .port_set_ether_type = mv88e6351_port_set_ether_type,
2761 .port_jumbo_config = mv88e6165_port_jumbo_config,
2762 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2763 .port_pause_config = mv88e6097_port_pause_config,
2764 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2765 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2766 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2767 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2768 .stats_get_strings = mv88e6320_stats_get_strings,
2769 .stats_get_stats = mv88e6390_stats_get_stats,
2770 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
2771 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
2772 .watchdog_ops = &mv88e6390_watchdog_ops,
2773 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2774 .reset = mv88e6352_g1_reset,
2775 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2776 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2777 };
2778
2779 static const struct mv88e6xxx_ops mv88e6161_ops = {
2780 /* MV88E6XXX_FAMILY_6165 */
2781 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2782 .phy_read = mv88e6165_phy_read,
2783 .phy_write = mv88e6165_phy_write,
2784 .port_set_link = mv88e6xxx_port_set_link,
2785 .port_set_duplex = mv88e6xxx_port_set_duplex,
2786 .port_set_speed = mv88e6185_port_set_speed,
2787 .port_tag_remap = mv88e6095_port_tag_remap,
2788 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2789 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2790 .port_set_ether_type = mv88e6351_port_set_ether_type,
2791 .port_jumbo_config = mv88e6165_port_jumbo_config,
2792 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2793 .port_pause_config = mv88e6097_port_pause_config,
2794 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2795 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2796 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2797 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2798 .stats_get_strings = mv88e6095_stats_get_strings,
2799 .stats_get_stats = mv88e6095_stats_get_stats,
2800 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2801 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2802 .watchdog_ops = &mv88e6097_watchdog_ops,
2803 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2804 .reset = mv88e6352_g1_reset,
2805 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2806 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2807 };
2808
2809 static const struct mv88e6xxx_ops mv88e6165_ops = {
2810 /* MV88E6XXX_FAMILY_6165 */
2811 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2812 .phy_read = mv88e6165_phy_read,
2813 .phy_write = mv88e6165_phy_write,
2814 .port_set_link = mv88e6xxx_port_set_link,
2815 .port_set_duplex = mv88e6xxx_port_set_duplex,
2816 .port_set_speed = mv88e6185_port_set_speed,
2817 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2818 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2819 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2820 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2821 .stats_get_strings = mv88e6095_stats_get_strings,
2822 .stats_get_stats = mv88e6095_stats_get_stats,
2823 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2824 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2825 .watchdog_ops = &mv88e6097_watchdog_ops,
2826 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2827 .reset = mv88e6352_g1_reset,
2828 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2829 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2830 };
2831
2832 static const struct mv88e6xxx_ops mv88e6171_ops = {
2833 /* MV88E6XXX_FAMILY_6351 */
2834 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2835 .phy_read = mv88e6xxx_g2_smi_phy_read,
2836 .phy_write = mv88e6xxx_g2_smi_phy_write,
2837 .port_set_link = mv88e6xxx_port_set_link,
2838 .port_set_duplex = mv88e6xxx_port_set_duplex,
2839 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2840 .port_set_speed = mv88e6185_port_set_speed,
2841 .port_tag_remap = mv88e6095_port_tag_remap,
2842 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2843 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2844 .port_set_ether_type = mv88e6351_port_set_ether_type,
2845 .port_jumbo_config = mv88e6165_port_jumbo_config,
2846 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2847 .port_pause_config = mv88e6097_port_pause_config,
2848 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2849 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2850 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2851 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2852 .stats_get_strings = mv88e6095_stats_get_strings,
2853 .stats_get_stats = mv88e6095_stats_get_stats,
2854 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2855 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2856 .watchdog_ops = &mv88e6097_watchdog_ops,
2857 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2858 .reset = mv88e6352_g1_reset,
2859 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2860 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2861 };
2862
2863 static const struct mv88e6xxx_ops mv88e6172_ops = {
2864 /* MV88E6XXX_FAMILY_6352 */
2865 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2866 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2867 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2868 .phy_read = mv88e6xxx_g2_smi_phy_read,
2869 .phy_write = mv88e6xxx_g2_smi_phy_write,
2870 .port_set_link = mv88e6xxx_port_set_link,
2871 .port_set_duplex = mv88e6xxx_port_set_duplex,
2872 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2873 .port_set_speed = mv88e6352_port_set_speed,
2874 .port_tag_remap = mv88e6095_port_tag_remap,
2875 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2876 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2877 .port_set_ether_type = mv88e6351_port_set_ether_type,
2878 .port_jumbo_config = mv88e6165_port_jumbo_config,
2879 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2880 .port_pause_config = mv88e6097_port_pause_config,
2881 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2882 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2883 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2884 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2885 .stats_get_strings = mv88e6095_stats_get_strings,
2886 .stats_get_stats = mv88e6095_stats_get_stats,
2887 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2888 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2889 .watchdog_ops = &mv88e6097_watchdog_ops,
2890 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2891 .reset = mv88e6352_g1_reset,
2892 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2893 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2894 };
2895
2896 static const struct mv88e6xxx_ops mv88e6175_ops = {
2897 /* MV88E6XXX_FAMILY_6351 */
2898 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2899 .phy_read = mv88e6xxx_g2_smi_phy_read,
2900 .phy_write = mv88e6xxx_g2_smi_phy_write,
2901 .port_set_link = mv88e6xxx_port_set_link,
2902 .port_set_duplex = mv88e6xxx_port_set_duplex,
2903 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2904 .port_set_speed = mv88e6185_port_set_speed,
2905 .port_tag_remap = mv88e6095_port_tag_remap,
2906 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2907 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2908 .port_set_ether_type = mv88e6351_port_set_ether_type,
2909 .port_jumbo_config = mv88e6165_port_jumbo_config,
2910 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2911 .port_pause_config = mv88e6097_port_pause_config,
2912 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2913 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2914 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2915 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2916 .stats_get_strings = mv88e6095_stats_get_strings,
2917 .stats_get_stats = mv88e6095_stats_get_stats,
2918 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2919 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2920 .watchdog_ops = &mv88e6097_watchdog_ops,
2921 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2922 .reset = mv88e6352_g1_reset,
2923 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2925 };
2926
2927 static const struct mv88e6xxx_ops mv88e6176_ops = {
2928 /* MV88E6XXX_FAMILY_6352 */
2929 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2930 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2931 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2932 .phy_read = mv88e6xxx_g2_smi_phy_read,
2933 .phy_write = mv88e6xxx_g2_smi_phy_write,
2934 .port_set_link = mv88e6xxx_port_set_link,
2935 .port_set_duplex = mv88e6xxx_port_set_duplex,
2936 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2937 .port_set_speed = mv88e6352_port_set_speed,
2938 .port_tag_remap = mv88e6095_port_tag_remap,
2939 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2940 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2941 .port_set_ether_type = mv88e6351_port_set_ether_type,
2942 .port_jumbo_config = mv88e6165_port_jumbo_config,
2943 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2944 .port_pause_config = mv88e6097_port_pause_config,
2945 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2946 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2947 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2948 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2949 .stats_get_strings = mv88e6095_stats_get_strings,
2950 .stats_get_stats = mv88e6095_stats_get_stats,
2951 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2952 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2953 .watchdog_ops = &mv88e6097_watchdog_ops,
2954 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2955 .reset = mv88e6352_g1_reset,
2956 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2957 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2958 };
2959
2960 static const struct mv88e6xxx_ops mv88e6185_ops = {
2961 /* MV88E6XXX_FAMILY_6185 */
2962 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2963 .phy_read = mv88e6xxx_phy_ppu_read,
2964 .phy_write = mv88e6xxx_phy_ppu_write,
2965 .port_set_link = mv88e6xxx_port_set_link,
2966 .port_set_duplex = mv88e6xxx_port_set_duplex,
2967 .port_set_speed = mv88e6185_port_set_speed,
2968 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2969 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2970 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2971 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2972 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2973 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2974 .stats_get_strings = mv88e6095_stats_get_strings,
2975 .stats_get_stats = mv88e6095_stats_get_stats,
2976 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2977 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2978 .watchdog_ops = &mv88e6097_watchdog_ops,
2979 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2980 .ppu_enable = mv88e6185_g1_ppu_enable,
2981 .ppu_disable = mv88e6185_g1_ppu_disable,
2982 .reset = mv88e6185_g1_reset,
2983 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2984 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2985 };
2986
2987 static const struct mv88e6xxx_ops mv88e6190_ops = {
2988 /* MV88E6XXX_FAMILY_6390 */
2989 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2990 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2991 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2992 .phy_read = mv88e6xxx_g2_smi_phy_read,
2993 .phy_write = mv88e6xxx_g2_smi_phy_write,
2994 .port_set_link = mv88e6xxx_port_set_link,
2995 .port_set_duplex = mv88e6xxx_port_set_duplex,
2996 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2997 .port_set_speed = mv88e6390_port_set_speed,
2998 .port_tag_remap = mv88e6390_port_tag_remap,
2999 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3000 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3001 .port_set_ether_type = mv88e6351_port_set_ether_type,
3002 .port_pause_config = mv88e6390_port_pause_config,
3003 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3004 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3005 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3006 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3007 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3008 .stats_get_strings = mv88e6320_stats_get_strings,
3009 .stats_get_stats = mv88e6390_stats_get_stats,
3010 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3011 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3012 .watchdog_ops = &mv88e6390_watchdog_ops,
3013 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3014 .reset = mv88e6352_g1_reset,
3015 };
3016
3017 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3018 /* MV88E6XXX_FAMILY_6390 */
3019 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3020 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3021 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3022 .phy_read = mv88e6xxx_g2_smi_phy_read,
3023 .phy_write = mv88e6xxx_g2_smi_phy_write,
3024 .port_set_link = mv88e6xxx_port_set_link,
3025 .port_set_duplex = mv88e6xxx_port_set_duplex,
3026 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3027 .port_set_speed = mv88e6390x_port_set_speed,
3028 .port_tag_remap = mv88e6390_port_tag_remap,
3029 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3030 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3031 .port_set_ether_type = mv88e6351_port_set_ether_type,
3032 .port_pause_config = mv88e6390_port_pause_config,
3033 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3034 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3035 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3036 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3037 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3038 .stats_get_strings = mv88e6320_stats_get_strings,
3039 .stats_get_stats = mv88e6390_stats_get_stats,
3040 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3041 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3042 .watchdog_ops = &mv88e6390_watchdog_ops,
3043 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3044 .reset = mv88e6352_g1_reset,
3045 };
3046
3047 static const struct mv88e6xxx_ops mv88e6191_ops = {
3048 /* MV88E6XXX_FAMILY_6390 */
3049 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3050 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3051 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3052 .phy_read = mv88e6xxx_g2_smi_phy_read,
3053 .phy_write = mv88e6xxx_g2_smi_phy_write,
3054 .port_set_link = mv88e6xxx_port_set_link,
3055 .port_set_duplex = mv88e6xxx_port_set_duplex,
3056 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3057 .port_set_speed = mv88e6390_port_set_speed,
3058 .port_tag_remap = mv88e6390_port_tag_remap,
3059 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3060 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3061 .port_set_ether_type = mv88e6351_port_set_ether_type,
3062 .port_pause_config = mv88e6390_port_pause_config,
3063 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3064 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3065 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3066 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3067 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3068 .stats_get_strings = mv88e6320_stats_get_strings,
3069 .stats_get_stats = mv88e6390_stats_get_stats,
3070 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3071 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3072 .watchdog_ops = &mv88e6390_watchdog_ops,
3073 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3074 .reset = mv88e6352_g1_reset,
3075 };
3076
3077 static const struct mv88e6xxx_ops mv88e6240_ops = {
3078 /* MV88E6XXX_FAMILY_6352 */
3079 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3080 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3081 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3082 .phy_read = mv88e6xxx_g2_smi_phy_read,
3083 .phy_write = mv88e6xxx_g2_smi_phy_write,
3084 .port_set_link = mv88e6xxx_port_set_link,
3085 .port_set_duplex = mv88e6xxx_port_set_duplex,
3086 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3087 .port_set_speed = mv88e6352_port_set_speed,
3088 .port_tag_remap = mv88e6095_port_tag_remap,
3089 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3090 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3091 .port_set_ether_type = mv88e6351_port_set_ether_type,
3092 .port_jumbo_config = mv88e6165_port_jumbo_config,
3093 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3094 .port_pause_config = mv88e6097_port_pause_config,
3095 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3096 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3097 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3098 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3099 .stats_get_strings = mv88e6095_stats_get_strings,
3100 .stats_get_stats = mv88e6095_stats_get_stats,
3101 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3102 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3103 .watchdog_ops = &mv88e6097_watchdog_ops,
3104 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3105 .reset = mv88e6352_g1_reset,
3106 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3107 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3108 };
3109
3110 static const struct mv88e6xxx_ops mv88e6290_ops = {
3111 /* MV88E6XXX_FAMILY_6390 */
3112 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3113 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3114 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3115 .phy_read = mv88e6xxx_g2_smi_phy_read,
3116 .phy_write = mv88e6xxx_g2_smi_phy_write,
3117 .port_set_link = mv88e6xxx_port_set_link,
3118 .port_set_duplex = mv88e6xxx_port_set_duplex,
3119 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3120 .port_set_speed = mv88e6390_port_set_speed,
3121 .port_tag_remap = mv88e6390_port_tag_remap,
3122 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3123 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3124 .port_set_ether_type = mv88e6351_port_set_ether_type,
3125 .port_pause_config = mv88e6390_port_pause_config,
3126 .port_set_cmode = mv88e6390x_port_set_cmode,
3127 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3128 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3129 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3130 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3131 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3132 .stats_get_strings = mv88e6320_stats_get_strings,
3133 .stats_get_stats = mv88e6390_stats_get_stats,
3134 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3135 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3136 .watchdog_ops = &mv88e6390_watchdog_ops,
3137 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3138 .reset = mv88e6352_g1_reset,
3139 };
3140
3141 static const struct mv88e6xxx_ops mv88e6320_ops = {
3142 /* MV88E6XXX_FAMILY_6320 */
3143 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3144 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3145 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3146 .phy_read = mv88e6xxx_g2_smi_phy_read,
3147 .phy_write = mv88e6xxx_g2_smi_phy_write,
3148 .port_set_link = mv88e6xxx_port_set_link,
3149 .port_set_duplex = mv88e6xxx_port_set_duplex,
3150 .port_set_speed = mv88e6185_port_set_speed,
3151 .port_tag_remap = mv88e6095_port_tag_remap,
3152 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3153 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3154 .port_set_ether_type = mv88e6351_port_set_ether_type,
3155 .port_jumbo_config = mv88e6165_port_jumbo_config,
3156 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3157 .port_pause_config = mv88e6097_port_pause_config,
3158 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3159 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3160 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3161 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3162 .stats_get_strings = mv88e6320_stats_get_strings,
3163 .stats_get_stats = mv88e6320_stats_get_stats,
3164 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3165 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3166 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3167 .reset = mv88e6352_g1_reset,
3168 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3169 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3170 };
3171
3172 static const struct mv88e6xxx_ops mv88e6321_ops = {
3173 /* MV88E6XXX_FAMILY_6321 */
3174 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3175 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3176 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3177 .phy_read = mv88e6xxx_g2_smi_phy_read,
3178 .phy_write = mv88e6xxx_g2_smi_phy_write,
3179 .port_set_link = mv88e6xxx_port_set_link,
3180 .port_set_duplex = mv88e6xxx_port_set_duplex,
3181 .port_set_speed = mv88e6185_port_set_speed,
3182 .port_tag_remap = mv88e6095_port_tag_remap,
3183 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3184 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3185 .port_set_ether_type = mv88e6351_port_set_ether_type,
3186 .port_jumbo_config = mv88e6165_port_jumbo_config,
3187 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3188 .port_pause_config = mv88e6097_port_pause_config,
3189 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3190 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3191 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3192 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3193 .stats_get_strings = mv88e6320_stats_get_strings,
3194 .stats_get_stats = mv88e6320_stats_get_stats,
3195 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3196 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3197 .reset = mv88e6352_g1_reset,
3198 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3199 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3200 };
3201
3202 static const struct mv88e6xxx_ops mv88e6341_ops = {
3203 /* MV88E6XXX_FAMILY_6341 */
3204 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3205 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3207 .phy_read = mv88e6xxx_g2_smi_phy_read,
3208 .phy_write = mv88e6xxx_g2_smi_phy_write,
3209 .port_set_link = mv88e6xxx_port_set_link,
3210 .port_set_duplex = mv88e6xxx_port_set_duplex,
3211 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3212 .port_set_speed = mv88e6390_port_set_speed,
3213 .port_tag_remap = mv88e6095_port_tag_remap,
3214 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3215 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3216 .port_set_ether_type = mv88e6351_port_set_ether_type,
3217 .port_jumbo_config = mv88e6165_port_jumbo_config,
3218 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3219 .port_pause_config = mv88e6097_port_pause_config,
3220 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3222 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3223 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3224 .stats_get_strings = mv88e6320_stats_get_strings,
3225 .stats_get_stats = mv88e6390_stats_get_stats,
3226 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3227 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3228 .watchdog_ops = &mv88e6390_watchdog_ops,
3229 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3230 .reset = mv88e6352_g1_reset,
3231 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3232 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3233 };
3234
3235 static const struct mv88e6xxx_ops mv88e6350_ops = {
3236 /* MV88E6XXX_FAMILY_6351 */
3237 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3238 .phy_read = mv88e6xxx_g2_smi_phy_read,
3239 .phy_write = mv88e6xxx_g2_smi_phy_write,
3240 .port_set_link = mv88e6xxx_port_set_link,
3241 .port_set_duplex = mv88e6xxx_port_set_duplex,
3242 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3243 .port_set_speed = mv88e6185_port_set_speed,
3244 .port_tag_remap = mv88e6095_port_tag_remap,
3245 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3246 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3247 .port_set_ether_type = mv88e6351_port_set_ether_type,
3248 .port_jumbo_config = mv88e6165_port_jumbo_config,
3249 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3250 .port_pause_config = mv88e6097_port_pause_config,
3251 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3252 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3253 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3254 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3255 .stats_get_strings = mv88e6095_stats_get_strings,
3256 .stats_get_stats = mv88e6095_stats_get_stats,
3257 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3258 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3259 .watchdog_ops = &mv88e6097_watchdog_ops,
3260 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3261 .reset = mv88e6352_g1_reset,
3262 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3263 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3264 };
3265
3266 static const struct mv88e6xxx_ops mv88e6351_ops = {
3267 /* MV88E6XXX_FAMILY_6351 */
3268 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3269 .phy_read = mv88e6xxx_g2_smi_phy_read,
3270 .phy_write = mv88e6xxx_g2_smi_phy_write,
3271 .port_set_link = mv88e6xxx_port_set_link,
3272 .port_set_duplex = mv88e6xxx_port_set_duplex,
3273 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3274 .port_set_speed = mv88e6185_port_set_speed,
3275 .port_tag_remap = mv88e6095_port_tag_remap,
3276 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3277 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3278 .port_set_ether_type = mv88e6351_port_set_ether_type,
3279 .port_jumbo_config = mv88e6165_port_jumbo_config,
3280 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3281 .port_pause_config = mv88e6097_port_pause_config,
3282 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3283 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3284 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3285 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3286 .stats_get_strings = mv88e6095_stats_get_strings,
3287 .stats_get_stats = mv88e6095_stats_get_stats,
3288 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3289 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3290 .watchdog_ops = &mv88e6097_watchdog_ops,
3291 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3292 .reset = mv88e6352_g1_reset,
3293 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3294 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3295 };
3296
3297 static const struct mv88e6xxx_ops mv88e6352_ops = {
3298 /* MV88E6XXX_FAMILY_6352 */
3299 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3300 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3302 .phy_read = mv88e6xxx_g2_smi_phy_read,
3303 .phy_write = mv88e6xxx_g2_smi_phy_write,
3304 .port_set_link = mv88e6xxx_port_set_link,
3305 .port_set_duplex = mv88e6xxx_port_set_duplex,
3306 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3307 .port_set_speed = mv88e6352_port_set_speed,
3308 .port_tag_remap = mv88e6095_port_tag_remap,
3309 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3310 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3311 .port_set_ether_type = mv88e6351_port_set_ether_type,
3312 .port_jumbo_config = mv88e6165_port_jumbo_config,
3313 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3314 .port_pause_config = mv88e6097_port_pause_config,
3315 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3316 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3317 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3318 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3319 .stats_get_strings = mv88e6095_stats_get_strings,
3320 .stats_get_stats = mv88e6095_stats_get_stats,
3321 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3322 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3323 .watchdog_ops = &mv88e6097_watchdog_ops,
3324 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3325 .reset = mv88e6352_g1_reset,
3326 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3327 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3328 };
3329
3330 static const struct mv88e6xxx_ops mv88e6390_ops = {
3331 /* MV88E6XXX_FAMILY_6390 */
3332 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3333 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3334 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3335 .phy_read = mv88e6xxx_g2_smi_phy_read,
3336 .phy_write = mv88e6xxx_g2_smi_phy_write,
3337 .port_set_link = mv88e6xxx_port_set_link,
3338 .port_set_duplex = mv88e6xxx_port_set_duplex,
3339 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3340 .port_set_speed = mv88e6390_port_set_speed,
3341 .port_tag_remap = mv88e6390_port_tag_remap,
3342 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3343 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3344 .port_set_ether_type = mv88e6351_port_set_ether_type,
3345 .port_jumbo_config = mv88e6165_port_jumbo_config,
3346 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3347 .port_pause_config = mv88e6390_port_pause_config,
3348 .port_set_cmode = mv88e6390x_port_set_cmode,
3349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3351 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3352 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3353 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3354 .stats_get_strings = mv88e6320_stats_get_strings,
3355 .stats_get_stats = mv88e6390_stats_get_stats,
3356 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3357 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3358 .watchdog_ops = &mv88e6390_watchdog_ops,
3359 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3360 .reset = mv88e6352_g1_reset,
3361 };
3362
3363 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3364 /* MV88E6XXX_FAMILY_6390 */
3365 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3366 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3367 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3368 .phy_read = mv88e6xxx_g2_smi_phy_read,
3369 .phy_write = mv88e6xxx_g2_smi_phy_write,
3370 .port_set_link = mv88e6xxx_port_set_link,
3371 .port_set_duplex = mv88e6xxx_port_set_duplex,
3372 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3373 .port_set_speed = mv88e6390x_port_set_speed,
3374 .port_tag_remap = mv88e6390_port_tag_remap,
3375 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3376 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3377 .port_set_ether_type = mv88e6351_port_set_ether_type,
3378 .port_jumbo_config = mv88e6165_port_jumbo_config,
3379 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3380 .port_pause_config = mv88e6390_port_pause_config,
3381 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3382 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3383 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3384 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3385 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3386 .stats_get_strings = mv88e6320_stats_get_strings,
3387 .stats_get_stats = mv88e6390_stats_get_stats,
3388 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3389 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3390 .watchdog_ops = &mv88e6390_watchdog_ops,
3391 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3392 .reset = mv88e6352_g1_reset,
3393 };
3394
3395 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3396 [MV88E6085] = {
3397 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3398 .family = MV88E6XXX_FAMILY_6097,
3399 .name = "Marvell 88E6085",
3400 .num_databases = 4096,
3401 .num_ports = 10,
3402 .max_vid = 4095,
3403 .port_base_addr = 0x10,
3404 .global1_addr = 0x1b,
3405 .age_time_coeff = 15000,
3406 .g1_irqs = 8,
3407 .atu_move_port_mask = 0xf,
3408 .pvt = true,
3409 .tag_protocol = DSA_TAG_PROTO_DSA,
3410 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3411 .ops = &mv88e6085_ops,
3412 },
3413
3414 [MV88E6095] = {
3415 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3416 .family = MV88E6XXX_FAMILY_6095,
3417 .name = "Marvell 88E6095/88E6095F",
3418 .num_databases = 256,
3419 .num_ports = 11,
3420 .max_vid = 4095,
3421 .port_base_addr = 0x10,
3422 .global1_addr = 0x1b,
3423 .age_time_coeff = 15000,
3424 .g1_irqs = 8,
3425 .atu_move_port_mask = 0xf,
3426 .tag_protocol = DSA_TAG_PROTO_DSA,
3427 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3428 .ops = &mv88e6095_ops,
3429 },
3430
3431 [MV88E6097] = {
3432 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3433 .family = MV88E6XXX_FAMILY_6097,
3434 .name = "Marvell 88E6097/88E6097F",
3435 .num_databases = 4096,
3436 .num_ports = 11,
3437 .max_vid = 4095,
3438 .port_base_addr = 0x10,
3439 .global1_addr = 0x1b,
3440 .age_time_coeff = 15000,
3441 .g1_irqs = 8,
3442 .atu_move_port_mask = 0xf,
3443 .pvt = true,
3444 .tag_protocol = DSA_TAG_PROTO_EDSA,
3445 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3446 .ops = &mv88e6097_ops,
3447 },
3448
3449 [MV88E6123] = {
3450 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3451 .family = MV88E6XXX_FAMILY_6165,
3452 .name = "Marvell 88E6123",
3453 .num_databases = 4096,
3454 .num_ports = 3,
3455 .max_vid = 4095,
3456 .port_base_addr = 0x10,
3457 .global1_addr = 0x1b,
3458 .age_time_coeff = 15000,
3459 .g1_irqs = 9,
3460 .atu_move_port_mask = 0xf,
3461 .pvt = true,
3462 .tag_protocol = DSA_TAG_PROTO_DSA,
3463 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3464 .ops = &mv88e6123_ops,
3465 },
3466
3467 [MV88E6131] = {
3468 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3469 .family = MV88E6XXX_FAMILY_6185,
3470 .name = "Marvell 88E6131",
3471 .num_databases = 256,
3472 .num_ports = 8,
3473 .max_vid = 4095,
3474 .port_base_addr = 0x10,
3475 .global1_addr = 0x1b,
3476 .age_time_coeff = 15000,
3477 .g1_irqs = 9,
3478 .atu_move_port_mask = 0xf,
3479 .tag_protocol = DSA_TAG_PROTO_DSA,
3480 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3481 .ops = &mv88e6131_ops,
3482 },
3483
3484 [MV88E6141] = {
3485 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3486 .family = MV88E6XXX_FAMILY_6341,
3487 .name = "Marvell 88E6341",
3488 .num_databases = 4096,
3489 .num_ports = 6,
3490 .max_vid = 4095,
3491 .port_base_addr = 0x10,
3492 .global1_addr = 0x1b,
3493 .age_time_coeff = 3750,
3494 .atu_move_port_mask = 0x1f,
3495 .pvt = true,
3496 .tag_protocol = DSA_TAG_PROTO_EDSA,
3497 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3498 .ops = &mv88e6141_ops,
3499 },
3500
3501 [MV88E6161] = {
3502 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3503 .family = MV88E6XXX_FAMILY_6165,
3504 .name = "Marvell 88E6161",
3505 .num_databases = 4096,
3506 .num_ports = 6,
3507 .max_vid = 4095,
3508 .port_base_addr = 0x10,
3509 .global1_addr = 0x1b,
3510 .age_time_coeff = 15000,
3511 .g1_irqs = 9,
3512 .atu_move_port_mask = 0xf,
3513 .pvt = true,
3514 .tag_protocol = DSA_TAG_PROTO_DSA,
3515 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3516 .ops = &mv88e6161_ops,
3517 },
3518
3519 [MV88E6165] = {
3520 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3521 .family = MV88E6XXX_FAMILY_6165,
3522 .name = "Marvell 88E6165",
3523 .num_databases = 4096,
3524 .num_ports = 6,
3525 .max_vid = 4095,
3526 .port_base_addr = 0x10,
3527 .global1_addr = 0x1b,
3528 .age_time_coeff = 15000,
3529 .g1_irqs = 9,
3530 .atu_move_port_mask = 0xf,
3531 .pvt = true,
3532 .tag_protocol = DSA_TAG_PROTO_DSA,
3533 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3534 .ops = &mv88e6165_ops,
3535 },
3536
3537 [MV88E6171] = {
3538 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3539 .family = MV88E6XXX_FAMILY_6351,
3540 .name = "Marvell 88E6171",
3541 .num_databases = 4096,
3542 .num_ports = 7,
3543 .max_vid = 4095,
3544 .port_base_addr = 0x10,
3545 .global1_addr = 0x1b,
3546 .age_time_coeff = 15000,
3547 .g1_irqs = 9,
3548 .atu_move_port_mask = 0xf,
3549 .pvt = true,
3550 .tag_protocol = DSA_TAG_PROTO_EDSA,
3551 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3552 .ops = &mv88e6171_ops,
3553 },
3554
3555 [MV88E6172] = {
3556 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3557 .family = MV88E6XXX_FAMILY_6352,
3558 .name = "Marvell 88E6172",
3559 .num_databases = 4096,
3560 .num_ports = 7,
3561 .max_vid = 4095,
3562 .port_base_addr = 0x10,
3563 .global1_addr = 0x1b,
3564 .age_time_coeff = 15000,
3565 .g1_irqs = 9,
3566 .atu_move_port_mask = 0xf,
3567 .pvt = true,
3568 .tag_protocol = DSA_TAG_PROTO_EDSA,
3569 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3570 .ops = &mv88e6172_ops,
3571 },
3572
3573 [MV88E6175] = {
3574 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3575 .family = MV88E6XXX_FAMILY_6351,
3576 .name = "Marvell 88E6175",
3577 .num_databases = 4096,
3578 .num_ports = 7,
3579 .max_vid = 4095,
3580 .port_base_addr = 0x10,
3581 .global1_addr = 0x1b,
3582 .age_time_coeff = 15000,
3583 .g1_irqs = 9,
3584 .atu_move_port_mask = 0xf,
3585 .pvt = true,
3586 .tag_protocol = DSA_TAG_PROTO_EDSA,
3587 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3588 .ops = &mv88e6175_ops,
3589 },
3590
3591 [MV88E6176] = {
3592 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3593 .family = MV88E6XXX_FAMILY_6352,
3594 .name = "Marvell 88E6176",
3595 .num_databases = 4096,
3596 .num_ports = 7,
3597 .max_vid = 4095,
3598 .port_base_addr = 0x10,
3599 .global1_addr = 0x1b,
3600 .age_time_coeff = 15000,
3601 .g1_irqs = 9,
3602 .atu_move_port_mask = 0xf,
3603 .pvt = true,
3604 .tag_protocol = DSA_TAG_PROTO_EDSA,
3605 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3606 .ops = &mv88e6176_ops,
3607 },
3608
3609 [MV88E6185] = {
3610 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3611 .family = MV88E6XXX_FAMILY_6185,
3612 .name = "Marvell 88E6185",
3613 .num_databases = 256,
3614 .num_ports = 10,
3615 .max_vid = 4095,
3616 .port_base_addr = 0x10,
3617 .global1_addr = 0x1b,
3618 .age_time_coeff = 15000,
3619 .g1_irqs = 8,
3620 .atu_move_port_mask = 0xf,
3621 .tag_protocol = DSA_TAG_PROTO_EDSA,
3622 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3623 .ops = &mv88e6185_ops,
3624 },
3625
3626 [MV88E6190] = {
3627 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3628 .family = MV88E6XXX_FAMILY_6390,
3629 .name = "Marvell 88E6190",
3630 .num_databases = 4096,
3631 .num_ports = 11, /* 10 + Z80 */
3632 .port_base_addr = 0x0,
3633 .global1_addr = 0x1b,
3634 .tag_protocol = DSA_TAG_PROTO_DSA,
3635 .age_time_coeff = 3750,
3636 .g1_irqs = 9,
3637 .pvt = true,
3638 .atu_move_port_mask = 0x1f,
3639 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3640 .ops = &mv88e6190_ops,
3641 },
3642
3643 [MV88E6190X] = {
3644 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3645 .family = MV88E6XXX_FAMILY_6390,
3646 .name = "Marvell 88E6190X",
3647 .num_databases = 4096,
3648 .num_ports = 11, /* 10 + Z80 */
3649 .port_base_addr = 0x0,
3650 .global1_addr = 0x1b,
3651 .age_time_coeff = 3750,
3652 .g1_irqs = 9,
3653 .atu_move_port_mask = 0x1f,
3654 .pvt = true,
3655 .tag_protocol = DSA_TAG_PROTO_DSA,
3656 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3657 .ops = &mv88e6190x_ops,
3658 },
3659
3660 [MV88E6191] = {
3661 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3662 .family = MV88E6XXX_FAMILY_6390,
3663 .name = "Marvell 88E6191",
3664 .num_databases = 4096,
3665 .num_ports = 11, /* 10 + Z80 */
3666 .port_base_addr = 0x0,
3667 .global1_addr = 0x1b,
3668 .age_time_coeff = 3750,
3669 .g1_irqs = 9,
3670 .atu_move_port_mask = 0x1f,
3671 .pvt = true,
3672 .tag_protocol = DSA_TAG_PROTO_DSA,
3673 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3674 .ops = &mv88e6191_ops,
3675 },
3676
3677 [MV88E6240] = {
3678 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3679 .family = MV88E6XXX_FAMILY_6352,
3680 .name = "Marvell 88E6240",
3681 .num_databases = 4096,
3682 .num_ports = 7,
3683 .max_vid = 4095,
3684 .port_base_addr = 0x10,
3685 .global1_addr = 0x1b,
3686 .age_time_coeff = 15000,
3687 .g1_irqs = 9,
3688 .atu_move_port_mask = 0xf,
3689 .pvt = true,
3690 .tag_protocol = DSA_TAG_PROTO_EDSA,
3691 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3692 .ops = &mv88e6240_ops,
3693 },
3694
3695 [MV88E6290] = {
3696 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3697 .family = MV88E6XXX_FAMILY_6390,
3698 .name = "Marvell 88E6290",
3699 .num_databases = 4096,
3700 .num_ports = 11, /* 10 + Z80 */
3701 .port_base_addr = 0x0,
3702 .global1_addr = 0x1b,
3703 .age_time_coeff = 3750,
3704 .g1_irqs = 9,
3705 .atu_move_port_mask = 0x1f,
3706 .pvt = true,
3707 .tag_protocol = DSA_TAG_PROTO_DSA,
3708 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3709 .ops = &mv88e6290_ops,
3710 },
3711
3712 [MV88E6320] = {
3713 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3714 .family = MV88E6XXX_FAMILY_6320,
3715 .name = "Marvell 88E6320",
3716 .num_databases = 4096,
3717 .num_ports = 7,
3718 .max_vid = 4095,
3719 .port_base_addr = 0x10,
3720 .global1_addr = 0x1b,
3721 .age_time_coeff = 15000,
3722 .g1_irqs = 8,
3723 .atu_move_port_mask = 0xf,
3724 .pvt = true,
3725 .tag_protocol = DSA_TAG_PROTO_EDSA,
3726 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3727 .ops = &mv88e6320_ops,
3728 },
3729
3730 [MV88E6321] = {
3731 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3732 .family = MV88E6XXX_FAMILY_6320,
3733 .name = "Marvell 88E6321",
3734 .num_databases = 4096,
3735 .num_ports = 7,
3736 .max_vid = 4095,
3737 .port_base_addr = 0x10,
3738 .global1_addr = 0x1b,
3739 .age_time_coeff = 15000,
3740 .g1_irqs = 8,
3741 .atu_move_port_mask = 0xf,
3742 .tag_protocol = DSA_TAG_PROTO_EDSA,
3743 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3744 .ops = &mv88e6321_ops,
3745 },
3746
3747 [MV88E6341] = {
3748 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3749 .family = MV88E6XXX_FAMILY_6341,
3750 .name = "Marvell 88E6341",
3751 .num_databases = 4096,
3752 .num_ports = 6,
3753 .max_vid = 4095,
3754 .port_base_addr = 0x10,
3755 .global1_addr = 0x1b,
3756 .age_time_coeff = 3750,
3757 .atu_move_port_mask = 0x1f,
3758 .pvt = true,
3759 .tag_protocol = DSA_TAG_PROTO_EDSA,
3760 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3761 .ops = &mv88e6341_ops,
3762 },
3763
3764 [MV88E6350] = {
3765 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3766 .family = MV88E6XXX_FAMILY_6351,
3767 .name = "Marvell 88E6350",
3768 .num_databases = 4096,
3769 .num_ports = 7,
3770 .max_vid = 4095,
3771 .port_base_addr = 0x10,
3772 .global1_addr = 0x1b,
3773 .age_time_coeff = 15000,
3774 .g1_irqs = 9,
3775 .atu_move_port_mask = 0xf,
3776 .pvt = true,
3777 .tag_protocol = DSA_TAG_PROTO_EDSA,
3778 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3779 .ops = &mv88e6350_ops,
3780 },
3781
3782 [MV88E6351] = {
3783 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3784 .family = MV88E6XXX_FAMILY_6351,
3785 .name = "Marvell 88E6351",
3786 .num_databases = 4096,
3787 .num_ports = 7,
3788 .max_vid = 4095,
3789 .port_base_addr = 0x10,
3790 .global1_addr = 0x1b,
3791 .age_time_coeff = 15000,
3792 .g1_irqs = 9,
3793 .atu_move_port_mask = 0xf,
3794 .pvt = true,
3795 .tag_protocol = DSA_TAG_PROTO_EDSA,
3796 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3797 .ops = &mv88e6351_ops,
3798 },
3799
3800 [MV88E6352] = {
3801 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3802 .family = MV88E6XXX_FAMILY_6352,
3803 .name = "Marvell 88E6352",
3804 .num_databases = 4096,
3805 .num_ports = 7,
3806 .max_vid = 4095,
3807 .port_base_addr = 0x10,
3808 .global1_addr = 0x1b,
3809 .age_time_coeff = 15000,
3810 .g1_irqs = 9,
3811 .atu_move_port_mask = 0xf,
3812 .pvt = true,
3813 .tag_protocol = DSA_TAG_PROTO_EDSA,
3814 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3815 .ops = &mv88e6352_ops,
3816 },
3817 [MV88E6390] = {
3818 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3819 .family = MV88E6XXX_FAMILY_6390,
3820 .name = "Marvell 88E6390",
3821 .num_databases = 4096,
3822 .num_ports = 11, /* 10 + Z80 */
3823 .port_base_addr = 0x0,
3824 .global1_addr = 0x1b,
3825 .age_time_coeff = 3750,
3826 .g1_irqs = 9,
3827 .atu_move_port_mask = 0x1f,
3828 .pvt = true,
3829 .tag_protocol = DSA_TAG_PROTO_DSA,
3830 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3831 .ops = &mv88e6390_ops,
3832 },
3833 [MV88E6390X] = {
3834 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3835 .family = MV88E6XXX_FAMILY_6390,
3836 .name = "Marvell 88E6390X",
3837 .num_databases = 4096,
3838 .num_ports = 11, /* 10 + Z80 */
3839 .port_base_addr = 0x0,
3840 .global1_addr = 0x1b,
3841 .age_time_coeff = 3750,
3842 .g1_irqs = 9,
3843 .atu_move_port_mask = 0x1f,
3844 .pvt = true,
3845 .tag_protocol = DSA_TAG_PROTO_DSA,
3846 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3847 .ops = &mv88e6390x_ops,
3848 },
3849 };
3850
3851 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3852 {
3853 int i;
3854
3855 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3856 if (mv88e6xxx_table[i].prod_num == prod_num)
3857 return &mv88e6xxx_table[i];
3858
3859 return NULL;
3860 }
3861
3862 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3863 {
3864 const struct mv88e6xxx_info *info;
3865 unsigned int prod_num, rev;
3866 u16 id;
3867 int err;
3868
3869 mutex_lock(&chip->reg_lock);
3870 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3871 mutex_unlock(&chip->reg_lock);
3872 if (err)
3873 return err;
3874
3875 prod_num = (id & 0xfff0) >> 4;
3876 rev = id & 0x000f;
3877
3878 info = mv88e6xxx_lookup_info(prod_num);
3879 if (!info)
3880 return -ENODEV;
3881
3882 /* Update the compatible info with the probed one */
3883 chip->info = info;
3884
3885 err = mv88e6xxx_g2_require(chip);
3886 if (err)
3887 return err;
3888
3889 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3890 chip->info->prod_num, chip->info->name, rev);
3891
3892 return 0;
3893 }
3894
3895 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3896 {
3897 struct mv88e6xxx_chip *chip;
3898
3899 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3900 if (!chip)
3901 return NULL;
3902
3903 chip->dev = dev;
3904
3905 mutex_init(&chip->reg_lock);
3906 INIT_LIST_HEAD(&chip->mdios);
3907
3908 return chip;
3909 }
3910
3911 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3912 {
3913 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
3914 mv88e6xxx_ppu_state_init(chip);
3915 }
3916
3917 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3918 {
3919 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
3920 mv88e6xxx_ppu_state_destroy(chip);
3921 }
3922
3923 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3924 struct mii_bus *bus, int sw_addr)
3925 {
3926 if (sw_addr == 0)
3927 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3928 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3929 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3930 else
3931 return -EINVAL;
3932
3933 chip->bus = bus;
3934 chip->sw_addr = sw_addr;
3935
3936 return 0;
3937 }
3938
3939 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3940 {
3941 struct mv88e6xxx_chip *chip = ds->priv;
3942
3943 return chip->info->tag_protocol;
3944 }
3945
3946 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3947 struct device *host_dev, int sw_addr,
3948 void **priv)
3949 {
3950 struct mv88e6xxx_chip *chip;
3951 struct mii_bus *bus;
3952 int err;
3953
3954 bus = dsa_host_dev_to_mii_bus(host_dev);
3955 if (!bus)
3956 return NULL;
3957
3958 chip = mv88e6xxx_alloc_chip(dsa_dev);
3959 if (!chip)
3960 return NULL;
3961
3962 /* Legacy SMI probing will only support chips similar to 88E6085 */
3963 chip->info = &mv88e6xxx_table[MV88E6085];
3964
3965 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3966 if (err)
3967 goto free;
3968
3969 err = mv88e6xxx_detect(chip);
3970 if (err)
3971 goto free;
3972
3973 mutex_lock(&chip->reg_lock);
3974 err = mv88e6xxx_switch_reset(chip);
3975 mutex_unlock(&chip->reg_lock);
3976 if (err)
3977 goto free;
3978
3979 mv88e6xxx_phy_init(chip);
3980
3981 err = mv88e6xxx_mdios_register(chip, NULL);
3982 if (err)
3983 goto free;
3984
3985 *priv = chip;
3986
3987 return chip->info->name;
3988 free:
3989 devm_kfree(dsa_dev, chip);
3990
3991 return NULL;
3992 }
3993
3994 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3995 const struct switchdev_obj_port_mdb *mdb,
3996 struct switchdev_trans *trans)
3997 {
3998 /* We don't need any dynamic resource from the kernel (yet),
3999 * so skip the prepare phase.
4000 */
4001
4002 return 0;
4003 }
4004
4005 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4006 const struct switchdev_obj_port_mdb *mdb,
4007 struct switchdev_trans *trans)
4008 {
4009 struct mv88e6xxx_chip *chip = ds->priv;
4010
4011 mutex_lock(&chip->reg_lock);
4012 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4013 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4014 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4015 mutex_unlock(&chip->reg_lock);
4016 }
4017
4018 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4019 const struct switchdev_obj_port_mdb *mdb)
4020 {
4021 struct mv88e6xxx_chip *chip = ds->priv;
4022 int err;
4023
4024 mutex_lock(&chip->reg_lock);
4025 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4026 GLOBAL_ATU_DATA_STATE_UNUSED);
4027 mutex_unlock(&chip->reg_lock);
4028
4029 return err;
4030 }
4031
4032 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4033 struct switchdev_obj_port_mdb *mdb,
4034 int (*cb)(struct switchdev_obj *obj))
4035 {
4036 struct mv88e6xxx_chip *chip = ds->priv;
4037 int err;
4038
4039 mutex_lock(&chip->reg_lock);
4040 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4041 mutex_unlock(&chip->reg_lock);
4042
4043 return err;
4044 }
4045
4046 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4047 .probe = mv88e6xxx_drv_probe,
4048 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4049 .setup = mv88e6xxx_setup,
4050 .set_addr = mv88e6xxx_set_addr,
4051 .adjust_link = mv88e6xxx_adjust_link,
4052 .get_strings = mv88e6xxx_get_strings,
4053 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4054 .get_sset_count = mv88e6xxx_get_sset_count,
4055 .set_eee = mv88e6xxx_set_eee,
4056 .get_eee = mv88e6xxx_get_eee,
4057 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4058 .get_eeprom = mv88e6xxx_get_eeprom,
4059 .set_eeprom = mv88e6xxx_set_eeprom,
4060 .get_regs_len = mv88e6xxx_get_regs_len,
4061 .get_regs = mv88e6xxx_get_regs,
4062 .set_ageing_time = mv88e6xxx_set_ageing_time,
4063 .port_bridge_join = mv88e6xxx_port_bridge_join,
4064 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4065 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4066 .port_fast_age = mv88e6xxx_port_fast_age,
4067 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4068 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4069 .port_vlan_add = mv88e6xxx_port_vlan_add,
4070 .port_vlan_del = mv88e6xxx_port_vlan_del,
4071 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4072 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4073 .port_fdb_add = mv88e6xxx_port_fdb_add,
4074 .port_fdb_del = mv88e6xxx_port_fdb_del,
4075 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4076 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4077 .port_mdb_add = mv88e6xxx_port_mdb_add,
4078 .port_mdb_del = mv88e6xxx_port_mdb_del,
4079 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4080 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4081 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4082 };
4083
4084 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4085 .ops = &mv88e6xxx_switch_ops,
4086 };
4087
4088 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4089 {
4090 struct device *dev = chip->dev;
4091 struct dsa_switch *ds;
4092
4093 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4094 if (!ds)
4095 return -ENOMEM;
4096
4097 ds->priv = chip;
4098 ds->ops = &mv88e6xxx_switch_ops;
4099 ds->ageing_time_min = chip->info->age_time_coeff;
4100 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4101
4102 dev_set_drvdata(dev, ds);
4103
4104 return dsa_register_switch(ds, dev);
4105 }
4106
4107 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4108 {
4109 dsa_unregister_switch(chip->ds);
4110 }
4111
4112 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4113 {
4114 struct device *dev = &mdiodev->dev;
4115 struct device_node *np = dev->of_node;
4116 const struct mv88e6xxx_info *compat_info;
4117 struct mv88e6xxx_chip *chip;
4118 u32 eeprom_len;
4119 int err;
4120
4121 compat_info = of_device_get_match_data(dev);
4122 if (!compat_info)
4123 return -EINVAL;
4124
4125 chip = mv88e6xxx_alloc_chip(dev);
4126 if (!chip)
4127 return -ENOMEM;
4128
4129 chip->info = compat_info;
4130
4131 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4132 if (err)
4133 return err;
4134
4135 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4136 if (IS_ERR(chip->reset))
4137 return PTR_ERR(chip->reset);
4138
4139 err = mv88e6xxx_detect(chip);
4140 if (err)
4141 return err;
4142
4143 mv88e6xxx_phy_init(chip);
4144
4145 if (chip->info->ops->get_eeprom &&
4146 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4147 chip->eeprom_len = eeprom_len;
4148
4149 mutex_lock(&chip->reg_lock);
4150 err = mv88e6xxx_switch_reset(chip);
4151 mutex_unlock(&chip->reg_lock);
4152 if (err)
4153 goto out;
4154
4155 chip->irq = of_irq_get(np, 0);
4156 if (chip->irq == -EPROBE_DEFER) {
4157 err = chip->irq;
4158 goto out;
4159 }
4160
4161 if (chip->irq > 0) {
4162 /* Has to be performed before the MDIO bus is created,
4163 * because the PHYs will link there interrupts to these
4164 * interrupt controllers
4165 */
4166 mutex_lock(&chip->reg_lock);
4167 err = mv88e6xxx_g1_irq_setup(chip);
4168 mutex_unlock(&chip->reg_lock);
4169
4170 if (err)
4171 goto out;
4172
4173 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4174 err = mv88e6xxx_g2_irq_setup(chip);
4175 if (err)
4176 goto out_g1_irq;
4177 }
4178 }
4179
4180 err = mv88e6xxx_mdios_register(chip, np);
4181 if (err)
4182 goto out_g2_irq;
4183
4184 err = mv88e6xxx_register_switch(chip);
4185 if (err)
4186 goto out_mdio;
4187
4188 return 0;
4189
4190 out_mdio:
4191 mv88e6xxx_mdios_unregister(chip);
4192 out_g2_irq:
4193 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4194 mv88e6xxx_g2_irq_free(chip);
4195 out_g1_irq:
4196 if (chip->irq > 0) {
4197 mutex_lock(&chip->reg_lock);
4198 mv88e6xxx_g1_irq_free(chip);
4199 mutex_unlock(&chip->reg_lock);
4200 }
4201 out:
4202 return err;
4203 }
4204
4205 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4206 {
4207 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4208 struct mv88e6xxx_chip *chip = ds->priv;
4209
4210 mv88e6xxx_phy_destroy(chip);
4211 mv88e6xxx_unregister_switch(chip);
4212 mv88e6xxx_mdios_unregister(chip);
4213
4214 if (chip->irq > 0) {
4215 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4216 mv88e6xxx_g2_irq_free(chip);
4217 mv88e6xxx_g1_irq_free(chip);
4218 }
4219 }
4220
4221 static const struct of_device_id mv88e6xxx_of_match[] = {
4222 {
4223 .compatible = "marvell,mv88e6085",
4224 .data = &mv88e6xxx_table[MV88E6085],
4225 },
4226 {
4227 .compatible = "marvell,mv88e6190",
4228 .data = &mv88e6xxx_table[MV88E6190],
4229 },
4230 { /* sentinel */ },
4231 };
4232
4233 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4234
4235 static struct mdio_driver mv88e6xxx_driver = {
4236 .probe = mv88e6xxx_probe,
4237 .remove = mv88e6xxx_remove,
4238 .mdiodrv.driver = {
4239 .name = "mv88e6085",
4240 .of_match_table = mv88e6xxx_of_match,
4241 },
4242 };
4243
4244 static int __init mv88e6xxx_init(void)
4245 {
4246 register_switch_driver(&mv88e6xxx_switch_drv);
4247 return mdio_driver_register(&mv88e6xxx_driver);
4248 }
4249 module_init(mv88e6xxx_init);
4250
4251 static void __exit mv88e6xxx_cleanup(void)
4252 {
4253 mdio_driver_unregister(&mv88e6xxx_driver);
4254 unregister_switch_driver(&mv88e6xxx_switch_drv);
4255 }
4256 module_exit(mv88e6xxx_cleanup);
4257
4258 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4259 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4260 MODULE_LICENSE("GPL");
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