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net: dsa: mv88e6xxx: Move g1 stats code in global1.[ch]
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 /*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
34 #include <net/dsa.h>
35 #include <net/switchdev.h>
36
37 #include "mv88e6xxx.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "port.h"
41
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
43 {
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
46 dump_stack();
47 }
48 }
49
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
60 */
61
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
64 {
65 if (!chip->smi_ops)
66 return -EOPNOTSUPP;
67
68 return chip->smi_ops->read(chip, addr, reg, val);
69 }
70
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
73 {
74 if (!chip->smi_ops)
75 return -EOPNOTSUPP;
76
77 return chip->smi_ops->write(chip, addr, reg, val);
78 }
79
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
82 {
83 int ret;
84
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92 }
93
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
96 {
97 int ret;
98
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
100 if (ret < 0)
101 return ret;
102
103 return 0;
104 }
105
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109 };
110
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
112 {
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
118 if (ret < 0)
119 return ret;
120
121 if ((ret & SMI_CMD_BUSY) == 0)
122 return 0;
123 }
124
125 return -ETIMEDOUT;
126 }
127
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
130 {
131 int ret;
132
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
135 if (ret < 0)
136 return ret;
137
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
141 if (ret < 0)
142 return ret;
143
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
146 if (ret < 0)
147 return ret;
148
149 /* Read the data. */
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
151 if (ret < 0)
152 return ret;
153
154 *val = ret & 0xffff;
155
156 return 0;
157 }
158
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
161 {
162 int ret;
163
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
182 if (ret < 0)
183 return ret;
184
185 return 0;
186 }
187
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191 };
192
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
194 {
195 int err;
196
197 assert_reg_lock(chip);
198
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
200 if (err)
201 return err;
202
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
204 addr, reg, *val);
205
206 return 0;
207 }
208
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
210 {
211 int err;
212
213 assert_reg_lock(chip);
214
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
216 if (err)
217 return err;
218
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
220 addr, reg, val);
221
222 return 0;
223 }
224
225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227 {
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
230 if (!chip->info->ops->phy_read)
231 return -EOPNOTSUPP;
232
233 return chip->info->ops->phy_read(chip, addr, reg, val);
234 }
235
236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238 {
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
241 if (!chip->info->ops->phy_write)
242 return -EOPNOTSUPP;
243
244 return chip->info->ops->phy_write(chip, addr, reg, val);
245 }
246
247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248 {
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253 }
254
255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256 {
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265 }
266
267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269 {
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283 }
284
285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287 {
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301 }
302
303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304 {
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307 }
308
309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310 {
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313 }
314
315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316 {
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321 }
322
323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324 {
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329 }
330
331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332 {
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354 out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356 }
357
358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359 {
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363 }
364
365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366 {
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383 out:
384 mutex_unlock(&chip->reg_lock);
385 }
386
387 static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393 };
394
395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398 {
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406 }
407
408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411 };
412
413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414 {
415 int irq, virq;
416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
423
424 for (irq = 0; irq < 16; irq++) {
425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
426 irq_dispose_mapping(virq);
427 }
428
429 irq_domain_remove(chip->g1_irq.domain);
430 }
431
432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433 {
434 int err, irq, virq;
435 u16 reg, mask;
436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
451 if (err)
452 goto out_mapping;
453
454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
455
456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457 if (err)
458 goto out_disable;
459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
463 goto out_disable;
464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
470 goto out_disable;
471
472 return 0;
473
474 out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478 out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
485
486 return err;
487 }
488
489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
490 {
491 int i;
492
493 for (i = 0; i < 16; i++) {
494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
507 dev_err(chip->dev, "Timeout while waiting for switch\n");
508 return -ETIMEDOUT;
509 }
510
511 /* Indirect write to single pointer-data register with an Update bit */
512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
513 {
514 u16 val;
515 int err;
516
517 /* Wait until the previous operation is completed */
518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526 }
527
528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
529 {
530 u16 val;
531 int i, err;
532
533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
534 if (err)
535 return err;
536
537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
538 val & ~GLOBAL_CONTROL_PPU_ENABLE);
539 if (err)
540 return err;
541
542 for (i = 0; i < 16; i++) {
543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
544 if (err)
545 return err;
546
547 usleep_range(1000, 2000);
548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
549 return 0;
550 }
551
552 return -ETIMEDOUT;
553 }
554
555 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
556 {
557 u16 val;
558 int i, err;
559
560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
561 if (err)
562 return err;
563
564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
565 val | GLOBAL_CONTROL_PPU_ENABLE);
566 if (err)
567 return err;
568
569 for (i = 0; i < 16; i++) {
570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
571 if (err)
572 return err;
573
574 usleep_range(1000, 2000);
575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
576 return 0;
577 }
578
579 return -ETIMEDOUT;
580 }
581
582 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
583 {
584 struct mv88e6xxx_chip *chip;
585
586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
587
588 mutex_lock(&chip->reg_lock);
589
590 if (mutex_trylock(&chip->ppu_mutex)) {
591 if (mv88e6xxx_ppu_enable(chip) == 0)
592 chip->ppu_disabled = 0;
593 mutex_unlock(&chip->ppu_mutex);
594 }
595
596 mutex_unlock(&chip->reg_lock);
597 }
598
599 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
600 {
601 struct mv88e6xxx_chip *chip = (void *)_ps;
602
603 schedule_work(&chip->ppu_work);
604 }
605
606 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
607 {
608 int ret;
609
610 mutex_lock(&chip->ppu_mutex);
611
612 /* If the PHY polling unit is enabled, disable it so that
613 * we can access the PHY registers. If it was already
614 * disabled, cancel the timer that is going to re-enable
615 * it.
616 */
617 if (!chip->ppu_disabled) {
618 ret = mv88e6xxx_ppu_disable(chip);
619 if (ret < 0) {
620 mutex_unlock(&chip->ppu_mutex);
621 return ret;
622 }
623 chip->ppu_disabled = 1;
624 } else {
625 del_timer(&chip->ppu_timer);
626 ret = 0;
627 }
628
629 return ret;
630 }
631
632 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
633 {
634 /* Schedule a timer to re-enable the PHY polling unit. */
635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
636 mutex_unlock(&chip->ppu_mutex);
637 }
638
639 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
640 {
641 mutex_init(&chip->ppu_mutex);
642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
644 (unsigned long)chip);
645 }
646
647 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
648 {
649 del_timer_sync(&chip->ppu_timer);
650 }
651
652 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
653 int reg, u16 *val)
654 {
655 int err;
656
657 err = mv88e6xxx_ppu_access_get(chip);
658 if (!err) {
659 err = mv88e6xxx_read(chip, addr, reg, val);
660 mv88e6xxx_ppu_access_put(chip);
661 }
662
663 return err;
664 }
665
666 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
667 int reg, u16 val)
668 {
669 int err;
670
671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
674 mv88e6xxx_ppu_access_put(chip);
675 }
676
677 return err;
678 }
679
680 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
681 {
682 return chip->info->family == MV88E6XXX_FAMILY_6065;
683 }
684
685 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
686 {
687 return chip->info->family == MV88E6XXX_FAMILY_6095;
688 }
689
690 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
691 {
692 return chip->info->family == MV88E6XXX_FAMILY_6097;
693 }
694
695 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
696 {
697 return chip->info->family == MV88E6XXX_FAMILY_6165;
698 }
699
700 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
701 {
702 return chip->info->family == MV88E6XXX_FAMILY_6185;
703 }
704
705 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
706 {
707 return chip->info->family == MV88E6XXX_FAMILY_6320;
708 }
709
710 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
711 {
712 return chip->info->family == MV88E6XXX_FAMILY_6351;
713 }
714
715 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
716 {
717 return chip->info->family == MV88E6XXX_FAMILY_6352;
718 }
719
720 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
721 int link, int speed, int duplex,
722 phy_interface_t mode)
723 {
724 int err;
725
726 if (!chip->info->ops->port_set_link)
727 return 0;
728
729 /* Port's MAC control must not be changed unless the link is down */
730 err = chip->info->ops->port_set_link(chip, port, 0);
731 if (err)
732 return err;
733
734 if (chip->info->ops->port_set_speed) {
735 err = chip->info->ops->port_set_speed(chip, port, speed);
736 if (err && err != -EOPNOTSUPP)
737 goto restore_link;
738 }
739
740 if (chip->info->ops->port_set_duplex) {
741 err = chip->info->ops->port_set_duplex(chip, port, duplex);
742 if (err && err != -EOPNOTSUPP)
743 goto restore_link;
744 }
745
746 if (chip->info->ops->port_set_rgmii_delay) {
747 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
748 if (err && err != -EOPNOTSUPP)
749 goto restore_link;
750 }
751
752 err = 0;
753 restore_link:
754 if (chip->info->ops->port_set_link(chip, port, link))
755 netdev_err(chip->ds->ports[port].netdev,
756 "failed to restore MAC's link\n");
757
758 return err;
759 }
760
761 /* We expect the switch to perform auto negotiation if there is a real
762 * phy. However, in the case of a fixed link phy, we force the port
763 * settings from the fixed link settings.
764 */
765 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
766 struct phy_device *phydev)
767 {
768 struct mv88e6xxx_chip *chip = ds->priv;
769 int err;
770
771 if (!phy_is_pseudo_fixed_link(phydev))
772 return;
773
774 mutex_lock(&chip->reg_lock);
775 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
776 phydev->duplex, phydev->interface);
777 mutex_unlock(&chip->reg_lock);
778
779 if (err && err != -EOPNOTSUPP)
780 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
781 }
782
783 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
784 {
785 if (!chip->info->ops->stats_snapshot)
786 return -EOPNOTSUPP;
787
788 return chip->info->ops->stats_snapshot(chip, port);
789 }
790
791 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
792 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
793 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
794 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
795 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
796 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
797 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
798 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
799 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
800 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
801 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
802 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
803 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
804 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
805 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
806 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
807 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
808 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
809 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
810 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
811 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
812 { "single", 4, 0x14, STATS_TYPE_BANK0, },
813 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
814 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
815 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
816 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
817 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
818 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
819 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
820 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
821 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
822 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
823 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
824 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
825 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
826 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
827 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
828 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
829 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
830 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
831 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
832 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
833 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
834 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
835 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
836 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
837 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
838 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
839 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
840 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
841 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
842 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
843 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
844 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
845 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
846 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
847 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
848 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
849 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
850 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
851 };
852
853 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
854 struct mv88e6xxx_hw_stat *s,
855 int port, u16 bank1_select,
856 u16 histogram)
857 {
858 u32 low;
859 u32 high = 0;
860 u16 reg = 0;
861 int err;
862 u64 value;
863
864 switch (s->type) {
865 case STATS_TYPE_PORT:
866 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
867 if (err)
868 return UINT64_MAX;
869
870 low = reg;
871 if (s->sizeof_stat == 4) {
872 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
873 if (err)
874 return UINT64_MAX;
875 high = reg;
876 }
877 break;
878 case STATS_TYPE_BANK1:
879 reg = bank1_select;
880 /* fall through */
881 case STATS_TYPE_BANK0:
882 reg |= s->reg | histogram;
883 mv88e6xxx_g1_stats_read(chip, reg, &low);
884 if (s->sizeof_stat == 8)
885 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
886 }
887 value = (((u64)high) << 16) | low;
888 return value;
889 }
890
891 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
892 uint8_t *data, int types)
893 {
894 struct mv88e6xxx_hw_stat *stat;
895 int i, j;
896
897 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
898 stat = &mv88e6xxx_hw_stats[i];
899 if (stat->type & types) {
900 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
901 ETH_GSTRING_LEN);
902 j++;
903 }
904 }
905 }
906
907 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
908 uint8_t *data)
909 {
910 mv88e6xxx_stats_get_strings(chip, data,
911 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
912 }
913
914 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
915 uint8_t *data)
916 {
917 mv88e6xxx_stats_get_strings(chip, data,
918 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
919 }
920
921 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
922 uint8_t *data)
923 {
924 struct mv88e6xxx_chip *chip = ds->priv;
925
926 if (chip->info->ops->stats_get_strings)
927 chip->info->ops->stats_get_strings(chip, data);
928 }
929
930 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
931 int types)
932 {
933 struct mv88e6xxx_hw_stat *stat;
934 int i, j;
935
936 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
937 stat = &mv88e6xxx_hw_stats[i];
938 if (stat->type & types)
939 j++;
940 }
941 return j;
942 }
943
944 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
945 {
946 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
947 STATS_TYPE_PORT);
948 }
949
950 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
951 {
952 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
953 STATS_TYPE_BANK1);
954 }
955
956 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
957 {
958 struct mv88e6xxx_chip *chip = ds->priv;
959
960 if (chip->info->ops->stats_get_sset_count)
961 return chip->info->ops->stats_get_sset_count(chip);
962
963 return 0;
964 }
965
966 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
967 uint64_t *data, int types,
968 u16 bank1_select, u16 histogram)
969 {
970 struct mv88e6xxx_hw_stat *stat;
971 int i, j;
972
973 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
974 stat = &mv88e6xxx_hw_stats[i];
975 if (stat->type & types) {
976 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
977 bank1_select,
978 histogram);
979 j++;
980 }
981 }
982 }
983
984 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
985 uint64_t *data)
986 {
987 return mv88e6xxx_stats_get_stats(chip, port, data,
988 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
989 0, GLOBAL_STATS_OP_HIST_RX_TX);
990 }
991
992 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
994 {
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_9,
998 GLOBAL_STATS_OP_HIST_RX_TX);
999 }
1000
1001 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1002 uint64_t *data)
1003 {
1004 return mv88e6xxx_stats_get_stats(chip, port, data,
1005 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1006 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
1007 }
1008
1009 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1010 uint64_t *data)
1011 {
1012 if (chip->info->ops->stats_get_stats)
1013 chip->info->ops->stats_get_stats(chip, port, data);
1014 }
1015
1016 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1017 uint64_t *data)
1018 {
1019 struct mv88e6xxx_chip *chip = ds->priv;
1020 int ret;
1021
1022 mutex_lock(&chip->reg_lock);
1023
1024 ret = mv88e6xxx_stats_snapshot(chip, port);
1025 if (ret < 0) {
1026 mutex_unlock(&chip->reg_lock);
1027 return;
1028 }
1029
1030 mv88e6xxx_get_stats(chip, port, data);
1031
1032 mutex_unlock(&chip->reg_lock);
1033 }
1034
1035 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1036 {
1037 if (chip->info->ops->stats_set_histogram)
1038 return chip->info->ops->stats_set_histogram(chip);
1039
1040 return 0;
1041 }
1042
1043 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1044 {
1045 return 32 * sizeof(u16);
1046 }
1047
1048 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1049 struct ethtool_regs *regs, void *_p)
1050 {
1051 struct mv88e6xxx_chip *chip = ds->priv;
1052 int err;
1053 u16 reg;
1054 u16 *p = _p;
1055 int i;
1056
1057 regs->version = 0;
1058
1059 memset(p, 0xff, 32 * sizeof(u16));
1060
1061 mutex_lock(&chip->reg_lock);
1062
1063 for (i = 0; i < 32; i++) {
1064
1065 err = mv88e6xxx_port_read(chip, port, i, &reg);
1066 if (!err)
1067 p[i] = reg;
1068 }
1069
1070 mutex_unlock(&chip->reg_lock);
1071 }
1072
1073 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1074 {
1075 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
1076 }
1077
1078 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1079 struct ethtool_eee *e)
1080 {
1081 struct mv88e6xxx_chip *chip = ds->priv;
1082 u16 reg;
1083 int err;
1084
1085 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1086 return -EOPNOTSUPP;
1087
1088 mutex_lock(&chip->reg_lock);
1089
1090 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1091 if (err)
1092 goto out;
1093
1094 e->eee_enabled = !!(reg & 0x0200);
1095 e->tx_lpi_enabled = !!(reg & 0x0100);
1096
1097 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
1098 if (err)
1099 goto out;
1100
1101 e->eee_active = !!(reg & PORT_STATUS_EEE);
1102 out:
1103 mutex_unlock(&chip->reg_lock);
1104
1105 return err;
1106 }
1107
1108 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1109 struct phy_device *phydev, struct ethtool_eee *e)
1110 {
1111 struct mv88e6xxx_chip *chip = ds->priv;
1112 u16 reg;
1113 int err;
1114
1115 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1116 return -EOPNOTSUPP;
1117
1118 mutex_lock(&chip->reg_lock);
1119
1120 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1121 if (err)
1122 goto out;
1123
1124 reg &= ~0x0300;
1125 if (e->eee_enabled)
1126 reg |= 0x0200;
1127 if (e->tx_lpi_enabled)
1128 reg |= 0x0100;
1129
1130 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1131 out:
1132 mutex_unlock(&chip->reg_lock);
1133
1134 return err;
1135 }
1136
1137 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1138 {
1139 u16 val;
1140 int err;
1141
1142 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
1143 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1144 if (err)
1145 return err;
1146 } else if (mv88e6xxx_num_databases(chip) == 256) {
1147 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1148 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1149 if (err)
1150 return err;
1151
1152 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1153 (val & 0xfff) | ((fid << 8) & 0xf000));
1154 if (err)
1155 return err;
1156
1157 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1158 cmd |= fid & 0xf;
1159 }
1160
1161 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1162 if (err)
1163 return err;
1164
1165 return _mv88e6xxx_atu_wait(chip);
1166 }
1167
1168 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1169 struct mv88e6xxx_atu_entry *entry)
1170 {
1171 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1172
1173 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1174 unsigned int mask, shift;
1175
1176 if (entry->trunk) {
1177 data |= GLOBAL_ATU_DATA_TRUNK;
1178 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1179 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1180 } else {
1181 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1182 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1183 }
1184
1185 data |= (entry->portv_trunkid << shift) & mask;
1186 }
1187
1188 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1189 }
1190
1191 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1192 struct mv88e6xxx_atu_entry *entry,
1193 bool static_too)
1194 {
1195 int op;
1196 int err;
1197
1198 err = _mv88e6xxx_atu_wait(chip);
1199 if (err)
1200 return err;
1201
1202 err = _mv88e6xxx_atu_data_write(chip, entry);
1203 if (err)
1204 return err;
1205
1206 if (entry->fid) {
1207 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1208 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1209 } else {
1210 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1211 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1212 }
1213
1214 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1215 }
1216
1217 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1218 u16 fid, bool static_too)
1219 {
1220 struct mv88e6xxx_atu_entry entry = {
1221 .fid = fid,
1222 .state = 0, /* EntryState bits must be 0 */
1223 };
1224
1225 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1226 }
1227
1228 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1229 int from_port, int to_port, bool static_too)
1230 {
1231 struct mv88e6xxx_atu_entry entry = {
1232 .trunk = false,
1233 .fid = fid,
1234 };
1235
1236 /* EntryState bits must be 0xF */
1237 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1238
1239 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1240 entry.portv_trunkid = (to_port & 0x0f) << 4;
1241 entry.portv_trunkid |= from_port & 0x0f;
1242
1243 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1244 }
1245
1246 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1247 int port, bool static_too)
1248 {
1249 /* Destination port 0xF means remove the entries */
1250 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1251 }
1252
1253 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1254 {
1255 struct net_device *bridge = chip->ports[port].bridge_dev;
1256 struct dsa_switch *ds = chip->ds;
1257 u16 output_ports = 0;
1258 int i;
1259
1260 /* allow CPU port or DSA link(s) to send frames to every port */
1261 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1262 output_ports = ~0;
1263 } else {
1264 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1265 /* allow sending frames to every group member */
1266 if (bridge && chip->ports[i].bridge_dev == bridge)
1267 output_ports |= BIT(i);
1268
1269 /* allow sending frames to CPU port and DSA link(s) */
1270 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1271 output_ports |= BIT(i);
1272 }
1273 }
1274
1275 /* prevent frames from going back out of the port they came in on */
1276 output_ports &= ~BIT(port);
1277
1278 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1279 }
1280
1281 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1282 u8 state)
1283 {
1284 struct mv88e6xxx_chip *chip = ds->priv;
1285 int stp_state;
1286 int err;
1287
1288 switch (state) {
1289 case BR_STATE_DISABLED:
1290 stp_state = PORT_CONTROL_STATE_DISABLED;
1291 break;
1292 case BR_STATE_BLOCKING:
1293 case BR_STATE_LISTENING:
1294 stp_state = PORT_CONTROL_STATE_BLOCKING;
1295 break;
1296 case BR_STATE_LEARNING:
1297 stp_state = PORT_CONTROL_STATE_LEARNING;
1298 break;
1299 case BR_STATE_FORWARDING:
1300 default:
1301 stp_state = PORT_CONTROL_STATE_FORWARDING;
1302 break;
1303 }
1304
1305 mutex_lock(&chip->reg_lock);
1306 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1307 mutex_unlock(&chip->reg_lock);
1308
1309 if (err)
1310 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1311 }
1312
1313 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1314 {
1315 struct mv88e6xxx_chip *chip = ds->priv;
1316 int err;
1317
1318 mutex_lock(&chip->reg_lock);
1319 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1320 mutex_unlock(&chip->reg_lock);
1321
1322 if (err)
1323 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1324 }
1325
1326 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1327 {
1328 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1329 }
1330
1331 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1332 {
1333 int err;
1334
1335 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1336 if (err)
1337 return err;
1338
1339 return _mv88e6xxx_vtu_wait(chip);
1340 }
1341
1342 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1343 {
1344 int ret;
1345
1346 ret = _mv88e6xxx_vtu_wait(chip);
1347 if (ret < 0)
1348 return ret;
1349
1350 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1351 }
1352
1353 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1354 struct mv88e6xxx_vtu_entry *entry,
1355 unsigned int nibble_offset)
1356 {
1357 u16 regs[3];
1358 int i, err;
1359
1360 for (i = 0; i < 3; ++i) {
1361 u16 *reg = &regs[i];
1362
1363 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1364 if (err)
1365 return err;
1366 }
1367
1368 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1369 unsigned int shift = (i % 4) * 4 + nibble_offset;
1370 u16 reg = regs[i / 4];
1371
1372 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1373 }
1374
1375 return 0;
1376 }
1377
1378 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1379 struct mv88e6xxx_vtu_entry *entry)
1380 {
1381 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1382 }
1383
1384 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1385 struct mv88e6xxx_vtu_entry *entry)
1386 {
1387 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1388 }
1389
1390 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1391 struct mv88e6xxx_vtu_entry *entry,
1392 unsigned int nibble_offset)
1393 {
1394 u16 regs[3] = { 0 };
1395 int i, err;
1396
1397 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1398 unsigned int shift = (i % 4) * 4 + nibble_offset;
1399 u8 data = entry->data[i];
1400
1401 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1402 }
1403
1404 for (i = 0; i < 3; ++i) {
1405 u16 reg = regs[i];
1406
1407 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1408 if (err)
1409 return err;
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1416 struct mv88e6xxx_vtu_entry *entry)
1417 {
1418 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1419 }
1420
1421 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1422 struct mv88e6xxx_vtu_entry *entry)
1423 {
1424 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1425 }
1426
1427 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1428 {
1429 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1430 vid & GLOBAL_VTU_VID_MASK);
1431 }
1432
1433 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1434 struct mv88e6xxx_vtu_entry *entry)
1435 {
1436 struct mv88e6xxx_vtu_entry next = { 0 };
1437 u16 val;
1438 int err;
1439
1440 err = _mv88e6xxx_vtu_wait(chip);
1441 if (err)
1442 return err;
1443
1444 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1445 if (err)
1446 return err;
1447
1448 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1449 if (err)
1450 return err;
1451
1452 next.vid = val & GLOBAL_VTU_VID_MASK;
1453 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1454
1455 if (next.valid) {
1456 err = mv88e6xxx_vtu_data_read(chip, &next);
1457 if (err)
1458 return err;
1459
1460 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1461 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1462 if (err)
1463 return err;
1464
1465 next.fid = val & GLOBAL_VTU_FID_MASK;
1466 } else if (mv88e6xxx_num_databases(chip) == 256) {
1467 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1468 * VTU DBNum[3:0] are located in VTU Operation 3:0
1469 */
1470 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1471 if (err)
1472 return err;
1473
1474 next.fid = (val & 0xf00) >> 4;
1475 next.fid |= val & 0xf;
1476 }
1477
1478 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1479 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1480 if (err)
1481 return err;
1482
1483 next.sid = val & GLOBAL_VTU_SID_MASK;
1484 }
1485 }
1486
1487 *entry = next;
1488 return 0;
1489 }
1490
1491 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1492 struct switchdev_obj_port_vlan *vlan,
1493 int (*cb)(struct switchdev_obj *obj))
1494 {
1495 struct mv88e6xxx_chip *chip = ds->priv;
1496 struct mv88e6xxx_vtu_entry next;
1497 u16 pvid;
1498 int err;
1499
1500 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1501 return -EOPNOTSUPP;
1502
1503 mutex_lock(&chip->reg_lock);
1504
1505 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1506 if (err)
1507 goto unlock;
1508
1509 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1510 if (err)
1511 goto unlock;
1512
1513 do {
1514 err = _mv88e6xxx_vtu_getnext(chip, &next);
1515 if (err)
1516 break;
1517
1518 if (!next.valid)
1519 break;
1520
1521 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1522 continue;
1523
1524 /* reinit and dump this VLAN obj */
1525 vlan->vid_begin = next.vid;
1526 vlan->vid_end = next.vid;
1527 vlan->flags = 0;
1528
1529 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1530 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1531
1532 if (next.vid == pvid)
1533 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1534
1535 err = cb(&vlan->obj);
1536 if (err)
1537 break;
1538 } while (next.vid < GLOBAL_VTU_VID_MASK);
1539
1540 unlock:
1541 mutex_unlock(&chip->reg_lock);
1542
1543 return err;
1544 }
1545
1546 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1547 struct mv88e6xxx_vtu_entry *entry)
1548 {
1549 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1550 u16 reg = 0;
1551 int err;
1552
1553 err = _mv88e6xxx_vtu_wait(chip);
1554 if (err)
1555 return err;
1556
1557 if (!entry->valid)
1558 goto loadpurge;
1559
1560 /* Write port member tags */
1561 err = mv88e6xxx_vtu_data_write(chip, entry);
1562 if (err)
1563 return err;
1564
1565 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1566 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1567 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1568 if (err)
1569 return err;
1570 }
1571
1572 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1573 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1574 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1575 if (err)
1576 return err;
1577 } else if (mv88e6xxx_num_databases(chip) == 256) {
1578 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1579 * VTU DBNum[3:0] are located in VTU Operation 3:0
1580 */
1581 op |= (entry->fid & 0xf0) << 8;
1582 op |= entry->fid & 0xf;
1583 }
1584
1585 reg = GLOBAL_VTU_VID_VALID;
1586 loadpurge:
1587 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1588 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1589 if (err)
1590 return err;
1591
1592 return _mv88e6xxx_vtu_cmd(chip, op);
1593 }
1594
1595 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1596 struct mv88e6xxx_vtu_entry *entry)
1597 {
1598 struct mv88e6xxx_vtu_entry next = { 0 };
1599 u16 val;
1600 int err;
1601
1602 err = _mv88e6xxx_vtu_wait(chip);
1603 if (err)
1604 return err;
1605
1606 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1607 sid & GLOBAL_VTU_SID_MASK);
1608 if (err)
1609 return err;
1610
1611 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1612 if (err)
1613 return err;
1614
1615 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1616 if (err)
1617 return err;
1618
1619 next.sid = val & GLOBAL_VTU_SID_MASK;
1620
1621 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1622 if (err)
1623 return err;
1624
1625 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1626
1627 if (next.valid) {
1628 err = mv88e6xxx_stu_data_read(chip, &next);
1629 if (err)
1630 return err;
1631 }
1632
1633 *entry = next;
1634 return 0;
1635 }
1636
1637 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1638 struct mv88e6xxx_vtu_entry *entry)
1639 {
1640 u16 reg = 0;
1641 int err;
1642
1643 err = _mv88e6xxx_vtu_wait(chip);
1644 if (err)
1645 return err;
1646
1647 if (!entry->valid)
1648 goto loadpurge;
1649
1650 /* Write port states */
1651 err = mv88e6xxx_stu_data_write(chip, entry);
1652 if (err)
1653 return err;
1654
1655 reg = GLOBAL_VTU_VID_VALID;
1656 loadpurge:
1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1658 if (err)
1659 return err;
1660
1661 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1662 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1663 if (err)
1664 return err;
1665
1666 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1667 }
1668
1669 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1670 {
1671 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1672 struct mv88e6xxx_vtu_entry vlan;
1673 int i, err;
1674
1675 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1676
1677 /* Set every FID bit used by the (un)bridged ports */
1678 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1679 err = mv88e6xxx_port_get_fid(chip, i, fid);
1680 if (err)
1681 return err;
1682
1683 set_bit(*fid, fid_bitmap);
1684 }
1685
1686 /* Set every FID bit used by the VLAN entries */
1687 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1688 if (err)
1689 return err;
1690
1691 do {
1692 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1693 if (err)
1694 return err;
1695
1696 if (!vlan.valid)
1697 break;
1698
1699 set_bit(vlan.fid, fid_bitmap);
1700 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1701
1702 /* The reset value 0x000 is used to indicate that multiple address
1703 * databases are not needed. Return the next positive available.
1704 */
1705 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1706 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1707 return -ENOSPC;
1708
1709 /* Clear the database */
1710 return _mv88e6xxx_atu_flush(chip, *fid, true);
1711 }
1712
1713 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1714 struct mv88e6xxx_vtu_entry *entry)
1715 {
1716 struct dsa_switch *ds = chip->ds;
1717 struct mv88e6xxx_vtu_entry vlan = {
1718 .valid = true,
1719 .vid = vid,
1720 };
1721 int i, err;
1722
1723 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1724 if (err)
1725 return err;
1726
1727 /* exclude all ports except the CPU and DSA ports */
1728 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1729 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1730 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1731 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1732
1733 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1734 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1735 struct mv88e6xxx_vtu_entry vstp;
1736
1737 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1738 * implemented, only one STU entry is needed to cover all VTU
1739 * entries. Thus, validate the SID 0.
1740 */
1741 vlan.sid = 0;
1742 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1743 if (err)
1744 return err;
1745
1746 if (vstp.sid != vlan.sid || !vstp.valid) {
1747 memset(&vstp, 0, sizeof(vstp));
1748 vstp.valid = true;
1749 vstp.sid = vlan.sid;
1750
1751 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1752 if (err)
1753 return err;
1754 }
1755 }
1756
1757 *entry = vlan;
1758 return 0;
1759 }
1760
1761 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1762 struct mv88e6xxx_vtu_entry *entry, bool creat)
1763 {
1764 int err;
1765
1766 if (!vid)
1767 return -EINVAL;
1768
1769 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1770 if (err)
1771 return err;
1772
1773 err = _mv88e6xxx_vtu_getnext(chip, entry);
1774 if (err)
1775 return err;
1776
1777 if (entry->vid != vid || !entry->valid) {
1778 if (!creat)
1779 return -EOPNOTSUPP;
1780 /* -ENOENT would've been more appropriate, but switchdev expects
1781 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1782 */
1783
1784 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1785 }
1786
1787 return err;
1788 }
1789
1790 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1791 u16 vid_begin, u16 vid_end)
1792 {
1793 struct mv88e6xxx_chip *chip = ds->priv;
1794 struct mv88e6xxx_vtu_entry vlan;
1795 int i, err;
1796
1797 if (!vid_begin)
1798 return -EOPNOTSUPP;
1799
1800 mutex_lock(&chip->reg_lock);
1801
1802 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1803 if (err)
1804 goto unlock;
1805
1806 do {
1807 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1808 if (err)
1809 goto unlock;
1810
1811 if (!vlan.valid)
1812 break;
1813
1814 if (vlan.vid > vid_end)
1815 break;
1816
1817 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1818 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1819 continue;
1820
1821 if (vlan.data[i] ==
1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1823 continue;
1824
1825 if (chip->ports[i].bridge_dev ==
1826 chip->ports[port].bridge_dev)
1827 break; /* same bridge, check next VLAN */
1828
1829 netdev_warn(ds->ports[port].netdev,
1830 "hardware VLAN %d already used by %s\n",
1831 vlan.vid,
1832 netdev_name(chip->ports[i].bridge_dev));
1833 err = -EOPNOTSUPP;
1834 goto unlock;
1835 }
1836 } while (vlan.vid < vid_end);
1837
1838 unlock:
1839 mutex_unlock(&chip->reg_lock);
1840
1841 return err;
1842 }
1843
1844 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1845 bool vlan_filtering)
1846 {
1847 struct mv88e6xxx_chip *chip = ds->priv;
1848 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1849 PORT_CONTROL_2_8021Q_DISABLED;
1850 int err;
1851
1852 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1853 return -EOPNOTSUPP;
1854
1855 mutex_lock(&chip->reg_lock);
1856 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1857 mutex_unlock(&chip->reg_lock);
1858
1859 return err;
1860 }
1861
1862 static int
1863 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1864 const struct switchdev_obj_port_vlan *vlan,
1865 struct switchdev_trans *trans)
1866 {
1867 struct mv88e6xxx_chip *chip = ds->priv;
1868 int err;
1869
1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1871 return -EOPNOTSUPP;
1872
1873 /* If the requested port doesn't belong to the same bridge as the VLAN
1874 * members, do not support it (yet) and fallback to software VLAN.
1875 */
1876 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1877 vlan->vid_end);
1878 if (err)
1879 return err;
1880
1881 /* We don't need any dynamic resource from the kernel (yet),
1882 * so skip the prepare phase.
1883 */
1884 return 0;
1885 }
1886
1887 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1888 u16 vid, bool untagged)
1889 {
1890 struct mv88e6xxx_vtu_entry vlan;
1891 int err;
1892
1893 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1894 if (err)
1895 return err;
1896
1897 vlan.data[port] = untagged ?
1898 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1899 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1900
1901 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1902 }
1903
1904 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1905 const struct switchdev_obj_port_vlan *vlan,
1906 struct switchdev_trans *trans)
1907 {
1908 struct mv88e6xxx_chip *chip = ds->priv;
1909 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1910 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1911 u16 vid;
1912
1913 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1914 return;
1915
1916 mutex_lock(&chip->reg_lock);
1917
1918 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1919 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1920 netdev_err(ds->ports[port].netdev,
1921 "failed to add VLAN %d%c\n",
1922 vid, untagged ? 'u' : 't');
1923
1924 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1925 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1926 vlan->vid_end);
1927
1928 mutex_unlock(&chip->reg_lock);
1929 }
1930
1931 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1932 int port, u16 vid)
1933 {
1934 struct dsa_switch *ds = chip->ds;
1935 struct mv88e6xxx_vtu_entry vlan;
1936 int i, err;
1937
1938 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1939 if (err)
1940 return err;
1941
1942 /* Tell switchdev if this VLAN is handled in software */
1943 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1944 return -EOPNOTSUPP;
1945
1946 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1947
1948 /* keep the VLAN unless all ports are excluded */
1949 vlan.valid = false;
1950 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1951 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1952 continue;
1953
1954 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1955 vlan.valid = true;
1956 break;
1957 }
1958 }
1959
1960 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1961 if (err)
1962 return err;
1963
1964 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1965 }
1966
1967 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1968 const struct switchdev_obj_port_vlan *vlan)
1969 {
1970 struct mv88e6xxx_chip *chip = ds->priv;
1971 u16 pvid, vid;
1972 int err = 0;
1973
1974 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1975 return -EOPNOTSUPP;
1976
1977 mutex_lock(&chip->reg_lock);
1978
1979 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1980 if (err)
1981 goto unlock;
1982
1983 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1984 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1985 if (err)
1986 goto unlock;
1987
1988 if (vid == pvid) {
1989 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1990 if (err)
1991 goto unlock;
1992 }
1993 }
1994
1995 unlock:
1996 mutex_unlock(&chip->reg_lock);
1997
1998 return err;
1999 }
2000
2001 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2002 const unsigned char *addr)
2003 {
2004 int i, err;
2005
2006 for (i = 0; i < 3; i++) {
2007 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2008 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2009 if (err)
2010 return err;
2011 }
2012
2013 return 0;
2014 }
2015
2016 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2017 unsigned char *addr)
2018 {
2019 u16 val;
2020 int i, err;
2021
2022 for (i = 0; i < 3; i++) {
2023 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2024 if (err)
2025 return err;
2026
2027 addr[i * 2] = val >> 8;
2028 addr[i * 2 + 1] = val & 0xff;
2029 }
2030
2031 return 0;
2032 }
2033
2034 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2035 struct mv88e6xxx_atu_entry *entry)
2036 {
2037 int ret;
2038
2039 ret = _mv88e6xxx_atu_wait(chip);
2040 if (ret < 0)
2041 return ret;
2042
2043 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2044 if (ret < 0)
2045 return ret;
2046
2047 ret = _mv88e6xxx_atu_data_write(chip, entry);
2048 if (ret < 0)
2049 return ret;
2050
2051 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2052 }
2053
2054 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2055 struct mv88e6xxx_atu_entry *entry);
2056
2057 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2058 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2059 {
2060 struct mv88e6xxx_atu_entry next;
2061 int err;
2062
2063 eth_broadcast_addr(next.mac);
2064
2065 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2066 if (err)
2067 return err;
2068
2069 do {
2070 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2071 if (err)
2072 return err;
2073
2074 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2075 break;
2076
2077 if (ether_addr_equal(next.mac, addr)) {
2078 *entry = next;
2079 return 0;
2080 }
2081 } while (!is_broadcast_ether_addr(next.mac));
2082
2083 memset(entry, 0, sizeof(*entry));
2084 entry->fid = fid;
2085 ether_addr_copy(entry->mac, addr);
2086
2087 return 0;
2088 }
2089
2090 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2091 const unsigned char *addr, u16 vid,
2092 u8 state)
2093 {
2094 struct mv88e6xxx_vtu_entry vlan;
2095 struct mv88e6xxx_atu_entry entry;
2096 int err;
2097
2098 /* Null VLAN ID corresponds to the port private database */
2099 if (vid == 0)
2100 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2101 else
2102 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2103 if (err)
2104 return err;
2105
2106 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2107 if (err)
2108 return err;
2109
2110 /* Purge the ATU entry only if no port is using it anymore */
2111 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2112 entry.portv_trunkid &= ~BIT(port);
2113 if (!entry.portv_trunkid)
2114 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2115 } else {
2116 entry.portv_trunkid |= BIT(port);
2117 entry.state = state;
2118 }
2119
2120 return _mv88e6xxx_atu_load(chip, &entry);
2121 }
2122
2123 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2124 const struct switchdev_obj_port_fdb *fdb,
2125 struct switchdev_trans *trans)
2126 {
2127 /* We don't need any dynamic resource from the kernel (yet),
2128 * so skip the prepare phase.
2129 */
2130 return 0;
2131 }
2132
2133 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2134 const struct switchdev_obj_port_fdb *fdb,
2135 struct switchdev_trans *trans)
2136 {
2137 struct mv88e6xxx_chip *chip = ds->priv;
2138
2139 mutex_lock(&chip->reg_lock);
2140 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2141 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2142 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2143 mutex_unlock(&chip->reg_lock);
2144 }
2145
2146 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2147 const struct switchdev_obj_port_fdb *fdb)
2148 {
2149 struct mv88e6xxx_chip *chip = ds->priv;
2150 int err;
2151
2152 mutex_lock(&chip->reg_lock);
2153 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2154 GLOBAL_ATU_DATA_STATE_UNUSED);
2155 mutex_unlock(&chip->reg_lock);
2156
2157 return err;
2158 }
2159
2160 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2161 struct mv88e6xxx_atu_entry *entry)
2162 {
2163 struct mv88e6xxx_atu_entry next = { 0 };
2164 u16 val;
2165 int err;
2166
2167 next.fid = fid;
2168
2169 err = _mv88e6xxx_atu_wait(chip);
2170 if (err)
2171 return err;
2172
2173 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2174 if (err)
2175 return err;
2176
2177 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2178 if (err)
2179 return err;
2180
2181 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2182 if (err)
2183 return err;
2184
2185 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2186 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2187 unsigned int mask, shift;
2188
2189 if (val & GLOBAL_ATU_DATA_TRUNK) {
2190 next.trunk = true;
2191 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2192 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2193 } else {
2194 next.trunk = false;
2195 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2196 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2197 }
2198
2199 next.portv_trunkid = (val & mask) >> shift;
2200 }
2201
2202 *entry = next;
2203 return 0;
2204 }
2205
2206 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2207 u16 fid, u16 vid, int port,
2208 struct switchdev_obj *obj,
2209 int (*cb)(struct switchdev_obj *obj))
2210 {
2211 struct mv88e6xxx_atu_entry addr = {
2212 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2213 };
2214 int err;
2215
2216 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2217 if (err)
2218 return err;
2219
2220 do {
2221 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2222 if (err)
2223 return err;
2224
2225 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2226 break;
2227
2228 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2229 continue;
2230
2231 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2232 struct switchdev_obj_port_fdb *fdb;
2233
2234 if (!is_unicast_ether_addr(addr.mac))
2235 continue;
2236
2237 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2238 fdb->vid = vid;
2239 ether_addr_copy(fdb->addr, addr.mac);
2240 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2241 fdb->ndm_state = NUD_NOARP;
2242 else
2243 fdb->ndm_state = NUD_REACHABLE;
2244 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2245 struct switchdev_obj_port_mdb *mdb;
2246
2247 if (!is_multicast_ether_addr(addr.mac))
2248 continue;
2249
2250 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2251 mdb->vid = vid;
2252 ether_addr_copy(mdb->addr, addr.mac);
2253 } else {
2254 return -EOPNOTSUPP;
2255 }
2256
2257 err = cb(obj);
2258 if (err)
2259 return err;
2260 } while (!is_broadcast_ether_addr(addr.mac));
2261
2262 return err;
2263 }
2264
2265 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2266 struct switchdev_obj *obj,
2267 int (*cb)(struct switchdev_obj *obj))
2268 {
2269 struct mv88e6xxx_vtu_entry vlan = {
2270 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2271 };
2272 u16 fid;
2273 int err;
2274
2275 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2276 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2277 if (err)
2278 return err;
2279
2280 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2281 if (err)
2282 return err;
2283
2284 /* Dump VLANs' Filtering Information Databases */
2285 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2286 if (err)
2287 return err;
2288
2289 do {
2290 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2291 if (err)
2292 return err;
2293
2294 if (!vlan.valid)
2295 break;
2296
2297 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2298 obj, cb);
2299 if (err)
2300 return err;
2301 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2302
2303 return err;
2304 }
2305
2306 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2307 struct switchdev_obj_port_fdb *fdb,
2308 int (*cb)(struct switchdev_obj *obj))
2309 {
2310 struct mv88e6xxx_chip *chip = ds->priv;
2311 int err;
2312
2313 mutex_lock(&chip->reg_lock);
2314 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2315 mutex_unlock(&chip->reg_lock);
2316
2317 return err;
2318 }
2319
2320 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2321 struct net_device *bridge)
2322 {
2323 struct mv88e6xxx_chip *chip = ds->priv;
2324 int i, err = 0;
2325
2326 mutex_lock(&chip->reg_lock);
2327
2328 /* Assign the bridge and remap each port's VLANTable */
2329 chip->ports[port].bridge_dev = bridge;
2330
2331 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2332 if (chip->ports[i].bridge_dev == bridge) {
2333 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2334 if (err)
2335 break;
2336 }
2337 }
2338
2339 mutex_unlock(&chip->reg_lock);
2340
2341 return err;
2342 }
2343
2344 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2345 {
2346 struct mv88e6xxx_chip *chip = ds->priv;
2347 struct net_device *bridge = chip->ports[port].bridge_dev;
2348 int i;
2349
2350 mutex_lock(&chip->reg_lock);
2351
2352 /* Unassign the bridge and remap each port's VLANTable */
2353 chip->ports[port].bridge_dev = NULL;
2354
2355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2356 if (i == port || chip->ports[i].bridge_dev == bridge)
2357 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2358 netdev_warn(ds->ports[i].netdev,
2359 "failed to remap\n");
2360
2361 mutex_unlock(&chip->reg_lock);
2362 }
2363
2364 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2365 {
2366 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2367 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2368 struct gpio_desc *gpiod = chip->reset;
2369 unsigned long timeout;
2370 u16 reg;
2371 int err;
2372 int i;
2373
2374 /* Set all ports to the disabled state. */
2375 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2376 err = mv88e6xxx_port_set_state(chip, i,
2377 PORT_CONTROL_STATE_DISABLED);
2378 if (err)
2379 return err;
2380 }
2381
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2384
2385 /* If there is a gpio connected to the reset pin, toggle it */
2386 if (gpiod) {
2387 gpiod_set_value_cansleep(gpiod, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod, 0);
2390 usleep_range(10000, 20000);
2391 }
2392
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2396 */
2397 if (ppu_active)
2398 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2399 else
2400 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2401 if (err)
2402 return err;
2403
2404 /* Wait up to one second for reset to complete. */
2405 timeout = jiffies + 1 * HZ;
2406 while (time_before(jiffies, timeout)) {
2407 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2408 if (err)
2409 return err;
2410
2411 if ((reg & is_reset) == is_reset)
2412 break;
2413 usleep_range(1000, 2000);
2414 }
2415 if (time_after(jiffies, timeout))
2416 err = -ETIMEDOUT;
2417 else
2418 err = 0;
2419
2420 return err;
2421 }
2422
2423 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2424 {
2425 u16 val;
2426 int err;
2427
2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (err)
2431 return err;
2432
2433 if (val & BMCR_PDOWN) {
2434 val &= ~BMCR_PDOWN;
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2436 }
2437
2438 return err;
2439 }
2440
2441 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2442 {
2443 struct dsa_switch *ds = chip->ds;
2444 int err;
2445 u16 reg;
2446
2447 /* MAC Forcing register: don't force link, speed, duplex or flow control
2448 * state to any particular values on physical ports, but force the CPU
2449 * port and all DSA ports to their maximum bandwidth and full duplex.
2450 */
2451 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2452 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2453 SPEED_MAX, DUPLEX_FULL,
2454 PHY_INTERFACE_MODE_NA);
2455 else
2456 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2457 SPEED_UNFORCED, DUPLEX_UNFORCED,
2458 PHY_INTERFACE_MODE_NA);
2459 if (err)
2460 return err;
2461
2462 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2463 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2464 * tunneling, determine priority by looking at 802.1p and IP
2465 * priority fields (IP prio has precedence), and set STP state
2466 * to Forwarding.
2467 *
2468 * If this is the CPU link, use DSA or EDSA tagging depending
2469 * on which tagging mode was configured.
2470 *
2471 * If this is a link to another switch, use DSA tagging mode.
2472 *
2473 * If this is the upstream port for this switch, enable
2474 * forwarding of unknown unicasts and multicasts.
2475 */
2476 reg = 0;
2477 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2478 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2479 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2480 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2481 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2482 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2483 PORT_CONTROL_STATE_FORWARDING;
2484 if (dsa_is_cpu_port(ds, port)) {
2485 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2486 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2487 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2488 else
2489 reg |= PORT_CONTROL_DSA_TAG;
2490 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2491 PORT_CONTROL_FORWARD_UNKNOWN;
2492 }
2493 if (dsa_is_dsa_port(ds, port)) {
2494 if (mv88e6xxx_6095_family(chip) ||
2495 mv88e6xxx_6185_family(chip))
2496 reg |= PORT_CONTROL_DSA_TAG;
2497 if (mv88e6xxx_6352_family(chip) ||
2498 mv88e6xxx_6351_family(chip) ||
2499 mv88e6xxx_6165_family(chip) ||
2500 mv88e6xxx_6097_family(chip) ||
2501 mv88e6xxx_6320_family(chip)) {
2502 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2503 }
2504
2505 if (port == dsa_upstream_port(ds))
2506 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2507 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2508 }
2509 if (reg) {
2510 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2511 if (err)
2512 return err;
2513 }
2514
2515 /* If this port is connected to a SerDes, make sure the SerDes is not
2516 * powered down.
2517 */
2518 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2519 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2520 if (err)
2521 return err;
2522 reg &= PORT_STATUS_CMODE_MASK;
2523 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2524 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2525 (reg == PORT_STATUS_CMODE_SGMII)) {
2526 err = mv88e6xxx_serdes_power_on(chip);
2527 if (err < 0)
2528 return err;
2529 }
2530 }
2531
2532 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2533 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2534 * untagged frames on this port, do a destination address lookup on all
2535 * received packets as usual, disable ARP mirroring and don't send a
2536 * copy of all transmitted/received frames on this port to the CPU.
2537 */
2538 reg = 0;
2539 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2540 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2541 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2542 mv88e6xxx_6185_family(chip))
2543 reg = PORT_CONTROL_2_MAP_DA;
2544
2545 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2546 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2547 reg |= PORT_CONTROL_2_JUMBO_10240;
2548
2549 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2550 /* Set the upstream port this port should use */
2551 reg |= dsa_upstream_port(ds);
2552 /* enable forwarding of unknown multicast addresses to
2553 * the upstream port
2554 */
2555 if (port == dsa_upstream_port(ds))
2556 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2557 }
2558
2559 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2560
2561 if (reg) {
2562 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2563 if (err)
2564 return err;
2565 }
2566
2567 /* Port Association Vector: when learning source addresses
2568 * of packets, add the address to the address database using
2569 * a port bitmap that has only the bit for this port set and
2570 * the other bits clear.
2571 */
2572 reg = 1 << port;
2573 /* Disable learning for CPU port */
2574 if (dsa_is_cpu_port(ds, port))
2575 reg = 0;
2576
2577 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2578 if (err)
2579 return err;
2580
2581 /* Egress rate control 2: disable egress rate control. */
2582 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2583 if (err)
2584 return err;
2585
2586 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2587 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2588 mv88e6xxx_6320_family(chip)) {
2589 /* Do not limit the period of time that this port can
2590 * be paused for by the remote end or the period of
2591 * time that this port can pause the remote end.
2592 */
2593 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2594 if (err)
2595 return err;
2596
2597 /* Port ATU control: disable limiting the number of
2598 * address database entries that this port is allowed
2599 * to use.
2600 */
2601 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2602 0x0000);
2603 /* Priority Override: disable DA, SA and VTU priority
2604 * override.
2605 */
2606 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2607 0x0000);
2608 if (err)
2609 return err;
2610
2611 /* Port Ethertype: use the Ethertype DSA Ethertype
2612 * value.
2613 */
2614 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2615 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2616 ETH_P_EDSA);
2617 if (err)
2618 return err;
2619 }
2620
2621 /* Tag Remap: use an identity 802.1p prio -> switch
2622 * prio mapping.
2623 */
2624 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2625 0x3210);
2626 if (err)
2627 return err;
2628
2629 /* Tag Remap 2: use an identity 802.1p prio -> switch
2630 * prio mapping.
2631 */
2632 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2633 0x7654);
2634 if (err)
2635 return err;
2636 }
2637
2638 /* Rate Control: disable ingress rate limiting. */
2639 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2640 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2641 mv88e6xxx_6320_family(chip)) {
2642 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2643 0x0001);
2644 if (err)
2645 return err;
2646 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2647 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2648 0x0000);
2649 if (err)
2650 return err;
2651 }
2652
2653 /* Port Control 1: disable trunking, disable sending
2654 * learning messages to this port.
2655 */
2656 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2657 if (err)
2658 return err;
2659
2660 /* Port based VLAN map: give each port the same default address
2661 * database, and allow bidirectional communication between the
2662 * CPU and DSA port(s), and the other ports.
2663 */
2664 err = mv88e6xxx_port_set_fid(chip, port, 0);
2665 if (err)
2666 return err;
2667
2668 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2669 if (err)
2670 return err;
2671
2672 /* Default VLAN ID and priority: don't set a default VLAN
2673 * ID, and set the default packet priority to zero.
2674 */
2675 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2676 }
2677
2678 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2679 {
2680 int err;
2681
2682 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2683 if (err)
2684 return err;
2685
2686 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2687 if (err)
2688 return err;
2689
2690 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2691 if (err)
2692 return err;
2693
2694 return 0;
2695 }
2696
2697 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2698 unsigned int msecs)
2699 {
2700 const unsigned int coeff = chip->info->age_time_coeff;
2701 const unsigned int min = 0x01 * coeff;
2702 const unsigned int max = 0xff * coeff;
2703 u8 age_time;
2704 u16 val;
2705 int err;
2706
2707 if (msecs < min || msecs > max)
2708 return -ERANGE;
2709
2710 /* Round to nearest multiple of coeff */
2711 age_time = (msecs + coeff / 2) / coeff;
2712
2713 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2714 if (err)
2715 return err;
2716
2717 /* AgeTime is 11:4 bits */
2718 val &= ~0xff0;
2719 val |= age_time << 4;
2720
2721 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2722 }
2723
2724 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2725 unsigned int ageing_time)
2726 {
2727 struct mv88e6xxx_chip *chip = ds->priv;
2728 int err;
2729
2730 mutex_lock(&chip->reg_lock);
2731 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2732 mutex_unlock(&chip->reg_lock);
2733
2734 return err;
2735 }
2736
2737 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2738 {
2739 struct dsa_switch *ds = chip->ds;
2740 u32 upstream_port = dsa_upstream_port(ds);
2741 u16 reg;
2742 int err;
2743
2744 /* Enable the PHY Polling Unit if present, don't discard any packets,
2745 * and mask all interrupt sources.
2746 */
2747 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2748 if (err < 0)
2749 return err;
2750
2751 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
2752 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2753 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2754 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2755
2756 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2757 if (err)
2758 return err;
2759
2760 /* Configure the upstream port, and configure it as the port to which
2761 * ingress and egress and ARP monitor frames are to be sent.
2762 */
2763 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2764 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2765 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2766 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2767 if (err)
2768 return err;
2769
2770 /* Disable remote management, and set the switch's DSA device number. */
2771 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2772 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2773 (ds->index & 0x1f));
2774 if (err)
2775 return err;
2776
2777 /* Clear all the VTU and STU entries */
2778 err = _mv88e6xxx_vtu_stu_flush(chip);
2779 if (err < 0)
2780 return err;
2781
2782 /* Set the default address aging time to 5 minutes, and
2783 * enable address learn messages to be sent to all message
2784 * ports.
2785 */
2786 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2787 GLOBAL_ATU_CONTROL_LEARN2ALL);
2788 if (err)
2789 return err;
2790
2791 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2792 if (err)
2793 return err;
2794
2795 /* Clear all ATU entries */
2796 err = _mv88e6xxx_atu_flush(chip, 0, true);
2797 if (err)
2798 return err;
2799
2800 /* Configure the IP ToS mapping registers. */
2801 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2802 if (err)
2803 return err;
2804 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2805 if (err)
2806 return err;
2807 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2808 if (err)
2809 return err;
2810 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2811 if (err)
2812 return err;
2813 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2814 if (err)
2815 return err;
2816 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2817 if (err)
2818 return err;
2819 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2820 if (err)
2821 return err;
2822 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2823 if (err)
2824 return err;
2825
2826 /* Configure the IEEE 802.1p priority mapping register. */
2827 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2828 if (err)
2829 return err;
2830
2831 /* Initialize the statistics unit */
2832 err = mv88e6xxx_stats_set_histogram(chip);
2833 if (err)
2834 return err;
2835
2836 /* Clear the statistics counters for all ports */
2837 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2838 GLOBAL_STATS_OP_FLUSH_ALL);
2839 if (err)
2840 return err;
2841
2842 /* Wait for the flush to complete. */
2843 err = mv88e6xxx_g1_stats_wait(chip);
2844 if (err)
2845 return err;
2846
2847 return 0;
2848 }
2849
2850 static int mv88e6xxx_setup(struct dsa_switch *ds)
2851 {
2852 struct mv88e6xxx_chip *chip = ds->priv;
2853 int err;
2854 int i;
2855
2856 chip->ds = ds;
2857 ds->slave_mii_bus = chip->mdio_bus;
2858
2859 mutex_lock(&chip->reg_lock);
2860
2861 /* Setup Switch Port Registers */
2862 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2863 err = mv88e6xxx_setup_port(chip, i);
2864 if (err)
2865 goto unlock;
2866 }
2867
2868 /* Setup Switch Global 1 Registers */
2869 err = mv88e6xxx_g1_setup(chip);
2870 if (err)
2871 goto unlock;
2872
2873 /* Setup Switch Global 2 Registers */
2874 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2875 err = mv88e6xxx_g2_setup(chip);
2876 if (err)
2877 goto unlock;
2878 }
2879
2880 unlock:
2881 mutex_unlock(&chip->reg_lock);
2882
2883 return err;
2884 }
2885
2886 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2887 {
2888 struct mv88e6xxx_chip *chip = ds->priv;
2889 int err;
2890
2891 if (!chip->info->ops->set_switch_mac)
2892 return -EOPNOTSUPP;
2893
2894 mutex_lock(&chip->reg_lock);
2895 err = chip->info->ops->set_switch_mac(chip, addr);
2896 mutex_unlock(&chip->reg_lock);
2897
2898 return err;
2899 }
2900
2901 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2902 {
2903 struct mv88e6xxx_chip *chip = bus->priv;
2904 u16 val;
2905 int err;
2906
2907 if (phy >= mv88e6xxx_num_ports(chip))
2908 return 0xffff;
2909
2910 mutex_lock(&chip->reg_lock);
2911 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2912 mutex_unlock(&chip->reg_lock);
2913
2914 return err ? err : val;
2915 }
2916
2917 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2918 {
2919 struct mv88e6xxx_chip *chip = bus->priv;
2920 int err;
2921
2922 if (phy >= mv88e6xxx_num_ports(chip))
2923 return 0xffff;
2924
2925 mutex_lock(&chip->reg_lock);
2926 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2927 mutex_unlock(&chip->reg_lock);
2928
2929 return err;
2930 }
2931
2932 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2933 struct device_node *np)
2934 {
2935 static int index;
2936 struct mii_bus *bus;
2937 int err;
2938
2939 if (np)
2940 chip->mdio_np = of_get_child_by_name(np, "mdio");
2941
2942 bus = devm_mdiobus_alloc(chip->dev);
2943 if (!bus)
2944 return -ENOMEM;
2945
2946 bus->priv = (void *)chip;
2947 if (np) {
2948 bus->name = np->full_name;
2949 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2950 } else {
2951 bus->name = "mv88e6xxx SMI";
2952 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2953 }
2954
2955 bus->read = mv88e6xxx_mdio_read;
2956 bus->write = mv88e6xxx_mdio_write;
2957 bus->parent = chip->dev;
2958
2959 if (chip->mdio_np)
2960 err = of_mdiobus_register(bus, chip->mdio_np);
2961 else
2962 err = mdiobus_register(bus);
2963 if (err) {
2964 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2965 goto out;
2966 }
2967 chip->mdio_bus = bus;
2968
2969 return 0;
2970
2971 out:
2972 if (chip->mdio_np)
2973 of_node_put(chip->mdio_np);
2974
2975 return err;
2976 }
2977
2978 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
2979
2980 {
2981 struct mii_bus *bus = chip->mdio_bus;
2982
2983 mdiobus_unregister(bus);
2984
2985 if (chip->mdio_np)
2986 of_node_put(chip->mdio_np);
2987 }
2988
2989 #ifdef CONFIG_NET_DSA_HWMON
2990
2991 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2992 {
2993 struct mv88e6xxx_chip *chip = ds->priv;
2994 u16 val;
2995 int ret;
2996
2997 *temp = 0;
2998
2999 mutex_lock(&chip->reg_lock);
3000
3001 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3002 if (ret < 0)
3003 goto error;
3004
3005 /* Enable temperature sensor */
3006 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3007 if (ret < 0)
3008 goto error;
3009
3010 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3011 if (ret < 0)
3012 goto error;
3013
3014 /* Wait for temperature to stabilize */
3015 usleep_range(10000, 12000);
3016
3017 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3018 if (ret < 0)
3019 goto error;
3020
3021 /* Disable temperature sensor */
3022 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3023 if (ret < 0)
3024 goto error;
3025
3026 *temp = ((val & 0x1f) - 5) * 5;
3027
3028 error:
3029 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3030 mutex_unlock(&chip->reg_lock);
3031 return ret;
3032 }
3033
3034 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3035 {
3036 struct mv88e6xxx_chip *chip = ds->priv;
3037 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3038 u16 val;
3039 int ret;
3040
3041 *temp = 0;
3042
3043 mutex_lock(&chip->reg_lock);
3044 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3045 mutex_unlock(&chip->reg_lock);
3046 if (ret < 0)
3047 return ret;
3048
3049 *temp = (val & 0xff) - 25;
3050
3051 return 0;
3052 }
3053
3054 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3055 {
3056 struct mv88e6xxx_chip *chip = ds->priv;
3057
3058 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3059 return -EOPNOTSUPP;
3060
3061 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3062 return mv88e63xx_get_temp(ds, temp);
3063
3064 return mv88e61xx_get_temp(ds, temp);
3065 }
3066
3067 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3068 {
3069 struct mv88e6xxx_chip *chip = ds->priv;
3070 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3071 u16 val;
3072 int ret;
3073
3074 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3075 return -EOPNOTSUPP;
3076
3077 *temp = 0;
3078
3079 mutex_lock(&chip->reg_lock);
3080 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3081 mutex_unlock(&chip->reg_lock);
3082 if (ret < 0)
3083 return ret;
3084
3085 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3086
3087 return 0;
3088 }
3089
3090 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3091 {
3092 struct mv88e6xxx_chip *chip = ds->priv;
3093 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3094 u16 val;
3095 int err;
3096
3097 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3098 return -EOPNOTSUPP;
3099
3100 mutex_lock(&chip->reg_lock);
3101 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3102 if (err)
3103 goto unlock;
3104 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3105 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3106 (val & 0xe0ff) | (temp << 8));
3107 unlock:
3108 mutex_unlock(&chip->reg_lock);
3109
3110 return err;
3111 }
3112
3113 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3114 {
3115 struct mv88e6xxx_chip *chip = ds->priv;
3116 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3117 u16 val;
3118 int ret;
3119
3120 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3121 return -EOPNOTSUPP;
3122
3123 *alarm = false;
3124
3125 mutex_lock(&chip->reg_lock);
3126 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3127 mutex_unlock(&chip->reg_lock);
3128 if (ret < 0)
3129 return ret;
3130
3131 *alarm = !!(val & 0x40);
3132
3133 return 0;
3134 }
3135 #endif /* CONFIG_NET_DSA_HWMON */
3136
3137 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3138 {
3139 struct mv88e6xxx_chip *chip = ds->priv;
3140
3141 return chip->eeprom_len;
3142 }
3143
3144 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3145 struct ethtool_eeprom *eeprom, u8 *data)
3146 {
3147 struct mv88e6xxx_chip *chip = ds->priv;
3148 int err;
3149
3150 if (!chip->info->ops->get_eeprom)
3151 return -EOPNOTSUPP;
3152
3153 mutex_lock(&chip->reg_lock);
3154 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3155 mutex_unlock(&chip->reg_lock);
3156
3157 if (err)
3158 return err;
3159
3160 eeprom->magic = 0xc3ec4951;
3161
3162 return 0;
3163 }
3164
3165 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3166 struct ethtool_eeprom *eeprom, u8 *data)
3167 {
3168 struct mv88e6xxx_chip *chip = ds->priv;
3169 int err;
3170
3171 if (!chip->info->ops->set_eeprom)
3172 return -EOPNOTSUPP;
3173
3174 if (eeprom->magic != 0xc3ec4951)
3175 return -EINVAL;
3176
3177 mutex_lock(&chip->reg_lock);
3178 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3179 mutex_unlock(&chip->reg_lock);
3180
3181 return err;
3182 }
3183
3184 static const struct mv88e6xxx_ops mv88e6085_ops = {
3185 /* MV88E6XXX_FAMILY_6097 */
3186 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3187 .phy_read = mv88e6xxx_phy_ppu_read,
3188 .phy_write = mv88e6xxx_phy_ppu_write,
3189 .port_set_link = mv88e6xxx_port_set_link,
3190 .port_set_duplex = mv88e6xxx_port_set_duplex,
3191 .port_set_speed = mv88e6185_port_set_speed,
3192 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3193 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3194 .stats_get_strings = mv88e6095_stats_get_strings,
3195 .stats_get_stats = mv88e6095_stats_get_stats,
3196 };
3197
3198 static const struct mv88e6xxx_ops mv88e6095_ops = {
3199 /* MV88E6XXX_FAMILY_6095 */
3200 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3201 .phy_read = mv88e6xxx_phy_ppu_read,
3202 .phy_write = mv88e6xxx_phy_ppu_write,
3203 .port_set_link = mv88e6xxx_port_set_link,
3204 .port_set_duplex = mv88e6xxx_port_set_duplex,
3205 .port_set_speed = mv88e6185_port_set_speed,
3206 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3207 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3208 .stats_get_strings = mv88e6095_stats_get_strings,
3209 .stats_get_stats = mv88e6095_stats_get_stats,
3210 };
3211
3212 static const struct mv88e6xxx_ops mv88e6123_ops = {
3213 /* MV88E6XXX_FAMILY_6165 */
3214 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3215 .phy_read = mv88e6xxx_read,
3216 .phy_write = mv88e6xxx_write,
3217 .port_set_link = mv88e6xxx_port_set_link,
3218 .port_set_duplex = mv88e6xxx_port_set_duplex,
3219 .port_set_speed = mv88e6185_port_set_speed,
3220 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3221 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3222 .stats_get_strings = mv88e6095_stats_get_strings,
3223 .stats_get_stats = mv88e6095_stats_get_stats,
3224 };
3225
3226 static const struct mv88e6xxx_ops mv88e6131_ops = {
3227 /* MV88E6XXX_FAMILY_6185 */
3228 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3229 .phy_read = mv88e6xxx_phy_ppu_read,
3230 .phy_write = mv88e6xxx_phy_ppu_write,
3231 .port_set_link = mv88e6xxx_port_set_link,
3232 .port_set_duplex = mv88e6xxx_port_set_duplex,
3233 .port_set_speed = mv88e6185_port_set_speed,
3234 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3236 .stats_get_strings = mv88e6095_stats_get_strings,
3237 .stats_get_stats = mv88e6095_stats_get_stats,
3238 };
3239
3240 static const struct mv88e6xxx_ops mv88e6161_ops = {
3241 /* MV88E6XXX_FAMILY_6165 */
3242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3243 .phy_read = mv88e6xxx_read,
3244 .phy_write = mv88e6xxx_write,
3245 .port_set_link = mv88e6xxx_port_set_link,
3246 .port_set_duplex = mv88e6xxx_port_set_duplex,
3247 .port_set_speed = mv88e6185_port_set_speed,
3248 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3249 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3250 .stats_get_strings = mv88e6095_stats_get_strings,
3251 .stats_get_stats = mv88e6095_stats_get_stats,
3252 };
3253
3254 static const struct mv88e6xxx_ops mv88e6165_ops = {
3255 /* MV88E6XXX_FAMILY_6165 */
3256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3257 .phy_read = mv88e6xxx_read,
3258 .phy_write = mv88e6xxx_write,
3259 .port_set_link = mv88e6xxx_port_set_link,
3260 .port_set_duplex = mv88e6xxx_port_set_duplex,
3261 .port_set_speed = mv88e6185_port_set_speed,
3262 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3263 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3264 .stats_get_strings = mv88e6095_stats_get_strings,
3265 .stats_get_stats = mv88e6095_stats_get_stats,
3266 };
3267
3268 static const struct mv88e6xxx_ops mv88e6171_ops = {
3269 /* MV88E6XXX_FAMILY_6351 */
3270 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3271 .phy_read = mv88e6xxx_g2_smi_phy_read,
3272 .phy_write = mv88e6xxx_g2_smi_phy_write,
3273 .port_set_link = mv88e6xxx_port_set_link,
3274 .port_set_duplex = mv88e6xxx_port_set_duplex,
3275 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3276 .port_set_speed = mv88e6185_port_set_speed,
3277 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3278 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3279 .stats_get_strings = mv88e6095_stats_get_strings,
3280 .stats_get_stats = mv88e6095_stats_get_stats,
3281 };
3282
3283 static const struct mv88e6xxx_ops mv88e6172_ops = {
3284 /* MV88E6XXX_FAMILY_6352 */
3285 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3286 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3287 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3288 .phy_read = mv88e6xxx_g2_smi_phy_read,
3289 .phy_write = mv88e6xxx_g2_smi_phy_write,
3290 .port_set_link = mv88e6xxx_port_set_link,
3291 .port_set_duplex = mv88e6xxx_port_set_duplex,
3292 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3293 .port_set_speed = mv88e6352_port_set_speed,
3294 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3295 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3296 .stats_get_strings = mv88e6095_stats_get_strings,
3297 .stats_get_stats = mv88e6095_stats_get_stats,
3298 };
3299
3300 static const struct mv88e6xxx_ops mv88e6175_ops = {
3301 /* MV88E6XXX_FAMILY_6351 */
3302 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3303 .phy_read = mv88e6xxx_g2_smi_phy_read,
3304 .phy_write = mv88e6xxx_g2_smi_phy_write,
3305 .port_set_link = mv88e6xxx_port_set_link,
3306 .port_set_duplex = mv88e6xxx_port_set_duplex,
3307 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3308 .port_set_speed = mv88e6185_port_set_speed,
3309 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3310 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3311 .stats_get_strings = mv88e6095_stats_get_strings,
3312 .stats_get_stats = mv88e6095_stats_get_stats,
3313 };
3314
3315 static const struct mv88e6xxx_ops mv88e6176_ops = {
3316 /* MV88E6XXX_FAMILY_6352 */
3317 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3318 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3319 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3320 .phy_read = mv88e6xxx_g2_smi_phy_read,
3321 .phy_write = mv88e6xxx_g2_smi_phy_write,
3322 .port_set_link = mv88e6xxx_port_set_link,
3323 .port_set_duplex = mv88e6xxx_port_set_duplex,
3324 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3325 .port_set_speed = mv88e6352_port_set_speed,
3326 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3327 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3328 .stats_get_strings = mv88e6095_stats_get_strings,
3329 .stats_get_stats = mv88e6095_stats_get_stats,
3330 };
3331
3332 static const struct mv88e6xxx_ops mv88e6185_ops = {
3333 /* MV88E6XXX_FAMILY_6185 */
3334 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3335 .phy_read = mv88e6xxx_phy_ppu_read,
3336 .phy_write = mv88e6xxx_phy_ppu_write,
3337 .port_set_link = mv88e6xxx_port_set_link,
3338 .port_set_duplex = mv88e6xxx_port_set_duplex,
3339 .port_set_speed = mv88e6185_port_set_speed,
3340 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3341 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3342 .stats_get_strings = mv88e6095_stats_get_strings,
3343 .stats_get_stats = mv88e6095_stats_get_stats,
3344 };
3345
3346 static const struct mv88e6xxx_ops mv88e6190_ops = {
3347 /* MV88E6XXX_FAMILY_6390 */
3348 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3349 .phy_read = mv88e6xxx_g2_smi_phy_read,
3350 .phy_write = mv88e6xxx_g2_smi_phy_write,
3351 .port_set_link = mv88e6xxx_port_set_link,
3352 .port_set_duplex = mv88e6xxx_port_set_duplex,
3353 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3354 .port_set_speed = mv88e6390_port_set_speed,
3355 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3356 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3357 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3358 .stats_get_strings = mv88e6320_stats_get_strings,
3359 .stats_get_stats = mv88e6390_stats_get_stats,
3360 };
3361
3362 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3363 /* MV88E6XXX_FAMILY_6390 */
3364 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3365 .phy_read = mv88e6xxx_g2_smi_phy_read,
3366 .phy_write = mv88e6xxx_g2_smi_phy_write,
3367 .port_set_link = mv88e6xxx_port_set_link,
3368 .port_set_duplex = mv88e6xxx_port_set_duplex,
3369 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3370 .port_set_speed = mv88e6390x_port_set_speed,
3371 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3372 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3373 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3374 .stats_get_strings = mv88e6320_stats_get_strings,
3375 .stats_get_stats = mv88e6390_stats_get_stats,
3376 };
3377
3378 static const struct mv88e6xxx_ops mv88e6191_ops = {
3379 /* MV88E6XXX_FAMILY_6390 */
3380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3381 .phy_read = mv88e6xxx_g2_smi_phy_read,
3382 .phy_write = mv88e6xxx_g2_smi_phy_write,
3383 .port_set_link = mv88e6xxx_port_set_link,
3384 .port_set_duplex = mv88e6xxx_port_set_duplex,
3385 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3386 .port_set_speed = mv88e6390_port_set_speed,
3387 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3388 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3389 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3390 .stats_get_strings = mv88e6320_stats_get_strings,
3391 .stats_get_stats = mv88e6390_stats_get_stats,
3392 };
3393
3394 static const struct mv88e6xxx_ops mv88e6240_ops = {
3395 /* MV88E6XXX_FAMILY_6352 */
3396 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3397 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3399 .phy_read = mv88e6xxx_g2_smi_phy_read,
3400 .phy_write = mv88e6xxx_g2_smi_phy_write,
3401 .port_set_link = mv88e6xxx_port_set_link,
3402 .port_set_duplex = mv88e6xxx_port_set_duplex,
3403 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3404 .port_set_speed = mv88e6352_port_set_speed,
3405 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3406 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3407 .stats_get_strings = mv88e6095_stats_get_strings,
3408 .stats_get_stats = mv88e6095_stats_get_stats,
3409 };
3410
3411 static const struct mv88e6xxx_ops mv88e6290_ops = {
3412 /* MV88E6XXX_FAMILY_6390 */
3413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3414 .phy_read = mv88e6xxx_g2_smi_phy_read,
3415 .phy_write = mv88e6xxx_g2_smi_phy_write,
3416 .port_set_link = mv88e6xxx_port_set_link,
3417 .port_set_duplex = mv88e6xxx_port_set_duplex,
3418 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3419 .port_set_speed = mv88e6390_port_set_speed,
3420 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3421 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3422 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3423 .stats_get_strings = mv88e6320_stats_get_strings,
3424 .stats_get_stats = mv88e6390_stats_get_stats,
3425 };
3426
3427 static const struct mv88e6xxx_ops mv88e6320_ops = {
3428 /* MV88E6XXX_FAMILY_6320 */
3429 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3430 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3431 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3432 .phy_read = mv88e6xxx_g2_smi_phy_read,
3433 .phy_write = mv88e6xxx_g2_smi_phy_write,
3434 .port_set_link = mv88e6xxx_port_set_link,
3435 .port_set_duplex = mv88e6xxx_port_set_duplex,
3436 .port_set_speed = mv88e6185_port_set_speed,
3437 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3438 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3439 .stats_get_strings = mv88e6320_stats_get_strings,
3440 .stats_get_stats = mv88e6320_stats_get_stats,
3441 };
3442
3443 static const struct mv88e6xxx_ops mv88e6321_ops = {
3444 /* MV88E6XXX_FAMILY_6321 */
3445 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3446 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3447 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3448 .phy_read = mv88e6xxx_g2_smi_phy_read,
3449 .phy_write = mv88e6xxx_g2_smi_phy_write,
3450 .port_set_link = mv88e6xxx_port_set_link,
3451 .port_set_duplex = mv88e6xxx_port_set_duplex,
3452 .port_set_speed = mv88e6185_port_set_speed,
3453 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3454 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3455 .stats_get_strings = mv88e6320_stats_get_strings,
3456 .stats_get_stats = mv88e6320_stats_get_stats,
3457 };
3458
3459 static const struct mv88e6xxx_ops mv88e6350_ops = {
3460 /* MV88E6XXX_FAMILY_6351 */
3461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3462 .phy_read = mv88e6xxx_g2_smi_phy_read,
3463 .phy_write = mv88e6xxx_g2_smi_phy_write,
3464 .port_set_link = mv88e6xxx_port_set_link,
3465 .port_set_duplex = mv88e6xxx_port_set_duplex,
3466 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3467 .port_set_speed = mv88e6185_port_set_speed,
3468 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3469 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3470 .stats_get_strings = mv88e6095_stats_get_strings,
3471 .stats_get_stats = mv88e6095_stats_get_stats,
3472 };
3473
3474 static const struct mv88e6xxx_ops mv88e6351_ops = {
3475 /* MV88E6XXX_FAMILY_6351 */
3476 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3477 .phy_read = mv88e6xxx_g2_smi_phy_read,
3478 .phy_write = mv88e6xxx_g2_smi_phy_write,
3479 .port_set_link = mv88e6xxx_port_set_link,
3480 .port_set_duplex = mv88e6xxx_port_set_duplex,
3481 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3482 .port_set_speed = mv88e6185_port_set_speed,
3483 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3484 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3485 .stats_get_strings = mv88e6095_stats_get_strings,
3486 .stats_get_stats = mv88e6095_stats_get_stats,
3487 };
3488
3489 static const struct mv88e6xxx_ops mv88e6352_ops = {
3490 /* MV88E6XXX_FAMILY_6352 */
3491 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3492 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3494 .phy_read = mv88e6xxx_g2_smi_phy_read,
3495 .phy_write = mv88e6xxx_g2_smi_phy_write,
3496 .port_set_link = mv88e6xxx_port_set_link,
3497 .port_set_duplex = mv88e6xxx_port_set_duplex,
3498 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3499 .port_set_speed = mv88e6352_port_set_speed,
3500 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3501 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3502 .stats_get_strings = mv88e6095_stats_get_strings,
3503 .stats_get_stats = mv88e6095_stats_get_stats,
3504 };
3505
3506 static const struct mv88e6xxx_ops mv88e6390_ops = {
3507 /* MV88E6XXX_FAMILY_6390 */
3508 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3509 .phy_read = mv88e6xxx_g2_smi_phy_read,
3510 .phy_write = mv88e6xxx_g2_smi_phy_write,
3511 .port_set_link = mv88e6xxx_port_set_link,
3512 .port_set_duplex = mv88e6xxx_port_set_duplex,
3513 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3514 .port_set_speed = mv88e6390_port_set_speed,
3515 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3516 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3517 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3518 .stats_get_strings = mv88e6320_stats_get_strings,
3519 .stats_get_stats = mv88e6390_stats_get_stats,
3520 };
3521
3522 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3523 /* MV88E6XXX_FAMILY_6390 */
3524 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3525 .phy_read = mv88e6xxx_g2_smi_phy_read,
3526 .phy_write = mv88e6xxx_g2_smi_phy_write,
3527 .port_set_link = mv88e6xxx_port_set_link,
3528 .port_set_duplex = mv88e6xxx_port_set_duplex,
3529 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3530 .port_set_speed = mv88e6390x_port_set_speed,
3531 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3532 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3533 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3534 .stats_get_strings = mv88e6320_stats_get_strings,
3535 .stats_get_stats = mv88e6390_stats_get_stats,
3536 };
3537
3538 static const struct mv88e6xxx_ops mv88e6391_ops = {
3539 /* MV88E6XXX_FAMILY_6390 */
3540 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3541 .phy_read = mv88e6xxx_g2_smi_phy_read,
3542 .phy_write = mv88e6xxx_g2_smi_phy_write,
3543 .port_set_link = mv88e6xxx_port_set_link,
3544 .port_set_duplex = mv88e6xxx_port_set_duplex,
3545 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3546 .port_set_speed = mv88e6390_port_set_speed,
3547 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3548 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3549 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3550 .stats_get_strings = mv88e6320_stats_get_strings,
3551 .stats_get_stats = mv88e6390_stats_get_stats,
3552 };
3553
3554 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3555 [MV88E6085] = {
3556 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3557 .family = MV88E6XXX_FAMILY_6097,
3558 .name = "Marvell 88E6085",
3559 .num_databases = 4096,
3560 .num_ports = 10,
3561 .port_base_addr = 0x10,
3562 .global1_addr = 0x1b,
3563 .age_time_coeff = 15000,
3564 .g1_irqs = 8,
3565 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3566 .ops = &mv88e6085_ops,
3567 },
3568
3569 [MV88E6095] = {
3570 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3571 .family = MV88E6XXX_FAMILY_6095,
3572 .name = "Marvell 88E6095/88E6095F",
3573 .num_databases = 256,
3574 .num_ports = 11,
3575 .port_base_addr = 0x10,
3576 .global1_addr = 0x1b,
3577 .age_time_coeff = 15000,
3578 .g1_irqs = 8,
3579 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3580 .ops = &mv88e6095_ops,
3581 },
3582
3583 [MV88E6123] = {
3584 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3585 .family = MV88E6XXX_FAMILY_6165,
3586 .name = "Marvell 88E6123",
3587 .num_databases = 4096,
3588 .num_ports = 3,
3589 .port_base_addr = 0x10,
3590 .global1_addr = 0x1b,
3591 .age_time_coeff = 15000,
3592 .g1_irqs = 9,
3593 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3594 .ops = &mv88e6123_ops,
3595 },
3596
3597 [MV88E6131] = {
3598 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3599 .family = MV88E6XXX_FAMILY_6185,
3600 .name = "Marvell 88E6131",
3601 .num_databases = 256,
3602 .num_ports = 8,
3603 .port_base_addr = 0x10,
3604 .global1_addr = 0x1b,
3605 .age_time_coeff = 15000,
3606 .g1_irqs = 9,
3607 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3608 .ops = &mv88e6131_ops,
3609 },
3610
3611 [MV88E6161] = {
3612 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3613 .family = MV88E6XXX_FAMILY_6165,
3614 .name = "Marvell 88E6161",
3615 .num_databases = 4096,
3616 .num_ports = 6,
3617 .port_base_addr = 0x10,
3618 .global1_addr = 0x1b,
3619 .age_time_coeff = 15000,
3620 .g1_irqs = 9,
3621 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3622 .ops = &mv88e6161_ops,
3623 },
3624
3625 [MV88E6165] = {
3626 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3627 .family = MV88E6XXX_FAMILY_6165,
3628 .name = "Marvell 88E6165",
3629 .num_databases = 4096,
3630 .num_ports = 6,
3631 .port_base_addr = 0x10,
3632 .global1_addr = 0x1b,
3633 .age_time_coeff = 15000,
3634 .g1_irqs = 9,
3635 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3636 .ops = &mv88e6165_ops,
3637 },
3638
3639 [MV88E6171] = {
3640 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3641 .family = MV88E6XXX_FAMILY_6351,
3642 .name = "Marvell 88E6171",
3643 .num_databases = 4096,
3644 .num_ports = 7,
3645 .port_base_addr = 0x10,
3646 .global1_addr = 0x1b,
3647 .age_time_coeff = 15000,
3648 .g1_irqs = 9,
3649 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3650 .ops = &mv88e6171_ops,
3651 },
3652
3653 [MV88E6172] = {
3654 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3655 .family = MV88E6XXX_FAMILY_6352,
3656 .name = "Marvell 88E6172",
3657 .num_databases = 4096,
3658 .num_ports = 7,
3659 .port_base_addr = 0x10,
3660 .global1_addr = 0x1b,
3661 .age_time_coeff = 15000,
3662 .g1_irqs = 9,
3663 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3664 .ops = &mv88e6172_ops,
3665 },
3666
3667 [MV88E6175] = {
3668 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3669 .family = MV88E6XXX_FAMILY_6351,
3670 .name = "Marvell 88E6175",
3671 .num_databases = 4096,
3672 .num_ports = 7,
3673 .port_base_addr = 0x10,
3674 .global1_addr = 0x1b,
3675 .age_time_coeff = 15000,
3676 .g1_irqs = 9,
3677 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3678 .ops = &mv88e6175_ops,
3679 },
3680
3681 [MV88E6176] = {
3682 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3683 .family = MV88E6XXX_FAMILY_6352,
3684 .name = "Marvell 88E6176",
3685 .num_databases = 4096,
3686 .num_ports = 7,
3687 .port_base_addr = 0x10,
3688 .global1_addr = 0x1b,
3689 .age_time_coeff = 15000,
3690 .g1_irqs = 9,
3691 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3692 .ops = &mv88e6176_ops,
3693 },
3694
3695 [MV88E6185] = {
3696 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3697 .family = MV88E6XXX_FAMILY_6185,
3698 .name = "Marvell 88E6185",
3699 .num_databases = 256,
3700 .num_ports = 10,
3701 .port_base_addr = 0x10,
3702 .global1_addr = 0x1b,
3703 .age_time_coeff = 15000,
3704 .g1_irqs = 8,
3705 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3706 .ops = &mv88e6185_ops,
3707 },
3708
3709 [MV88E6190] = {
3710 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3711 .family = MV88E6XXX_FAMILY_6390,
3712 .name = "Marvell 88E6190",
3713 .num_databases = 4096,
3714 .num_ports = 11, /* 10 + Z80 */
3715 .port_base_addr = 0x0,
3716 .global1_addr = 0x1b,
3717 .age_time_coeff = 15000,
3718 .g1_irqs = 9,
3719 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3720 .ops = &mv88e6190_ops,
3721 },
3722
3723 [MV88E6190X] = {
3724 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3725 .family = MV88E6XXX_FAMILY_6390,
3726 .name = "Marvell 88E6190X",
3727 .num_databases = 4096,
3728 .num_ports = 11, /* 10 + Z80 */
3729 .port_base_addr = 0x0,
3730 .global1_addr = 0x1b,
3731 .age_time_coeff = 15000,
3732 .g1_irqs = 9,
3733 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3734 .ops = &mv88e6190x_ops,
3735 },
3736
3737 [MV88E6191] = {
3738 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3739 .family = MV88E6XXX_FAMILY_6390,
3740 .name = "Marvell 88E6191",
3741 .num_databases = 4096,
3742 .num_ports = 11, /* 10 + Z80 */
3743 .port_base_addr = 0x0,
3744 .global1_addr = 0x1b,
3745 .age_time_coeff = 15000,
3746 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3747 .ops = &mv88e6391_ops,
3748 },
3749
3750 [MV88E6240] = {
3751 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3752 .family = MV88E6XXX_FAMILY_6352,
3753 .name = "Marvell 88E6240",
3754 .num_databases = 4096,
3755 .num_ports = 7,
3756 .port_base_addr = 0x10,
3757 .global1_addr = 0x1b,
3758 .age_time_coeff = 15000,
3759 .g1_irqs = 9,
3760 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3761 .ops = &mv88e6240_ops,
3762 },
3763
3764 [MV88E6290] = {
3765 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3766 .family = MV88E6XXX_FAMILY_6390,
3767 .name = "Marvell 88E6290",
3768 .num_databases = 4096,
3769 .num_ports = 11, /* 10 + Z80 */
3770 .port_base_addr = 0x0,
3771 .global1_addr = 0x1b,
3772 .age_time_coeff = 15000,
3773 .g1_irqs = 9,
3774 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3775 .ops = &mv88e6290_ops,
3776 },
3777
3778 [MV88E6320] = {
3779 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3780 .family = MV88E6XXX_FAMILY_6320,
3781 .name = "Marvell 88E6320",
3782 .num_databases = 4096,
3783 .num_ports = 7,
3784 .port_base_addr = 0x10,
3785 .global1_addr = 0x1b,
3786 .age_time_coeff = 15000,
3787 .g1_irqs = 8,
3788 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3789 .ops = &mv88e6320_ops,
3790 },
3791
3792 [MV88E6321] = {
3793 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3794 .family = MV88E6XXX_FAMILY_6320,
3795 .name = "Marvell 88E6321",
3796 .num_databases = 4096,
3797 .num_ports = 7,
3798 .port_base_addr = 0x10,
3799 .global1_addr = 0x1b,
3800 .age_time_coeff = 15000,
3801 .g1_irqs = 8,
3802 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3803 .ops = &mv88e6321_ops,
3804 },
3805
3806 [MV88E6350] = {
3807 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3808 .family = MV88E6XXX_FAMILY_6351,
3809 .name = "Marvell 88E6350",
3810 .num_databases = 4096,
3811 .num_ports = 7,
3812 .port_base_addr = 0x10,
3813 .global1_addr = 0x1b,
3814 .age_time_coeff = 15000,
3815 .g1_irqs = 9,
3816 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3817 .ops = &mv88e6350_ops,
3818 },
3819
3820 [MV88E6351] = {
3821 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3822 .family = MV88E6XXX_FAMILY_6351,
3823 .name = "Marvell 88E6351",
3824 .num_databases = 4096,
3825 .num_ports = 7,
3826 .port_base_addr = 0x10,
3827 .global1_addr = 0x1b,
3828 .age_time_coeff = 15000,
3829 .g1_irqs = 9,
3830 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3831 .ops = &mv88e6351_ops,
3832 },
3833
3834 [MV88E6352] = {
3835 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3836 .family = MV88E6XXX_FAMILY_6352,
3837 .name = "Marvell 88E6352",
3838 .num_databases = 4096,
3839 .num_ports = 7,
3840 .port_base_addr = 0x10,
3841 .global1_addr = 0x1b,
3842 .age_time_coeff = 15000,
3843 .g1_irqs = 9,
3844 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3845 .ops = &mv88e6352_ops,
3846 },
3847 [MV88E6390] = {
3848 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3849 .family = MV88E6XXX_FAMILY_6390,
3850 .name = "Marvell 88E6390",
3851 .num_databases = 4096,
3852 .num_ports = 11, /* 10 + Z80 */
3853 .port_base_addr = 0x0,
3854 .global1_addr = 0x1b,
3855 .age_time_coeff = 15000,
3856 .g1_irqs = 9,
3857 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3858 .ops = &mv88e6390_ops,
3859 },
3860 [MV88E6390X] = {
3861 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3862 .family = MV88E6XXX_FAMILY_6390,
3863 .name = "Marvell 88E6390X",
3864 .num_databases = 4096,
3865 .num_ports = 11, /* 10 + Z80 */
3866 .port_base_addr = 0x0,
3867 .global1_addr = 0x1b,
3868 .age_time_coeff = 15000,
3869 .g1_irqs = 9,
3870 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3871 .ops = &mv88e6390x_ops,
3872 },
3873 };
3874
3875 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3876 {
3877 int i;
3878
3879 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3880 if (mv88e6xxx_table[i].prod_num == prod_num)
3881 return &mv88e6xxx_table[i];
3882
3883 return NULL;
3884 }
3885
3886 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3887 {
3888 const struct mv88e6xxx_info *info;
3889 unsigned int prod_num, rev;
3890 u16 id;
3891 int err;
3892
3893 mutex_lock(&chip->reg_lock);
3894 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3895 mutex_unlock(&chip->reg_lock);
3896 if (err)
3897 return err;
3898
3899 prod_num = (id & 0xfff0) >> 4;
3900 rev = id & 0x000f;
3901
3902 info = mv88e6xxx_lookup_info(prod_num);
3903 if (!info)
3904 return -ENODEV;
3905
3906 /* Update the compatible info with the probed one */
3907 chip->info = info;
3908
3909 err = mv88e6xxx_g2_require(chip);
3910 if (err)
3911 return err;
3912
3913 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3914 chip->info->prod_num, chip->info->name, rev);
3915
3916 return 0;
3917 }
3918
3919 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3920 {
3921 struct mv88e6xxx_chip *chip;
3922
3923 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3924 if (!chip)
3925 return NULL;
3926
3927 chip->dev = dev;
3928
3929 mutex_init(&chip->reg_lock);
3930
3931 return chip;
3932 }
3933
3934 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3935 {
3936 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3937 mv88e6xxx_ppu_state_init(chip);
3938 }
3939
3940 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3941 {
3942 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3943 mv88e6xxx_ppu_state_destroy(chip);
3944 }
3945
3946 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3947 struct mii_bus *bus, int sw_addr)
3948 {
3949 /* ADDR[0] pin is unavailable externally and considered zero */
3950 if (sw_addr & 0x1)
3951 return -EINVAL;
3952
3953 if (sw_addr == 0)
3954 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3955 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3956 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3957 else
3958 return -EINVAL;
3959
3960 chip->bus = bus;
3961 chip->sw_addr = sw_addr;
3962
3963 return 0;
3964 }
3965
3966 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3967 {
3968 struct mv88e6xxx_chip *chip = ds->priv;
3969
3970 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3971 return DSA_TAG_PROTO_EDSA;
3972
3973 return DSA_TAG_PROTO_DSA;
3974 }
3975
3976 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3977 struct device *host_dev, int sw_addr,
3978 void **priv)
3979 {
3980 struct mv88e6xxx_chip *chip;
3981 struct mii_bus *bus;
3982 int err;
3983
3984 bus = dsa_host_dev_to_mii_bus(host_dev);
3985 if (!bus)
3986 return NULL;
3987
3988 chip = mv88e6xxx_alloc_chip(dsa_dev);
3989 if (!chip)
3990 return NULL;
3991
3992 /* Legacy SMI probing will only support chips similar to 88E6085 */
3993 chip->info = &mv88e6xxx_table[MV88E6085];
3994
3995 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3996 if (err)
3997 goto free;
3998
3999 err = mv88e6xxx_detect(chip);
4000 if (err)
4001 goto free;
4002
4003 mutex_lock(&chip->reg_lock);
4004 err = mv88e6xxx_switch_reset(chip);
4005 mutex_unlock(&chip->reg_lock);
4006 if (err)
4007 goto free;
4008
4009 mv88e6xxx_phy_init(chip);
4010
4011 err = mv88e6xxx_mdio_register(chip, NULL);
4012 if (err)
4013 goto free;
4014
4015 *priv = chip;
4016
4017 return chip->info->name;
4018 free:
4019 devm_kfree(dsa_dev, chip);
4020
4021 return NULL;
4022 }
4023
4024 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4025 const struct switchdev_obj_port_mdb *mdb,
4026 struct switchdev_trans *trans)
4027 {
4028 /* We don't need any dynamic resource from the kernel (yet),
4029 * so skip the prepare phase.
4030 */
4031
4032 return 0;
4033 }
4034
4035 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4036 const struct switchdev_obj_port_mdb *mdb,
4037 struct switchdev_trans *trans)
4038 {
4039 struct mv88e6xxx_chip *chip = ds->priv;
4040
4041 mutex_lock(&chip->reg_lock);
4042 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4043 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4044 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4045 mutex_unlock(&chip->reg_lock);
4046 }
4047
4048 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4049 const struct switchdev_obj_port_mdb *mdb)
4050 {
4051 struct mv88e6xxx_chip *chip = ds->priv;
4052 int err;
4053
4054 mutex_lock(&chip->reg_lock);
4055 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4056 GLOBAL_ATU_DATA_STATE_UNUSED);
4057 mutex_unlock(&chip->reg_lock);
4058
4059 return err;
4060 }
4061
4062 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4063 struct switchdev_obj_port_mdb *mdb,
4064 int (*cb)(struct switchdev_obj *obj))
4065 {
4066 struct mv88e6xxx_chip *chip = ds->priv;
4067 int err;
4068
4069 mutex_lock(&chip->reg_lock);
4070 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4071 mutex_unlock(&chip->reg_lock);
4072
4073 return err;
4074 }
4075
4076 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
4077 .probe = mv88e6xxx_drv_probe,
4078 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4079 .setup = mv88e6xxx_setup,
4080 .set_addr = mv88e6xxx_set_addr,
4081 .adjust_link = mv88e6xxx_adjust_link,
4082 .get_strings = mv88e6xxx_get_strings,
4083 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4084 .get_sset_count = mv88e6xxx_get_sset_count,
4085 .set_eee = mv88e6xxx_set_eee,
4086 .get_eee = mv88e6xxx_get_eee,
4087 #ifdef CONFIG_NET_DSA_HWMON
4088 .get_temp = mv88e6xxx_get_temp,
4089 .get_temp_limit = mv88e6xxx_get_temp_limit,
4090 .set_temp_limit = mv88e6xxx_set_temp_limit,
4091 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4092 #endif
4093 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4094 .get_eeprom = mv88e6xxx_get_eeprom,
4095 .set_eeprom = mv88e6xxx_set_eeprom,
4096 .get_regs_len = mv88e6xxx_get_regs_len,
4097 .get_regs = mv88e6xxx_get_regs,
4098 .set_ageing_time = mv88e6xxx_set_ageing_time,
4099 .port_bridge_join = mv88e6xxx_port_bridge_join,
4100 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4101 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4102 .port_fast_age = mv88e6xxx_port_fast_age,
4103 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4104 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4105 .port_vlan_add = mv88e6xxx_port_vlan_add,
4106 .port_vlan_del = mv88e6xxx_port_vlan_del,
4107 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4108 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4109 .port_fdb_add = mv88e6xxx_port_fdb_add,
4110 .port_fdb_del = mv88e6xxx_port_fdb_del,
4111 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4112 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4113 .port_mdb_add = mv88e6xxx_port_mdb_add,
4114 .port_mdb_del = mv88e6xxx_port_mdb_del,
4115 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4116 };
4117
4118 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4119 struct device_node *np)
4120 {
4121 struct device *dev = chip->dev;
4122 struct dsa_switch *ds;
4123
4124 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4125 if (!ds)
4126 return -ENOMEM;
4127
4128 ds->dev = dev;
4129 ds->priv = chip;
4130 ds->ops = &mv88e6xxx_switch_ops;
4131
4132 dev_set_drvdata(dev, ds);
4133
4134 return dsa_register_switch(ds, np);
4135 }
4136
4137 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4138 {
4139 dsa_unregister_switch(chip->ds);
4140 }
4141
4142 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4143 {
4144 struct device *dev = &mdiodev->dev;
4145 struct device_node *np = dev->of_node;
4146 const struct mv88e6xxx_info *compat_info;
4147 struct mv88e6xxx_chip *chip;
4148 u32 eeprom_len;
4149 int err;
4150
4151 compat_info = of_device_get_match_data(dev);
4152 if (!compat_info)
4153 return -EINVAL;
4154
4155 chip = mv88e6xxx_alloc_chip(dev);
4156 if (!chip)
4157 return -ENOMEM;
4158
4159 chip->info = compat_info;
4160
4161 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4162 if (err)
4163 return err;
4164
4165 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4166 if (IS_ERR(chip->reset))
4167 return PTR_ERR(chip->reset);
4168
4169 err = mv88e6xxx_detect(chip);
4170 if (err)
4171 return err;
4172
4173 mv88e6xxx_phy_init(chip);
4174
4175 if (chip->info->ops->get_eeprom &&
4176 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4177 chip->eeprom_len = eeprom_len;
4178
4179 mutex_lock(&chip->reg_lock);
4180 err = mv88e6xxx_switch_reset(chip);
4181 mutex_unlock(&chip->reg_lock);
4182 if (err)
4183 goto out;
4184
4185 chip->irq = of_irq_get(np, 0);
4186 if (chip->irq == -EPROBE_DEFER) {
4187 err = chip->irq;
4188 goto out;
4189 }
4190
4191 if (chip->irq > 0) {
4192 /* Has to be performed before the MDIO bus is created,
4193 * because the PHYs will link there interrupts to these
4194 * interrupt controllers
4195 */
4196 mutex_lock(&chip->reg_lock);
4197 err = mv88e6xxx_g1_irq_setup(chip);
4198 mutex_unlock(&chip->reg_lock);
4199
4200 if (err)
4201 goto out;
4202
4203 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4204 err = mv88e6xxx_g2_irq_setup(chip);
4205 if (err)
4206 goto out_g1_irq;
4207 }
4208 }
4209
4210 err = mv88e6xxx_mdio_register(chip, np);
4211 if (err)
4212 goto out_g2_irq;
4213
4214 err = mv88e6xxx_register_switch(chip, np);
4215 if (err)
4216 goto out_mdio;
4217
4218 return 0;
4219
4220 out_mdio:
4221 mv88e6xxx_mdio_unregister(chip);
4222 out_g2_irq:
4223 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4224 mv88e6xxx_g2_irq_free(chip);
4225 out_g1_irq:
4226 if (chip->irq > 0) {
4227 mutex_lock(&chip->reg_lock);
4228 mv88e6xxx_g1_irq_free(chip);
4229 mutex_unlock(&chip->reg_lock);
4230 }
4231 out:
4232 return err;
4233 }
4234
4235 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4236 {
4237 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4238 struct mv88e6xxx_chip *chip = ds->priv;
4239
4240 mv88e6xxx_phy_destroy(chip);
4241 mv88e6xxx_unregister_switch(chip);
4242 mv88e6xxx_mdio_unregister(chip);
4243
4244 if (chip->irq > 0) {
4245 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4246 mv88e6xxx_g2_irq_free(chip);
4247 mv88e6xxx_g1_irq_free(chip);
4248 }
4249 }
4250
4251 static const struct of_device_id mv88e6xxx_of_match[] = {
4252 {
4253 .compatible = "marvell,mv88e6085",
4254 .data = &mv88e6xxx_table[MV88E6085],
4255 },
4256 {
4257 .compatible = "marvell,mv88e6190",
4258 .data = &mv88e6xxx_table[MV88E6190],
4259 },
4260 { /* sentinel */ },
4261 };
4262
4263 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4264
4265 static struct mdio_driver mv88e6xxx_driver = {
4266 .probe = mv88e6xxx_probe,
4267 .remove = mv88e6xxx_remove,
4268 .mdiodrv.driver = {
4269 .name = "mv88e6085",
4270 .of_match_table = mv88e6xxx_of_match,
4271 },
4272 };
4273
4274 static int __init mv88e6xxx_init(void)
4275 {
4276 register_switch_driver(&mv88e6xxx_switch_ops);
4277 return mdio_driver_register(&mv88e6xxx_driver);
4278 }
4279 module_init(mv88e6xxx_init);
4280
4281 static void __exit mv88e6xxx_cleanup(void)
4282 {
4283 mdio_driver_unregister(&mv88e6xxx_driver);
4284 unregister_switch_driver(&mv88e6xxx_switch_ops);
4285 }
4286 module_exit(mv88e6xxx_cleanup);
4287
4288 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4289 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4290 MODULE_LICENSE("GPL");
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