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net: dsa: mv88e6xxx: move VTU flush
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 /*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
34 #include <net/dsa.h>
35 #include <net/switchdev.h>
36
37 #include "mv88e6xxx.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "port.h"
41
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
43 {
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
46 dump_stack();
47 }
48 }
49
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
60 */
61
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
64 {
65 if (!chip->smi_ops)
66 return -EOPNOTSUPP;
67
68 return chip->smi_ops->read(chip, addr, reg, val);
69 }
70
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
73 {
74 if (!chip->smi_ops)
75 return -EOPNOTSUPP;
76
77 return chip->smi_ops->write(chip, addr, reg, val);
78 }
79
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
82 {
83 int ret;
84
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92 }
93
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
96 {
97 int ret;
98
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
100 if (ret < 0)
101 return ret;
102
103 return 0;
104 }
105
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109 };
110
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
112 {
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
118 if (ret < 0)
119 return ret;
120
121 if ((ret & SMI_CMD_BUSY) == 0)
122 return 0;
123 }
124
125 return -ETIMEDOUT;
126 }
127
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
130 {
131 int ret;
132
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
135 if (ret < 0)
136 return ret;
137
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
141 if (ret < 0)
142 return ret;
143
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
146 if (ret < 0)
147 return ret;
148
149 /* Read the data. */
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
151 if (ret < 0)
152 return ret;
153
154 *val = ret & 0xffff;
155
156 return 0;
157 }
158
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
161 {
162 int ret;
163
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
182 if (ret < 0)
183 return ret;
184
185 return 0;
186 }
187
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191 };
192
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
194 {
195 int err;
196
197 assert_reg_lock(chip);
198
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
200 if (err)
201 return err;
202
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
204 addr, reg, *val);
205
206 return 0;
207 }
208
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
210 {
211 int err;
212
213 assert_reg_lock(chip);
214
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
216 if (err)
217 return err;
218
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
220 addr, reg, val);
221
222 return 0;
223 }
224
225 static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
228 {
229 return mv88e6xxx_read(chip, addr, reg, val);
230 }
231
232 static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
235 {
236 return mv88e6xxx_write(chip, addr, reg, val);
237 }
238
239 static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240 {
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249 }
250
251 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253 {
254 int addr = phy; /* PHY devices addresses start at 0x0 */
255 struct mii_bus *bus;
256
257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
259 return -EOPNOTSUPP;
260
261 if (!chip->info->ops->phy_read)
262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
265 }
266
267 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269 {
270 int addr = phy; /* PHY devices addresses start at 0x0 */
271 struct mii_bus *bus;
272
273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
275 return -EOPNOTSUPP;
276
277 if (!chip->info->ops->phy_write)
278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
281 }
282
283 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284 {
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289 }
290
291 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292 {
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301 }
302
303 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305 {
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319 }
320
321 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323 {
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337 }
338
339 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340 {
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343 }
344
345 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346 {
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349 }
350
351 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352 {
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357 }
358
359 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360 {
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365 }
366
367 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368 {
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390 out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392 }
393
394 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395 {
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399 }
400
401 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402 {
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419 out:
420 mutex_unlock(&chip->reg_lock);
421 }
422
423 static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429 };
430
431 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434 {
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442 }
443
444 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447 };
448
449 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450 {
451 int irq, virq;
452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
459
460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
462 irq_dispose_mapping(virq);
463 }
464
465 irq_domain_remove(chip->g1_irq.domain);
466 }
467
468 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469 {
470 int err, irq, virq;
471 u16 reg, mask;
472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
487 if (err)
488 goto out_mapping;
489
490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
491
492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
493 if (err)
494 goto out_disable;
495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
499 goto out_disable;
500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
506 goto out_disable;
507
508 return 0;
509
510 out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514 out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
521
522 return err;
523 }
524
525 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
526 {
527 int i;
528
529 for (i = 0; i < 16; i++) {
530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
543 dev_err(chip->dev, "Timeout while waiting for switch\n");
544 return -ETIMEDOUT;
545 }
546
547 /* Indirect write to single pointer-data register with an Update bit */
548 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
549 {
550 u16 val;
551 int err;
552
553 /* Wait until the previous operation is completed */
554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562 }
563
564 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
565 {
566 if (!chip->info->ops->ppu_disable)
567 return 0;
568
569 return chip->info->ops->ppu_disable(chip);
570 }
571
572 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
573 {
574 if (!chip->info->ops->ppu_enable)
575 return 0;
576
577 return chip->info->ops->ppu_enable(chip);
578 }
579
580 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581 {
582 struct mv88e6xxx_chip *chip;
583
584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
585
586 mutex_lock(&chip->reg_lock);
587
588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
592 }
593
594 mutex_unlock(&chip->reg_lock);
595 }
596
597 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598 {
599 struct mv88e6xxx_chip *chip = (void *)_ps;
600
601 schedule_work(&chip->ppu_work);
602 }
603
604 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
605 {
606 int ret;
607
608 mutex_lock(&chip->ppu_mutex);
609
610 /* If the PHY polling unit is enabled, disable it so that
611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
617 if (ret < 0) {
618 mutex_unlock(&chip->ppu_mutex);
619 return ret;
620 }
621 chip->ppu_disabled = 1;
622 } else {
623 del_timer(&chip->ppu_timer);
624 ret = 0;
625 }
626
627 return ret;
628 }
629
630 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
631 {
632 /* Schedule a timer to re-enable the PHY polling unit. */
633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
635 }
636
637 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
638 {
639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
643 }
644
645 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646 {
647 del_timer_sync(&chip->ppu_timer);
648 }
649
650 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
653 {
654 int err;
655
656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
659 mv88e6xxx_ppu_access_put(chip);
660 }
661
662 return err;
663 }
664
665 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
668 {
669 int err;
670
671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
674 mv88e6xxx_ppu_access_put(chip);
675 }
676
677 return err;
678 }
679
680 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
681 {
682 return chip->info->family == MV88E6XXX_FAMILY_6097;
683 }
684
685 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
686 {
687 return chip->info->family == MV88E6XXX_FAMILY_6165;
688 }
689
690 static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
691 {
692 return chip->info->family == MV88E6XXX_FAMILY_6341;
693 }
694
695 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
696 {
697 return chip->info->family == MV88E6XXX_FAMILY_6351;
698 }
699
700 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
701 {
702 return chip->info->family == MV88E6XXX_FAMILY_6352;
703 }
704
705 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
706 int link, int speed, int duplex,
707 phy_interface_t mode)
708 {
709 int err;
710
711 if (!chip->info->ops->port_set_link)
712 return 0;
713
714 /* Port's MAC control must not be changed unless the link is down */
715 err = chip->info->ops->port_set_link(chip, port, 0);
716 if (err)
717 return err;
718
719 if (chip->info->ops->port_set_speed) {
720 err = chip->info->ops->port_set_speed(chip, port, speed);
721 if (err && err != -EOPNOTSUPP)
722 goto restore_link;
723 }
724
725 if (chip->info->ops->port_set_duplex) {
726 err = chip->info->ops->port_set_duplex(chip, port, duplex);
727 if (err && err != -EOPNOTSUPP)
728 goto restore_link;
729 }
730
731 if (chip->info->ops->port_set_rgmii_delay) {
732 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
733 if (err && err != -EOPNOTSUPP)
734 goto restore_link;
735 }
736
737 if (chip->info->ops->port_set_cmode) {
738 err = chip->info->ops->port_set_cmode(chip, port, mode);
739 if (err && err != -EOPNOTSUPP)
740 goto restore_link;
741 }
742
743 err = 0;
744 restore_link:
745 if (chip->info->ops->port_set_link(chip, port, link))
746 netdev_err(chip->ds->ports[port].netdev,
747 "failed to restore MAC's link\n");
748
749 return err;
750 }
751
752 /* We expect the switch to perform auto negotiation if there is a real
753 * phy. However, in the case of a fixed link phy, we force the port
754 * settings from the fixed link settings.
755 */
756 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
757 struct phy_device *phydev)
758 {
759 struct mv88e6xxx_chip *chip = ds->priv;
760 int err;
761
762 if (!phy_is_pseudo_fixed_link(phydev))
763 return;
764
765 mutex_lock(&chip->reg_lock);
766 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
767 phydev->duplex, phydev->interface);
768 mutex_unlock(&chip->reg_lock);
769
770 if (err && err != -EOPNOTSUPP)
771 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
772 }
773
774 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
775 {
776 if (!chip->info->ops->stats_snapshot)
777 return -EOPNOTSUPP;
778
779 return chip->info->ops->stats_snapshot(chip, port);
780 }
781
782 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
783 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
784 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
785 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
786 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
787 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
788 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
789 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
790 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
791 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
792 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
793 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
794 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
795 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
796 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
797 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
798 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
799 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
800 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
801 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
802 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
803 { "single", 4, 0x14, STATS_TYPE_BANK0, },
804 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
805 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
806 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
807 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
808 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
809 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
810 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
811 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
812 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
813 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
814 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
815 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
816 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
817 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
818 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
819 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
820 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
821 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
822 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
823 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
824 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
825 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
826 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
827 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
828 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
829 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
830 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
831 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
832 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
833 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
834 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
835 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
836 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
837 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
838 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
839 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
840 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
841 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
842 };
843
844 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
845 struct mv88e6xxx_hw_stat *s,
846 int port, u16 bank1_select,
847 u16 histogram)
848 {
849 u32 low;
850 u32 high = 0;
851 u16 reg = 0;
852 int err;
853 u64 value;
854
855 switch (s->type) {
856 case STATS_TYPE_PORT:
857 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
858 if (err)
859 return UINT64_MAX;
860
861 low = reg;
862 if (s->sizeof_stat == 4) {
863 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
864 if (err)
865 return UINT64_MAX;
866 high = reg;
867 }
868 break;
869 case STATS_TYPE_BANK1:
870 reg = bank1_select;
871 /* fall through */
872 case STATS_TYPE_BANK0:
873 reg |= s->reg | histogram;
874 mv88e6xxx_g1_stats_read(chip, reg, &low);
875 if (s->sizeof_stat == 8)
876 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
877 }
878 value = (((u64)high) << 16) | low;
879 return value;
880 }
881
882 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
883 uint8_t *data, int types)
884 {
885 struct mv88e6xxx_hw_stat *stat;
886 int i, j;
887
888 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
889 stat = &mv88e6xxx_hw_stats[i];
890 if (stat->type & types) {
891 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
892 ETH_GSTRING_LEN);
893 j++;
894 }
895 }
896 }
897
898 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
899 uint8_t *data)
900 {
901 mv88e6xxx_stats_get_strings(chip, data,
902 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
903 }
904
905 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
906 uint8_t *data)
907 {
908 mv88e6xxx_stats_get_strings(chip, data,
909 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
910 }
911
912 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
913 uint8_t *data)
914 {
915 struct mv88e6xxx_chip *chip = ds->priv;
916
917 if (chip->info->ops->stats_get_strings)
918 chip->info->ops->stats_get_strings(chip, data);
919 }
920
921 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
922 int types)
923 {
924 struct mv88e6xxx_hw_stat *stat;
925 int i, j;
926
927 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
928 stat = &mv88e6xxx_hw_stats[i];
929 if (stat->type & types)
930 j++;
931 }
932 return j;
933 }
934
935 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
936 {
937 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
938 STATS_TYPE_PORT);
939 }
940
941 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
942 {
943 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
944 STATS_TYPE_BANK1);
945 }
946
947 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
948 {
949 struct mv88e6xxx_chip *chip = ds->priv;
950
951 if (chip->info->ops->stats_get_sset_count)
952 return chip->info->ops->stats_get_sset_count(chip);
953
954 return 0;
955 }
956
957 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
958 uint64_t *data, int types,
959 u16 bank1_select, u16 histogram)
960 {
961 struct mv88e6xxx_hw_stat *stat;
962 int i, j;
963
964 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
965 stat = &mv88e6xxx_hw_stats[i];
966 if (stat->type & types) {
967 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
968 bank1_select,
969 histogram);
970 j++;
971 }
972 }
973 }
974
975 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
976 uint64_t *data)
977 {
978 return mv88e6xxx_stats_get_stats(chip, port, data,
979 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
980 0, GLOBAL_STATS_OP_HIST_RX_TX);
981 }
982
983 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
984 uint64_t *data)
985 {
986 return mv88e6xxx_stats_get_stats(chip, port, data,
987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
988 GLOBAL_STATS_OP_BANK_1_BIT_9,
989 GLOBAL_STATS_OP_HIST_RX_TX);
990 }
991
992 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
994 {
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
998 }
999
1000 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1001 uint64_t *data)
1002 {
1003 if (chip->info->ops->stats_get_stats)
1004 chip->info->ops->stats_get_stats(chip, port, data);
1005 }
1006
1007 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1008 uint64_t *data)
1009 {
1010 struct mv88e6xxx_chip *chip = ds->priv;
1011 int ret;
1012
1013 mutex_lock(&chip->reg_lock);
1014
1015 ret = mv88e6xxx_stats_snapshot(chip, port);
1016 if (ret < 0) {
1017 mutex_unlock(&chip->reg_lock);
1018 return;
1019 }
1020
1021 mv88e6xxx_get_stats(chip, port, data);
1022
1023 mutex_unlock(&chip->reg_lock);
1024 }
1025
1026 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1027 {
1028 if (chip->info->ops->stats_set_histogram)
1029 return chip->info->ops->stats_set_histogram(chip);
1030
1031 return 0;
1032 }
1033
1034 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1035 {
1036 return 32 * sizeof(u16);
1037 }
1038
1039 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1040 struct ethtool_regs *regs, void *_p)
1041 {
1042 struct mv88e6xxx_chip *chip = ds->priv;
1043 int err;
1044 u16 reg;
1045 u16 *p = _p;
1046 int i;
1047
1048 regs->version = 0;
1049
1050 memset(p, 0xff, 32 * sizeof(u16));
1051
1052 mutex_lock(&chip->reg_lock);
1053
1054 for (i = 0; i < 32; i++) {
1055
1056 err = mv88e6xxx_port_read(chip, port, i, &reg);
1057 if (!err)
1058 p[i] = reg;
1059 }
1060
1061 mutex_unlock(&chip->reg_lock);
1062 }
1063
1064 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1065 struct ethtool_eee *e)
1066 {
1067 struct mv88e6xxx_chip *chip = ds->priv;
1068 u16 reg;
1069 int err;
1070
1071 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1072 return -EOPNOTSUPP;
1073
1074 mutex_lock(&chip->reg_lock);
1075
1076 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1077 if (err)
1078 goto out;
1079
1080 e->eee_enabled = !!(reg & 0x0200);
1081 e->tx_lpi_enabled = !!(reg & 0x0100);
1082
1083 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
1084 if (err)
1085 goto out;
1086
1087 e->eee_active = !!(reg & PORT_STATUS_EEE);
1088 out:
1089 mutex_unlock(&chip->reg_lock);
1090
1091 return err;
1092 }
1093
1094 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1095 struct phy_device *phydev, struct ethtool_eee *e)
1096 {
1097 struct mv88e6xxx_chip *chip = ds->priv;
1098 u16 reg;
1099 int err;
1100
1101 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1102 return -EOPNOTSUPP;
1103
1104 mutex_lock(&chip->reg_lock);
1105
1106 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1107 if (err)
1108 goto out;
1109
1110 reg &= ~0x0300;
1111 if (e->eee_enabled)
1112 reg |= 0x0200;
1113 if (e->tx_lpi_enabled)
1114 reg |= 0x0100;
1115
1116 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1117 out:
1118 mutex_unlock(&chip->reg_lock);
1119
1120 return err;
1121 }
1122
1123 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1124 {
1125 struct dsa_switch *ds = NULL;
1126 struct net_device *br;
1127 u16 pvlan;
1128 int i;
1129
1130 if (dev < DSA_MAX_SWITCHES)
1131 ds = chip->ds->dst->ds[dev];
1132
1133 /* Prevent frames from unknown switch or port */
1134 if (!ds || port >= ds->num_ports)
1135 return 0;
1136
1137 /* Frames from DSA links and CPU ports can egress any local port */
1138 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1139 return mv88e6xxx_port_mask(chip);
1140
1141 br = ds->ports[port].bridge_dev;
1142 pvlan = 0;
1143
1144 /* Frames from user ports can egress any local DSA links and CPU ports,
1145 * as well as any local member of their bridge group.
1146 */
1147 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1148 if (dsa_is_cpu_port(chip->ds, i) ||
1149 dsa_is_dsa_port(chip->ds, i) ||
1150 (br && chip->ds->ports[i].bridge_dev == br))
1151 pvlan |= BIT(i);
1152
1153 return pvlan;
1154 }
1155
1156 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1157 {
1158 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1159
1160 /* prevent frames from going back out of the port they came in on */
1161 output_ports &= ~BIT(port);
1162
1163 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1164 }
1165
1166 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1167 u8 state)
1168 {
1169 struct mv88e6xxx_chip *chip = ds->priv;
1170 int stp_state;
1171 int err;
1172
1173 switch (state) {
1174 case BR_STATE_DISABLED:
1175 stp_state = PORT_CONTROL_STATE_DISABLED;
1176 break;
1177 case BR_STATE_BLOCKING:
1178 case BR_STATE_LISTENING:
1179 stp_state = PORT_CONTROL_STATE_BLOCKING;
1180 break;
1181 case BR_STATE_LEARNING:
1182 stp_state = PORT_CONTROL_STATE_LEARNING;
1183 break;
1184 case BR_STATE_FORWARDING:
1185 default:
1186 stp_state = PORT_CONTROL_STATE_FORWARDING;
1187 break;
1188 }
1189
1190 mutex_lock(&chip->reg_lock);
1191 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1192 mutex_unlock(&chip->reg_lock);
1193
1194 if (err)
1195 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1196 }
1197
1198 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1199 {
1200 int err;
1201
1202 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1203 if (err)
1204 return err;
1205
1206 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1207 if (err)
1208 return err;
1209
1210 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1211 }
1212
1213 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1214 {
1215 u16 pvlan = 0;
1216
1217 if (!mv88e6xxx_has_pvt(chip))
1218 return -EOPNOTSUPP;
1219
1220 /* Skip the local source device, which uses in-chip port VLAN */
1221 if (dev != chip->ds->index)
1222 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1223
1224 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1225 }
1226
1227 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1228 {
1229 int dev, port;
1230 int err;
1231
1232 if (!mv88e6xxx_has_pvt(chip))
1233 return 0;
1234
1235 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1236 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1237 */
1238 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1239 if (err)
1240 return err;
1241
1242 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1243 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1244 err = mv88e6xxx_pvt_map(chip, dev, port);
1245 if (err)
1246 return err;
1247 }
1248 }
1249
1250 return 0;
1251 }
1252
1253 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1254 {
1255 struct mv88e6xxx_chip *chip = ds->priv;
1256 int err;
1257
1258 mutex_lock(&chip->reg_lock);
1259 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1260 mutex_unlock(&chip->reg_lock);
1261
1262 if (err)
1263 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1264 }
1265
1266 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1267 struct mv88e6xxx_vtu_entry *entry,
1268 unsigned int nibble_offset)
1269 {
1270 u16 regs[3];
1271 int i, err;
1272
1273 for (i = 0; i < 3; ++i) {
1274 u16 *reg = &regs[i];
1275
1276 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1277 if (err)
1278 return err;
1279 }
1280
1281 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1282 unsigned int shift = (i % 4) * 4 + nibble_offset;
1283 u16 reg = regs[i / 4];
1284
1285 entry->state[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1286 }
1287
1288 return 0;
1289 }
1290
1291 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1292 struct mv88e6xxx_vtu_entry *entry)
1293 {
1294 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1295 }
1296
1297 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1298 struct mv88e6xxx_vtu_entry *entry)
1299 {
1300 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1301 }
1302
1303 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1304 struct mv88e6xxx_vtu_entry *entry,
1305 unsigned int nibble_offset)
1306 {
1307 u16 regs[3] = { 0 };
1308 int i, err;
1309
1310 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1311 unsigned int shift = (i % 4) * 4 + nibble_offset;
1312 u8 data = entry->state[i];
1313
1314 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1315 }
1316
1317 for (i = 0; i < 3; ++i) {
1318 u16 reg = regs[i];
1319
1320 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1321 if (err)
1322 return err;
1323 }
1324
1325 return 0;
1326 }
1327
1328 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1329 struct mv88e6xxx_vtu_entry *entry)
1330 {
1331 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1332 }
1333
1334 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1335 struct mv88e6xxx_vtu_entry *entry)
1336 {
1337 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1338 }
1339
1340 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1341 {
1342 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1343 vid & GLOBAL_VTU_VID_MASK);
1344 }
1345
1346 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1347 struct mv88e6xxx_vtu_entry *entry)
1348 {
1349 struct mv88e6xxx_vtu_entry next = { 0 };
1350 u16 val;
1351 int err;
1352
1353 err = mv88e6xxx_g1_vtu_op_wait(chip);
1354 if (err)
1355 return err;
1356
1357 err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1358 if (err)
1359 return err;
1360
1361 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1362 if (err)
1363 return err;
1364
1365 next.vid = val & GLOBAL_VTU_VID_MASK;
1366 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1367
1368 if (next.valid) {
1369 err = mv88e6xxx_vtu_data_read(chip, &next);
1370 if (err)
1371 return err;
1372
1373 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1374 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1375 if (err)
1376 return err;
1377
1378 next.fid = val & GLOBAL_VTU_FID_MASK;
1379 } else if (mv88e6xxx_num_databases(chip) == 256) {
1380 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1381 * VTU DBNum[3:0] are located in VTU Operation 3:0
1382 */
1383 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1384 if (err)
1385 return err;
1386
1387 next.fid = (val & 0xf00) >> 4;
1388 next.fid |= val & 0xf;
1389 }
1390
1391 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1392 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1393 if (err)
1394 return err;
1395
1396 next.sid = val & GLOBAL_VTU_SID_MASK;
1397 }
1398 }
1399
1400 *entry = next;
1401 return 0;
1402 }
1403
1404 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1405 {
1406 if (!chip->info->max_vid)
1407 return 0;
1408
1409 return mv88e6xxx_g1_vtu_flush(chip);
1410 }
1411
1412 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1413 struct switchdev_obj_port_vlan *vlan,
1414 int (*cb)(struct switchdev_obj *obj))
1415 {
1416 struct mv88e6xxx_chip *chip = ds->priv;
1417 struct mv88e6xxx_vtu_entry next;
1418 u16 pvid;
1419 int err;
1420
1421 if (!chip->info->max_vid)
1422 return -EOPNOTSUPP;
1423
1424 mutex_lock(&chip->reg_lock);
1425
1426 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1427 if (err)
1428 goto unlock;
1429
1430 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1431 if (err)
1432 goto unlock;
1433
1434 do {
1435 err = _mv88e6xxx_vtu_getnext(chip, &next);
1436 if (err)
1437 break;
1438
1439 if (!next.valid)
1440 break;
1441
1442 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1443 continue;
1444
1445 /* reinit and dump this VLAN obj */
1446 vlan->vid_begin = next.vid;
1447 vlan->vid_end = next.vid;
1448 vlan->flags = 0;
1449
1450 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1451 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1452
1453 if (next.vid == pvid)
1454 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1455
1456 err = cb(&vlan->obj);
1457 if (err)
1458 break;
1459 } while (next.vid < chip->info->max_vid);
1460
1461 unlock:
1462 mutex_unlock(&chip->reg_lock);
1463
1464 return err;
1465 }
1466
1467 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1468 struct mv88e6xxx_vtu_entry *entry)
1469 {
1470 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1471 u16 reg = 0;
1472 int err;
1473
1474 err = mv88e6xxx_g1_vtu_op_wait(chip);
1475 if (err)
1476 return err;
1477
1478 if (!entry->valid)
1479 goto loadpurge;
1480
1481 /* Write port member tags */
1482 err = mv88e6xxx_vtu_data_write(chip, entry);
1483 if (err)
1484 return err;
1485
1486 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1487 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1488 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1489 if (err)
1490 return err;
1491 }
1492
1493 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1494 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1495 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1496 if (err)
1497 return err;
1498 } else if (mv88e6xxx_num_databases(chip) == 256) {
1499 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1500 * VTU DBNum[3:0] are located in VTU Operation 3:0
1501 */
1502 op |= (entry->fid & 0xf0) << 8;
1503 op |= entry->fid & 0xf;
1504 }
1505
1506 reg = GLOBAL_VTU_VID_VALID;
1507 loadpurge:
1508 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1509 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1510 if (err)
1511 return err;
1512
1513 return mv88e6xxx_g1_vtu_op(chip, op);
1514 }
1515
1516 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1517 struct mv88e6xxx_vtu_entry *entry)
1518 {
1519 struct mv88e6xxx_vtu_entry next = { 0 };
1520 u16 val;
1521 int err;
1522
1523 err = mv88e6xxx_g1_vtu_op_wait(chip);
1524 if (err)
1525 return err;
1526
1527 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1528 sid & GLOBAL_VTU_SID_MASK);
1529 if (err)
1530 return err;
1531
1532 err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1533 if (err)
1534 return err;
1535
1536 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1537 if (err)
1538 return err;
1539
1540 next.sid = val & GLOBAL_VTU_SID_MASK;
1541
1542 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1543 if (err)
1544 return err;
1545
1546 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1547
1548 if (next.valid) {
1549 err = mv88e6xxx_stu_data_read(chip, &next);
1550 if (err)
1551 return err;
1552 }
1553
1554 *entry = next;
1555 return 0;
1556 }
1557
1558 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1559 struct mv88e6xxx_vtu_entry *entry)
1560 {
1561 u16 reg = 0;
1562 int err;
1563
1564 err = mv88e6xxx_g1_vtu_op_wait(chip);
1565 if (err)
1566 return err;
1567
1568 if (!entry->valid)
1569 goto loadpurge;
1570
1571 /* Write port states */
1572 err = mv88e6xxx_stu_data_write(chip, entry);
1573 if (err)
1574 return err;
1575
1576 reg = GLOBAL_VTU_VID_VALID;
1577 loadpurge:
1578 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1579 if (err)
1580 return err;
1581
1582 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1583 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1584 if (err)
1585 return err;
1586
1587 return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1588 }
1589
1590 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1591 {
1592 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1593 struct mv88e6xxx_vtu_entry vlan;
1594 int i, err;
1595
1596 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1597
1598 /* Set every FID bit used by the (un)bridged ports */
1599 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1600 err = mv88e6xxx_port_get_fid(chip, i, fid);
1601 if (err)
1602 return err;
1603
1604 set_bit(*fid, fid_bitmap);
1605 }
1606
1607 /* Set every FID bit used by the VLAN entries */
1608 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1609 if (err)
1610 return err;
1611
1612 do {
1613 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1614 if (err)
1615 return err;
1616
1617 if (!vlan.valid)
1618 break;
1619
1620 set_bit(vlan.fid, fid_bitmap);
1621 } while (vlan.vid < chip->info->max_vid);
1622
1623 /* The reset value 0x000 is used to indicate that multiple address
1624 * databases are not needed. Return the next positive available.
1625 */
1626 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1627 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1628 return -ENOSPC;
1629
1630 /* Clear the database */
1631 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1632 }
1633
1634 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1635 struct mv88e6xxx_vtu_entry *entry)
1636 {
1637 struct dsa_switch *ds = chip->ds;
1638 struct mv88e6xxx_vtu_entry vlan = {
1639 .valid = true,
1640 .vid = vid,
1641 };
1642 int i, err;
1643
1644 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1645 if (err)
1646 return err;
1647
1648 /* exclude all ports except the CPU and DSA ports */
1649 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1650 vlan.member[i] = dsa_is_cpu_port(ds, i) ||
1651 dsa_is_dsa_port(ds, i)
1652 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1653 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1654
1655 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1656 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1657 mv88e6xxx_6341_family(chip)) {
1658 struct mv88e6xxx_vtu_entry vstp;
1659
1660 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1661 * implemented, only one STU entry is needed to cover all VTU
1662 * entries. Thus, validate the SID 0.
1663 */
1664 vlan.sid = 0;
1665 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1666 if (err)
1667 return err;
1668
1669 if (vstp.sid != vlan.sid || !vstp.valid) {
1670 memset(&vstp, 0, sizeof(vstp));
1671 vstp.valid = true;
1672 vstp.sid = vlan.sid;
1673
1674 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1675 if (err)
1676 return err;
1677 }
1678 }
1679
1680 *entry = vlan;
1681 return 0;
1682 }
1683
1684 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1685 struct mv88e6xxx_vtu_entry *entry, bool creat)
1686 {
1687 int err;
1688
1689 if (!vid)
1690 return -EINVAL;
1691
1692 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1693 if (err)
1694 return err;
1695
1696 err = _mv88e6xxx_vtu_getnext(chip, entry);
1697 if (err)
1698 return err;
1699
1700 if (entry->vid != vid || !entry->valid) {
1701 if (!creat)
1702 return -EOPNOTSUPP;
1703 /* -ENOENT would've been more appropriate, but switchdev expects
1704 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1705 */
1706
1707 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1708 }
1709
1710 return err;
1711 }
1712
1713 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1714 u16 vid_begin, u16 vid_end)
1715 {
1716 struct mv88e6xxx_chip *chip = ds->priv;
1717 struct mv88e6xxx_vtu_entry vlan;
1718 int i, err;
1719
1720 if (!vid_begin)
1721 return -EOPNOTSUPP;
1722
1723 mutex_lock(&chip->reg_lock);
1724
1725 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1726 if (err)
1727 goto unlock;
1728
1729 do {
1730 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1731 if (err)
1732 goto unlock;
1733
1734 if (!vlan.valid)
1735 break;
1736
1737 if (vlan.vid > vid_end)
1738 break;
1739
1740 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1741 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1742 continue;
1743
1744 if (!ds->ports[port].netdev)
1745 continue;
1746
1747 if (vlan.member[i] ==
1748 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1749 continue;
1750
1751 if (ds->ports[i].bridge_dev ==
1752 ds->ports[port].bridge_dev)
1753 break; /* same bridge, check next VLAN */
1754
1755 if (!ds->ports[i].bridge_dev)
1756 continue;
1757
1758 netdev_warn(ds->ports[port].netdev,
1759 "hardware VLAN %d already used by %s\n",
1760 vlan.vid,
1761 netdev_name(ds->ports[i].bridge_dev));
1762 err = -EOPNOTSUPP;
1763 goto unlock;
1764 }
1765 } while (vlan.vid < vid_end);
1766
1767 unlock:
1768 mutex_unlock(&chip->reg_lock);
1769
1770 return err;
1771 }
1772
1773 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1774 bool vlan_filtering)
1775 {
1776 struct mv88e6xxx_chip *chip = ds->priv;
1777 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1778 PORT_CONTROL_2_8021Q_DISABLED;
1779 int err;
1780
1781 if (!chip->info->max_vid)
1782 return -EOPNOTSUPP;
1783
1784 mutex_lock(&chip->reg_lock);
1785 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1786 mutex_unlock(&chip->reg_lock);
1787
1788 return err;
1789 }
1790
1791 static int
1792 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1793 const struct switchdev_obj_port_vlan *vlan,
1794 struct switchdev_trans *trans)
1795 {
1796 struct mv88e6xxx_chip *chip = ds->priv;
1797 int err;
1798
1799 if (!chip->info->max_vid)
1800 return -EOPNOTSUPP;
1801
1802 /* If the requested port doesn't belong to the same bridge as the VLAN
1803 * members, do not support it (yet) and fallback to software VLAN.
1804 */
1805 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1806 vlan->vid_end);
1807 if (err)
1808 return err;
1809
1810 /* We don't need any dynamic resource from the kernel (yet),
1811 * so skip the prepare phase.
1812 */
1813 return 0;
1814 }
1815
1816 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1817 u16 vid, bool untagged)
1818 {
1819 struct mv88e6xxx_vtu_entry vlan;
1820 int err;
1821
1822 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1823 if (err)
1824 return err;
1825
1826 vlan.member[port] = untagged ?
1827 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1828 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1829
1830 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1831 }
1832
1833 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1834 const struct switchdev_obj_port_vlan *vlan,
1835 struct switchdev_trans *trans)
1836 {
1837 struct mv88e6xxx_chip *chip = ds->priv;
1838 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1839 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1840 u16 vid;
1841
1842 if (!chip->info->max_vid)
1843 return;
1844
1845 mutex_lock(&chip->reg_lock);
1846
1847 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1848 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1849 netdev_err(ds->ports[port].netdev,
1850 "failed to add VLAN %d%c\n",
1851 vid, untagged ? 'u' : 't');
1852
1853 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1854 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1855 vlan->vid_end);
1856
1857 mutex_unlock(&chip->reg_lock);
1858 }
1859
1860 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1861 int port, u16 vid)
1862 {
1863 struct dsa_switch *ds = chip->ds;
1864 struct mv88e6xxx_vtu_entry vlan;
1865 int i, err;
1866
1867 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1868 if (err)
1869 return err;
1870
1871 /* Tell switchdev if this VLAN is handled in software */
1872 if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1873 return -EOPNOTSUPP;
1874
1875 vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1876
1877 /* keep the VLAN unless all ports are excluded */
1878 vlan.valid = false;
1879 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1880 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1881 continue;
1882
1883 if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1884 vlan.valid = true;
1885 break;
1886 }
1887 }
1888
1889 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1890 if (err)
1891 return err;
1892
1893 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1894 }
1895
1896 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1897 const struct switchdev_obj_port_vlan *vlan)
1898 {
1899 struct mv88e6xxx_chip *chip = ds->priv;
1900 u16 pvid, vid;
1901 int err = 0;
1902
1903 if (!chip->info->max_vid)
1904 return -EOPNOTSUPP;
1905
1906 mutex_lock(&chip->reg_lock);
1907
1908 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1909 if (err)
1910 goto unlock;
1911
1912 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1913 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1914 if (err)
1915 goto unlock;
1916
1917 if (vid == pvid) {
1918 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1919 if (err)
1920 goto unlock;
1921 }
1922 }
1923
1924 unlock:
1925 mutex_unlock(&chip->reg_lock);
1926
1927 return err;
1928 }
1929
1930 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1931 const unsigned char *addr, u16 vid,
1932 u8 state)
1933 {
1934 struct mv88e6xxx_vtu_entry vlan;
1935 struct mv88e6xxx_atu_entry entry;
1936 int err;
1937
1938 /* Null VLAN ID corresponds to the port private database */
1939 if (vid == 0)
1940 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1941 else
1942 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1943 if (err)
1944 return err;
1945
1946 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1947 ether_addr_copy(entry.mac, addr);
1948 eth_addr_dec(entry.mac);
1949
1950 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1951 if (err)
1952 return err;
1953
1954 /* Initialize a fresh ATU entry if it isn't found */
1955 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1956 !ether_addr_equal(entry.mac, addr)) {
1957 memset(&entry, 0, sizeof(entry));
1958 ether_addr_copy(entry.mac, addr);
1959 }
1960
1961 /* Purge the ATU entry only if no port is using it anymore */
1962 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
1963 entry.portvec &= ~BIT(port);
1964 if (!entry.portvec)
1965 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1966 } else {
1967 entry.portvec |= BIT(port);
1968 entry.state = state;
1969 }
1970
1971 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1972 }
1973
1974 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1975 const struct switchdev_obj_port_fdb *fdb,
1976 struct switchdev_trans *trans)
1977 {
1978 /* We don't need any dynamic resource from the kernel (yet),
1979 * so skip the prepare phase.
1980 */
1981 return 0;
1982 }
1983
1984 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1985 const struct switchdev_obj_port_fdb *fdb,
1986 struct switchdev_trans *trans)
1987 {
1988 struct mv88e6xxx_chip *chip = ds->priv;
1989
1990 mutex_lock(&chip->reg_lock);
1991 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1992 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1993 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
1994 mutex_unlock(&chip->reg_lock);
1995 }
1996
1997 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1998 const struct switchdev_obj_port_fdb *fdb)
1999 {
2000 struct mv88e6xxx_chip *chip = ds->priv;
2001 int err;
2002
2003 mutex_lock(&chip->reg_lock);
2004 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2005 GLOBAL_ATU_DATA_STATE_UNUSED);
2006 mutex_unlock(&chip->reg_lock);
2007
2008 return err;
2009 }
2010
2011 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2012 u16 fid, u16 vid, int port,
2013 struct switchdev_obj *obj,
2014 int (*cb)(struct switchdev_obj *obj))
2015 {
2016 struct mv88e6xxx_atu_entry addr;
2017 int err;
2018
2019 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2020 eth_broadcast_addr(addr.mac);
2021
2022 do {
2023 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2024 if (err)
2025 return err;
2026
2027 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2028 break;
2029
2030 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2031 continue;
2032
2033 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2034 struct switchdev_obj_port_fdb *fdb;
2035
2036 if (!is_unicast_ether_addr(addr.mac))
2037 continue;
2038
2039 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2040 fdb->vid = vid;
2041 ether_addr_copy(fdb->addr, addr.mac);
2042 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2043 fdb->ndm_state = NUD_NOARP;
2044 else
2045 fdb->ndm_state = NUD_REACHABLE;
2046 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2047 struct switchdev_obj_port_mdb *mdb;
2048
2049 if (!is_multicast_ether_addr(addr.mac))
2050 continue;
2051
2052 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2053 mdb->vid = vid;
2054 ether_addr_copy(mdb->addr, addr.mac);
2055 } else {
2056 return -EOPNOTSUPP;
2057 }
2058
2059 err = cb(obj);
2060 if (err)
2061 return err;
2062 } while (!is_broadcast_ether_addr(addr.mac));
2063
2064 return err;
2065 }
2066
2067 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2068 struct switchdev_obj *obj,
2069 int (*cb)(struct switchdev_obj *obj))
2070 {
2071 struct mv88e6xxx_vtu_entry vlan = {
2072 .vid = chip->info->max_vid,
2073 };
2074 u16 fid;
2075 int err;
2076
2077 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2078 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2079 if (err)
2080 return err;
2081
2082 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2083 if (err)
2084 return err;
2085
2086 /* Dump VLANs' Filtering Information Databases */
2087 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2088 if (err)
2089 return err;
2090
2091 do {
2092 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2093 if (err)
2094 return err;
2095
2096 if (!vlan.valid)
2097 break;
2098
2099 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2100 obj, cb);
2101 if (err)
2102 return err;
2103 } while (vlan.vid < chip->info->max_vid);
2104
2105 return err;
2106 }
2107
2108 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2109 struct switchdev_obj_port_fdb *fdb,
2110 int (*cb)(struct switchdev_obj *obj))
2111 {
2112 struct mv88e6xxx_chip *chip = ds->priv;
2113 int err;
2114
2115 mutex_lock(&chip->reg_lock);
2116 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2117 mutex_unlock(&chip->reg_lock);
2118
2119 return err;
2120 }
2121
2122 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2123 struct net_device *br)
2124 {
2125 struct dsa_switch *ds;
2126 int port;
2127 int dev;
2128 int err;
2129
2130 /* Remap the Port VLAN of each local bridge group member */
2131 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
2132 if (chip->ds->ports[port].bridge_dev == br) {
2133 err = mv88e6xxx_port_vlan_map(chip, port);
2134 if (err)
2135 return err;
2136 }
2137 }
2138
2139 if (!mv88e6xxx_has_pvt(chip))
2140 return 0;
2141
2142 /* Remap the Port VLAN of each cross-chip bridge group member */
2143 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
2144 ds = chip->ds->dst->ds[dev];
2145 if (!ds)
2146 break;
2147
2148 for (port = 0; port < ds->num_ports; ++port) {
2149 if (ds->ports[port].bridge_dev == br) {
2150 err = mv88e6xxx_pvt_map(chip, dev, port);
2151 if (err)
2152 return err;
2153 }
2154 }
2155 }
2156
2157 return 0;
2158 }
2159
2160 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2161 struct net_device *br)
2162 {
2163 struct mv88e6xxx_chip *chip = ds->priv;
2164 int err;
2165
2166 mutex_lock(&chip->reg_lock);
2167 err = mv88e6xxx_bridge_map(chip, br);
2168 mutex_unlock(&chip->reg_lock);
2169
2170 return err;
2171 }
2172
2173 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2174 struct net_device *br)
2175 {
2176 struct mv88e6xxx_chip *chip = ds->priv;
2177
2178 mutex_lock(&chip->reg_lock);
2179 if (mv88e6xxx_bridge_map(chip, br) ||
2180 mv88e6xxx_port_vlan_map(chip, port))
2181 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2182 mutex_unlock(&chip->reg_lock);
2183 }
2184
2185 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2186 int port, struct net_device *br)
2187 {
2188 struct mv88e6xxx_chip *chip = ds->priv;
2189 int err;
2190
2191 if (!mv88e6xxx_has_pvt(chip))
2192 return 0;
2193
2194 mutex_lock(&chip->reg_lock);
2195 err = mv88e6xxx_pvt_map(chip, dev, port);
2196 mutex_unlock(&chip->reg_lock);
2197
2198 return err;
2199 }
2200
2201 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2202 int port, struct net_device *br)
2203 {
2204 struct mv88e6xxx_chip *chip = ds->priv;
2205
2206 if (!mv88e6xxx_has_pvt(chip))
2207 return;
2208
2209 mutex_lock(&chip->reg_lock);
2210 if (mv88e6xxx_pvt_map(chip, dev, port))
2211 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2212 mutex_unlock(&chip->reg_lock);
2213 }
2214
2215 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2216 {
2217 if (chip->info->ops->reset)
2218 return chip->info->ops->reset(chip);
2219
2220 return 0;
2221 }
2222
2223 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2224 {
2225 struct gpio_desc *gpiod = chip->reset;
2226
2227 /* If there is a GPIO connected to the reset pin, toggle it */
2228 if (gpiod) {
2229 gpiod_set_value_cansleep(gpiod, 1);
2230 usleep_range(10000, 20000);
2231 gpiod_set_value_cansleep(gpiod, 0);
2232 usleep_range(10000, 20000);
2233 }
2234 }
2235
2236 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2237 {
2238 int i, err;
2239
2240 /* Set all ports to the Disabled state */
2241 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2242 err = mv88e6xxx_port_set_state(chip, i,
2243 PORT_CONTROL_STATE_DISABLED);
2244 if (err)
2245 return err;
2246 }
2247
2248 /* Wait for transmit queues to drain,
2249 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2250 */
2251 usleep_range(2000, 4000);
2252
2253 return 0;
2254 }
2255
2256 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2257 {
2258 int err;
2259
2260 err = mv88e6xxx_disable_ports(chip);
2261 if (err)
2262 return err;
2263
2264 mv88e6xxx_hardware_reset(chip);
2265
2266 return mv88e6xxx_software_reset(chip);
2267 }
2268
2269 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2270 {
2271 u16 val;
2272 int err;
2273
2274 /* Clear Power Down bit */
2275 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2276 if (err)
2277 return err;
2278
2279 if (val & BMCR_PDOWN) {
2280 val &= ~BMCR_PDOWN;
2281 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2282 }
2283
2284 return err;
2285 }
2286
2287 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2288 enum mv88e6xxx_frame_mode frame, u16 egress,
2289 u16 etype)
2290 {
2291 int err;
2292
2293 if (!chip->info->ops->port_set_frame_mode)
2294 return -EOPNOTSUPP;
2295
2296 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2297 if (err)
2298 return err;
2299
2300 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2301 if (err)
2302 return err;
2303
2304 if (chip->info->ops->port_set_ether_type)
2305 return chip->info->ops->port_set_ether_type(chip, port, etype);
2306
2307 return 0;
2308 }
2309
2310 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2311 {
2312 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2313 PORT_CONTROL_EGRESS_UNMODIFIED,
2314 PORT_ETH_TYPE_DEFAULT);
2315 }
2316
2317 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2318 {
2319 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2320 PORT_CONTROL_EGRESS_UNMODIFIED,
2321 PORT_ETH_TYPE_DEFAULT);
2322 }
2323
2324 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2325 {
2326 return mv88e6xxx_set_port_mode(chip, port,
2327 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2328 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2329 }
2330
2331 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2332 {
2333 if (dsa_is_dsa_port(chip->ds, port))
2334 return mv88e6xxx_set_port_mode_dsa(chip, port);
2335
2336 if (dsa_is_normal_port(chip->ds, port))
2337 return mv88e6xxx_set_port_mode_normal(chip, port);
2338
2339 /* Setup CPU port mode depending on its supported tag format */
2340 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2341 return mv88e6xxx_set_port_mode_dsa(chip, port);
2342
2343 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2344 return mv88e6xxx_set_port_mode_edsa(chip, port);
2345
2346 return -EINVAL;
2347 }
2348
2349 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2350 {
2351 bool message = dsa_is_dsa_port(chip->ds, port);
2352
2353 return mv88e6xxx_port_set_message_port(chip, port, message);
2354 }
2355
2356 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2357 {
2358 bool flood = port == dsa_upstream_port(chip->ds);
2359
2360 /* Upstream ports flood frames with unknown unicast or multicast DA */
2361 if (chip->info->ops->port_set_egress_floods)
2362 return chip->info->ops->port_set_egress_floods(chip, port,
2363 flood, flood);
2364
2365 return 0;
2366 }
2367
2368 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2369 {
2370 struct dsa_switch *ds = chip->ds;
2371 int err;
2372 u16 reg;
2373
2374 /* MAC Forcing register: don't force link, speed, duplex or flow control
2375 * state to any particular values on physical ports, but force the CPU
2376 * port and all DSA ports to their maximum bandwidth and full duplex.
2377 */
2378 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2379 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2380 SPEED_MAX, DUPLEX_FULL,
2381 PHY_INTERFACE_MODE_NA);
2382 else
2383 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2384 SPEED_UNFORCED, DUPLEX_UNFORCED,
2385 PHY_INTERFACE_MODE_NA);
2386 if (err)
2387 return err;
2388
2389 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2390 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2391 * tunneling, determine priority by looking at 802.1p and IP
2392 * priority fields (IP prio has precedence), and set STP state
2393 * to Forwarding.
2394 *
2395 * If this is the CPU link, use DSA or EDSA tagging depending
2396 * on which tagging mode was configured.
2397 *
2398 * If this is a link to another switch, use DSA tagging mode.
2399 *
2400 * If this is the upstream port for this switch, enable
2401 * forwarding of unknown unicasts and multicasts.
2402 */
2403 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2404 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2405 PORT_CONTROL_STATE_FORWARDING;
2406 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2407 if (err)
2408 return err;
2409
2410 err = mv88e6xxx_setup_port_mode(chip, port);
2411 if (err)
2412 return err;
2413
2414 err = mv88e6xxx_setup_egress_floods(chip, port);
2415 if (err)
2416 return err;
2417
2418 /* If this port is connected to a SerDes, make sure the SerDes is not
2419 * powered down.
2420 */
2421 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2422 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2423 if (err)
2424 return err;
2425 reg &= PORT_STATUS_CMODE_MASK;
2426 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2427 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2428 (reg == PORT_STATUS_CMODE_SGMII)) {
2429 err = mv88e6xxx_serdes_power_on(chip);
2430 if (err < 0)
2431 return err;
2432 }
2433 }
2434
2435 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2436 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2437 * untagged frames on this port, do a destination address lookup on all
2438 * received packets as usual, disable ARP mirroring and don't send a
2439 * copy of all transmitted/received frames on this port to the CPU.
2440 */
2441 err = mv88e6xxx_port_set_map_da(chip, port);
2442 if (err)
2443 return err;
2444
2445 reg = 0;
2446 if (chip->info->ops->port_set_upstream_port) {
2447 err = chip->info->ops->port_set_upstream_port(
2448 chip, port, dsa_upstream_port(ds));
2449 if (err)
2450 return err;
2451 }
2452
2453 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2454 PORT_CONTROL_2_8021Q_DISABLED);
2455 if (err)
2456 return err;
2457
2458 if (chip->info->ops->port_jumbo_config) {
2459 err = chip->info->ops->port_jumbo_config(chip, port);
2460 if (err)
2461 return err;
2462 }
2463
2464 /* Port Association Vector: when learning source addresses
2465 * of packets, add the address to the address database using
2466 * a port bitmap that has only the bit for this port set and
2467 * the other bits clear.
2468 */
2469 reg = 1 << port;
2470 /* Disable learning for CPU port */
2471 if (dsa_is_cpu_port(ds, port))
2472 reg = 0;
2473
2474 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2475 if (err)
2476 return err;
2477
2478 /* Egress rate control 2: disable egress rate control. */
2479 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2480 if (err)
2481 return err;
2482
2483 if (chip->info->ops->port_pause_config) {
2484 err = chip->info->ops->port_pause_config(chip, port);
2485 if (err)
2486 return err;
2487 }
2488
2489 if (chip->info->ops->port_disable_learn_limit) {
2490 err = chip->info->ops->port_disable_learn_limit(chip, port);
2491 if (err)
2492 return err;
2493 }
2494
2495 if (chip->info->ops->port_disable_pri_override) {
2496 err = chip->info->ops->port_disable_pri_override(chip, port);
2497 if (err)
2498 return err;
2499 }
2500
2501 if (chip->info->ops->port_tag_remap) {
2502 err = chip->info->ops->port_tag_remap(chip, port);
2503 if (err)
2504 return err;
2505 }
2506
2507 if (chip->info->ops->port_egress_rate_limiting) {
2508 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2509 if (err)
2510 return err;
2511 }
2512
2513 err = mv88e6xxx_setup_message_port(chip, port);
2514 if (err)
2515 return err;
2516
2517 /* Port based VLAN map: give each port the same default address
2518 * database, and allow bidirectional communication between the
2519 * CPU and DSA port(s), and the other ports.
2520 */
2521 err = mv88e6xxx_port_set_fid(chip, port, 0);
2522 if (err)
2523 return err;
2524
2525 err = mv88e6xxx_port_vlan_map(chip, port);
2526 if (err)
2527 return err;
2528
2529 /* Default VLAN ID and priority: don't set a default VLAN
2530 * ID, and set the default packet priority to zero.
2531 */
2532 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2533 }
2534
2535 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2536 {
2537 int err;
2538
2539 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2540 if (err)
2541 return err;
2542
2543 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2544 if (err)
2545 return err;
2546
2547 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2548 if (err)
2549 return err;
2550
2551 return 0;
2552 }
2553
2554 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2555 unsigned int ageing_time)
2556 {
2557 struct mv88e6xxx_chip *chip = ds->priv;
2558 int err;
2559
2560 mutex_lock(&chip->reg_lock);
2561 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2562 mutex_unlock(&chip->reg_lock);
2563
2564 return err;
2565 }
2566
2567 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2568 {
2569 struct dsa_switch *ds = chip->ds;
2570 u32 upstream_port = dsa_upstream_port(ds);
2571 int err;
2572
2573 /* Enable the PHY Polling Unit if present, don't discard any packets,
2574 * and mask all interrupt sources.
2575 */
2576 err = mv88e6xxx_ppu_enable(chip);
2577 if (err)
2578 return err;
2579
2580 if (chip->info->ops->g1_set_cpu_port) {
2581 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2582 if (err)
2583 return err;
2584 }
2585
2586 if (chip->info->ops->g1_set_egress_port) {
2587 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2588 if (err)
2589 return err;
2590 }
2591
2592 /* Disable remote management, and set the switch's DSA device number. */
2593 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2594 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2595 (ds->index & 0x1f));
2596 if (err)
2597 return err;
2598
2599 /* Configure the IP ToS mapping registers. */
2600 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2601 if (err)
2602 return err;
2603 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2604 if (err)
2605 return err;
2606 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2607 if (err)
2608 return err;
2609 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2610 if (err)
2611 return err;
2612 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2613 if (err)
2614 return err;
2615 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2616 if (err)
2617 return err;
2618 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2619 if (err)
2620 return err;
2621 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2622 if (err)
2623 return err;
2624
2625 /* Configure the IEEE 802.1p priority mapping register. */
2626 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2627 if (err)
2628 return err;
2629
2630 /* Initialize the statistics unit */
2631 err = mv88e6xxx_stats_set_histogram(chip);
2632 if (err)
2633 return err;
2634
2635 /* Clear the statistics counters for all ports */
2636 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2637 GLOBAL_STATS_OP_FLUSH_ALL);
2638 if (err)
2639 return err;
2640
2641 /* Wait for the flush to complete. */
2642 err = mv88e6xxx_g1_stats_wait(chip);
2643 if (err)
2644 return err;
2645
2646 return 0;
2647 }
2648
2649 static int mv88e6xxx_setup(struct dsa_switch *ds)
2650 {
2651 struct mv88e6xxx_chip *chip = ds->priv;
2652 int err;
2653 int i;
2654
2655 chip->ds = ds;
2656 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2657
2658 mutex_lock(&chip->reg_lock);
2659
2660 /* Setup Switch Port Registers */
2661 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2662 err = mv88e6xxx_setup_port(chip, i);
2663 if (err)
2664 goto unlock;
2665 }
2666
2667 /* Setup Switch Global 1 Registers */
2668 err = mv88e6xxx_g1_setup(chip);
2669 if (err)
2670 goto unlock;
2671
2672 /* Setup Switch Global 2 Registers */
2673 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2674 err = mv88e6xxx_g2_setup(chip);
2675 if (err)
2676 goto unlock;
2677 }
2678
2679 err = mv88e6xxx_vtu_setup(chip);
2680 if (err)
2681 goto unlock;
2682
2683 err = mv88e6xxx_pvt_setup(chip);
2684 if (err)
2685 goto unlock;
2686
2687 err = mv88e6xxx_atu_setup(chip);
2688 if (err)
2689 goto unlock;
2690
2691 /* Some generations have the configuration of sending reserved
2692 * management frames to the CPU in global2, others in
2693 * global1. Hence it does not fit the two setup functions
2694 * above.
2695 */
2696 if (chip->info->ops->mgmt_rsvd2cpu) {
2697 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2698 if (err)
2699 goto unlock;
2700 }
2701
2702 unlock:
2703 mutex_unlock(&chip->reg_lock);
2704
2705 return err;
2706 }
2707
2708 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2709 {
2710 struct mv88e6xxx_chip *chip = ds->priv;
2711 int err;
2712
2713 if (!chip->info->ops->set_switch_mac)
2714 return -EOPNOTSUPP;
2715
2716 mutex_lock(&chip->reg_lock);
2717 err = chip->info->ops->set_switch_mac(chip, addr);
2718 mutex_unlock(&chip->reg_lock);
2719
2720 return err;
2721 }
2722
2723 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2724 {
2725 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2726 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2727 u16 val;
2728 int err;
2729
2730 if (!chip->info->ops->phy_read)
2731 return -EOPNOTSUPP;
2732
2733 mutex_lock(&chip->reg_lock);
2734 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2735 mutex_unlock(&chip->reg_lock);
2736
2737 if (reg == MII_PHYSID2) {
2738 /* Some internal PHYS don't have a model number. Use
2739 * the mv88e6390 family model number instead.
2740 */
2741 if (!(val & 0x3f0))
2742 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2743 }
2744
2745 return err ? err : val;
2746 }
2747
2748 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2749 {
2750 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2751 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2752 int err;
2753
2754 if (!chip->info->ops->phy_write)
2755 return -EOPNOTSUPP;
2756
2757 mutex_lock(&chip->reg_lock);
2758 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2759 mutex_unlock(&chip->reg_lock);
2760
2761 return err;
2762 }
2763
2764 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2765 struct device_node *np,
2766 bool external)
2767 {
2768 static int index;
2769 struct mv88e6xxx_mdio_bus *mdio_bus;
2770 struct mii_bus *bus;
2771 int err;
2772
2773 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2774 if (!bus)
2775 return -ENOMEM;
2776
2777 mdio_bus = bus->priv;
2778 mdio_bus->bus = bus;
2779 mdio_bus->chip = chip;
2780 INIT_LIST_HEAD(&mdio_bus->list);
2781 mdio_bus->external = external;
2782
2783 if (np) {
2784 bus->name = np->full_name;
2785 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2786 } else {
2787 bus->name = "mv88e6xxx SMI";
2788 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2789 }
2790
2791 bus->read = mv88e6xxx_mdio_read;
2792 bus->write = mv88e6xxx_mdio_write;
2793 bus->parent = chip->dev;
2794
2795 if (np)
2796 err = of_mdiobus_register(bus, np);
2797 else
2798 err = mdiobus_register(bus);
2799 if (err) {
2800 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2801 return err;
2802 }
2803
2804 if (external)
2805 list_add_tail(&mdio_bus->list, &chip->mdios);
2806 else
2807 list_add(&mdio_bus->list, &chip->mdios);
2808
2809 return 0;
2810 }
2811
2812 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2813 { .compatible = "marvell,mv88e6xxx-mdio-external",
2814 .data = (void *)true },
2815 { },
2816 };
2817
2818 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2819 struct device_node *np)
2820 {
2821 const struct of_device_id *match;
2822 struct device_node *child;
2823 int err;
2824
2825 /* Always register one mdio bus for the internal/default mdio
2826 * bus. This maybe represented in the device tree, but is
2827 * optional.
2828 */
2829 child = of_get_child_by_name(np, "mdio");
2830 err = mv88e6xxx_mdio_register(chip, child, false);
2831 if (err)
2832 return err;
2833
2834 /* Walk the device tree, and see if there are any other nodes
2835 * which say they are compatible with the external mdio
2836 * bus.
2837 */
2838 for_each_available_child_of_node(np, child) {
2839 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2840 if (match) {
2841 err = mv88e6xxx_mdio_register(chip, child, true);
2842 if (err)
2843 return err;
2844 }
2845 }
2846
2847 return 0;
2848 }
2849
2850 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2851
2852 {
2853 struct mv88e6xxx_mdio_bus *mdio_bus;
2854 struct mii_bus *bus;
2855
2856 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2857 bus = mdio_bus->bus;
2858
2859 mdiobus_unregister(bus);
2860 }
2861 }
2862
2863 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2864 {
2865 struct mv88e6xxx_chip *chip = ds->priv;
2866
2867 return chip->eeprom_len;
2868 }
2869
2870 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2871 struct ethtool_eeprom *eeprom, u8 *data)
2872 {
2873 struct mv88e6xxx_chip *chip = ds->priv;
2874 int err;
2875
2876 if (!chip->info->ops->get_eeprom)
2877 return -EOPNOTSUPP;
2878
2879 mutex_lock(&chip->reg_lock);
2880 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2881 mutex_unlock(&chip->reg_lock);
2882
2883 if (err)
2884 return err;
2885
2886 eeprom->magic = 0xc3ec4951;
2887
2888 return 0;
2889 }
2890
2891 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2892 struct ethtool_eeprom *eeprom, u8 *data)
2893 {
2894 struct mv88e6xxx_chip *chip = ds->priv;
2895 int err;
2896
2897 if (!chip->info->ops->set_eeprom)
2898 return -EOPNOTSUPP;
2899
2900 if (eeprom->magic != 0xc3ec4951)
2901 return -EINVAL;
2902
2903 mutex_lock(&chip->reg_lock);
2904 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2905 mutex_unlock(&chip->reg_lock);
2906
2907 return err;
2908 }
2909
2910 static const struct mv88e6xxx_ops mv88e6085_ops = {
2911 /* MV88E6XXX_FAMILY_6097 */
2912 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2913 .phy_read = mv88e6xxx_phy_ppu_read,
2914 .phy_write = mv88e6xxx_phy_ppu_write,
2915 .port_set_link = mv88e6xxx_port_set_link,
2916 .port_set_duplex = mv88e6xxx_port_set_duplex,
2917 .port_set_speed = mv88e6185_port_set_speed,
2918 .port_tag_remap = mv88e6095_port_tag_remap,
2919 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2920 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2921 .port_set_ether_type = mv88e6351_port_set_ether_type,
2922 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2923 .port_pause_config = mv88e6097_port_pause_config,
2924 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2925 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2926 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2927 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2928 .stats_get_strings = mv88e6095_stats_get_strings,
2929 .stats_get_stats = mv88e6095_stats_get_stats,
2930 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2931 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2932 .watchdog_ops = &mv88e6097_watchdog_ops,
2933 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2934 .ppu_enable = mv88e6185_g1_ppu_enable,
2935 .ppu_disable = mv88e6185_g1_ppu_disable,
2936 .reset = mv88e6185_g1_reset,
2937 };
2938
2939 static const struct mv88e6xxx_ops mv88e6095_ops = {
2940 /* MV88E6XXX_FAMILY_6095 */
2941 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2942 .phy_read = mv88e6xxx_phy_ppu_read,
2943 .phy_write = mv88e6xxx_phy_ppu_write,
2944 .port_set_link = mv88e6xxx_port_set_link,
2945 .port_set_duplex = mv88e6xxx_port_set_duplex,
2946 .port_set_speed = mv88e6185_port_set_speed,
2947 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2948 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2949 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2950 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2951 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2952 .stats_get_strings = mv88e6095_stats_get_strings,
2953 .stats_get_stats = mv88e6095_stats_get_stats,
2954 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2955 .ppu_enable = mv88e6185_g1_ppu_enable,
2956 .ppu_disable = mv88e6185_g1_ppu_disable,
2957 .reset = mv88e6185_g1_reset,
2958 };
2959
2960 static const struct mv88e6xxx_ops mv88e6097_ops = {
2961 /* MV88E6XXX_FAMILY_6097 */
2962 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2963 .phy_read = mv88e6xxx_g2_smi_phy_read,
2964 .phy_write = mv88e6xxx_g2_smi_phy_write,
2965 .port_set_link = mv88e6xxx_port_set_link,
2966 .port_set_duplex = mv88e6xxx_port_set_duplex,
2967 .port_set_speed = mv88e6185_port_set_speed,
2968 .port_tag_remap = mv88e6095_port_tag_remap,
2969 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2970 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2971 .port_set_ether_type = mv88e6351_port_set_ether_type,
2972 .port_jumbo_config = mv88e6165_port_jumbo_config,
2973 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2974 .port_pause_config = mv88e6097_port_pause_config,
2975 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2976 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2977 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2978 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2979 .stats_get_strings = mv88e6095_stats_get_strings,
2980 .stats_get_stats = mv88e6095_stats_get_stats,
2981 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2982 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2983 .watchdog_ops = &mv88e6097_watchdog_ops,
2984 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2985 .reset = mv88e6352_g1_reset,
2986 };
2987
2988 static const struct mv88e6xxx_ops mv88e6123_ops = {
2989 /* MV88E6XXX_FAMILY_6165 */
2990 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2991 .phy_read = mv88e6165_phy_read,
2992 .phy_write = mv88e6165_phy_write,
2993 .port_set_link = mv88e6xxx_port_set_link,
2994 .port_set_duplex = mv88e6xxx_port_set_duplex,
2995 .port_set_speed = mv88e6185_port_set_speed,
2996 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2997 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2998 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2999 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3000 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3001 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3002 .stats_get_strings = mv88e6095_stats_get_strings,
3003 .stats_get_stats = mv88e6095_stats_get_stats,
3004 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3005 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3006 .watchdog_ops = &mv88e6097_watchdog_ops,
3007 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3008 .reset = mv88e6352_g1_reset,
3009 };
3010
3011 static const struct mv88e6xxx_ops mv88e6131_ops = {
3012 /* MV88E6XXX_FAMILY_6185 */
3013 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3014 .phy_read = mv88e6xxx_phy_ppu_read,
3015 .phy_write = mv88e6xxx_phy_ppu_write,
3016 .port_set_link = mv88e6xxx_port_set_link,
3017 .port_set_duplex = mv88e6xxx_port_set_duplex,
3018 .port_set_speed = mv88e6185_port_set_speed,
3019 .port_tag_remap = mv88e6095_port_tag_remap,
3020 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3021 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3022 .port_set_ether_type = mv88e6351_port_set_ether_type,
3023 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3024 .port_jumbo_config = mv88e6165_port_jumbo_config,
3025 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3026 .port_pause_config = mv88e6097_port_pause_config,
3027 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3028 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3029 .stats_get_strings = mv88e6095_stats_get_strings,
3030 .stats_get_stats = mv88e6095_stats_get_stats,
3031 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3032 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3033 .watchdog_ops = &mv88e6097_watchdog_ops,
3034 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3035 .ppu_enable = mv88e6185_g1_ppu_enable,
3036 .ppu_disable = mv88e6185_g1_ppu_disable,
3037 .reset = mv88e6185_g1_reset,
3038 };
3039
3040 static const struct mv88e6xxx_ops mv88e6141_ops = {
3041 /* MV88E6XXX_FAMILY_6341 */
3042 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3043 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3044 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3045 .phy_read = mv88e6xxx_g2_smi_phy_read,
3046 .phy_write = mv88e6xxx_g2_smi_phy_write,
3047 .port_set_link = mv88e6xxx_port_set_link,
3048 .port_set_duplex = mv88e6xxx_port_set_duplex,
3049 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3050 .port_set_speed = mv88e6390_port_set_speed,
3051 .port_tag_remap = mv88e6095_port_tag_remap,
3052 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3053 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3054 .port_set_ether_type = mv88e6351_port_set_ether_type,
3055 .port_jumbo_config = mv88e6165_port_jumbo_config,
3056 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3057 .port_pause_config = mv88e6097_port_pause_config,
3058 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3059 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3060 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3061 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3062 .stats_get_strings = mv88e6320_stats_get_strings,
3063 .stats_get_stats = mv88e6390_stats_get_stats,
3064 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3065 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3066 .watchdog_ops = &mv88e6390_watchdog_ops,
3067 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3068 .reset = mv88e6352_g1_reset,
3069 };
3070
3071 static const struct mv88e6xxx_ops mv88e6161_ops = {
3072 /* MV88E6XXX_FAMILY_6165 */
3073 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3074 .phy_read = mv88e6165_phy_read,
3075 .phy_write = mv88e6165_phy_write,
3076 .port_set_link = mv88e6xxx_port_set_link,
3077 .port_set_duplex = mv88e6xxx_port_set_duplex,
3078 .port_set_speed = mv88e6185_port_set_speed,
3079 .port_tag_remap = mv88e6095_port_tag_remap,
3080 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3081 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3082 .port_set_ether_type = mv88e6351_port_set_ether_type,
3083 .port_jumbo_config = mv88e6165_port_jumbo_config,
3084 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3085 .port_pause_config = mv88e6097_port_pause_config,
3086 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3087 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3088 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3089 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3090 .stats_get_strings = mv88e6095_stats_get_strings,
3091 .stats_get_stats = mv88e6095_stats_get_stats,
3092 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3093 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3094 .watchdog_ops = &mv88e6097_watchdog_ops,
3095 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3096 .reset = mv88e6352_g1_reset,
3097 };
3098
3099 static const struct mv88e6xxx_ops mv88e6165_ops = {
3100 /* MV88E6XXX_FAMILY_6165 */
3101 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3102 .phy_read = mv88e6165_phy_read,
3103 .phy_write = mv88e6165_phy_write,
3104 .port_set_link = mv88e6xxx_port_set_link,
3105 .port_set_duplex = mv88e6xxx_port_set_duplex,
3106 .port_set_speed = mv88e6185_port_set_speed,
3107 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3108 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3109 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3110 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3111 .stats_get_strings = mv88e6095_stats_get_strings,
3112 .stats_get_stats = mv88e6095_stats_get_stats,
3113 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3114 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3115 .watchdog_ops = &mv88e6097_watchdog_ops,
3116 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3117 .reset = mv88e6352_g1_reset,
3118 };
3119
3120 static const struct mv88e6xxx_ops mv88e6171_ops = {
3121 /* MV88E6XXX_FAMILY_6351 */
3122 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3123 .phy_read = mv88e6xxx_g2_smi_phy_read,
3124 .phy_write = mv88e6xxx_g2_smi_phy_write,
3125 .port_set_link = mv88e6xxx_port_set_link,
3126 .port_set_duplex = mv88e6xxx_port_set_duplex,
3127 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3128 .port_set_speed = mv88e6185_port_set_speed,
3129 .port_tag_remap = mv88e6095_port_tag_remap,
3130 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3131 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3132 .port_set_ether_type = mv88e6351_port_set_ether_type,
3133 .port_jumbo_config = mv88e6165_port_jumbo_config,
3134 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3135 .port_pause_config = mv88e6097_port_pause_config,
3136 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3137 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3138 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3139 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3140 .stats_get_strings = mv88e6095_stats_get_strings,
3141 .stats_get_stats = mv88e6095_stats_get_stats,
3142 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3143 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3144 .watchdog_ops = &mv88e6097_watchdog_ops,
3145 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3146 .reset = mv88e6352_g1_reset,
3147 };
3148
3149 static const struct mv88e6xxx_ops mv88e6172_ops = {
3150 /* MV88E6XXX_FAMILY_6352 */
3151 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3152 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3153 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3154 .phy_read = mv88e6xxx_g2_smi_phy_read,
3155 .phy_write = mv88e6xxx_g2_smi_phy_write,
3156 .port_set_link = mv88e6xxx_port_set_link,
3157 .port_set_duplex = mv88e6xxx_port_set_duplex,
3158 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3159 .port_set_speed = mv88e6352_port_set_speed,
3160 .port_tag_remap = mv88e6095_port_tag_remap,
3161 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3162 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3163 .port_set_ether_type = mv88e6351_port_set_ether_type,
3164 .port_jumbo_config = mv88e6165_port_jumbo_config,
3165 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3166 .port_pause_config = mv88e6097_port_pause_config,
3167 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3168 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3169 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3170 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3171 .stats_get_strings = mv88e6095_stats_get_strings,
3172 .stats_get_stats = mv88e6095_stats_get_stats,
3173 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3174 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3175 .watchdog_ops = &mv88e6097_watchdog_ops,
3176 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3177 .reset = mv88e6352_g1_reset,
3178 };
3179
3180 static const struct mv88e6xxx_ops mv88e6175_ops = {
3181 /* MV88E6XXX_FAMILY_6351 */
3182 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3183 .phy_read = mv88e6xxx_g2_smi_phy_read,
3184 .phy_write = mv88e6xxx_g2_smi_phy_write,
3185 .port_set_link = mv88e6xxx_port_set_link,
3186 .port_set_duplex = mv88e6xxx_port_set_duplex,
3187 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3188 .port_set_speed = mv88e6185_port_set_speed,
3189 .port_tag_remap = mv88e6095_port_tag_remap,
3190 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3191 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3192 .port_set_ether_type = mv88e6351_port_set_ether_type,
3193 .port_jumbo_config = mv88e6165_port_jumbo_config,
3194 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3195 .port_pause_config = mv88e6097_port_pause_config,
3196 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3197 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3198 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3199 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3200 .stats_get_strings = mv88e6095_stats_get_strings,
3201 .stats_get_stats = mv88e6095_stats_get_stats,
3202 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3203 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3204 .watchdog_ops = &mv88e6097_watchdog_ops,
3205 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3206 .reset = mv88e6352_g1_reset,
3207 };
3208
3209 static const struct mv88e6xxx_ops mv88e6176_ops = {
3210 /* MV88E6XXX_FAMILY_6352 */
3211 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3212 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3213 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3214 .phy_read = mv88e6xxx_g2_smi_phy_read,
3215 .phy_write = mv88e6xxx_g2_smi_phy_write,
3216 .port_set_link = mv88e6xxx_port_set_link,
3217 .port_set_duplex = mv88e6xxx_port_set_duplex,
3218 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3219 .port_set_speed = mv88e6352_port_set_speed,
3220 .port_tag_remap = mv88e6095_port_tag_remap,
3221 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3222 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3223 .port_set_ether_type = mv88e6351_port_set_ether_type,
3224 .port_jumbo_config = mv88e6165_port_jumbo_config,
3225 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3226 .port_pause_config = mv88e6097_port_pause_config,
3227 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3228 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3229 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3230 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3231 .stats_get_strings = mv88e6095_stats_get_strings,
3232 .stats_get_stats = mv88e6095_stats_get_stats,
3233 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3234 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3235 .watchdog_ops = &mv88e6097_watchdog_ops,
3236 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3237 .reset = mv88e6352_g1_reset,
3238 };
3239
3240 static const struct mv88e6xxx_ops mv88e6185_ops = {
3241 /* MV88E6XXX_FAMILY_6185 */
3242 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3243 .phy_read = mv88e6xxx_phy_ppu_read,
3244 .phy_write = mv88e6xxx_phy_ppu_write,
3245 .port_set_link = mv88e6xxx_port_set_link,
3246 .port_set_duplex = mv88e6xxx_port_set_duplex,
3247 .port_set_speed = mv88e6185_port_set_speed,
3248 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3249 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3250 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3251 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3252 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3253 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3254 .stats_get_strings = mv88e6095_stats_get_strings,
3255 .stats_get_stats = mv88e6095_stats_get_stats,
3256 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3257 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3258 .watchdog_ops = &mv88e6097_watchdog_ops,
3259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3260 .ppu_enable = mv88e6185_g1_ppu_enable,
3261 .ppu_disable = mv88e6185_g1_ppu_disable,
3262 .reset = mv88e6185_g1_reset,
3263 };
3264
3265 static const struct mv88e6xxx_ops mv88e6190_ops = {
3266 /* MV88E6XXX_FAMILY_6390 */
3267 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3268 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3270 .phy_read = mv88e6xxx_g2_smi_phy_read,
3271 .phy_write = mv88e6xxx_g2_smi_phy_write,
3272 .port_set_link = mv88e6xxx_port_set_link,
3273 .port_set_duplex = mv88e6xxx_port_set_duplex,
3274 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3275 .port_set_speed = mv88e6390_port_set_speed,
3276 .port_tag_remap = mv88e6390_port_tag_remap,
3277 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3278 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3279 .port_set_ether_type = mv88e6351_port_set_ether_type,
3280 .port_pause_config = mv88e6390_port_pause_config,
3281 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3282 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3283 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3284 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3285 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3286 .stats_get_strings = mv88e6320_stats_get_strings,
3287 .stats_get_stats = mv88e6390_stats_get_stats,
3288 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3289 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3290 .watchdog_ops = &mv88e6390_watchdog_ops,
3291 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3292 .reset = mv88e6352_g1_reset,
3293 };
3294
3295 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3296 /* MV88E6XXX_FAMILY_6390 */
3297 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3298 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3299 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3300 .phy_read = mv88e6xxx_g2_smi_phy_read,
3301 .phy_write = mv88e6xxx_g2_smi_phy_write,
3302 .port_set_link = mv88e6xxx_port_set_link,
3303 .port_set_duplex = mv88e6xxx_port_set_duplex,
3304 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3305 .port_set_speed = mv88e6390x_port_set_speed,
3306 .port_tag_remap = mv88e6390_port_tag_remap,
3307 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3308 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3309 .port_set_ether_type = mv88e6351_port_set_ether_type,
3310 .port_pause_config = mv88e6390_port_pause_config,
3311 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3312 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3313 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3314 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3315 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3316 .stats_get_strings = mv88e6320_stats_get_strings,
3317 .stats_get_stats = mv88e6390_stats_get_stats,
3318 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3319 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3320 .watchdog_ops = &mv88e6390_watchdog_ops,
3321 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3322 .reset = mv88e6352_g1_reset,
3323 };
3324
3325 static const struct mv88e6xxx_ops mv88e6191_ops = {
3326 /* MV88E6XXX_FAMILY_6390 */
3327 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3328 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3329 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3330 .phy_read = mv88e6xxx_g2_smi_phy_read,
3331 .phy_write = mv88e6xxx_g2_smi_phy_write,
3332 .port_set_link = mv88e6xxx_port_set_link,
3333 .port_set_duplex = mv88e6xxx_port_set_duplex,
3334 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3335 .port_set_speed = mv88e6390_port_set_speed,
3336 .port_tag_remap = mv88e6390_port_tag_remap,
3337 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3338 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3339 .port_set_ether_type = mv88e6351_port_set_ether_type,
3340 .port_pause_config = mv88e6390_port_pause_config,
3341 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3342 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3343 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3344 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3345 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3346 .stats_get_strings = mv88e6320_stats_get_strings,
3347 .stats_get_stats = mv88e6390_stats_get_stats,
3348 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3349 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3350 .watchdog_ops = &mv88e6390_watchdog_ops,
3351 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3352 .reset = mv88e6352_g1_reset,
3353 };
3354
3355 static const struct mv88e6xxx_ops mv88e6240_ops = {
3356 /* MV88E6XXX_FAMILY_6352 */
3357 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3358 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3359 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3360 .phy_read = mv88e6xxx_g2_smi_phy_read,
3361 .phy_write = mv88e6xxx_g2_smi_phy_write,
3362 .port_set_link = mv88e6xxx_port_set_link,
3363 .port_set_duplex = mv88e6xxx_port_set_duplex,
3364 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3365 .port_set_speed = mv88e6352_port_set_speed,
3366 .port_tag_remap = mv88e6095_port_tag_remap,
3367 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3368 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3369 .port_set_ether_type = mv88e6351_port_set_ether_type,
3370 .port_jumbo_config = mv88e6165_port_jumbo_config,
3371 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3372 .port_pause_config = mv88e6097_port_pause_config,
3373 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3374 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3375 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3376 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3377 .stats_get_strings = mv88e6095_stats_get_strings,
3378 .stats_get_stats = mv88e6095_stats_get_stats,
3379 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3380 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3381 .watchdog_ops = &mv88e6097_watchdog_ops,
3382 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3383 .reset = mv88e6352_g1_reset,
3384 };
3385
3386 static const struct mv88e6xxx_ops mv88e6290_ops = {
3387 /* MV88E6XXX_FAMILY_6390 */
3388 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3389 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3390 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3391 .phy_read = mv88e6xxx_g2_smi_phy_read,
3392 .phy_write = mv88e6xxx_g2_smi_phy_write,
3393 .port_set_link = mv88e6xxx_port_set_link,
3394 .port_set_duplex = mv88e6xxx_port_set_duplex,
3395 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3396 .port_set_speed = mv88e6390_port_set_speed,
3397 .port_tag_remap = mv88e6390_port_tag_remap,
3398 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3399 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3400 .port_set_ether_type = mv88e6351_port_set_ether_type,
3401 .port_pause_config = mv88e6390_port_pause_config,
3402 .port_set_cmode = mv88e6390x_port_set_cmode,
3403 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3404 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3405 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3406 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3407 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3408 .stats_get_strings = mv88e6320_stats_get_strings,
3409 .stats_get_stats = mv88e6390_stats_get_stats,
3410 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3411 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3412 .watchdog_ops = &mv88e6390_watchdog_ops,
3413 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3414 .reset = mv88e6352_g1_reset,
3415 };
3416
3417 static const struct mv88e6xxx_ops mv88e6320_ops = {
3418 /* MV88E6XXX_FAMILY_6320 */
3419 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3420 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3421 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3422 .phy_read = mv88e6xxx_g2_smi_phy_read,
3423 .phy_write = mv88e6xxx_g2_smi_phy_write,
3424 .port_set_link = mv88e6xxx_port_set_link,
3425 .port_set_duplex = mv88e6xxx_port_set_duplex,
3426 .port_set_speed = mv88e6185_port_set_speed,
3427 .port_tag_remap = mv88e6095_port_tag_remap,
3428 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3429 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3430 .port_set_ether_type = mv88e6351_port_set_ether_type,
3431 .port_jumbo_config = mv88e6165_port_jumbo_config,
3432 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3433 .port_pause_config = mv88e6097_port_pause_config,
3434 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3435 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3436 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3437 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3438 .stats_get_strings = mv88e6320_stats_get_strings,
3439 .stats_get_stats = mv88e6320_stats_get_stats,
3440 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3441 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3442 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3443 .reset = mv88e6352_g1_reset,
3444 };
3445
3446 static const struct mv88e6xxx_ops mv88e6321_ops = {
3447 /* MV88E6XXX_FAMILY_6321 */
3448 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3449 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3450 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3451 .phy_read = mv88e6xxx_g2_smi_phy_read,
3452 .phy_write = mv88e6xxx_g2_smi_phy_write,
3453 .port_set_link = mv88e6xxx_port_set_link,
3454 .port_set_duplex = mv88e6xxx_port_set_duplex,
3455 .port_set_speed = mv88e6185_port_set_speed,
3456 .port_tag_remap = mv88e6095_port_tag_remap,
3457 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3458 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3459 .port_set_ether_type = mv88e6351_port_set_ether_type,
3460 .port_jumbo_config = mv88e6165_port_jumbo_config,
3461 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3462 .port_pause_config = mv88e6097_port_pause_config,
3463 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3464 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3465 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3466 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3467 .stats_get_strings = mv88e6320_stats_get_strings,
3468 .stats_get_stats = mv88e6320_stats_get_stats,
3469 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3470 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3471 .reset = mv88e6352_g1_reset,
3472 };
3473
3474 static const struct mv88e6xxx_ops mv88e6341_ops = {
3475 /* MV88E6XXX_FAMILY_6341 */
3476 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3477 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3478 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3479 .phy_read = mv88e6xxx_g2_smi_phy_read,
3480 .phy_write = mv88e6xxx_g2_smi_phy_write,
3481 .port_set_link = mv88e6xxx_port_set_link,
3482 .port_set_duplex = mv88e6xxx_port_set_duplex,
3483 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3484 .port_set_speed = mv88e6390_port_set_speed,
3485 .port_tag_remap = mv88e6095_port_tag_remap,
3486 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3487 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3488 .port_set_ether_type = mv88e6351_port_set_ether_type,
3489 .port_jumbo_config = mv88e6165_port_jumbo_config,
3490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3491 .port_pause_config = mv88e6097_port_pause_config,
3492 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3493 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3494 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3495 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3496 .stats_get_strings = mv88e6320_stats_get_strings,
3497 .stats_get_stats = mv88e6390_stats_get_stats,
3498 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3499 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3500 .watchdog_ops = &mv88e6390_watchdog_ops,
3501 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3502 .reset = mv88e6352_g1_reset,
3503 };
3504
3505 static const struct mv88e6xxx_ops mv88e6350_ops = {
3506 /* MV88E6XXX_FAMILY_6351 */
3507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3508 .phy_read = mv88e6xxx_g2_smi_phy_read,
3509 .phy_write = mv88e6xxx_g2_smi_phy_write,
3510 .port_set_link = mv88e6xxx_port_set_link,
3511 .port_set_duplex = mv88e6xxx_port_set_duplex,
3512 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3513 .port_set_speed = mv88e6185_port_set_speed,
3514 .port_tag_remap = mv88e6095_port_tag_remap,
3515 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3516 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3517 .port_set_ether_type = mv88e6351_port_set_ether_type,
3518 .port_jumbo_config = mv88e6165_port_jumbo_config,
3519 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3520 .port_pause_config = mv88e6097_port_pause_config,
3521 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3522 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3523 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3524 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3525 .stats_get_strings = mv88e6095_stats_get_strings,
3526 .stats_get_stats = mv88e6095_stats_get_stats,
3527 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3528 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3529 .watchdog_ops = &mv88e6097_watchdog_ops,
3530 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3531 .reset = mv88e6352_g1_reset,
3532 };
3533
3534 static const struct mv88e6xxx_ops mv88e6351_ops = {
3535 /* MV88E6XXX_FAMILY_6351 */
3536 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3537 .phy_read = mv88e6xxx_g2_smi_phy_read,
3538 .phy_write = mv88e6xxx_g2_smi_phy_write,
3539 .port_set_link = mv88e6xxx_port_set_link,
3540 .port_set_duplex = mv88e6xxx_port_set_duplex,
3541 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3542 .port_set_speed = mv88e6185_port_set_speed,
3543 .port_tag_remap = mv88e6095_port_tag_remap,
3544 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3545 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3546 .port_set_ether_type = mv88e6351_port_set_ether_type,
3547 .port_jumbo_config = mv88e6165_port_jumbo_config,
3548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3549 .port_pause_config = mv88e6097_port_pause_config,
3550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3552 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3553 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3554 .stats_get_strings = mv88e6095_stats_get_strings,
3555 .stats_get_stats = mv88e6095_stats_get_stats,
3556 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3557 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3558 .watchdog_ops = &mv88e6097_watchdog_ops,
3559 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3560 .reset = mv88e6352_g1_reset,
3561 };
3562
3563 static const struct mv88e6xxx_ops mv88e6352_ops = {
3564 /* MV88E6XXX_FAMILY_6352 */
3565 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3566 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3567 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3568 .phy_read = mv88e6xxx_g2_smi_phy_read,
3569 .phy_write = mv88e6xxx_g2_smi_phy_write,
3570 .port_set_link = mv88e6xxx_port_set_link,
3571 .port_set_duplex = mv88e6xxx_port_set_duplex,
3572 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3573 .port_set_speed = mv88e6352_port_set_speed,
3574 .port_tag_remap = mv88e6095_port_tag_remap,
3575 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3576 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3577 .port_set_ether_type = mv88e6351_port_set_ether_type,
3578 .port_jumbo_config = mv88e6165_port_jumbo_config,
3579 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3580 .port_pause_config = mv88e6097_port_pause_config,
3581 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3582 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3583 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3584 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3585 .stats_get_strings = mv88e6095_stats_get_strings,
3586 .stats_get_stats = mv88e6095_stats_get_stats,
3587 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3588 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3589 .watchdog_ops = &mv88e6097_watchdog_ops,
3590 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3591 .reset = mv88e6352_g1_reset,
3592 };
3593
3594 static const struct mv88e6xxx_ops mv88e6390_ops = {
3595 /* MV88E6XXX_FAMILY_6390 */
3596 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3597 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3599 .phy_read = mv88e6xxx_g2_smi_phy_read,
3600 .phy_write = mv88e6xxx_g2_smi_phy_write,
3601 .port_set_link = mv88e6xxx_port_set_link,
3602 .port_set_duplex = mv88e6xxx_port_set_duplex,
3603 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3604 .port_set_speed = mv88e6390_port_set_speed,
3605 .port_tag_remap = mv88e6390_port_tag_remap,
3606 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3607 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3608 .port_set_ether_type = mv88e6351_port_set_ether_type,
3609 .port_jumbo_config = mv88e6165_port_jumbo_config,
3610 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3611 .port_pause_config = mv88e6390_port_pause_config,
3612 .port_set_cmode = mv88e6390x_port_set_cmode,
3613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3615 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3616 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3617 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3618 .stats_get_strings = mv88e6320_stats_get_strings,
3619 .stats_get_stats = mv88e6390_stats_get_stats,
3620 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3621 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3622 .watchdog_ops = &mv88e6390_watchdog_ops,
3623 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3624 .reset = mv88e6352_g1_reset,
3625 };
3626
3627 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3628 /* MV88E6XXX_FAMILY_6390 */
3629 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3630 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3631 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3632 .phy_read = mv88e6xxx_g2_smi_phy_read,
3633 .phy_write = mv88e6xxx_g2_smi_phy_write,
3634 .port_set_link = mv88e6xxx_port_set_link,
3635 .port_set_duplex = mv88e6xxx_port_set_duplex,
3636 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3637 .port_set_speed = mv88e6390x_port_set_speed,
3638 .port_tag_remap = mv88e6390_port_tag_remap,
3639 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3640 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3641 .port_set_ether_type = mv88e6351_port_set_ether_type,
3642 .port_jumbo_config = mv88e6165_port_jumbo_config,
3643 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3644 .port_pause_config = mv88e6390_port_pause_config,
3645 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3646 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3647 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3648 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3649 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3650 .stats_get_strings = mv88e6320_stats_get_strings,
3651 .stats_get_stats = mv88e6390_stats_get_stats,
3652 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3653 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3654 .watchdog_ops = &mv88e6390_watchdog_ops,
3655 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3656 .reset = mv88e6352_g1_reset,
3657 };
3658
3659 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3660 [MV88E6085] = {
3661 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3662 .family = MV88E6XXX_FAMILY_6097,
3663 .name = "Marvell 88E6085",
3664 .num_databases = 4096,
3665 .num_ports = 10,
3666 .max_vid = 4095,
3667 .port_base_addr = 0x10,
3668 .global1_addr = 0x1b,
3669 .age_time_coeff = 15000,
3670 .g1_irqs = 8,
3671 .atu_move_port_mask = 0xf,
3672 .pvt = true,
3673 .tag_protocol = DSA_TAG_PROTO_DSA,
3674 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3675 .ops = &mv88e6085_ops,
3676 },
3677
3678 [MV88E6095] = {
3679 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3680 .family = MV88E6XXX_FAMILY_6095,
3681 .name = "Marvell 88E6095/88E6095F",
3682 .num_databases = 256,
3683 .num_ports = 11,
3684 .max_vid = 4095,
3685 .port_base_addr = 0x10,
3686 .global1_addr = 0x1b,
3687 .age_time_coeff = 15000,
3688 .g1_irqs = 8,
3689 .atu_move_port_mask = 0xf,
3690 .tag_protocol = DSA_TAG_PROTO_DSA,
3691 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3692 .ops = &mv88e6095_ops,
3693 },
3694
3695 [MV88E6097] = {
3696 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3697 .family = MV88E6XXX_FAMILY_6097,
3698 .name = "Marvell 88E6097/88E6097F",
3699 .num_databases = 4096,
3700 .num_ports = 11,
3701 .max_vid = 4095,
3702 .port_base_addr = 0x10,
3703 .global1_addr = 0x1b,
3704 .age_time_coeff = 15000,
3705 .g1_irqs = 8,
3706 .atu_move_port_mask = 0xf,
3707 .pvt = true,
3708 .tag_protocol = DSA_TAG_PROTO_EDSA,
3709 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3710 .ops = &mv88e6097_ops,
3711 },
3712
3713 [MV88E6123] = {
3714 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3715 .family = MV88E6XXX_FAMILY_6165,
3716 .name = "Marvell 88E6123",
3717 .num_databases = 4096,
3718 .num_ports = 3,
3719 .max_vid = 4095,
3720 .port_base_addr = 0x10,
3721 .global1_addr = 0x1b,
3722 .age_time_coeff = 15000,
3723 .g1_irqs = 9,
3724 .atu_move_port_mask = 0xf,
3725 .pvt = true,
3726 .tag_protocol = DSA_TAG_PROTO_DSA,
3727 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3728 .ops = &mv88e6123_ops,
3729 },
3730
3731 [MV88E6131] = {
3732 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3733 .family = MV88E6XXX_FAMILY_6185,
3734 .name = "Marvell 88E6131",
3735 .num_databases = 256,
3736 .num_ports = 8,
3737 .max_vid = 4095,
3738 .port_base_addr = 0x10,
3739 .global1_addr = 0x1b,
3740 .age_time_coeff = 15000,
3741 .g1_irqs = 9,
3742 .atu_move_port_mask = 0xf,
3743 .tag_protocol = DSA_TAG_PROTO_DSA,
3744 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3745 .ops = &mv88e6131_ops,
3746 },
3747
3748 [MV88E6141] = {
3749 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3750 .family = MV88E6XXX_FAMILY_6341,
3751 .name = "Marvell 88E6341",
3752 .num_databases = 4096,
3753 .num_ports = 6,
3754 .max_vid = 4095,
3755 .port_base_addr = 0x10,
3756 .global1_addr = 0x1b,
3757 .age_time_coeff = 3750,
3758 .atu_move_port_mask = 0x1f,
3759 .pvt = true,
3760 .tag_protocol = DSA_TAG_PROTO_EDSA,
3761 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3762 .ops = &mv88e6141_ops,
3763 },
3764
3765 [MV88E6161] = {
3766 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3767 .family = MV88E6XXX_FAMILY_6165,
3768 .name = "Marvell 88E6161",
3769 .num_databases = 4096,
3770 .num_ports = 6,
3771 .max_vid = 4095,
3772 .port_base_addr = 0x10,
3773 .global1_addr = 0x1b,
3774 .age_time_coeff = 15000,
3775 .g1_irqs = 9,
3776 .atu_move_port_mask = 0xf,
3777 .pvt = true,
3778 .tag_protocol = DSA_TAG_PROTO_DSA,
3779 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3780 .ops = &mv88e6161_ops,
3781 },
3782
3783 [MV88E6165] = {
3784 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3785 .family = MV88E6XXX_FAMILY_6165,
3786 .name = "Marvell 88E6165",
3787 .num_databases = 4096,
3788 .num_ports = 6,
3789 .max_vid = 4095,
3790 .port_base_addr = 0x10,
3791 .global1_addr = 0x1b,
3792 .age_time_coeff = 15000,
3793 .g1_irqs = 9,
3794 .atu_move_port_mask = 0xf,
3795 .pvt = true,
3796 .tag_protocol = DSA_TAG_PROTO_DSA,
3797 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3798 .ops = &mv88e6165_ops,
3799 },
3800
3801 [MV88E6171] = {
3802 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3803 .family = MV88E6XXX_FAMILY_6351,
3804 .name = "Marvell 88E6171",
3805 .num_databases = 4096,
3806 .num_ports = 7,
3807 .max_vid = 4095,
3808 .port_base_addr = 0x10,
3809 .global1_addr = 0x1b,
3810 .age_time_coeff = 15000,
3811 .g1_irqs = 9,
3812 .atu_move_port_mask = 0xf,
3813 .pvt = true,
3814 .tag_protocol = DSA_TAG_PROTO_EDSA,
3815 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3816 .ops = &mv88e6171_ops,
3817 },
3818
3819 [MV88E6172] = {
3820 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3821 .family = MV88E6XXX_FAMILY_6352,
3822 .name = "Marvell 88E6172",
3823 .num_databases = 4096,
3824 .num_ports = 7,
3825 .max_vid = 4095,
3826 .port_base_addr = 0x10,
3827 .global1_addr = 0x1b,
3828 .age_time_coeff = 15000,
3829 .g1_irqs = 9,
3830 .atu_move_port_mask = 0xf,
3831 .pvt = true,
3832 .tag_protocol = DSA_TAG_PROTO_EDSA,
3833 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3834 .ops = &mv88e6172_ops,
3835 },
3836
3837 [MV88E6175] = {
3838 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3839 .family = MV88E6XXX_FAMILY_6351,
3840 .name = "Marvell 88E6175",
3841 .num_databases = 4096,
3842 .num_ports = 7,
3843 .max_vid = 4095,
3844 .port_base_addr = 0x10,
3845 .global1_addr = 0x1b,
3846 .age_time_coeff = 15000,
3847 .g1_irqs = 9,
3848 .atu_move_port_mask = 0xf,
3849 .pvt = true,
3850 .tag_protocol = DSA_TAG_PROTO_EDSA,
3851 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3852 .ops = &mv88e6175_ops,
3853 },
3854
3855 [MV88E6176] = {
3856 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3857 .family = MV88E6XXX_FAMILY_6352,
3858 .name = "Marvell 88E6176",
3859 .num_databases = 4096,
3860 .num_ports = 7,
3861 .max_vid = 4095,
3862 .port_base_addr = 0x10,
3863 .global1_addr = 0x1b,
3864 .age_time_coeff = 15000,
3865 .g1_irqs = 9,
3866 .atu_move_port_mask = 0xf,
3867 .pvt = true,
3868 .tag_protocol = DSA_TAG_PROTO_EDSA,
3869 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3870 .ops = &mv88e6176_ops,
3871 },
3872
3873 [MV88E6185] = {
3874 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3875 .family = MV88E6XXX_FAMILY_6185,
3876 .name = "Marvell 88E6185",
3877 .num_databases = 256,
3878 .num_ports = 10,
3879 .max_vid = 4095,
3880 .port_base_addr = 0x10,
3881 .global1_addr = 0x1b,
3882 .age_time_coeff = 15000,
3883 .g1_irqs = 8,
3884 .atu_move_port_mask = 0xf,
3885 .tag_protocol = DSA_TAG_PROTO_EDSA,
3886 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3887 .ops = &mv88e6185_ops,
3888 },
3889
3890 [MV88E6190] = {
3891 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3892 .family = MV88E6XXX_FAMILY_6390,
3893 .name = "Marvell 88E6190",
3894 .num_databases = 4096,
3895 .num_ports = 11, /* 10 + Z80 */
3896 .port_base_addr = 0x0,
3897 .global1_addr = 0x1b,
3898 .tag_protocol = DSA_TAG_PROTO_DSA,
3899 .age_time_coeff = 3750,
3900 .g1_irqs = 9,
3901 .pvt = true,
3902 .atu_move_port_mask = 0x1f,
3903 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3904 .ops = &mv88e6190_ops,
3905 },
3906
3907 [MV88E6190X] = {
3908 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3909 .family = MV88E6XXX_FAMILY_6390,
3910 .name = "Marvell 88E6190X",
3911 .num_databases = 4096,
3912 .num_ports = 11, /* 10 + Z80 */
3913 .port_base_addr = 0x0,
3914 .global1_addr = 0x1b,
3915 .age_time_coeff = 3750,
3916 .g1_irqs = 9,
3917 .atu_move_port_mask = 0x1f,
3918 .pvt = true,
3919 .tag_protocol = DSA_TAG_PROTO_DSA,
3920 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3921 .ops = &mv88e6190x_ops,
3922 },
3923
3924 [MV88E6191] = {
3925 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3926 .family = MV88E6XXX_FAMILY_6390,
3927 .name = "Marvell 88E6191",
3928 .num_databases = 4096,
3929 .num_ports = 11, /* 10 + Z80 */
3930 .port_base_addr = 0x0,
3931 .global1_addr = 0x1b,
3932 .age_time_coeff = 3750,
3933 .g1_irqs = 9,
3934 .atu_move_port_mask = 0x1f,
3935 .pvt = true,
3936 .tag_protocol = DSA_TAG_PROTO_DSA,
3937 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3938 .ops = &mv88e6191_ops,
3939 },
3940
3941 [MV88E6240] = {
3942 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3943 .family = MV88E6XXX_FAMILY_6352,
3944 .name = "Marvell 88E6240",
3945 .num_databases = 4096,
3946 .num_ports = 7,
3947 .max_vid = 4095,
3948 .port_base_addr = 0x10,
3949 .global1_addr = 0x1b,
3950 .age_time_coeff = 15000,
3951 .g1_irqs = 9,
3952 .atu_move_port_mask = 0xf,
3953 .pvt = true,
3954 .tag_protocol = DSA_TAG_PROTO_EDSA,
3955 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3956 .ops = &mv88e6240_ops,
3957 },
3958
3959 [MV88E6290] = {
3960 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3961 .family = MV88E6XXX_FAMILY_6390,
3962 .name = "Marvell 88E6290",
3963 .num_databases = 4096,
3964 .num_ports = 11, /* 10 + Z80 */
3965 .port_base_addr = 0x0,
3966 .global1_addr = 0x1b,
3967 .age_time_coeff = 3750,
3968 .g1_irqs = 9,
3969 .atu_move_port_mask = 0x1f,
3970 .pvt = true,
3971 .tag_protocol = DSA_TAG_PROTO_DSA,
3972 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3973 .ops = &mv88e6290_ops,
3974 },
3975
3976 [MV88E6320] = {
3977 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3978 .family = MV88E6XXX_FAMILY_6320,
3979 .name = "Marvell 88E6320",
3980 .num_databases = 4096,
3981 .num_ports = 7,
3982 .max_vid = 4095,
3983 .port_base_addr = 0x10,
3984 .global1_addr = 0x1b,
3985 .age_time_coeff = 15000,
3986 .g1_irqs = 8,
3987 .atu_move_port_mask = 0xf,
3988 .pvt = true,
3989 .tag_protocol = DSA_TAG_PROTO_EDSA,
3990 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3991 .ops = &mv88e6320_ops,
3992 },
3993
3994 [MV88E6321] = {
3995 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3996 .family = MV88E6XXX_FAMILY_6320,
3997 .name = "Marvell 88E6321",
3998 .num_databases = 4096,
3999 .num_ports = 7,
4000 .max_vid = 4095,
4001 .port_base_addr = 0x10,
4002 .global1_addr = 0x1b,
4003 .age_time_coeff = 15000,
4004 .g1_irqs = 8,
4005 .atu_move_port_mask = 0xf,
4006 .tag_protocol = DSA_TAG_PROTO_EDSA,
4007 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
4008 .ops = &mv88e6321_ops,
4009 },
4010
4011 [MV88E6341] = {
4012 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4013 .family = MV88E6XXX_FAMILY_6341,
4014 .name = "Marvell 88E6341",
4015 .num_databases = 4096,
4016 .num_ports = 6,
4017 .max_vid = 4095,
4018 .port_base_addr = 0x10,
4019 .global1_addr = 0x1b,
4020 .age_time_coeff = 3750,
4021 .atu_move_port_mask = 0x1f,
4022 .pvt = true,
4023 .tag_protocol = DSA_TAG_PROTO_EDSA,
4024 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4025 .ops = &mv88e6341_ops,
4026 },
4027
4028 [MV88E6350] = {
4029 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4030 .family = MV88E6XXX_FAMILY_6351,
4031 .name = "Marvell 88E6350",
4032 .num_databases = 4096,
4033 .num_ports = 7,
4034 .max_vid = 4095,
4035 .port_base_addr = 0x10,
4036 .global1_addr = 0x1b,
4037 .age_time_coeff = 15000,
4038 .g1_irqs = 9,
4039 .atu_move_port_mask = 0xf,
4040 .pvt = true,
4041 .tag_protocol = DSA_TAG_PROTO_EDSA,
4042 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4043 .ops = &mv88e6350_ops,
4044 },
4045
4046 [MV88E6351] = {
4047 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4048 .family = MV88E6XXX_FAMILY_6351,
4049 .name = "Marvell 88E6351",
4050 .num_databases = 4096,
4051 .num_ports = 7,
4052 .max_vid = 4095,
4053 .port_base_addr = 0x10,
4054 .global1_addr = 0x1b,
4055 .age_time_coeff = 15000,
4056 .g1_irqs = 9,
4057 .atu_move_port_mask = 0xf,
4058 .pvt = true,
4059 .tag_protocol = DSA_TAG_PROTO_EDSA,
4060 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4061 .ops = &mv88e6351_ops,
4062 },
4063
4064 [MV88E6352] = {
4065 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4066 .family = MV88E6XXX_FAMILY_6352,
4067 .name = "Marvell 88E6352",
4068 .num_databases = 4096,
4069 .num_ports = 7,
4070 .max_vid = 4095,
4071 .port_base_addr = 0x10,
4072 .global1_addr = 0x1b,
4073 .age_time_coeff = 15000,
4074 .g1_irqs = 9,
4075 .atu_move_port_mask = 0xf,
4076 .pvt = true,
4077 .tag_protocol = DSA_TAG_PROTO_EDSA,
4078 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4079 .ops = &mv88e6352_ops,
4080 },
4081 [MV88E6390] = {
4082 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4083 .family = MV88E6XXX_FAMILY_6390,
4084 .name = "Marvell 88E6390",
4085 .num_databases = 4096,
4086 .num_ports = 11, /* 10 + Z80 */
4087 .port_base_addr = 0x0,
4088 .global1_addr = 0x1b,
4089 .age_time_coeff = 3750,
4090 .g1_irqs = 9,
4091 .atu_move_port_mask = 0x1f,
4092 .pvt = true,
4093 .tag_protocol = DSA_TAG_PROTO_DSA,
4094 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4095 .ops = &mv88e6390_ops,
4096 },
4097 [MV88E6390X] = {
4098 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4099 .family = MV88E6XXX_FAMILY_6390,
4100 .name = "Marvell 88E6390X",
4101 .num_databases = 4096,
4102 .num_ports = 11, /* 10 + Z80 */
4103 .port_base_addr = 0x0,
4104 .global1_addr = 0x1b,
4105 .age_time_coeff = 3750,
4106 .g1_irqs = 9,
4107 .atu_move_port_mask = 0x1f,
4108 .pvt = true,
4109 .tag_protocol = DSA_TAG_PROTO_DSA,
4110 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4111 .ops = &mv88e6390x_ops,
4112 },
4113 };
4114
4115 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4116 {
4117 int i;
4118
4119 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4120 if (mv88e6xxx_table[i].prod_num == prod_num)
4121 return &mv88e6xxx_table[i];
4122
4123 return NULL;
4124 }
4125
4126 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4127 {
4128 const struct mv88e6xxx_info *info;
4129 unsigned int prod_num, rev;
4130 u16 id;
4131 int err;
4132
4133 mutex_lock(&chip->reg_lock);
4134 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4135 mutex_unlock(&chip->reg_lock);
4136 if (err)
4137 return err;
4138
4139 prod_num = (id & 0xfff0) >> 4;
4140 rev = id & 0x000f;
4141
4142 info = mv88e6xxx_lookup_info(prod_num);
4143 if (!info)
4144 return -ENODEV;
4145
4146 /* Update the compatible info with the probed one */
4147 chip->info = info;
4148
4149 err = mv88e6xxx_g2_require(chip);
4150 if (err)
4151 return err;
4152
4153 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4154 chip->info->prod_num, chip->info->name, rev);
4155
4156 return 0;
4157 }
4158
4159 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4160 {
4161 struct mv88e6xxx_chip *chip;
4162
4163 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4164 if (!chip)
4165 return NULL;
4166
4167 chip->dev = dev;
4168
4169 mutex_init(&chip->reg_lock);
4170 INIT_LIST_HEAD(&chip->mdios);
4171
4172 return chip;
4173 }
4174
4175 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4176 {
4177 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4178 mv88e6xxx_ppu_state_init(chip);
4179 }
4180
4181 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4182 {
4183 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4184 mv88e6xxx_ppu_state_destroy(chip);
4185 }
4186
4187 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4188 struct mii_bus *bus, int sw_addr)
4189 {
4190 if (sw_addr == 0)
4191 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4192 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
4193 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4194 else
4195 return -EINVAL;
4196
4197 chip->bus = bus;
4198 chip->sw_addr = sw_addr;
4199
4200 return 0;
4201 }
4202
4203 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4204 {
4205 struct mv88e6xxx_chip *chip = ds->priv;
4206
4207 return chip->info->tag_protocol;
4208 }
4209
4210 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4211 struct device *host_dev, int sw_addr,
4212 void **priv)
4213 {
4214 struct mv88e6xxx_chip *chip;
4215 struct mii_bus *bus;
4216 int err;
4217
4218 bus = dsa_host_dev_to_mii_bus(host_dev);
4219 if (!bus)
4220 return NULL;
4221
4222 chip = mv88e6xxx_alloc_chip(dsa_dev);
4223 if (!chip)
4224 return NULL;
4225
4226 /* Legacy SMI probing will only support chips similar to 88E6085 */
4227 chip->info = &mv88e6xxx_table[MV88E6085];
4228
4229 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4230 if (err)
4231 goto free;
4232
4233 err = mv88e6xxx_detect(chip);
4234 if (err)
4235 goto free;
4236
4237 mutex_lock(&chip->reg_lock);
4238 err = mv88e6xxx_switch_reset(chip);
4239 mutex_unlock(&chip->reg_lock);
4240 if (err)
4241 goto free;
4242
4243 mv88e6xxx_phy_init(chip);
4244
4245 err = mv88e6xxx_mdios_register(chip, NULL);
4246 if (err)
4247 goto free;
4248
4249 *priv = chip;
4250
4251 return chip->info->name;
4252 free:
4253 devm_kfree(dsa_dev, chip);
4254
4255 return NULL;
4256 }
4257
4258 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4259 const struct switchdev_obj_port_mdb *mdb,
4260 struct switchdev_trans *trans)
4261 {
4262 /* We don't need any dynamic resource from the kernel (yet),
4263 * so skip the prepare phase.
4264 */
4265
4266 return 0;
4267 }
4268
4269 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4270 const struct switchdev_obj_port_mdb *mdb,
4271 struct switchdev_trans *trans)
4272 {
4273 struct mv88e6xxx_chip *chip = ds->priv;
4274
4275 mutex_lock(&chip->reg_lock);
4276 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4277 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4278 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4279 mutex_unlock(&chip->reg_lock);
4280 }
4281
4282 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4283 const struct switchdev_obj_port_mdb *mdb)
4284 {
4285 struct mv88e6xxx_chip *chip = ds->priv;
4286 int err;
4287
4288 mutex_lock(&chip->reg_lock);
4289 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4290 GLOBAL_ATU_DATA_STATE_UNUSED);
4291 mutex_unlock(&chip->reg_lock);
4292
4293 return err;
4294 }
4295
4296 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4297 struct switchdev_obj_port_mdb *mdb,
4298 int (*cb)(struct switchdev_obj *obj))
4299 {
4300 struct mv88e6xxx_chip *chip = ds->priv;
4301 int err;
4302
4303 mutex_lock(&chip->reg_lock);
4304 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4305 mutex_unlock(&chip->reg_lock);
4306
4307 return err;
4308 }
4309
4310 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4311 .probe = mv88e6xxx_drv_probe,
4312 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4313 .setup = mv88e6xxx_setup,
4314 .set_addr = mv88e6xxx_set_addr,
4315 .adjust_link = mv88e6xxx_adjust_link,
4316 .get_strings = mv88e6xxx_get_strings,
4317 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4318 .get_sset_count = mv88e6xxx_get_sset_count,
4319 .set_eee = mv88e6xxx_set_eee,
4320 .get_eee = mv88e6xxx_get_eee,
4321 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4322 .get_eeprom = mv88e6xxx_get_eeprom,
4323 .set_eeprom = mv88e6xxx_set_eeprom,
4324 .get_regs_len = mv88e6xxx_get_regs_len,
4325 .get_regs = mv88e6xxx_get_regs,
4326 .set_ageing_time = mv88e6xxx_set_ageing_time,
4327 .port_bridge_join = mv88e6xxx_port_bridge_join,
4328 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4329 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4330 .port_fast_age = mv88e6xxx_port_fast_age,
4331 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4332 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4333 .port_vlan_add = mv88e6xxx_port_vlan_add,
4334 .port_vlan_del = mv88e6xxx_port_vlan_del,
4335 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4336 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4337 .port_fdb_add = mv88e6xxx_port_fdb_add,
4338 .port_fdb_del = mv88e6xxx_port_fdb_del,
4339 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4340 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4341 .port_mdb_add = mv88e6xxx_port_mdb_add,
4342 .port_mdb_del = mv88e6xxx_port_mdb_del,
4343 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4344 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4345 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4346 };
4347
4348 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4349 .ops = &mv88e6xxx_switch_ops,
4350 };
4351
4352 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4353 {
4354 struct device *dev = chip->dev;
4355 struct dsa_switch *ds;
4356
4357 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4358 if (!ds)
4359 return -ENOMEM;
4360
4361 ds->priv = chip;
4362 ds->ops = &mv88e6xxx_switch_ops;
4363 ds->ageing_time_min = chip->info->age_time_coeff;
4364 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4365
4366 dev_set_drvdata(dev, ds);
4367
4368 return dsa_register_switch(ds, dev);
4369 }
4370
4371 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4372 {
4373 dsa_unregister_switch(chip->ds);
4374 }
4375
4376 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4377 {
4378 struct device *dev = &mdiodev->dev;
4379 struct device_node *np = dev->of_node;
4380 const struct mv88e6xxx_info *compat_info;
4381 struct mv88e6xxx_chip *chip;
4382 u32 eeprom_len;
4383 int err;
4384
4385 compat_info = of_device_get_match_data(dev);
4386 if (!compat_info)
4387 return -EINVAL;
4388
4389 chip = mv88e6xxx_alloc_chip(dev);
4390 if (!chip)
4391 return -ENOMEM;
4392
4393 chip->info = compat_info;
4394
4395 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4396 if (err)
4397 return err;
4398
4399 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4400 if (IS_ERR(chip->reset))
4401 return PTR_ERR(chip->reset);
4402
4403 err = mv88e6xxx_detect(chip);
4404 if (err)
4405 return err;
4406
4407 mv88e6xxx_phy_init(chip);
4408
4409 if (chip->info->ops->get_eeprom &&
4410 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4411 chip->eeprom_len = eeprom_len;
4412
4413 mutex_lock(&chip->reg_lock);
4414 err = mv88e6xxx_switch_reset(chip);
4415 mutex_unlock(&chip->reg_lock);
4416 if (err)
4417 goto out;
4418
4419 chip->irq = of_irq_get(np, 0);
4420 if (chip->irq == -EPROBE_DEFER) {
4421 err = chip->irq;
4422 goto out;
4423 }
4424
4425 if (chip->irq > 0) {
4426 /* Has to be performed before the MDIO bus is created,
4427 * because the PHYs will link there interrupts to these
4428 * interrupt controllers
4429 */
4430 mutex_lock(&chip->reg_lock);
4431 err = mv88e6xxx_g1_irq_setup(chip);
4432 mutex_unlock(&chip->reg_lock);
4433
4434 if (err)
4435 goto out;
4436
4437 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4438 err = mv88e6xxx_g2_irq_setup(chip);
4439 if (err)
4440 goto out_g1_irq;
4441 }
4442 }
4443
4444 err = mv88e6xxx_mdios_register(chip, np);
4445 if (err)
4446 goto out_g2_irq;
4447
4448 err = mv88e6xxx_register_switch(chip);
4449 if (err)
4450 goto out_mdio;
4451
4452 return 0;
4453
4454 out_mdio:
4455 mv88e6xxx_mdios_unregister(chip);
4456 out_g2_irq:
4457 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4458 mv88e6xxx_g2_irq_free(chip);
4459 out_g1_irq:
4460 if (chip->irq > 0) {
4461 mutex_lock(&chip->reg_lock);
4462 mv88e6xxx_g1_irq_free(chip);
4463 mutex_unlock(&chip->reg_lock);
4464 }
4465 out:
4466 return err;
4467 }
4468
4469 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4470 {
4471 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4472 struct mv88e6xxx_chip *chip = ds->priv;
4473
4474 mv88e6xxx_phy_destroy(chip);
4475 mv88e6xxx_unregister_switch(chip);
4476 mv88e6xxx_mdios_unregister(chip);
4477
4478 if (chip->irq > 0) {
4479 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4480 mv88e6xxx_g2_irq_free(chip);
4481 mv88e6xxx_g1_irq_free(chip);
4482 }
4483 }
4484
4485 static const struct of_device_id mv88e6xxx_of_match[] = {
4486 {
4487 .compatible = "marvell,mv88e6085",
4488 .data = &mv88e6xxx_table[MV88E6085],
4489 },
4490 {
4491 .compatible = "marvell,mv88e6190",
4492 .data = &mv88e6xxx_table[MV88E6190],
4493 },
4494 { /* sentinel */ },
4495 };
4496
4497 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4498
4499 static struct mdio_driver mv88e6xxx_driver = {
4500 .probe = mv88e6xxx_probe,
4501 .remove = mv88e6xxx_remove,
4502 .mdiodrv.driver = {
4503 .name = "mv88e6085",
4504 .of_match_table = mv88e6xxx_of_match,
4505 },
4506 };
4507
4508 static int __init mv88e6xxx_init(void)
4509 {
4510 register_switch_driver(&mv88e6xxx_switch_drv);
4511 return mdio_driver_register(&mv88e6xxx_driver);
4512 }
4513 module_init(mv88e6xxx_init);
4514
4515 static void __exit mv88e6xxx_cleanup(void)
4516 {
4517 mdio_driver_unregister(&mv88e6xxx_driver);
4518 unregister_switch_driver(&mv88e6xxx_switch_drv);
4519 }
4520 module_exit(mv88e6xxx_cleanup);
4521
4522 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4523 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4524 MODULE_LICENSE("GPL");
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