2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
45 static void assert_reg_lock(struct mv88e6xxx_chip
*chip
)
47 if (unlikely(!mutex_is_locked(&chip
->reg_lock
))) {
48 dev_err(chip
->dev
, "Switch registers lock not held!\n");
53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip
*chip
,
66 int addr
, int reg
, u16
*val
)
71 return chip
->smi_ops
->read(chip
, addr
, reg
, val
);
74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip
*chip
,
75 int addr
, int reg
, u16 val
)
80 return chip
->smi_ops
->write(chip
, addr
, reg
, val
);
83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip
*chip
,
84 int addr
, int reg
, u16
*val
)
88 ret
= mdiobus_read_nested(chip
->bus
, addr
, reg
);
97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip
*chip
,
98 int addr
, int reg
, u16 val
)
102 ret
= mdiobus_write_nested(chip
->bus
, addr
, reg
, val
);
109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops
= {
110 .read
= mv88e6xxx_smi_single_chip_read
,
111 .write
= mv88e6xxx_smi_single_chip_write
,
114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip
*chip
)
119 for (i
= 0; i
< 16; i
++) {
120 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
);
124 if ((ret
& SMI_CMD_BUSY
) == 0)
131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip
*chip
,
132 int addr
, int reg
, u16
*val
)
136 /* Wait for the bus to become free. */
137 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
141 /* Transmit the read command. */
142 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
143 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
147 /* Wait for the read command to complete. */
148 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
153 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
);
162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip
*chip
,
163 int addr
, int reg
, u16 val
)
167 /* Wait for the bus to become free. */
168 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
172 /* Transmit the data to write. */
173 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
, val
);
177 /* Transmit the write command. */
178 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
179 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
183 /* Wait for the write command to complete. */
184 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops
= {
192 .read
= mv88e6xxx_smi_multi_chip_read
,
193 .write
= mv88e6xxx_smi_multi_chip_write
,
196 int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
)
200 assert_reg_lock(chip
);
202 err
= mv88e6xxx_smi_read(chip
, addr
, reg
, val
);
206 dev_dbg(chip
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
212 int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
)
216 assert_reg_lock(chip
);
218 err
= mv88e6xxx_smi_write(chip
, addr
, reg
, val
);
222 dev_dbg(chip
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
228 struct mii_bus
*mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip
*chip
)
230 struct mv88e6xxx_mdio_bus
*mdio_bus
;
232 mdio_bus
= list_first_entry(&chip
->mdios
, struct mv88e6xxx_mdio_bus
,
237 return mdio_bus
->bus
;
240 static void mv88e6xxx_g1_irq_mask(struct irq_data
*d
)
242 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
243 unsigned int n
= d
->hwirq
;
245 chip
->g1_irq
.masked
|= (1 << n
);
248 static void mv88e6xxx_g1_irq_unmask(struct irq_data
*d
)
250 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
251 unsigned int n
= d
->hwirq
;
253 chip
->g1_irq
.masked
&= ~(1 << n
);
256 static irqreturn_t
mv88e6xxx_g1_irq_thread_fn(int irq
, void *dev_id
)
258 struct mv88e6xxx_chip
*chip
= dev_id
;
259 unsigned int nhandled
= 0;
260 unsigned int sub_irq
;
265 mutex_lock(&chip
->reg_lock
);
266 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
267 mutex_unlock(&chip
->reg_lock
);
272 for (n
= 0; n
< chip
->g1_irq
.nirqs
; ++n
) {
273 if (reg
& (1 << n
)) {
274 sub_irq
= irq_find_mapping(chip
->g1_irq
.domain
, n
);
275 handle_nested_irq(sub_irq
);
280 return (nhandled
> 0 ? IRQ_HANDLED
: IRQ_NONE
);
283 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data
*d
)
285 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
287 mutex_lock(&chip
->reg_lock
);
290 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data
*d
)
292 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
293 u16 mask
= GENMASK(chip
->g1_irq
.nirqs
, 0);
297 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, ®
);
302 reg
|= (~chip
->g1_irq
.masked
& mask
);
304 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, reg
);
309 mutex_unlock(&chip
->reg_lock
);
312 static const struct irq_chip mv88e6xxx_g1_irq_chip
= {
313 .name
= "mv88e6xxx-g1",
314 .irq_mask
= mv88e6xxx_g1_irq_mask
,
315 .irq_unmask
= mv88e6xxx_g1_irq_unmask
,
316 .irq_bus_lock
= mv88e6xxx_g1_irq_bus_lock
,
317 .irq_bus_sync_unlock
= mv88e6xxx_g1_irq_bus_sync_unlock
,
320 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain
*d
,
322 irq_hw_number_t hwirq
)
324 struct mv88e6xxx_chip
*chip
= d
->host_data
;
326 irq_set_chip_data(irq
, d
->host_data
);
327 irq_set_chip_and_handler(irq
, &chip
->g1_irq
.chip
, handle_level_irq
);
328 irq_set_noprobe(irq
);
333 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops
= {
334 .map
= mv88e6xxx_g1_irq_domain_map
,
335 .xlate
= irq_domain_xlate_twocell
,
338 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip
*chip
)
343 mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
344 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
345 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
347 free_irq(chip
->irq
, chip
);
349 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++) {
350 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
351 irq_dispose_mapping(virq
);
354 irq_domain_remove(chip
->g1_irq
.domain
);
357 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip
*chip
)
362 chip
->g1_irq
.nirqs
= chip
->info
->g1_irqs
;
363 chip
->g1_irq
.domain
= irq_domain_add_simple(
364 NULL
, chip
->g1_irq
.nirqs
, 0,
365 &mv88e6xxx_g1_irq_domain_ops
, chip
);
366 if (!chip
->g1_irq
.domain
)
369 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++)
370 irq_create_mapping(chip
->g1_irq
.domain
, irq
);
372 chip
->g1_irq
.chip
= mv88e6xxx_g1_irq_chip
;
373 chip
->g1_irq
.masked
= ~0;
375 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
379 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
381 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
385 /* Reading the interrupt status clears (most of) them */
386 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
390 err
= request_threaded_irq(chip
->irq
, NULL
,
391 mv88e6xxx_g1_irq_thread_fn
,
392 IRQF_ONESHOT
| IRQF_TRIGGER_FALLING
,
393 dev_name(chip
->dev
), chip
);
400 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
401 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
404 for (irq
= 0; irq
< 16; irq
++) {
405 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
406 irq_dispose_mapping(virq
);
409 irq_domain_remove(chip
->g1_irq
.domain
);
414 int mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 mask
)
418 for (i
= 0; i
< 16; i
++) {
422 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
429 usleep_range(1000, 2000);
432 dev_err(chip
->dev
, "Timeout while waiting for switch\n");
436 /* Indirect write to single pointer-data register with an Update bit */
437 int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 update
)
442 /* Wait until the previous operation is completed */
443 err
= mv88e6xxx_wait(chip
, addr
, reg
, BIT(15));
447 /* Set the Update bit to trigger a write operation */
448 val
= BIT(15) | update
;
450 return mv88e6xxx_write(chip
, addr
, reg
, val
);
453 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip
*chip
, int port
,
454 int link
, int speed
, int duplex
,
455 phy_interface_t mode
)
459 if (!chip
->info
->ops
->port_set_link
)
462 /* Port's MAC control must not be changed unless the link is down */
463 err
= chip
->info
->ops
->port_set_link(chip
, port
, 0);
467 if (chip
->info
->ops
->port_set_speed
) {
468 err
= chip
->info
->ops
->port_set_speed(chip
, port
, speed
);
469 if (err
&& err
!= -EOPNOTSUPP
)
473 if (chip
->info
->ops
->port_set_duplex
) {
474 err
= chip
->info
->ops
->port_set_duplex(chip
, port
, duplex
);
475 if (err
&& err
!= -EOPNOTSUPP
)
479 if (chip
->info
->ops
->port_set_rgmii_delay
) {
480 err
= chip
->info
->ops
->port_set_rgmii_delay(chip
, port
, mode
);
481 if (err
&& err
!= -EOPNOTSUPP
)
485 if (chip
->info
->ops
->port_set_cmode
) {
486 err
= chip
->info
->ops
->port_set_cmode(chip
, port
, mode
);
487 if (err
&& err
!= -EOPNOTSUPP
)
493 if (chip
->info
->ops
->port_set_link(chip
, port
, link
))
494 dev_err(chip
->dev
, "p%d: failed to restore MAC's link\n", port
);
499 /* We expect the switch to perform auto negotiation if there is a real
500 * phy. However, in the case of a fixed link phy, we force the port
501 * settings from the fixed link settings.
503 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
504 struct phy_device
*phydev
)
506 struct mv88e6xxx_chip
*chip
= ds
->priv
;
509 if (!phy_is_pseudo_fixed_link(phydev
))
512 mutex_lock(&chip
->reg_lock
);
513 err
= mv88e6xxx_port_setup_mac(chip
, port
, phydev
->link
, phydev
->speed
,
514 phydev
->duplex
, phydev
->interface
);
515 mutex_unlock(&chip
->reg_lock
);
517 if (err
&& err
!= -EOPNOTSUPP
)
518 dev_err(ds
->dev
, "p%d: failed to configure MAC\n", port
);
521 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
)
523 if (!chip
->info
->ops
->stats_snapshot
)
526 return chip
->info
->ops
->stats_snapshot(chip
, port
);
529 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
530 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0
, },
531 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0
, },
532 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0
, },
533 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0
, },
534 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0
, },
535 { "in_pause", 4, 0x16, STATS_TYPE_BANK0
, },
536 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0
, },
537 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0
, },
538 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0
, },
539 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0
, },
540 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0
, },
541 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0
, },
542 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0
, },
543 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0
, },
544 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0
, },
545 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0
, },
546 { "out_pause", 4, 0x15, STATS_TYPE_BANK0
, },
547 { "excessive", 4, 0x11, STATS_TYPE_BANK0
, },
548 { "collisions", 4, 0x1e, STATS_TYPE_BANK0
, },
549 { "deferred", 4, 0x05, STATS_TYPE_BANK0
, },
550 { "single", 4, 0x14, STATS_TYPE_BANK0
, },
551 { "multiple", 4, 0x17, STATS_TYPE_BANK0
, },
552 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0
, },
553 { "late", 4, 0x1f, STATS_TYPE_BANK0
, },
554 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0
, },
555 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0
, },
556 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0
, },
557 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0
, },
558 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0
, },
559 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0
, },
560 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT
, },
561 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT
, },
562 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT
, },
563 { "in_discards", 4, 0x00, STATS_TYPE_BANK1
, },
564 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1
, },
565 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1
, },
566 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1
, },
567 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1
, },
568 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1
, },
569 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1
, },
570 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1
, },
571 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1
, },
572 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1
, },
573 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1
, },
574 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1
, },
575 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1
, },
576 { "in_management", 4, 0x0f, STATS_TYPE_BANK1
, },
577 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1
, },
578 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1
, },
579 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1
, },
580 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1
, },
581 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1
, },
582 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1
, },
583 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1
, },
584 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1
, },
585 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1
, },
586 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1
, },
587 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1
, },
588 { "out_management", 4, 0x1f, STATS_TYPE_BANK1
, },
591 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip
*chip
,
592 struct mv88e6xxx_hw_stat
*s
,
593 int port
, u16 bank1_select
,
603 case STATS_TYPE_PORT
:
604 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
, ®
);
609 if (s
->sizeof_stat
== 4) {
610 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
+ 1, ®
);
616 case STATS_TYPE_BANK1
:
619 case STATS_TYPE_BANK0
:
620 reg
|= s
->reg
| histogram
;
621 mv88e6xxx_g1_stats_read(chip
, reg
, &low
);
622 if (s
->sizeof_stat
== 8)
623 mv88e6xxx_g1_stats_read(chip
, reg
+ 1, &high
);
628 value
= (((u64
)high
) << 16) | low
;
632 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip
*chip
,
633 uint8_t *data
, int types
)
635 struct mv88e6xxx_hw_stat
*stat
;
638 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
639 stat
= &mv88e6xxx_hw_stats
[i
];
640 if (stat
->type
& types
) {
641 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
648 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip
*chip
,
651 mv88e6xxx_stats_get_strings(chip
, data
,
652 STATS_TYPE_BANK0
| STATS_TYPE_PORT
);
655 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip
*chip
,
658 mv88e6xxx_stats_get_strings(chip
, data
,
659 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
);
662 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
665 struct mv88e6xxx_chip
*chip
= ds
->priv
;
667 if (chip
->info
->ops
->stats_get_strings
)
668 chip
->info
->ops
->stats_get_strings(chip
, data
);
671 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip
*chip
,
674 struct mv88e6xxx_hw_stat
*stat
;
677 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
678 stat
= &mv88e6xxx_hw_stats
[i
];
679 if (stat
->type
& types
)
685 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
687 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
691 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
693 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
697 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
699 struct mv88e6xxx_chip
*chip
= ds
->priv
;
701 if (chip
->info
->ops
->stats_get_sset_count
)
702 return chip
->info
->ops
->stats_get_sset_count(chip
);
707 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
708 uint64_t *data
, int types
,
709 u16 bank1_select
, u16 histogram
)
711 struct mv88e6xxx_hw_stat
*stat
;
714 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
715 stat
= &mv88e6xxx_hw_stats
[i
];
716 if (stat
->type
& types
) {
717 mutex_lock(&chip
->reg_lock
);
718 data
[j
] = _mv88e6xxx_get_ethtool_stat(chip
, stat
, port
,
721 mutex_unlock(&chip
->reg_lock
);
728 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
731 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
732 STATS_TYPE_BANK0
| STATS_TYPE_PORT
,
733 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
736 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
739 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
740 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
741 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9
,
742 MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
745 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
748 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
749 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
750 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10
,
754 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
757 if (chip
->info
->ops
->stats_get_stats
)
758 chip
->info
->ops
->stats_get_stats(chip
, port
, data
);
761 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
764 struct mv88e6xxx_chip
*chip
= ds
->priv
;
767 mutex_lock(&chip
->reg_lock
);
769 ret
= mv88e6xxx_stats_snapshot(chip
, port
);
770 mutex_unlock(&chip
->reg_lock
);
775 mv88e6xxx_get_stats(chip
, port
, data
);
779 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip
*chip
)
781 if (chip
->info
->ops
->stats_set_histogram
)
782 return chip
->info
->ops
->stats_set_histogram(chip
);
787 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
789 return 32 * sizeof(u16
);
792 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
793 struct ethtool_regs
*regs
, void *_p
)
795 struct mv88e6xxx_chip
*chip
= ds
->priv
;
803 memset(p
, 0xff, 32 * sizeof(u16
));
805 mutex_lock(&chip
->reg_lock
);
807 for (i
= 0; i
< 32; i
++) {
809 err
= mv88e6xxx_port_read(chip
, port
, i
, ®
);
814 mutex_unlock(&chip
->reg_lock
);
817 static int mv88e6xxx_get_mac_eee(struct dsa_switch
*ds
, int port
,
818 struct ethtool_eee
*e
)
820 /* Nothing to do on the port's MAC */
824 static int mv88e6xxx_set_mac_eee(struct dsa_switch
*ds
, int port
,
825 struct ethtool_eee
*e
)
827 /* Nothing to do on the port's MAC */
831 static u16
mv88e6xxx_port_vlan(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
833 struct dsa_switch
*ds
= NULL
;
834 struct net_device
*br
;
838 if (dev
< DSA_MAX_SWITCHES
)
839 ds
= chip
->ds
->dst
->ds
[dev
];
841 /* Prevent frames from unknown switch or port */
842 if (!ds
|| port
>= ds
->num_ports
)
845 /* Frames from DSA links and CPU ports can egress any local port */
846 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
847 return mv88e6xxx_port_mask(chip
);
849 br
= ds
->ports
[port
].bridge_dev
;
852 /* Frames from user ports can egress any local DSA links and CPU ports,
853 * as well as any local member of their bridge group.
855 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
856 if (dsa_is_cpu_port(chip
->ds
, i
) ||
857 dsa_is_dsa_port(chip
->ds
, i
) ||
858 (br
&& dsa_to_port(chip
->ds
, i
)->bridge_dev
== br
))
864 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip
*chip
, int port
)
866 u16 output_ports
= mv88e6xxx_port_vlan(chip
, chip
->ds
->index
, port
);
868 /* prevent frames from going back out of the port they came in on */
869 output_ports
&= ~BIT(port
);
871 return mv88e6xxx_port_set_vlan_map(chip
, port
, output_ports
);
874 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
877 struct mv88e6xxx_chip
*chip
= ds
->priv
;
880 mutex_lock(&chip
->reg_lock
);
881 err
= mv88e6xxx_port_set_state(chip
, port
, state
);
882 mutex_unlock(&chip
->reg_lock
);
885 dev_err(ds
->dev
, "p%d: failed to update state\n", port
);
888 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip
*chip
)
890 if (chip
->info
->ops
->pot_clear
)
891 return chip
->info
->ops
->pot_clear(chip
);
896 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip
*chip
)
898 if (chip
->info
->ops
->mgmt_rsvd2cpu
)
899 return chip
->info
->ops
->mgmt_rsvd2cpu(chip
);
904 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip
*chip
)
908 err
= mv88e6xxx_g1_atu_flush(chip
, 0, true);
912 err
= mv88e6xxx_g1_atu_set_learn2all(chip
, true);
916 return mv88e6xxx_g1_atu_set_age_time(chip
, 300000);
919 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip
*chip
)
924 if (!chip
->info
->ops
->irl_init_all
)
927 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
928 /* Disable ingress rate limiting by resetting all per port
929 * ingress rate limit resources to their initial state.
931 err
= chip
->info
->ops
->irl_init_all(chip
, port
);
939 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip
*chip
)
941 if (chip
->info
->ops
->set_switch_mac
) {
944 eth_random_addr(addr
);
946 return chip
->info
->ops
->set_switch_mac(chip
, addr
);
952 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
956 if (!mv88e6xxx_has_pvt(chip
))
959 /* Skip the local source device, which uses in-chip port VLAN */
960 if (dev
!= chip
->ds
->index
)
961 pvlan
= mv88e6xxx_port_vlan(chip
, dev
, port
);
963 return mv88e6xxx_g2_pvt_write(chip
, dev
, port
, pvlan
);
966 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip
*chip
)
971 if (!mv88e6xxx_has_pvt(chip
))
974 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
975 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
977 err
= mv88e6xxx_g2_misc_4_bit_port(chip
);
981 for (dev
= 0; dev
< MV88E6XXX_MAX_PVT_SWITCHES
; ++dev
) {
982 for (port
= 0; port
< MV88E6XXX_MAX_PVT_PORTS
; ++port
) {
983 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
992 static void mv88e6xxx_port_fast_age(struct dsa_switch
*ds
, int port
)
994 struct mv88e6xxx_chip
*chip
= ds
->priv
;
997 mutex_lock(&chip
->reg_lock
);
998 err
= mv88e6xxx_g1_atu_remove(chip
, 0, port
, false);
999 mutex_unlock(&chip
->reg_lock
);
1002 dev_err(ds
->dev
, "p%d: failed to flush ATU\n", port
);
1005 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip
*chip
)
1007 if (!chip
->info
->max_vid
)
1010 return mv88e6xxx_g1_vtu_flush(chip
);
1013 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip
*chip
,
1014 struct mv88e6xxx_vtu_entry
*entry
)
1016 if (!chip
->info
->ops
->vtu_getnext
)
1019 return chip
->info
->ops
->vtu_getnext(chip
, entry
);
1022 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
1023 struct mv88e6xxx_vtu_entry
*entry
)
1025 if (!chip
->info
->ops
->vtu_loadpurge
)
1028 return chip
->info
->ops
->vtu_loadpurge(chip
, entry
);
1031 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip
*chip
, u16
*fid
)
1033 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1034 struct mv88e6xxx_vtu_entry vlan
= {
1035 .vid
= chip
->info
->max_vid
,
1039 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1041 /* Set every FID bit used by the (un)bridged ports */
1042 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1043 err
= mv88e6xxx_port_get_fid(chip
, i
, fid
);
1047 set_bit(*fid
, fid_bitmap
);
1050 /* Set every FID bit used by the VLAN entries */
1052 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1059 set_bit(vlan
.fid
, fid_bitmap
);
1060 } while (vlan
.vid
< chip
->info
->max_vid
);
1062 /* The reset value 0x000 is used to indicate that multiple address
1063 * databases are not needed. Return the next positive available.
1065 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1066 if (unlikely(*fid
>= mv88e6xxx_num_databases(chip
)))
1069 /* Clear the database */
1070 return mv88e6xxx_g1_atu_flush(chip
, *fid
, true);
1073 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip
*chip
, u16 vid
,
1074 struct mv88e6xxx_vtu_entry
*entry
, bool new)
1081 entry
->vid
= vid
- 1;
1082 entry
->valid
= false;
1084 err
= mv88e6xxx_vtu_getnext(chip
, entry
);
1088 if (entry
->vid
== vid
&& entry
->valid
)
1094 /* Initialize a fresh VLAN entry */
1095 memset(entry
, 0, sizeof(*entry
));
1096 entry
->valid
= true;
1099 /* Exclude all ports */
1100 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
1102 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1104 return mv88e6xxx_atu_new(chip
, &entry
->fid
);
1107 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1111 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1112 u16 vid_begin
, u16 vid_end
)
1114 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1115 struct mv88e6xxx_vtu_entry vlan
= {
1116 .vid
= vid_begin
- 1,
1120 /* DSA and CPU ports have to be members of multiple vlans */
1121 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1127 mutex_lock(&chip
->reg_lock
);
1130 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1137 if (vlan
.vid
> vid_end
)
1140 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1141 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1144 if (!ds
->ports
[i
].slave
)
1147 if (vlan
.member
[i
] ==
1148 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1151 if (dsa_to_port(ds
, i
)->bridge_dev
==
1152 ds
->ports
[port
].bridge_dev
)
1153 break; /* same bridge, check next VLAN */
1155 if (!dsa_to_port(ds
, i
)->bridge_dev
)
1158 dev_err(ds
->dev
, "p%d: hw VLAN %d already used by port %d in %s\n",
1160 netdev_name(dsa_to_port(ds
, i
)->bridge_dev
));
1164 } while (vlan
.vid
< vid_end
);
1167 mutex_unlock(&chip
->reg_lock
);
1172 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1173 bool vlan_filtering
)
1175 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1176 u16 mode
= vlan_filtering
? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE
:
1177 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
;
1180 if (!chip
->info
->max_vid
)
1183 mutex_lock(&chip
->reg_lock
);
1184 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
, mode
);
1185 mutex_unlock(&chip
->reg_lock
);
1191 mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1192 const struct switchdev_obj_port_vlan
*vlan
)
1194 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1197 if (!chip
->info
->max_vid
)
1200 /* If the requested port doesn't belong to the same bridge as the VLAN
1201 * members, do not support it (yet) and fallback to software VLAN.
1203 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1208 /* We don't need any dynamic resource from the kernel (yet),
1209 * so skip the prepare phase.
1214 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip
*chip
, int port
,
1215 const unsigned char *addr
, u16 vid
,
1218 struct mv88e6xxx_vtu_entry vlan
;
1219 struct mv88e6xxx_atu_entry entry
;
1222 /* Null VLAN ID corresponds to the port private database */
1224 err
= mv88e6xxx_port_get_fid(chip
, port
, &vlan
.fid
);
1226 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1230 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1231 ether_addr_copy(entry
.mac
, addr
);
1232 eth_addr_dec(entry
.mac
);
1234 err
= mv88e6xxx_g1_atu_getnext(chip
, vlan
.fid
, &entry
);
1238 /* Initialize a fresh ATU entry if it isn't found */
1239 if (entry
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
||
1240 !ether_addr_equal(entry
.mac
, addr
)) {
1241 memset(&entry
, 0, sizeof(entry
));
1242 ether_addr_copy(entry
.mac
, addr
);
1245 /* Purge the ATU entry only if no port is using it anymore */
1246 if (state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
) {
1247 entry
.portvec
&= ~BIT(port
);
1249 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1251 entry
.portvec
|= BIT(port
);
1252 entry
.state
= state
;
1255 return mv88e6xxx_g1_atu_loadpurge(chip
, vlan
.fid
, &entry
);
1258 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip
*chip
, int port
,
1261 const char broadcast
[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1262 u8 state
= MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
;
1264 return mv88e6xxx_port_db_load_purge(chip
, port
, broadcast
, vid
, state
);
1267 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip
*chip
, u16 vid
)
1272 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
1273 err
= mv88e6xxx_port_add_broadcast(chip
, port
, vid
);
1281 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip
*chip
, int port
,
1284 struct mv88e6xxx_vtu_entry vlan
;
1287 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, true);
1291 vlan
.member
[port
] = member
;
1293 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1297 return mv88e6xxx_broadcast_setup(chip
, vid
);
1300 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1301 const struct switchdev_obj_port_vlan
*vlan
)
1303 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1304 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1305 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1309 if (!chip
->info
->max_vid
)
1312 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1313 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED
;
1315 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED
;
1317 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED
;
1319 mutex_lock(&chip
->reg_lock
);
1321 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
1322 if (_mv88e6xxx_port_vlan_add(chip
, port
, vid
, member
))
1323 dev_err(ds
->dev
, "p%d: failed to add VLAN %d%c\n", port
,
1324 vid
, untagged
? 'u' : 't');
1326 if (pvid
&& mv88e6xxx_port_set_pvid(chip
, port
, vlan
->vid_end
))
1327 dev_err(ds
->dev
, "p%d: failed to set PVID %d\n", port
,
1330 mutex_unlock(&chip
->reg_lock
);
1333 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip
*chip
,
1336 struct mv88e6xxx_vtu_entry vlan
;
1339 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1343 /* Tell switchdev if this VLAN is handled in software */
1344 if (vlan
.member
[port
] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1347 vlan
.member
[port
] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1349 /* keep the VLAN unless all ports are excluded */
1351 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1352 if (vlan
.member
[i
] !=
1353 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
1359 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1363 return mv88e6xxx_g1_atu_remove(chip
, vlan
.fid
, port
, false);
1366 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
1367 const struct switchdev_obj_port_vlan
*vlan
)
1369 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1373 if (!chip
->info
->max_vid
)
1376 mutex_lock(&chip
->reg_lock
);
1378 err
= mv88e6xxx_port_get_pvid(chip
, port
, &pvid
);
1382 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1383 err
= _mv88e6xxx_port_vlan_del(chip
, port
, vid
);
1388 err
= mv88e6xxx_port_set_pvid(chip
, port
, 0);
1395 mutex_unlock(&chip
->reg_lock
);
1400 static int mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1401 const unsigned char *addr
, u16 vid
)
1403 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1406 mutex_lock(&chip
->reg_lock
);
1407 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1408 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1409 mutex_unlock(&chip
->reg_lock
);
1414 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1415 const unsigned char *addr
, u16 vid
)
1417 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1420 mutex_lock(&chip
->reg_lock
);
1421 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1422 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
1423 mutex_unlock(&chip
->reg_lock
);
1428 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip
*chip
,
1429 u16 fid
, u16 vid
, int port
,
1430 dsa_fdb_dump_cb_t
*cb
, void *data
)
1432 struct mv88e6xxx_atu_entry addr
;
1436 addr
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1437 eth_broadcast_addr(addr
.mac
);
1440 mutex_lock(&chip
->reg_lock
);
1441 err
= mv88e6xxx_g1_atu_getnext(chip
, fid
, &addr
);
1442 mutex_unlock(&chip
->reg_lock
);
1446 if (addr
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
)
1449 if (addr
.trunk
|| (addr
.portvec
& BIT(port
)) == 0)
1452 if (!is_unicast_ether_addr(addr
.mac
))
1455 is_static
= (addr
.state
==
1456 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1457 err
= cb(addr
.mac
, vid
, is_static
, data
);
1460 } while (!is_broadcast_ether_addr(addr
.mac
));
1465 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip
*chip
, int port
,
1466 dsa_fdb_dump_cb_t
*cb
, void *data
)
1468 struct mv88e6xxx_vtu_entry vlan
= {
1469 .vid
= chip
->info
->max_vid
,
1474 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1475 mutex_lock(&chip
->reg_lock
);
1476 err
= mv88e6xxx_port_get_fid(chip
, port
, &fid
);
1477 mutex_unlock(&chip
->reg_lock
);
1482 err
= mv88e6xxx_port_db_dump_fid(chip
, fid
, 0, port
, cb
, data
);
1486 /* Dump VLANs' Filtering Information Databases */
1488 mutex_lock(&chip
->reg_lock
);
1489 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1490 mutex_unlock(&chip
->reg_lock
);
1497 err
= mv88e6xxx_port_db_dump_fid(chip
, vlan
.fid
, vlan
.vid
, port
,
1501 } while (vlan
.vid
< chip
->info
->max_vid
);
1506 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1507 dsa_fdb_dump_cb_t
*cb
, void *data
)
1509 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1511 return mv88e6xxx_port_db_dump(chip
, port
, cb
, data
);
1514 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip
*chip
,
1515 struct net_device
*br
)
1517 struct dsa_switch
*ds
;
1522 /* Remap the Port VLAN of each local bridge group member */
1523 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); ++port
) {
1524 if (chip
->ds
->ports
[port
].bridge_dev
== br
) {
1525 err
= mv88e6xxx_port_vlan_map(chip
, port
);
1531 if (!mv88e6xxx_has_pvt(chip
))
1534 /* Remap the Port VLAN of each cross-chip bridge group member */
1535 for (dev
= 0; dev
< DSA_MAX_SWITCHES
; ++dev
) {
1536 ds
= chip
->ds
->dst
->ds
[dev
];
1540 for (port
= 0; port
< ds
->num_ports
; ++port
) {
1541 if (ds
->ports
[port
].bridge_dev
== br
) {
1542 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1552 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1553 struct net_device
*br
)
1555 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1558 mutex_lock(&chip
->reg_lock
);
1559 err
= mv88e6xxx_bridge_map(chip
, br
);
1560 mutex_unlock(&chip
->reg_lock
);
1565 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1566 struct net_device
*br
)
1568 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1570 mutex_lock(&chip
->reg_lock
);
1571 if (mv88e6xxx_bridge_map(chip
, br
) ||
1572 mv88e6xxx_port_vlan_map(chip
, port
))
1573 dev_err(ds
->dev
, "failed to remap in-chip Port VLAN\n");
1574 mutex_unlock(&chip
->reg_lock
);
1577 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch
*ds
, int dev
,
1578 int port
, struct net_device
*br
)
1580 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1583 if (!mv88e6xxx_has_pvt(chip
))
1586 mutex_lock(&chip
->reg_lock
);
1587 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1588 mutex_unlock(&chip
->reg_lock
);
1593 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch
*ds
, int dev
,
1594 int port
, struct net_device
*br
)
1596 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1598 if (!mv88e6xxx_has_pvt(chip
))
1601 mutex_lock(&chip
->reg_lock
);
1602 if (mv88e6xxx_pvt_map(chip
, dev
, port
))
1603 dev_err(ds
->dev
, "failed to remap cross-chip Port VLAN\n");
1604 mutex_unlock(&chip
->reg_lock
);
1607 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip
*chip
)
1609 if (chip
->info
->ops
->reset
)
1610 return chip
->info
->ops
->reset(chip
);
1615 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip
*chip
)
1617 struct gpio_desc
*gpiod
= chip
->reset
;
1619 /* If there is a GPIO connected to the reset pin, toggle it */
1621 gpiod_set_value_cansleep(gpiod
, 1);
1622 usleep_range(10000, 20000);
1623 gpiod_set_value_cansleep(gpiod
, 0);
1624 usleep_range(10000, 20000);
1628 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip
*chip
)
1632 /* Set all ports to the Disabled state */
1633 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
1634 err
= mv88e6xxx_port_set_state(chip
, i
, BR_STATE_DISABLED
);
1639 /* Wait for transmit queues to drain,
1640 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1642 usleep_range(2000, 4000);
1647 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip
*chip
)
1651 err
= mv88e6xxx_disable_ports(chip
);
1655 mv88e6xxx_hardware_reset(chip
);
1657 return mv88e6xxx_software_reset(chip
);
1660 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip
*chip
, int port
,
1661 enum mv88e6xxx_frame_mode frame
,
1662 enum mv88e6xxx_egress_mode egress
, u16 etype
)
1666 if (!chip
->info
->ops
->port_set_frame_mode
)
1669 err
= mv88e6xxx_port_set_egress_mode(chip
, port
, egress
);
1673 err
= chip
->info
->ops
->port_set_frame_mode(chip
, port
, frame
);
1677 if (chip
->info
->ops
->port_set_ether_type
)
1678 return chip
->info
->ops
->port_set_ether_type(chip
, port
, etype
);
1683 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip
*chip
, int port
)
1685 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_NORMAL
,
1686 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1687 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1690 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip
*chip
, int port
)
1692 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_DSA
,
1693 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1694 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1697 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip
*chip
, int port
)
1699 return mv88e6xxx_set_port_mode(chip
, port
,
1700 MV88E6XXX_FRAME_MODE_ETHERTYPE
,
1701 MV88E6XXX_EGRESS_MODE_ETHERTYPE
,
1705 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip
*chip
, int port
)
1707 if (dsa_is_dsa_port(chip
->ds
, port
))
1708 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1710 if (dsa_is_user_port(chip
->ds
, port
))
1711 return mv88e6xxx_set_port_mode_normal(chip
, port
);
1713 /* Setup CPU port mode depending on its supported tag format */
1714 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_DSA
)
1715 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1717 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
1718 return mv88e6xxx_set_port_mode_edsa(chip
, port
);
1723 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip
*chip
, int port
)
1725 bool message
= dsa_is_dsa_port(chip
->ds
, port
);
1727 return mv88e6xxx_port_set_message_port(chip
, port
, message
);
1730 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip
*chip
, int port
)
1732 struct dsa_switch
*ds
= chip
->ds
;
1735 /* Upstream ports flood frames with unknown unicast or multicast DA */
1736 flood
= dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
);
1737 if (chip
->info
->ops
->port_set_egress_floods
)
1738 return chip
->info
->ops
->port_set_egress_floods(chip
, port
,
1744 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip
*chip
, int port
,
1747 if (chip
->info
->ops
->serdes_power
)
1748 return chip
->info
->ops
->serdes_power(chip
, port
, on
);
1753 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip
*chip
, int port
)
1755 struct dsa_switch
*ds
= chip
->ds
;
1759 upstream_port
= dsa_upstream_port(ds
, port
);
1760 if (chip
->info
->ops
->port_set_upstream_port
) {
1761 err
= chip
->info
->ops
->port_set_upstream_port(chip
, port
,
1767 if (port
== upstream_port
) {
1768 if (chip
->info
->ops
->set_cpu_port
) {
1769 err
= chip
->info
->ops
->set_cpu_port(chip
,
1775 if (chip
->info
->ops
->set_egress_port
) {
1776 err
= chip
->info
->ops
->set_egress_port(chip
,
1786 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip
, int port
)
1788 struct dsa_switch
*ds
= chip
->ds
;
1792 /* MAC Forcing register: don't force link, speed, duplex or flow control
1793 * state to any particular values on physical ports, but force the CPU
1794 * port and all DSA ports to their maximum bandwidth and full duplex.
1796 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1797 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_FORCED_UP
,
1798 SPEED_MAX
, DUPLEX_FULL
,
1799 PHY_INTERFACE_MODE_NA
);
1801 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_UNFORCED
,
1802 SPEED_UNFORCED
, DUPLEX_UNFORCED
,
1803 PHY_INTERFACE_MODE_NA
);
1807 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1808 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1809 * tunneling, determine priority by looking at 802.1p and IP
1810 * priority fields (IP prio has precedence), and set STP state
1813 * If this is the CPU link, use DSA or EDSA tagging depending
1814 * on which tagging mode was configured.
1816 * If this is a link to another switch, use DSA tagging mode.
1818 * If this is the upstream port for this switch, enable
1819 * forwarding of unknown unicasts and multicasts.
1821 reg
= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP
|
1822 MV88E6185_PORT_CTL0_USE_TAG
| MV88E6185_PORT_CTL0_USE_IP
|
1823 MV88E6XXX_PORT_CTL0_STATE_FORWARDING
;
1824 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
1828 err
= mv88e6xxx_setup_port_mode(chip
, port
);
1832 err
= mv88e6xxx_setup_egress_floods(chip
, port
);
1836 /* Enable the SERDES interface for DSA and CPU ports. Normal
1837 * ports SERDES are enabled when the port is enabled, thus
1838 * saving a bit of power.
1840 if ((dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))) {
1841 err
= mv88e6xxx_serdes_power(chip
, port
, true);
1846 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1847 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1848 * untagged frames on this port, do a destination address lookup on all
1849 * received packets as usual, disable ARP mirroring and don't send a
1850 * copy of all transmitted/received frames on this port to the CPU.
1852 err
= mv88e6xxx_port_set_map_da(chip
, port
);
1856 err
= mv88e6xxx_setup_upstream_port(chip
, port
);
1860 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
,
1861 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
);
1865 if (chip
->info
->ops
->port_set_jumbo_size
) {
1866 err
= chip
->info
->ops
->port_set_jumbo_size(chip
, port
, 10240);
1871 /* Port Association Vector: when learning source addresses
1872 * of packets, add the address to the address database using
1873 * a port bitmap that has only the bit for this port set and
1874 * the other bits clear.
1877 /* Disable learning for CPU port */
1878 if (dsa_is_cpu_port(ds
, port
))
1881 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_ASSOC_VECTOR
,
1886 /* Egress rate control 2: disable egress rate control. */
1887 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_EGRESS_RATE_CTL2
,
1892 if (chip
->info
->ops
->port_pause_limit
) {
1893 err
= chip
->info
->ops
->port_pause_limit(chip
, port
, 0, 0);
1898 if (chip
->info
->ops
->port_disable_learn_limit
) {
1899 err
= chip
->info
->ops
->port_disable_learn_limit(chip
, port
);
1904 if (chip
->info
->ops
->port_disable_pri_override
) {
1905 err
= chip
->info
->ops
->port_disable_pri_override(chip
, port
);
1910 if (chip
->info
->ops
->port_tag_remap
) {
1911 err
= chip
->info
->ops
->port_tag_remap(chip
, port
);
1916 if (chip
->info
->ops
->port_egress_rate_limiting
) {
1917 err
= chip
->info
->ops
->port_egress_rate_limiting(chip
, port
);
1922 err
= mv88e6xxx_setup_message_port(chip
, port
);
1926 /* Port based VLAN map: give each port the same default address
1927 * database, and allow bidirectional communication between the
1928 * CPU and DSA port(s), and the other ports.
1930 err
= mv88e6xxx_port_set_fid(chip
, port
, 0);
1934 err
= mv88e6xxx_port_vlan_map(chip
, port
);
1938 /* Default VLAN ID and priority: don't set a default VLAN
1939 * ID, and set the default packet priority to zero.
1941 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
, 0);
1944 static int mv88e6xxx_port_enable(struct dsa_switch
*ds
, int port
,
1945 struct phy_device
*phydev
)
1947 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1950 mutex_lock(&chip
->reg_lock
);
1951 err
= mv88e6xxx_serdes_power(chip
, port
, true);
1952 mutex_unlock(&chip
->reg_lock
);
1957 static void mv88e6xxx_port_disable(struct dsa_switch
*ds
, int port
,
1958 struct phy_device
*phydev
)
1960 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1962 mutex_lock(&chip
->reg_lock
);
1963 if (mv88e6xxx_serdes_power(chip
, port
, false))
1964 dev_err(chip
->dev
, "failed to power off SERDES\n");
1965 mutex_unlock(&chip
->reg_lock
);
1968 static int mv88e6xxx_set_ageing_time(struct dsa_switch
*ds
,
1969 unsigned int ageing_time
)
1971 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1974 mutex_lock(&chip
->reg_lock
);
1975 err
= mv88e6xxx_g1_atu_set_age_time(chip
, ageing_time
);
1976 mutex_unlock(&chip
->reg_lock
);
1981 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip
*chip
)
1983 struct dsa_switch
*ds
= chip
->ds
;
1986 /* Disable remote management, and set the switch's DSA device number. */
1987 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL2
,
1988 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE
|
1989 (ds
->index
& 0x1f));
1993 /* Configure the IP ToS mapping registers. */
1994 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_0
, 0x0000);
1997 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_1
, 0x0000);
2000 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_2
, 0x5555);
2003 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_3
, 0x5555);
2006 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_4
, 0xaaaa);
2009 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_5
, 0xaaaa);
2012 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_6
, 0xffff);
2015 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_7
, 0xffff);
2019 /* Configure the IEEE 802.1p priority mapping register. */
2020 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IEEE_PRI
, 0xfa41);
2024 /* Initialize the statistics unit */
2025 err
= mv88e6xxx_stats_set_histogram(chip
);
2029 return mv88e6xxx_g1_stats_clear(chip
);
2032 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
2034 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2039 ds
->slave_mii_bus
= mv88e6xxx_default_mdio_bus(chip
);
2041 mutex_lock(&chip
->reg_lock
);
2043 /* Setup Switch Port Registers */
2044 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
2045 if (dsa_is_unused_port(ds
, i
))
2048 err
= mv88e6xxx_setup_port(chip
, i
);
2053 /* Setup Switch Global 1 Registers */
2054 err
= mv88e6xxx_g1_setup(chip
);
2058 /* Setup Switch Global 2 Registers */
2059 if (chip
->info
->global2_addr
) {
2060 err
= mv88e6xxx_g2_setup(chip
);
2065 err
= mv88e6xxx_irl_setup(chip
);
2069 err
= mv88e6xxx_mac_setup(chip
);
2073 err
= mv88e6xxx_phy_setup(chip
);
2077 err
= mv88e6xxx_vtu_setup(chip
);
2081 err
= mv88e6xxx_pvt_setup(chip
);
2085 err
= mv88e6xxx_atu_setup(chip
);
2089 err
= mv88e6xxx_broadcast_setup(chip
, 0);
2093 err
= mv88e6xxx_pot_setup(chip
);
2097 err
= mv88e6xxx_rsvd2cpu_setup(chip
);
2101 /* Setup PTP Hardware Clock and timestamping */
2102 if (chip
->info
->ptp_support
) {
2103 err
= mv88e6xxx_ptp_setup(chip
);
2107 err
= mv88e6xxx_hwtstamp_setup(chip
);
2113 mutex_unlock(&chip
->reg_lock
);
2118 static int mv88e6xxx_mdio_read(struct mii_bus
*bus
, int phy
, int reg
)
2120 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2121 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2125 if (!chip
->info
->ops
->phy_read
)
2128 mutex_lock(&chip
->reg_lock
);
2129 err
= chip
->info
->ops
->phy_read(chip
, bus
, phy
, reg
, &val
);
2130 mutex_unlock(&chip
->reg_lock
);
2132 if (reg
== MII_PHYSID2
) {
2133 /* Some internal PHYS don't have a model number. Use
2134 * the mv88e6390 family model number instead.
2137 val
|= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
>> 4;
2140 return err
? err
: val
;
2143 static int mv88e6xxx_mdio_write(struct mii_bus
*bus
, int phy
, int reg
, u16 val
)
2145 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2146 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2149 if (!chip
->info
->ops
->phy_write
)
2152 mutex_lock(&chip
->reg_lock
);
2153 err
= chip
->info
->ops
->phy_write(chip
, bus
, phy
, reg
, val
);
2154 mutex_unlock(&chip
->reg_lock
);
2159 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip
*chip
,
2160 struct device_node
*np
,
2164 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2165 struct mii_bus
*bus
;
2169 mutex_lock(&chip
->reg_lock
);
2170 err
= mv88e6xxx_g2_scratch_gpio_set_smi(chip
, true);
2171 mutex_unlock(&chip
->reg_lock
);
2177 bus
= devm_mdiobus_alloc_size(chip
->dev
, sizeof(*mdio_bus
));
2181 mdio_bus
= bus
->priv
;
2182 mdio_bus
->bus
= bus
;
2183 mdio_bus
->chip
= chip
;
2184 INIT_LIST_HEAD(&mdio_bus
->list
);
2185 mdio_bus
->external
= external
;
2188 bus
->name
= np
->full_name
;
2189 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%pOF", np
);
2191 bus
->name
= "mv88e6xxx SMI";
2192 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "mv88e6xxx-%d", index
++);
2195 bus
->read
= mv88e6xxx_mdio_read
;
2196 bus
->write
= mv88e6xxx_mdio_write
;
2197 bus
->parent
= chip
->dev
;
2200 err
= of_mdiobus_register(bus
, np
);
2202 err
= mdiobus_register(bus
);
2204 dev_err(chip
->dev
, "Cannot register MDIO bus (%d)\n", err
);
2209 list_add_tail(&mdio_bus
->list
, &chip
->mdios
);
2211 list_add(&mdio_bus
->list
, &chip
->mdios
);
2216 static const struct of_device_id mv88e6xxx_mdio_external_match
[] = {
2217 { .compatible
= "marvell,mv88e6xxx-mdio-external",
2218 .data
= (void *)true },
2222 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip
*chip
)
2225 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2226 struct mii_bus
*bus
;
2228 list_for_each_entry(mdio_bus
, &chip
->mdios
, list
) {
2229 bus
= mdio_bus
->bus
;
2231 mdiobus_unregister(bus
);
2235 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip
*chip
,
2236 struct device_node
*np
)
2238 const struct of_device_id
*match
;
2239 struct device_node
*child
;
2242 /* Always register one mdio bus for the internal/default mdio
2243 * bus. This maybe represented in the device tree, but is
2246 child
= of_get_child_by_name(np
, "mdio");
2247 err
= mv88e6xxx_mdio_register(chip
, child
, false);
2251 /* Walk the device tree, and see if there are any other nodes
2252 * which say they are compatible with the external mdio
2255 for_each_available_child_of_node(np
, child
) {
2256 match
= of_match_node(mv88e6xxx_mdio_external_match
, child
);
2258 err
= mv88e6xxx_mdio_register(chip
, child
, true);
2260 mv88e6xxx_mdios_unregister(chip
);
2269 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
2271 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2273 return chip
->eeprom_len
;
2276 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
2277 struct ethtool_eeprom
*eeprom
, u8
*data
)
2279 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2282 if (!chip
->info
->ops
->get_eeprom
)
2285 mutex_lock(&chip
->reg_lock
);
2286 err
= chip
->info
->ops
->get_eeprom(chip
, eeprom
, data
);
2287 mutex_unlock(&chip
->reg_lock
);
2292 eeprom
->magic
= 0xc3ec4951;
2297 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
2298 struct ethtool_eeprom
*eeprom
, u8
*data
)
2300 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2303 if (!chip
->info
->ops
->set_eeprom
)
2306 if (eeprom
->magic
!= 0xc3ec4951)
2309 mutex_lock(&chip
->reg_lock
);
2310 err
= chip
->info
->ops
->set_eeprom(chip
, eeprom
, data
);
2311 mutex_unlock(&chip
->reg_lock
);
2316 static const struct mv88e6xxx_ops mv88e6085_ops
= {
2317 /* MV88E6XXX_FAMILY_6097 */
2318 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2319 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2320 .phy_read
= mv88e6185_phy_ppu_read
,
2321 .phy_write
= mv88e6185_phy_ppu_write
,
2322 .port_set_link
= mv88e6xxx_port_set_link
,
2323 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2324 .port_set_speed
= mv88e6185_port_set_speed
,
2325 .port_tag_remap
= mv88e6095_port_tag_remap
,
2326 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2327 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2328 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2329 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2330 .port_pause_limit
= mv88e6097_port_pause_limit
,
2331 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2332 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2333 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2334 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2335 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2336 .stats_get_strings
= mv88e6095_stats_get_strings
,
2337 .stats_get_stats
= mv88e6095_stats_get_stats
,
2338 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2339 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2340 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2341 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2342 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2343 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2344 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2345 .reset
= mv88e6185_g1_reset
,
2346 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2347 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2350 static const struct mv88e6xxx_ops mv88e6095_ops
= {
2351 /* MV88E6XXX_FAMILY_6095 */
2352 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2353 .phy_read
= mv88e6185_phy_ppu_read
,
2354 .phy_write
= mv88e6185_phy_ppu_write
,
2355 .port_set_link
= mv88e6xxx_port_set_link
,
2356 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2357 .port_set_speed
= mv88e6185_port_set_speed
,
2358 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2359 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2360 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2361 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2362 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2363 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2364 .stats_get_strings
= mv88e6095_stats_get_strings
,
2365 .stats_get_stats
= mv88e6095_stats_get_stats
,
2366 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2367 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2368 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2369 .reset
= mv88e6185_g1_reset
,
2370 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2371 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2374 static const struct mv88e6xxx_ops mv88e6097_ops
= {
2375 /* MV88E6XXX_FAMILY_6097 */
2376 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2377 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2378 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2379 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2380 .port_set_link
= mv88e6xxx_port_set_link
,
2381 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2382 .port_set_speed
= mv88e6185_port_set_speed
,
2383 .port_tag_remap
= mv88e6095_port_tag_remap
,
2384 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2385 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2386 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2387 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2388 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2389 .port_pause_limit
= mv88e6097_port_pause_limit
,
2390 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2391 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2392 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2393 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2394 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2395 .stats_get_strings
= mv88e6095_stats_get_strings
,
2396 .stats_get_stats
= mv88e6095_stats_get_stats
,
2397 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2398 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2399 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2400 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2401 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2402 .reset
= mv88e6352_g1_reset
,
2403 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2404 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2407 static const struct mv88e6xxx_ops mv88e6123_ops
= {
2408 /* MV88E6XXX_FAMILY_6165 */
2409 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2410 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2411 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2412 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2413 .port_set_link
= mv88e6xxx_port_set_link
,
2414 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2415 .port_set_speed
= mv88e6185_port_set_speed
,
2416 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2417 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2418 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2419 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2420 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2421 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2422 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2423 .stats_get_strings
= mv88e6095_stats_get_strings
,
2424 .stats_get_stats
= mv88e6095_stats_get_stats
,
2425 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2426 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2427 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2428 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2429 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2430 .reset
= mv88e6352_g1_reset
,
2431 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2432 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2435 static const struct mv88e6xxx_ops mv88e6131_ops
= {
2436 /* MV88E6XXX_FAMILY_6185 */
2437 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2438 .phy_read
= mv88e6185_phy_ppu_read
,
2439 .phy_write
= mv88e6185_phy_ppu_write
,
2440 .port_set_link
= mv88e6xxx_port_set_link
,
2441 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2442 .port_set_speed
= mv88e6185_port_set_speed
,
2443 .port_tag_remap
= mv88e6095_port_tag_remap
,
2444 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2445 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2446 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2447 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2448 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2449 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2450 .port_pause_limit
= mv88e6097_port_pause_limit
,
2451 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2452 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2453 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2454 .stats_get_strings
= mv88e6095_stats_get_strings
,
2455 .stats_get_stats
= mv88e6095_stats_get_stats
,
2456 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2457 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2458 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2459 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2460 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2461 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2462 .reset
= mv88e6185_g1_reset
,
2463 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2464 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2467 static const struct mv88e6xxx_ops mv88e6141_ops
= {
2468 /* MV88E6XXX_FAMILY_6341 */
2469 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2470 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2471 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2472 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2473 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2474 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2475 .port_set_link
= mv88e6xxx_port_set_link
,
2476 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2477 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2478 .port_set_speed
= mv88e6390_port_set_speed
,
2479 .port_tag_remap
= mv88e6095_port_tag_remap
,
2480 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2481 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2482 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2483 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2484 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2485 .port_pause_limit
= mv88e6097_port_pause_limit
,
2486 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2487 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2488 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2489 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2490 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2491 .stats_get_strings
= mv88e6320_stats_get_strings
,
2492 .stats_get_stats
= mv88e6390_stats_get_stats
,
2493 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2494 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2495 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2496 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2497 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2498 .reset
= mv88e6352_g1_reset
,
2499 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2500 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2501 .gpio_ops
= &mv88e6352_gpio_ops
,
2504 static const struct mv88e6xxx_ops mv88e6161_ops
= {
2505 /* MV88E6XXX_FAMILY_6165 */
2506 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2507 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2508 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2509 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2510 .port_set_link
= mv88e6xxx_port_set_link
,
2511 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2512 .port_set_speed
= mv88e6185_port_set_speed
,
2513 .port_tag_remap
= mv88e6095_port_tag_remap
,
2514 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2515 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2516 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2517 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2518 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2519 .port_pause_limit
= mv88e6097_port_pause_limit
,
2520 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2521 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2522 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2523 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2524 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2525 .stats_get_strings
= mv88e6095_stats_get_strings
,
2526 .stats_get_stats
= mv88e6095_stats_get_stats
,
2527 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2528 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2529 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2530 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2531 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2532 .reset
= mv88e6352_g1_reset
,
2533 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2534 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2537 static const struct mv88e6xxx_ops mv88e6165_ops
= {
2538 /* MV88E6XXX_FAMILY_6165 */
2539 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2540 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2541 .phy_read
= mv88e6165_phy_read
,
2542 .phy_write
= mv88e6165_phy_write
,
2543 .port_set_link
= mv88e6xxx_port_set_link
,
2544 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2545 .port_set_speed
= mv88e6185_port_set_speed
,
2546 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2547 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2548 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2549 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2550 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2551 .stats_get_strings
= mv88e6095_stats_get_strings
,
2552 .stats_get_stats
= mv88e6095_stats_get_stats
,
2553 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2554 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2555 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2556 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2557 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2558 .reset
= mv88e6352_g1_reset
,
2559 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2560 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2563 static const struct mv88e6xxx_ops mv88e6171_ops
= {
2564 /* MV88E6XXX_FAMILY_6351 */
2565 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2566 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2567 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2568 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2569 .port_set_link
= mv88e6xxx_port_set_link
,
2570 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2571 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2572 .port_set_speed
= mv88e6185_port_set_speed
,
2573 .port_tag_remap
= mv88e6095_port_tag_remap
,
2574 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2575 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2576 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2577 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2578 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2579 .port_pause_limit
= mv88e6097_port_pause_limit
,
2580 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2581 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2582 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2583 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2584 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2585 .stats_get_strings
= mv88e6095_stats_get_strings
,
2586 .stats_get_stats
= mv88e6095_stats_get_stats
,
2587 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2588 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2589 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2590 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2591 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2592 .reset
= mv88e6352_g1_reset
,
2593 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2594 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2597 static const struct mv88e6xxx_ops mv88e6172_ops
= {
2598 /* MV88E6XXX_FAMILY_6352 */
2599 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2600 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2601 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2602 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2603 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2604 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2605 .port_set_link
= mv88e6xxx_port_set_link
,
2606 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2607 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2608 .port_set_speed
= mv88e6352_port_set_speed
,
2609 .port_tag_remap
= mv88e6095_port_tag_remap
,
2610 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2611 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2612 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2613 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2614 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2615 .port_pause_limit
= mv88e6097_port_pause_limit
,
2616 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2617 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2618 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2619 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2620 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2621 .stats_get_strings
= mv88e6095_stats_get_strings
,
2622 .stats_get_stats
= mv88e6095_stats_get_stats
,
2623 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2624 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2625 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2626 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2627 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2628 .reset
= mv88e6352_g1_reset
,
2629 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2630 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2631 .serdes_power
= mv88e6352_serdes_power
,
2632 .gpio_ops
= &mv88e6352_gpio_ops
,
2635 static const struct mv88e6xxx_ops mv88e6175_ops
= {
2636 /* MV88E6XXX_FAMILY_6351 */
2637 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2638 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2639 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2640 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2641 .port_set_link
= mv88e6xxx_port_set_link
,
2642 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2643 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2644 .port_set_speed
= mv88e6185_port_set_speed
,
2645 .port_tag_remap
= mv88e6095_port_tag_remap
,
2646 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2647 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2648 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2649 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2650 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2651 .port_pause_limit
= mv88e6097_port_pause_limit
,
2652 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2653 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2654 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2655 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2656 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2657 .stats_get_strings
= mv88e6095_stats_get_strings
,
2658 .stats_get_stats
= mv88e6095_stats_get_stats
,
2659 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2660 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2661 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2662 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2663 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2664 .reset
= mv88e6352_g1_reset
,
2665 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2666 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2669 static const struct mv88e6xxx_ops mv88e6176_ops
= {
2670 /* MV88E6XXX_FAMILY_6352 */
2671 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2672 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2673 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2674 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2675 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2676 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2677 .port_set_link
= mv88e6xxx_port_set_link
,
2678 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2679 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2680 .port_set_speed
= mv88e6352_port_set_speed
,
2681 .port_tag_remap
= mv88e6095_port_tag_remap
,
2682 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2683 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2684 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2685 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2686 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2687 .port_pause_limit
= mv88e6097_port_pause_limit
,
2688 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2689 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2690 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2691 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2692 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2693 .stats_get_strings
= mv88e6095_stats_get_strings
,
2694 .stats_get_stats
= mv88e6095_stats_get_stats
,
2695 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2696 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2697 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2698 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2699 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2700 .reset
= mv88e6352_g1_reset
,
2701 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2702 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2703 .serdes_power
= mv88e6352_serdes_power
,
2704 .gpio_ops
= &mv88e6352_gpio_ops
,
2707 static const struct mv88e6xxx_ops mv88e6185_ops
= {
2708 /* MV88E6XXX_FAMILY_6185 */
2709 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2710 .phy_read
= mv88e6185_phy_ppu_read
,
2711 .phy_write
= mv88e6185_phy_ppu_write
,
2712 .port_set_link
= mv88e6xxx_port_set_link
,
2713 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2714 .port_set_speed
= mv88e6185_port_set_speed
,
2715 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2716 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2717 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2718 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2719 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2720 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2721 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2722 .stats_get_strings
= mv88e6095_stats_get_strings
,
2723 .stats_get_stats
= mv88e6095_stats_get_stats
,
2724 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2725 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2726 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2727 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2728 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2729 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2730 .reset
= mv88e6185_g1_reset
,
2731 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2732 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2735 static const struct mv88e6xxx_ops mv88e6190_ops
= {
2736 /* MV88E6XXX_FAMILY_6390 */
2737 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2738 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2739 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2740 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2741 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2742 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2743 .port_set_link
= mv88e6xxx_port_set_link
,
2744 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2745 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2746 .port_set_speed
= mv88e6390_port_set_speed
,
2747 .port_tag_remap
= mv88e6390_port_tag_remap
,
2748 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2749 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2750 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2751 .port_pause_limit
= mv88e6390_port_pause_limit
,
2752 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2753 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2754 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2755 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2756 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2757 .stats_get_strings
= mv88e6320_stats_get_strings
,
2758 .stats_get_stats
= mv88e6390_stats_get_stats
,
2759 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2760 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2761 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2762 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2763 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2764 .reset
= mv88e6352_g1_reset
,
2765 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2766 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2767 .serdes_power
= mv88e6390_serdes_power
,
2768 .gpio_ops
= &mv88e6352_gpio_ops
,
2771 static const struct mv88e6xxx_ops mv88e6190x_ops
= {
2772 /* MV88E6XXX_FAMILY_6390 */
2773 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2774 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2775 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2776 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2777 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2778 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2779 .port_set_link
= mv88e6xxx_port_set_link
,
2780 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2781 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2782 .port_set_speed
= mv88e6390x_port_set_speed
,
2783 .port_tag_remap
= mv88e6390_port_tag_remap
,
2784 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2785 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2786 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2787 .port_pause_limit
= mv88e6390_port_pause_limit
,
2788 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2789 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2790 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2791 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2792 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2793 .stats_get_strings
= mv88e6320_stats_get_strings
,
2794 .stats_get_stats
= mv88e6390_stats_get_stats
,
2795 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2796 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2797 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2798 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2799 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2800 .reset
= mv88e6352_g1_reset
,
2801 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2802 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2803 .serdes_power
= mv88e6390_serdes_power
,
2804 .gpio_ops
= &mv88e6352_gpio_ops
,
2807 static const struct mv88e6xxx_ops mv88e6191_ops
= {
2808 /* MV88E6XXX_FAMILY_6390 */
2809 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2810 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2811 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2812 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2813 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2814 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2815 .port_set_link
= mv88e6xxx_port_set_link
,
2816 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2817 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2818 .port_set_speed
= mv88e6390_port_set_speed
,
2819 .port_tag_remap
= mv88e6390_port_tag_remap
,
2820 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2821 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2822 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2823 .port_pause_limit
= mv88e6390_port_pause_limit
,
2824 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2825 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2826 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2827 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2828 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2829 .stats_get_strings
= mv88e6320_stats_get_strings
,
2830 .stats_get_stats
= mv88e6390_stats_get_stats
,
2831 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2832 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2833 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2834 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2835 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2836 .reset
= mv88e6352_g1_reset
,
2837 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2838 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2839 .serdes_power
= mv88e6390_serdes_power
,
2842 static const struct mv88e6xxx_ops mv88e6240_ops
= {
2843 /* MV88E6XXX_FAMILY_6352 */
2844 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2845 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2846 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2847 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2848 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2849 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2850 .port_set_link
= mv88e6xxx_port_set_link
,
2851 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2852 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2853 .port_set_speed
= mv88e6352_port_set_speed
,
2854 .port_tag_remap
= mv88e6095_port_tag_remap
,
2855 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2856 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2857 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2858 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2859 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2860 .port_pause_limit
= mv88e6097_port_pause_limit
,
2861 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2862 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2863 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2864 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2865 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2866 .stats_get_strings
= mv88e6095_stats_get_strings
,
2867 .stats_get_stats
= mv88e6095_stats_get_stats
,
2868 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2869 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2870 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2871 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2872 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2873 .reset
= mv88e6352_g1_reset
,
2874 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2875 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2876 .serdes_power
= mv88e6352_serdes_power
,
2877 .gpio_ops
= &mv88e6352_gpio_ops
,
2878 .avb_ops
= &mv88e6352_avb_ops
,
2881 static const struct mv88e6xxx_ops mv88e6290_ops
= {
2882 /* MV88E6XXX_FAMILY_6390 */
2883 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2884 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2885 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2886 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2887 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2888 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2889 .port_set_link
= mv88e6xxx_port_set_link
,
2890 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2891 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2892 .port_set_speed
= mv88e6390_port_set_speed
,
2893 .port_tag_remap
= mv88e6390_port_tag_remap
,
2894 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2895 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2896 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2897 .port_pause_limit
= mv88e6390_port_pause_limit
,
2898 .port_set_cmode
= mv88e6390x_port_set_cmode
,
2899 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2900 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2901 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2902 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2903 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2904 .stats_get_strings
= mv88e6320_stats_get_strings
,
2905 .stats_get_stats
= mv88e6390_stats_get_stats
,
2906 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2907 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2908 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2909 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2910 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2911 .reset
= mv88e6352_g1_reset
,
2912 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2913 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2914 .serdes_power
= mv88e6390_serdes_power
,
2915 .gpio_ops
= &mv88e6352_gpio_ops
,
2916 .avb_ops
= &mv88e6390_avb_ops
,
2919 static const struct mv88e6xxx_ops mv88e6320_ops
= {
2920 /* MV88E6XXX_FAMILY_6320 */
2921 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2922 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2923 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2924 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2925 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2926 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2927 .port_set_link
= mv88e6xxx_port_set_link
,
2928 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2929 .port_set_speed
= mv88e6185_port_set_speed
,
2930 .port_tag_remap
= mv88e6095_port_tag_remap
,
2931 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2932 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2933 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2934 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2935 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2936 .port_pause_limit
= mv88e6097_port_pause_limit
,
2937 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2938 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2939 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2940 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2941 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2942 .stats_get_strings
= mv88e6320_stats_get_strings
,
2943 .stats_get_stats
= mv88e6320_stats_get_stats
,
2944 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2945 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2946 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2947 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2948 .reset
= mv88e6352_g1_reset
,
2949 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2950 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2951 .gpio_ops
= &mv88e6352_gpio_ops
,
2952 .avb_ops
= &mv88e6352_avb_ops
,
2955 static const struct mv88e6xxx_ops mv88e6321_ops
= {
2956 /* MV88E6XXX_FAMILY_6320 */
2957 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2958 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2959 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2960 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2961 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2962 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2963 .port_set_link
= mv88e6xxx_port_set_link
,
2964 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2965 .port_set_speed
= mv88e6185_port_set_speed
,
2966 .port_tag_remap
= mv88e6095_port_tag_remap
,
2967 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2968 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2969 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2970 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2971 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2972 .port_pause_limit
= mv88e6097_port_pause_limit
,
2973 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2974 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2975 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2976 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2977 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2978 .stats_get_strings
= mv88e6320_stats_get_strings
,
2979 .stats_get_stats
= mv88e6320_stats_get_stats
,
2980 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2981 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2982 .reset
= mv88e6352_g1_reset
,
2983 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2984 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2985 .gpio_ops
= &mv88e6352_gpio_ops
,
2986 .avb_ops
= &mv88e6352_avb_ops
,
2989 static const struct mv88e6xxx_ops mv88e6341_ops
= {
2990 /* MV88E6XXX_FAMILY_6341 */
2991 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2992 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2993 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2994 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2995 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2996 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2997 .port_set_link
= mv88e6xxx_port_set_link
,
2998 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2999 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3000 .port_set_speed
= mv88e6390_port_set_speed
,
3001 .port_tag_remap
= mv88e6095_port_tag_remap
,
3002 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3003 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3004 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3005 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3006 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3007 .port_pause_limit
= mv88e6097_port_pause_limit
,
3008 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3009 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3010 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3011 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3012 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3013 .stats_get_strings
= mv88e6320_stats_get_strings
,
3014 .stats_get_stats
= mv88e6390_stats_get_stats
,
3015 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3016 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3017 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3018 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3019 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3020 .reset
= mv88e6352_g1_reset
,
3021 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3022 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3023 .gpio_ops
= &mv88e6352_gpio_ops
,
3024 .avb_ops
= &mv88e6390_avb_ops
,
3027 static const struct mv88e6xxx_ops mv88e6350_ops
= {
3028 /* MV88E6XXX_FAMILY_6351 */
3029 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3030 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3031 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3032 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3033 .port_set_link
= mv88e6xxx_port_set_link
,
3034 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3035 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3036 .port_set_speed
= mv88e6185_port_set_speed
,
3037 .port_tag_remap
= mv88e6095_port_tag_remap
,
3038 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3039 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3040 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3041 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3042 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3043 .port_pause_limit
= mv88e6097_port_pause_limit
,
3044 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3045 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3046 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3047 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3048 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3049 .stats_get_strings
= mv88e6095_stats_get_strings
,
3050 .stats_get_stats
= mv88e6095_stats_get_stats
,
3051 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3052 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3053 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3054 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3055 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3056 .reset
= mv88e6352_g1_reset
,
3057 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3058 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3061 static const struct mv88e6xxx_ops mv88e6351_ops
= {
3062 /* MV88E6XXX_FAMILY_6351 */
3063 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3064 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3065 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3066 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3067 .port_set_link
= mv88e6xxx_port_set_link
,
3068 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3069 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3070 .port_set_speed
= mv88e6185_port_set_speed
,
3071 .port_tag_remap
= mv88e6095_port_tag_remap
,
3072 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3073 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3074 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3075 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3076 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3077 .port_pause_limit
= mv88e6097_port_pause_limit
,
3078 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3079 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3080 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3081 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3082 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3083 .stats_get_strings
= mv88e6095_stats_get_strings
,
3084 .stats_get_stats
= mv88e6095_stats_get_stats
,
3085 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3086 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3087 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3088 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3089 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3090 .reset
= mv88e6352_g1_reset
,
3091 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3092 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3093 .avb_ops
= &mv88e6352_avb_ops
,
3096 static const struct mv88e6xxx_ops mv88e6352_ops
= {
3097 /* MV88E6XXX_FAMILY_6352 */
3098 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3099 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
3100 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
3101 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3102 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3103 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3104 .port_set_link
= mv88e6xxx_port_set_link
,
3105 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3106 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3107 .port_set_speed
= mv88e6352_port_set_speed
,
3108 .port_tag_remap
= mv88e6095_port_tag_remap
,
3109 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3110 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3111 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3112 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3113 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3114 .port_pause_limit
= mv88e6097_port_pause_limit
,
3115 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3116 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3117 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3118 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3119 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3120 .stats_get_strings
= mv88e6095_stats_get_strings
,
3121 .stats_get_stats
= mv88e6095_stats_get_stats
,
3122 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3123 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3124 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3125 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3126 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3127 .reset
= mv88e6352_g1_reset
,
3128 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3129 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3130 .serdes_power
= mv88e6352_serdes_power
,
3131 .gpio_ops
= &mv88e6352_gpio_ops
,
3132 .avb_ops
= &mv88e6352_avb_ops
,
3135 static const struct mv88e6xxx_ops mv88e6390_ops
= {
3136 /* MV88E6XXX_FAMILY_6390 */
3137 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3138 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3139 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3140 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3141 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3142 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3143 .port_set_link
= mv88e6xxx_port_set_link
,
3144 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3145 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3146 .port_set_speed
= mv88e6390_port_set_speed
,
3147 .port_tag_remap
= mv88e6390_port_tag_remap
,
3148 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3149 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3150 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3151 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3152 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3153 .port_pause_limit
= mv88e6390_port_pause_limit
,
3154 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3155 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3156 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3157 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3158 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3159 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3160 .stats_get_strings
= mv88e6320_stats_get_strings
,
3161 .stats_get_stats
= mv88e6390_stats_get_stats
,
3162 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3163 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3164 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3165 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3166 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3167 .reset
= mv88e6352_g1_reset
,
3168 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3169 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3170 .serdes_power
= mv88e6390_serdes_power
,
3171 .gpio_ops
= &mv88e6352_gpio_ops
,
3172 .avb_ops
= &mv88e6390_avb_ops
,
3175 static const struct mv88e6xxx_ops mv88e6390x_ops
= {
3176 /* MV88E6XXX_FAMILY_6390 */
3177 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3178 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3179 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3180 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3181 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3182 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3183 .port_set_link
= mv88e6xxx_port_set_link
,
3184 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3185 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3186 .port_set_speed
= mv88e6390x_port_set_speed
,
3187 .port_tag_remap
= mv88e6390_port_tag_remap
,
3188 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3189 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3190 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3191 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3192 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3193 .port_pause_limit
= mv88e6390_port_pause_limit
,
3194 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3195 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3196 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3197 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3198 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3199 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3200 .stats_get_strings
= mv88e6320_stats_get_strings
,
3201 .stats_get_stats
= mv88e6390_stats_get_stats
,
3202 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3203 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3204 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3205 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3206 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3207 .reset
= mv88e6352_g1_reset
,
3208 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3209 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3210 .serdes_power
= mv88e6390_serdes_power
,
3211 .gpio_ops
= &mv88e6352_gpio_ops
,
3212 .avb_ops
= &mv88e6390_avb_ops
,
3215 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3217 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6085
,
3218 .family
= MV88E6XXX_FAMILY_6097
,
3219 .name
= "Marvell 88E6085",
3220 .num_databases
= 4096,
3223 .port_base_addr
= 0x10,
3224 .global1_addr
= 0x1b,
3225 .global2_addr
= 0x1c,
3226 .age_time_coeff
= 15000,
3229 .atu_move_port_mask
= 0xf,
3232 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3233 .ops
= &mv88e6085_ops
,
3237 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6095
,
3238 .family
= MV88E6XXX_FAMILY_6095
,
3239 .name
= "Marvell 88E6095/88E6095F",
3240 .num_databases
= 256,
3243 .port_base_addr
= 0x10,
3244 .global1_addr
= 0x1b,
3245 .global2_addr
= 0x1c,
3246 .age_time_coeff
= 15000,
3248 .atu_move_port_mask
= 0xf,
3250 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3251 .ops
= &mv88e6095_ops
,
3255 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6097
,
3256 .family
= MV88E6XXX_FAMILY_6097
,
3257 .name
= "Marvell 88E6097/88E6097F",
3258 .num_databases
= 4096,
3261 .port_base_addr
= 0x10,
3262 .global1_addr
= 0x1b,
3263 .global2_addr
= 0x1c,
3264 .age_time_coeff
= 15000,
3267 .atu_move_port_mask
= 0xf,
3270 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3271 .ops
= &mv88e6097_ops
,
3275 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6123
,
3276 .family
= MV88E6XXX_FAMILY_6165
,
3277 .name
= "Marvell 88E6123",
3278 .num_databases
= 4096,
3281 .port_base_addr
= 0x10,
3282 .global1_addr
= 0x1b,
3283 .global2_addr
= 0x1c,
3284 .age_time_coeff
= 15000,
3287 .atu_move_port_mask
= 0xf,
3290 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3291 .ops
= &mv88e6123_ops
,
3295 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6131
,
3296 .family
= MV88E6XXX_FAMILY_6185
,
3297 .name
= "Marvell 88E6131",
3298 .num_databases
= 256,
3301 .port_base_addr
= 0x10,
3302 .global1_addr
= 0x1b,
3303 .global2_addr
= 0x1c,
3304 .age_time_coeff
= 15000,
3306 .atu_move_port_mask
= 0xf,
3308 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3309 .ops
= &mv88e6131_ops
,
3313 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6141
,
3314 .family
= MV88E6XXX_FAMILY_6341
,
3315 .name
= "Marvell 88E6341",
3316 .num_databases
= 4096,
3320 .port_base_addr
= 0x10,
3321 .global1_addr
= 0x1b,
3322 .global2_addr
= 0x1c,
3323 .age_time_coeff
= 3750,
3324 .atu_move_port_mask
= 0x1f,
3328 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3329 .ops
= &mv88e6141_ops
,
3333 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6161
,
3334 .family
= MV88E6XXX_FAMILY_6165
,
3335 .name
= "Marvell 88E6161",
3336 .num_databases
= 4096,
3339 .port_base_addr
= 0x10,
3340 .global1_addr
= 0x1b,
3341 .global2_addr
= 0x1c,
3342 .age_time_coeff
= 15000,
3345 .atu_move_port_mask
= 0xf,
3348 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3349 .ops
= &mv88e6161_ops
,
3353 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6165
,
3354 .family
= MV88E6XXX_FAMILY_6165
,
3355 .name
= "Marvell 88E6165",
3356 .num_databases
= 4096,
3359 .port_base_addr
= 0x10,
3360 .global1_addr
= 0x1b,
3361 .global2_addr
= 0x1c,
3362 .age_time_coeff
= 15000,
3365 .atu_move_port_mask
= 0xf,
3368 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3369 .ops
= &mv88e6165_ops
,
3373 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6171
,
3374 .family
= MV88E6XXX_FAMILY_6351
,
3375 .name
= "Marvell 88E6171",
3376 .num_databases
= 4096,
3379 .port_base_addr
= 0x10,
3380 .global1_addr
= 0x1b,
3381 .global2_addr
= 0x1c,
3382 .age_time_coeff
= 15000,
3385 .atu_move_port_mask
= 0xf,
3388 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3389 .ops
= &mv88e6171_ops
,
3393 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6172
,
3394 .family
= MV88E6XXX_FAMILY_6352
,
3395 .name
= "Marvell 88E6172",
3396 .num_databases
= 4096,
3400 .port_base_addr
= 0x10,
3401 .global1_addr
= 0x1b,
3402 .global2_addr
= 0x1c,
3403 .age_time_coeff
= 15000,
3406 .atu_move_port_mask
= 0xf,
3409 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3410 .ops
= &mv88e6172_ops
,
3414 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6175
,
3415 .family
= MV88E6XXX_FAMILY_6351
,
3416 .name
= "Marvell 88E6175",
3417 .num_databases
= 4096,
3420 .port_base_addr
= 0x10,
3421 .global1_addr
= 0x1b,
3422 .global2_addr
= 0x1c,
3423 .age_time_coeff
= 15000,
3426 .atu_move_port_mask
= 0xf,
3429 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3430 .ops
= &mv88e6175_ops
,
3434 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6176
,
3435 .family
= MV88E6XXX_FAMILY_6352
,
3436 .name
= "Marvell 88E6176",
3437 .num_databases
= 4096,
3441 .port_base_addr
= 0x10,
3442 .global1_addr
= 0x1b,
3443 .global2_addr
= 0x1c,
3444 .age_time_coeff
= 15000,
3447 .atu_move_port_mask
= 0xf,
3450 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3451 .ops
= &mv88e6176_ops
,
3455 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6185
,
3456 .family
= MV88E6XXX_FAMILY_6185
,
3457 .name
= "Marvell 88E6185",
3458 .num_databases
= 256,
3461 .port_base_addr
= 0x10,
3462 .global1_addr
= 0x1b,
3463 .global2_addr
= 0x1c,
3464 .age_time_coeff
= 15000,
3466 .atu_move_port_mask
= 0xf,
3468 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3469 .ops
= &mv88e6185_ops
,
3473 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190
,
3474 .family
= MV88E6XXX_FAMILY_6390
,
3475 .name
= "Marvell 88E6190",
3476 .num_databases
= 4096,
3477 .num_ports
= 11, /* 10 + Z80 */
3480 .port_base_addr
= 0x0,
3481 .global1_addr
= 0x1b,
3482 .global2_addr
= 0x1c,
3483 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3484 .age_time_coeff
= 3750,
3489 .atu_move_port_mask
= 0x1f,
3490 .ops
= &mv88e6190_ops
,
3494 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190X
,
3495 .family
= MV88E6XXX_FAMILY_6390
,
3496 .name
= "Marvell 88E6190X",
3497 .num_databases
= 4096,
3498 .num_ports
= 11, /* 10 + Z80 */
3501 .port_base_addr
= 0x0,
3502 .global1_addr
= 0x1b,
3503 .global2_addr
= 0x1c,
3504 .age_time_coeff
= 3750,
3507 .atu_move_port_mask
= 0x1f,
3510 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3511 .ops
= &mv88e6190x_ops
,
3515 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6191
,
3516 .family
= MV88E6XXX_FAMILY_6390
,
3517 .name
= "Marvell 88E6191",
3518 .num_databases
= 4096,
3519 .num_ports
= 11, /* 10 + Z80 */
3521 .port_base_addr
= 0x0,
3522 .global1_addr
= 0x1b,
3523 .global2_addr
= 0x1c,
3524 .age_time_coeff
= 3750,
3527 .atu_move_port_mask
= 0x1f,
3530 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3531 .ptp_support
= true,
3532 .ops
= &mv88e6191_ops
,
3536 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6240
,
3537 .family
= MV88E6XXX_FAMILY_6352
,
3538 .name
= "Marvell 88E6240",
3539 .num_databases
= 4096,
3543 .port_base_addr
= 0x10,
3544 .global1_addr
= 0x1b,
3545 .global2_addr
= 0x1c,
3546 .age_time_coeff
= 15000,
3549 .atu_move_port_mask
= 0xf,
3552 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3553 .ptp_support
= true,
3554 .ops
= &mv88e6240_ops
,
3558 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6290
,
3559 .family
= MV88E6XXX_FAMILY_6390
,
3560 .name
= "Marvell 88E6290",
3561 .num_databases
= 4096,
3562 .num_ports
= 11, /* 10 + Z80 */
3565 .port_base_addr
= 0x0,
3566 .global1_addr
= 0x1b,
3567 .global2_addr
= 0x1c,
3568 .age_time_coeff
= 3750,
3571 .atu_move_port_mask
= 0x1f,
3574 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3575 .ptp_support
= true,
3576 .ops
= &mv88e6290_ops
,
3580 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6320
,
3581 .family
= MV88E6XXX_FAMILY_6320
,
3582 .name
= "Marvell 88E6320",
3583 .num_databases
= 4096,
3587 .port_base_addr
= 0x10,
3588 .global1_addr
= 0x1b,
3589 .global2_addr
= 0x1c,
3590 .age_time_coeff
= 15000,
3592 .atu_move_port_mask
= 0xf,
3595 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3596 .ptp_support
= true,
3597 .ops
= &mv88e6320_ops
,
3601 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6321
,
3602 .family
= MV88E6XXX_FAMILY_6320
,
3603 .name
= "Marvell 88E6321",
3604 .num_databases
= 4096,
3608 .port_base_addr
= 0x10,
3609 .global1_addr
= 0x1b,
3610 .global2_addr
= 0x1c,
3611 .age_time_coeff
= 15000,
3613 .atu_move_port_mask
= 0xf,
3615 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3616 .ptp_support
= true,
3617 .ops
= &mv88e6321_ops
,
3621 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6341
,
3622 .family
= MV88E6XXX_FAMILY_6341
,
3623 .name
= "Marvell 88E6341",
3624 .num_databases
= 4096,
3628 .port_base_addr
= 0x10,
3629 .global1_addr
= 0x1b,
3630 .global2_addr
= 0x1c,
3631 .age_time_coeff
= 3750,
3632 .atu_move_port_mask
= 0x1f,
3636 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3637 .ptp_support
= true,
3638 .ops
= &mv88e6341_ops
,
3642 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6350
,
3643 .family
= MV88E6XXX_FAMILY_6351
,
3644 .name
= "Marvell 88E6350",
3645 .num_databases
= 4096,
3648 .port_base_addr
= 0x10,
3649 .global1_addr
= 0x1b,
3650 .global2_addr
= 0x1c,
3651 .age_time_coeff
= 15000,
3654 .atu_move_port_mask
= 0xf,
3657 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3658 .ops
= &mv88e6350_ops
,
3662 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6351
,
3663 .family
= MV88E6XXX_FAMILY_6351
,
3664 .name
= "Marvell 88E6351",
3665 .num_databases
= 4096,
3668 .port_base_addr
= 0x10,
3669 .global1_addr
= 0x1b,
3670 .global2_addr
= 0x1c,
3671 .age_time_coeff
= 15000,
3674 .atu_move_port_mask
= 0xf,
3677 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3678 .ops
= &mv88e6351_ops
,
3682 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6352
,
3683 .family
= MV88E6XXX_FAMILY_6352
,
3684 .name
= "Marvell 88E6352",
3685 .num_databases
= 4096,
3689 .port_base_addr
= 0x10,
3690 .global1_addr
= 0x1b,
3691 .global2_addr
= 0x1c,
3692 .age_time_coeff
= 15000,
3695 .atu_move_port_mask
= 0xf,
3698 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3699 .ptp_support
= true,
3700 .ops
= &mv88e6352_ops
,
3703 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
,
3704 .family
= MV88E6XXX_FAMILY_6390
,
3705 .name
= "Marvell 88E6390",
3706 .num_databases
= 4096,
3707 .num_ports
= 11, /* 10 + Z80 */
3710 .port_base_addr
= 0x0,
3711 .global1_addr
= 0x1b,
3712 .global2_addr
= 0x1c,
3713 .age_time_coeff
= 3750,
3716 .atu_move_port_mask
= 0x1f,
3719 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3720 .ptp_support
= true,
3721 .ops
= &mv88e6390_ops
,
3724 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390X
,
3725 .family
= MV88E6XXX_FAMILY_6390
,
3726 .name
= "Marvell 88E6390X",
3727 .num_databases
= 4096,
3728 .num_ports
= 11, /* 10 + Z80 */
3731 .port_base_addr
= 0x0,
3732 .global1_addr
= 0x1b,
3733 .global2_addr
= 0x1c,
3734 .age_time_coeff
= 3750,
3737 .atu_move_port_mask
= 0x1f,
3740 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3741 .ptp_support
= true,
3742 .ops
= &mv88e6390x_ops
,
3746 static const struct mv88e6xxx_info
*mv88e6xxx_lookup_info(unsigned int prod_num
)
3750 for (i
= 0; i
< ARRAY_SIZE(mv88e6xxx_table
); ++i
)
3751 if (mv88e6xxx_table
[i
].prod_num
== prod_num
)
3752 return &mv88e6xxx_table
[i
];
3757 static int mv88e6xxx_detect(struct mv88e6xxx_chip
*chip
)
3759 const struct mv88e6xxx_info
*info
;
3760 unsigned int prod_num
, rev
;
3764 mutex_lock(&chip
->reg_lock
);
3765 err
= mv88e6xxx_port_read(chip
, 0, MV88E6XXX_PORT_SWITCH_ID
, &id
);
3766 mutex_unlock(&chip
->reg_lock
);
3770 prod_num
= id
& MV88E6XXX_PORT_SWITCH_ID_PROD_MASK
;
3771 rev
= id
& MV88E6XXX_PORT_SWITCH_ID_REV_MASK
;
3773 info
= mv88e6xxx_lookup_info(prod_num
);
3777 /* Update the compatible info with the probed one */
3780 err
= mv88e6xxx_g2_require(chip
);
3784 dev_info(chip
->dev
, "switch 0x%x detected: %s, revision %u\n",
3785 chip
->info
->prod_num
, chip
->info
->name
, rev
);
3790 static struct mv88e6xxx_chip
*mv88e6xxx_alloc_chip(struct device
*dev
)
3792 struct mv88e6xxx_chip
*chip
;
3794 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
3800 mutex_init(&chip
->reg_lock
);
3801 INIT_LIST_HEAD(&chip
->mdios
);
3806 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip
*chip
,
3807 struct mii_bus
*bus
, int sw_addr
)
3810 chip
->smi_ops
= &mv88e6xxx_smi_single_chip_ops
;
3811 else if (chip
->info
->multi_chip
)
3812 chip
->smi_ops
= &mv88e6xxx_smi_multi_chip_ops
;
3817 chip
->sw_addr
= sw_addr
;
3822 static enum dsa_tag_protocol
mv88e6xxx_get_tag_protocol(struct dsa_switch
*ds
,
3825 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3827 return chip
->info
->tag_protocol
;
3830 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3831 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3832 struct device
*host_dev
, int sw_addr
,
3835 struct mv88e6xxx_chip
*chip
;
3836 struct mii_bus
*bus
;
3839 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3843 chip
= mv88e6xxx_alloc_chip(dsa_dev
);
3847 /* Legacy SMI probing will only support chips similar to 88E6085 */
3848 chip
->info
= &mv88e6xxx_table
[MV88E6085
];
3850 err
= mv88e6xxx_smi_init(chip
, bus
, sw_addr
);
3854 err
= mv88e6xxx_detect(chip
);
3858 mutex_lock(&chip
->reg_lock
);
3859 err
= mv88e6xxx_switch_reset(chip
);
3860 mutex_unlock(&chip
->reg_lock
);
3864 mv88e6xxx_phy_init(chip
);
3866 err
= mv88e6xxx_mdios_register(chip
, NULL
);
3872 return chip
->info
->name
;
3874 devm_kfree(dsa_dev
, chip
);
3880 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch
*ds
, int port
,
3881 const struct switchdev_obj_port_mdb
*mdb
)
3883 /* We don't need any dynamic resource from the kernel (yet),
3884 * so skip the prepare phase.
3890 static void mv88e6xxx_port_mdb_add(struct dsa_switch
*ds
, int port
,
3891 const struct switchdev_obj_port_mdb
*mdb
)
3893 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3895 mutex_lock(&chip
->reg_lock
);
3896 if (mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3897 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
))
3898 dev_err(ds
->dev
, "p%d: failed to load multicast MAC address\n",
3900 mutex_unlock(&chip
->reg_lock
);
3903 static int mv88e6xxx_port_mdb_del(struct dsa_switch
*ds
, int port
,
3904 const struct switchdev_obj_port_mdb
*mdb
)
3906 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3909 mutex_lock(&chip
->reg_lock
);
3910 err
= mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3911 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
3912 mutex_unlock(&chip
->reg_lock
);
3917 static const struct dsa_switch_ops mv88e6xxx_switch_ops
= {
3918 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3919 .probe
= mv88e6xxx_drv_probe
,
3921 .get_tag_protocol
= mv88e6xxx_get_tag_protocol
,
3922 .setup
= mv88e6xxx_setup
,
3923 .adjust_link
= mv88e6xxx_adjust_link
,
3924 .get_strings
= mv88e6xxx_get_strings
,
3925 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
3926 .get_sset_count
= mv88e6xxx_get_sset_count
,
3927 .port_enable
= mv88e6xxx_port_enable
,
3928 .port_disable
= mv88e6xxx_port_disable
,
3929 .get_mac_eee
= mv88e6xxx_get_mac_eee
,
3930 .set_mac_eee
= mv88e6xxx_set_mac_eee
,
3931 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
3932 .get_eeprom
= mv88e6xxx_get_eeprom
,
3933 .set_eeprom
= mv88e6xxx_set_eeprom
,
3934 .get_regs_len
= mv88e6xxx_get_regs_len
,
3935 .get_regs
= mv88e6xxx_get_regs
,
3936 .set_ageing_time
= mv88e6xxx_set_ageing_time
,
3937 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
3938 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
3939 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
3940 .port_fast_age
= mv88e6xxx_port_fast_age
,
3941 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
3942 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
3943 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
3944 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
3945 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
3946 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
3947 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
3948 .port_mdb_prepare
= mv88e6xxx_port_mdb_prepare
,
3949 .port_mdb_add
= mv88e6xxx_port_mdb_add
,
3950 .port_mdb_del
= mv88e6xxx_port_mdb_del
,
3951 .crosschip_bridge_join
= mv88e6xxx_crosschip_bridge_join
,
3952 .crosschip_bridge_leave
= mv88e6xxx_crosschip_bridge_leave
,
3953 .port_hwtstamp_set
= mv88e6xxx_port_hwtstamp_set
,
3954 .port_hwtstamp_get
= mv88e6xxx_port_hwtstamp_get
,
3955 .port_txtstamp
= mv88e6xxx_port_txtstamp
,
3956 .port_rxtstamp
= mv88e6xxx_port_rxtstamp
,
3957 .get_ts_info
= mv88e6xxx_get_ts_info
,
3960 static struct dsa_switch_driver mv88e6xxx_switch_drv
= {
3961 .ops
= &mv88e6xxx_switch_ops
,
3964 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip
*chip
)
3966 struct device
*dev
= chip
->dev
;
3967 struct dsa_switch
*ds
;
3969 ds
= dsa_switch_alloc(dev
, mv88e6xxx_num_ports(chip
));
3974 ds
->ops
= &mv88e6xxx_switch_ops
;
3975 ds
->ageing_time_min
= chip
->info
->age_time_coeff
;
3976 ds
->ageing_time_max
= chip
->info
->age_time_coeff
* U8_MAX
;
3978 dev_set_drvdata(dev
, ds
);
3980 return dsa_register_switch(ds
);
3983 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip
*chip
)
3985 dsa_unregister_switch(chip
->ds
);
3988 static int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
3990 struct device
*dev
= &mdiodev
->dev
;
3991 struct device_node
*np
= dev
->of_node
;
3992 const struct mv88e6xxx_info
*compat_info
;
3993 struct mv88e6xxx_chip
*chip
;
3997 compat_info
= of_device_get_match_data(dev
);
4001 chip
= mv88e6xxx_alloc_chip(dev
);
4005 chip
->info
= compat_info
;
4007 err
= mv88e6xxx_smi_init(chip
, mdiodev
->bus
, mdiodev
->addr
);
4011 chip
->reset
= devm_gpiod_get_optional(dev
, "reset", GPIOD_OUT_LOW
);
4012 if (IS_ERR(chip
->reset
))
4013 return PTR_ERR(chip
->reset
);
4015 err
= mv88e6xxx_detect(chip
);
4019 mv88e6xxx_phy_init(chip
);
4021 if (chip
->info
->ops
->get_eeprom
&&
4022 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
4023 chip
->eeprom_len
= eeprom_len
;
4025 mutex_lock(&chip
->reg_lock
);
4026 err
= mv88e6xxx_switch_reset(chip
);
4027 mutex_unlock(&chip
->reg_lock
);
4031 chip
->irq
= of_irq_get(np
, 0);
4032 if (chip
->irq
== -EPROBE_DEFER
) {
4037 if (chip
->irq
> 0) {
4038 /* Has to be performed before the MDIO bus is created,
4039 * because the PHYs will link there interrupts to these
4040 * interrupt controllers
4042 mutex_lock(&chip
->reg_lock
);
4043 err
= mv88e6xxx_g1_irq_setup(chip
);
4044 mutex_unlock(&chip
->reg_lock
);
4049 if (chip
->info
->g2_irqs
> 0) {
4050 err
= mv88e6xxx_g2_irq_setup(chip
);
4055 err
= mv88e6xxx_g1_atu_prob_irq_setup(chip
);
4059 err
= mv88e6xxx_g1_vtu_prob_irq_setup(chip
);
4061 goto out_g1_atu_prob_irq
;
4064 err
= mv88e6xxx_mdios_register(chip
, np
);
4066 goto out_g1_vtu_prob_irq
;
4068 err
= mv88e6xxx_register_switch(chip
);
4075 mv88e6xxx_mdios_unregister(chip
);
4076 out_g1_vtu_prob_irq
:
4078 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4079 out_g1_atu_prob_irq
:
4081 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4083 if (chip
->info
->g2_irqs
> 0 && chip
->irq
> 0)
4084 mv88e6xxx_g2_irq_free(chip
);
4086 if (chip
->irq
> 0) {
4087 mutex_lock(&chip
->reg_lock
);
4088 mv88e6xxx_g1_irq_free(chip
);
4089 mutex_unlock(&chip
->reg_lock
);
4095 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
4097 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
4098 struct mv88e6xxx_chip
*chip
= ds
->priv
;
4100 if (chip
->info
->ptp_support
) {
4101 mv88e6xxx_hwtstamp_free(chip
);
4102 mv88e6xxx_ptp_free(chip
);
4105 mv88e6xxx_phy_destroy(chip
);
4106 mv88e6xxx_unregister_switch(chip
);
4107 mv88e6xxx_mdios_unregister(chip
);
4109 if (chip
->irq
> 0) {
4110 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4111 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4112 if (chip
->info
->g2_irqs
> 0)
4113 mv88e6xxx_g2_irq_free(chip
);
4114 mutex_lock(&chip
->reg_lock
);
4115 mv88e6xxx_g1_irq_free(chip
);
4116 mutex_unlock(&chip
->reg_lock
);
4120 static const struct of_device_id mv88e6xxx_of_match
[] = {
4122 .compatible
= "marvell,mv88e6085",
4123 .data
= &mv88e6xxx_table
[MV88E6085
],
4126 .compatible
= "marvell,mv88e6190",
4127 .data
= &mv88e6xxx_table
[MV88E6190
],
4132 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
4134 static struct mdio_driver mv88e6xxx_driver
= {
4135 .probe
= mv88e6xxx_probe
,
4136 .remove
= mv88e6xxx_remove
,
4138 .name
= "mv88e6085",
4139 .of_match_table
= mv88e6xxx_of_match
,
4143 static int __init
mv88e6xxx_init(void)
4145 register_switch_driver(&mv88e6xxx_switch_drv
);
4146 return mdio_driver_register(&mv88e6xxx_driver
);
4148 module_init(mv88e6xxx_init
);
4150 static void __exit
mv88e6xxx_cleanup(void)
4152 mdio_driver_unregister(&mv88e6xxx_driver
);
4153 unregister_switch_driver(&mv88e6xxx_switch_drv
);
4155 module_exit(mv88e6xxx_cleanup
);
4157 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4158 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4159 MODULE_LICENSE("GPL");