2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
45 static void assert_reg_lock(struct mv88e6xxx_chip
*chip
)
47 if (unlikely(!mutex_is_locked(&chip
->reg_lock
))) {
48 dev_err(chip
->dev
, "Switch registers lock not held!\n");
53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip
*chip
,
66 int addr
, int reg
, u16
*val
)
71 return chip
->smi_ops
->read(chip
, addr
, reg
, val
);
74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip
*chip
,
75 int addr
, int reg
, u16 val
)
80 return chip
->smi_ops
->write(chip
, addr
, reg
, val
);
83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip
*chip
,
84 int addr
, int reg
, u16
*val
)
88 ret
= mdiobus_read_nested(chip
->bus
, addr
, reg
);
97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip
*chip
,
98 int addr
, int reg
, u16 val
)
102 ret
= mdiobus_write_nested(chip
->bus
, addr
, reg
, val
);
109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops
= {
110 .read
= mv88e6xxx_smi_single_chip_read
,
111 .write
= mv88e6xxx_smi_single_chip_write
,
114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip
*chip
)
119 for (i
= 0; i
< 16; i
++) {
120 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
);
124 if ((ret
& SMI_CMD_BUSY
) == 0)
131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip
*chip
,
132 int addr
, int reg
, u16
*val
)
136 /* Wait for the bus to become free. */
137 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
141 /* Transmit the read command. */
142 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
143 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
147 /* Wait for the read command to complete. */
148 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
153 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
);
162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip
*chip
,
163 int addr
, int reg
, u16 val
)
167 /* Wait for the bus to become free. */
168 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
172 /* Transmit the data to write. */
173 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
, val
);
177 /* Transmit the write command. */
178 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
179 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
183 /* Wait for the write command to complete. */
184 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops
= {
192 .read
= mv88e6xxx_smi_multi_chip_read
,
193 .write
= mv88e6xxx_smi_multi_chip_write
,
196 int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
)
200 assert_reg_lock(chip
);
202 err
= mv88e6xxx_smi_read(chip
, addr
, reg
, val
);
206 dev_dbg(chip
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
212 int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
)
216 assert_reg_lock(chip
);
218 err
= mv88e6xxx_smi_write(chip
, addr
, reg
, val
);
222 dev_dbg(chip
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
228 struct mii_bus
*mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip
*chip
)
230 struct mv88e6xxx_mdio_bus
*mdio_bus
;
232 mdio_bus
= list_first_entry(&chip
->mdios
, struct mv88e6xxx_mdio_bus
,
237 return mdio_bus
->bus
;
240 static void mv88e6xxx_g1_irq_mask(struct irq_data
*d
)
242 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
243 unsigned int n
= d
->hwirq
;
245 chip
->g1_irq
.masked
|= (1 << n
);
248 static void mv88e6xxx_g1_irq_unmask(struct irq_data
*d
)
250 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
251 unsigned int n
= d
->hwirq
;
253 chip
->g1_irq
.masked
&= ~(1 << n
);
256 static irqreturn_t
mv88e6xxx_g1_irq_thread_fn(int irq
, void *dev_id
)
258 struct mv88e6xxx_chip
*chip
= dev_id
;
259 unsigned int nhandled
= 0;
260 unsigned int sub_irq
;
265 mutex_lock(&chip
->reg_lock
);
266 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
267 mutex_unlock(&chip
->reg_lock
);
272 for (n
= 0; n
< chip
->g1_irq
.nirqs
; ++n
) {
273 if (reg
& (1 << n
)) {
274 sub_irq
= irq_find_mapping(chip
->g1_irq
.domain
, n
);
275 handle_nested_irq(sub_irq
);
280 return (nhandled
> 0 ? IRQ_HANDLED
: IRQ_NONE
);
283 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data
*d
)
285 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
287 mutex_lock(&chip
->reg_lock
);
290 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data
*d
)
292 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
293 u16 mask
= GENMASK(chip
->g1_irq
.nirqs
, 0);
297 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, ®
);
302 reg
|= (~chip
->g1_irq
.masked
& mask
);
304 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, reg
);
309 mutex_unlock(&chip
->reg_lock
);
312 static const struct irq_chip mv88e6xxx_g1_irq_chip
= {
313 .name
= "mv88e6xxx-g1",
314 .irq_mask
= mv88e6xxx_g1_irq_mask
,
315 .irq_unmask
= mv88e6xxx_g1_irq_unmask
,
316 .irq_bus_lock
= mv88e6xxx_g1_irq_bus_lock
,
317 .irq_bus_sync_unlock
= mv88e6xxx_g1_irq_bus_sync_unlock
,
320 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain
*d
,
322 irq_hw_number_t hwirq
)
324 struct mv88e6xxx_chip
*chip
= d
->host_data
;
326 irq_set_chip_data(irq
, d
->host_data
);
327 irq_set_chip_and_handler(irq
, &chip
->g1_irq
.chip
, handle_level_irq
);
328 irq_set_noprobe(irq
);
333 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops
= {
334 .map
= mv88e6xxx_g1_irq_domain_map
,
335 .xlate
= irq_domain_xlate_twocell
,
338 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip
*chip
)
343 mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
344 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
345 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
347 free_irq(chip
->irq
, chip
);
349 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++) {
350 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
351 irq_dispose_mapping(virq
);
354 irq_domain_remove(chip
->g1_irq
.domain
);
357 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip
*chip
)
362 chip
->g1_irq
.nirqs
= chip
->info
->g1_irqs
;
363 chip
->g1_irq
.domain
= irq_domain_add_simple(
364 NULL
, chip
->g1_irq
.nirqs
, 0,
365 &mv88e6xxx_g1_irq_domain_ops
, chip
);
366 if (!chip
->g1_irq
.domain
)
369 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++)
370 irq_create_mapping(chip
->g1_irq
.domain
, irq
);
372 chip
->g1_irq
.chip
= mv88e6xxx_g1_irq_chip
;
373 chip
->g1_irq
.masked
= ~0;
375 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
379 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
381 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
385 /* Reading the interrupt status clears (most of) them */
386 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
390 err
= request_threaded_irq(chip
->irq
, NULL
,
391 mv88e6xxx_g1_irq_thread_fn
,
392 IRQF_ONESHOT
| IRQF_TRIGGER_FALLING
,
393 dev_name(chip
->dev
), chip
);
400 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
401 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
404 for (irq
= 0; irq
< 16; irq
++) {
405 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
406 irq_dispose_mapping(virq
);
409 irq_domain_remove(chip
->g1_irq
.domain
);
414 int mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 mask
)
418 for (i
= 0; i
< 16; i
++) {
422 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
429 usleep_range(1000, 2000);
432 dev_err(chip
->dev
, "Timeout while waiting for switch\n");
436 /* Indirect write to single pointer-data register with an Update bit */
437 int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 update
)
442 /* Wait until the previous operation is completed */
443 err
= mv88e6xxx_wait(chip
, addr
, reg
, BIT(15));
447 /* Set the Update bit to trigger a write operation */
448 val
= BIT(15) | update
;
450 return mv88e6xxx_write(chip
, addr
, reg
, val
);
453 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip
*chip
, int port
,
454 int link
, int speed
, int duplex
,
455 phy_interface_t mode
)
459 if (!chip
->info
->ops
->port_set_link
)
462 /* Port's MAC control must not be changed unless the link is down */
463 err
= chip
->info
->ops
->port_set_link(chip
, port
, 0);
467 if (chip
->info
->ops
->port_set_speed
) {
468 err
= chip
->info
->ops
->port_set_speed(chip
, port
, speed
);
469 if (err
&& err
!= -EOPNOTSUPP
)
473 if (chip
->info
->ops
->port_set_duplex
) {
474 err
= chip
->info
->ops
->port_set_duplex(chip
, port
, duplex
);
475 if (err
&& err
!= -EOPNOTSUPP
)
479 if (chip
->info
->ops
->port_set_rgmii_delay
) {
480 err
= chip
->info
->ops
->port_set_rgmii_delay(chip
, port
, mode
);
481 if (err
&& err
!= -EOPNOTSUPP
)
485 if (chip
->info
->ops
->port_set_cmode
) {
486 err
= chip
->info
->ops
->port_set_cmode(chip
, port
, mode
);
487 if (err
&& err
!= -EOPNOTSUPP
)
493 if (chip
->info
->ops
->port_set_link(chip
, port
, link
))
494 dev_err(chip
->dev
, "p%d: failed to restore MAC's link\n", port
);
499 /* We expect the switch to perform auto negotiation if there is a real
500 * phy. However, in the case of a fixed link phy, we force the port
501 * settings from the fixed link settings.
503 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
504 struct phy_device
*phydev
)
506 struct mv88e6xxx_chip
*chip
= ds
->priv
;
509 if (!phy_is_pseudo_fixed_link(phydev
))
512 mutex_lock(&chip
->reg_lock
);
513 err
= mv88e6xxx_port_setup_mac(chip
, port
, phydev
->link
, phydev
->speed
,
514 phydev
->duplex
, phydev
->interface
);
515 mutex_unlock(&chip
->reg_lock
);
517 if (err
&& err
!= -EOPNOTSUPP
)
518 dev_err(ds
->dev
, "p%d: failed to configure MAC\n", port
);
521 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
)
523 if (!chip
->info
->ops
->stats_snapshot
)
526 return chip
->info
->ops
->stats_snapshot(chip
, port
);
529 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
530 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0
, },
531 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0
, },
532 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0
, },
533 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0
, },
534 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0
, },
535 { "in_pause", 4, 0x16, STATS_TYPE_BANK0
, },
536 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0
, },
537 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0
, },
538 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0
, },
539 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0
, },
540 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0
, },
541 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0
, },
542 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0
, },
543 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0
, },
544 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0
, },
545 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0
, },
546 { "out_pause", 4, 0x15, STATS_TYPE_BANK0
, },
547 { "excessive", 4, 0x11, STATS_TYPE_BANK0
, },
548 { "collisions", 4, 0x1e, STATS_TYPE_BANK0
, },
549 { "deferred", 4, 0x05, STATS_TYPE_BANK0
, },
550 { "single", 4, 0x14, STATS_TYPE_BANK0
, },
551 { "multiple", 4, 0x17, STATS_TYPE_BANK0
, },
552 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0
, },
553 { "late", 4, 0x1f, STATS_TYPE_BANK0
, },
554 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0
, },
555 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0
, },
556 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0
, },
557 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0
, },
558 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0
, },
559 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0
, },
560 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT
, },
561 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT
, },
562 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT
, },
563 { "in_discards", 4, 0x00, STATS_TYPE_BANK1
, },
564 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1
, },
565 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1
, },
566 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1
, },
567 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1
, },
568 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1
, },
569 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1
, },
570 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1
, },
571 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1
, },
572 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1
, },
573 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1
, },
574 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1
, },
575 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1
, },
576 { "in_management", 4, 0x0f, STATS_TYPE_BANK1
, },
577 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1
, },
578 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1
, },
579 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1
, },
580 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1
, },
581 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1
, },
582 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1
, },
583 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1
, },
584 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1
, },
585 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1
, },
586 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1
, },
587 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1
, },
588 { "out_management", 4, 0x1f, STATS_TYPE_BANK1
, },
591 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip
*chip
,
592 struct mv88e6xxx_hw_stat
*s
,
593 int port
, u16 bank1_select
,
603 case STATS_TYPE_PORT
:
604 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
, ®
);
609 if (s
->sizeof_stat
== 4) {
610 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
+ 1, ®
);
616 case STATS_TYPE_BANK1
:
619 case STATS_TYPE_BANK0
:
620 reg
|= s
->reg
| histogram
;
621 mv88e6xxx_g1_stats_read(chip
, reg
, &low
);
622 if (s
->sizeof_stat
== 8)
623 mv88e6xxx_g1_stats_read(chip
, reg
+ 1, &high
);
628 value
= (((u64
)high
) << 16) | low
;
632 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip
*chip
,
633 uint8_t *data
, int types
)
635 struct mv88e6xxx_hw_stat
*stat
;
638 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
639 stat
= &mv88e6xxx_hw_stats
[i
];
640 if (stat
->type
& types
) {
641 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
648 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip
*chip
,
651 mv88e6xxx_stats_get_strings(chip
, data
,
652 STATS_TYPE_BANK0
| STATS_TYPE_PORT
);
655 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip
*chip
,
658 mv88e6xxx_stats_get_strings(chip
, data
,
659 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
);
662 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
665 struct mv88e6xxx_chip
*chip
= ds
->priv
;
667 if (chip
->info
->ops
->stats_get_strings
)
668 chip
->info
->ops
->stats_get_strings(chip
, data
);
671 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip
*chip
,
674 struct mv88e6xxx_hw_stat
*stat
;
677 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
678 stat
= &mv88e6xxx_hw_stats
[i
];
679 if (stat
->type
& types
)
685 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
687 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
691 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
693 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
697 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
699 struct mv88e6xxx_chip
*chip
= ds
->priv
;
701 if (chip
->info
->ops
->stats_get_sset_count
)
702 return chip
->info
->ops
->stats_get_sset_count(chip
);
707 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
708 uint64_t *data
, int types
,
709 u16 bank1_select
, u16 histogram
)
711 struct mv88e6xxx_hw_stat
*stat
;
714 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
715 stat
= &mv88e6xxx_hw_stats
[i
];
716 if (stat
->type
& types
) {
717 data
[j
] = _mv88e6xxx_get_ethtool_stat(chip
, stat
, port
,
725 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
728 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
729 STATS_TYPE_BANK0
| STATS_TYPE_PORT
,
730 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
733 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
736 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
737 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
738 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9
,
739 MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
742 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
745 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
746 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
747 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10
,
751 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
754 if (chip
->info
->ops
->stats_get_stats
)
755 chip
->info
->ops
->stats_get_stats(chip
, port
, data
);
758 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
761 struct mv88e6xxx_chip
*chip
= ds
->priv
;
764 mutex_lock(&chip
->reg_lock
);
766 ret
= mv88e6xxx_stats_snapshot(chip
, port
);
768 mutex_unlock(&chip
->reg_lock
);
772 mv88e6xxx_get_stats(chip
, port
, data
);
774 mutex_unlock(&chip
->reg_lock
);
777 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip
*chip
)
779 if (chip
->info
->ops
->stats_set_histogram
)
780 return chip
->info
->ops
->stats_set_histogram(chip
);
785 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
787 return 32 * sizeof(u16
);
790 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
791 struct ethtool_regs
*regs
, void *_p
)
793 struct mv88e6xxx_chip
*chip
= ds
->priv
;
801 memset(p
, 0xff, 32 * sizeof(u16
));
803 mutex_lock(&chip
->reg_lock
);
805 for (i
= 0; i
< 32; i
++) {
807 err
= mv88e6xxx_port_read(chip
, port
, i
, ®
);
812 mutex_unlock(&chip
->reg_lock
);
815 static int mv88e6xxx_get_mac_eee(struct dsa_switch
*ds
, int port
,
816 struct ethtool_eee
*e
)
818 /* Nothing to do on the port's MAC */
822 static int mv88e6xxx_set_mac_eee(struct dsa_switch
*ds
, int port
,
823 struct ethtool_eee
*e
)
825 /* Nothing to do on the port's MAC */
829 static u16
mv88e6xxx_port_vlan(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
831 struct dsa_switch
*ds
= NULL
;
832 struct net_device
*br
;
836 if (dev
< DSA_MAX_SWITCHES
)
837 ds
= chip
->ds
->dst
->ds
[dev
];
839 /* Prevent frames from unknown switch or port */
840 if (!ds
|| port
>= ds
->num_ports
)
843 /* Frames from DSA links and CPU ports can egress any local port */
844 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
845 return mv88e6xxx_port_mask(chip
);
847 br
= ds
->ports
[port
].bridge_dev
;
850 /* Frames from user ports can egress any local DSA links and CPU ports,
851 * as well as any local member of their bridge group.
853 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
854 if (dsa_is_cpu_port(chip
->ds
, i
) ||
855 dsa_is_dsa_port(chip
->ds
, i
) ||
856 (br
&& dsa_to_port(chip
->ds
, i
)->bridge_dev
== br
))
862 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip
*chip
, int port
)
864 u16 output_ports
= mv88e6xxx_port_vlan(chip
, chip
->ds
->index
, port
);
866 /* prevent frames from going back out of the port they came in on */
867 output_ports
&= ~BIT(port
);
869 return mv88e6xxx_port_set_vlan_map(chip
, port
, output_ports
);
872 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
875 struct mv88e6xxx_chip
*chip
= ds
->priv
;
878 mutex_lock(&chip
->reg_lock
);
879 err
= mv88e6xxx_port_set_state(chip
, port
, state
);
880 mutex_unlock(&chip
->reg_lock
);
883 dev_err(ds
->dev
, "p%d: failed to update state\n", port
);
886 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip
*chip
)
888 if (chip
->info
->ops
->pot_clear
)
889 return chip
->info
->ops
->pot_clear(chip
);
894 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip
*chip
)
896 if (chip
->info
->ops
->mgmt_rsvd2cpu
)
897 return chip
->info
->ops
->mgmt_rsvd2cpu(chip
);
902 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip
*chip
)
906 err
= mv88e6xxx_g1_atu_flush(chip
, 0, true);
910 err
= mv88e6xxx_g1_atu_set_learn2all(chip
, true);
914 return mv88e6xxx_g1_atu_set_age_time(chip
, 300000);
917 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip
*chip
)
922 if (!chip
->info
->ops
->irl_init_all
)
925 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
926 /* Disable ingress rate limiting by resetting all per port
927 * ingress rate limit resources to their initial state.
929 err
= chip
->info
->ops
->irl_init_all(chip
, port
);
937 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip
*chip
)
939 if (chip
->info
->ops
->set_switch_mac
) {
942 eth_random_addr(addr
);
944 return chip
->info
->ops
->set_switch_mac(chip
, addr
);
950 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
954 if (!mv88e6xxx_has_pvt(chip
))
957 /* Skip the local source device, which uses in-chip port VLAN */
958 if (dev
!= chip
->ds
->index
)
959 pvlan
= mv88e6xxx_port_vlan(chip
, dev
, port
);
961 return mv88e6xxx_g2_pvt_write(chip
, dev
, port
, pvlan
);
964 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip
*chip
)
969 if (!mv88e6xxx_has_pvt(chip
))
972 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
973 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
975 err
= mv88e6xxx_g2_misc_4_bit_port(chip
);
979 for (dev
= 0; dev
< MV88E6XXX_MAX_PVT_SWITCHES
; ++dev
) {
980 for (port
= 0; port
< MV88E6XXX_MAX_PVT_PORTS
; ++port
) {
981 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
990 static void mv88e6xxx_port_fast_age(struct dsa_switch
*ds
, int port
)
992 struct mv88e6xxx_chip
*chip
= ds
->priv
;
995 mutex_lock(&chip
->reg_lock
);
996 err
= mv88e6xxx_g1_atu_remove(chip
, 0, port
, false);
997 mutex_unlock(&chip
->reg_lock
);
1000 dev_err(ds
->dev
, "p%d: failed to flush ATU\n", port
);
1003 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip
*chip
)
1005 if (!chip
->info
->max_vid
)
1008 return mv88e6xxx_g1_vtu_flush(chip
);
1011 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip
*chip
,
1012 struct mv88e6xxx_vtu_entry
*entry
)
1014 if (!chip
->info
->ops
->vtu_getnext
)
1017 return chip
->info
->ops
->vtu_getnext(chip
, entry
);
1020 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
1021 struct mv88e6xxx_vtu_entry
*entry
)
1023 if (!chip
->info
->ops
->vtu_loadpurge
)
1026 return chip
->info
->ops
->vtu_loadpurge(chip
, entry
);
1029 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip
*chip
, u16
*fid
)
1031 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1032 struct mv88e6xxx_vtu_entry vlan
= {
1033 .vid
= chip
->info
->max_vid
,
1037 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1039 /* Set every FID bit used by the (un)bridged ports */
1040 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1041 err
= mv88e6xxx_port_get_fid(chip
, i
, fid
);
1045 set_bit(*fid
, fid_bitmap
);
1048 /* Set every FID bit used by the VLAN entries */
1050 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1057 set_bit(vlan
.fid
, fid_bitmap
);
1058 } while (vlan
.vid
< chip
->info
->max_vid
);
1060 /* The reset value 0x000 is used to indicate that multiple address
1061 * databases are not needed. Return the next positive available.
1063 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1064 if (unlikely(*fid
>= mv88e6xxx_num_databases(chip
)))
1067 /* Clear the database */
1068 return mv88e6xxx_g1_atu_flush(chip
, *fid
, true);
1071 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip
*chip
, u16 vid
,
1072 struct mv88e6xxx_vtu_entry
*entry
, bool new)
1079 entry
->vid
= vid
- 1;
1080 entry
->valid
= false;
1082 err
= mv88e6xxx_vtu_getnext(chip
, entry
);
1086 if (entry
->vid
== vid
&& entry
->valid
)
1092 /* Initialize a fresh VLAN entry */
1093 memset(entry
, 0, sizeof(*entry
));
1094 entry
->valid
= true;
1097 /* Exclude all ports */
1098 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
1100 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1102 return mv88e6xxx_atu_new(chip
, &entry
->fid
);
1105 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1109 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1110 u16 vid_begin
, u16 vid_end
)
1112 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1113 struct mv88e6xxx_vtu_entry vlan
= {
1114 .vid
= vid_begin
- 1,
1118 /* DSA and CPU ports have to be members of multiple vlans */
1119 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1125 mutex_lock(&chip
->reg_lock
);
1128 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1135 if (vlan
.vid
> vid_end
)
1138 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1139 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1142 if (!ds
->ports
[i
].slave
)
1145 if (vlan
.member
[i
] ==
1146 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1149 if (dsa_to_port(ds
, i
)->bridge_dev
==
1150 ds
->ports
[port
].bridge_dev
)
1151 break; /* same bridge, check next VLAN */
1153 if (!dsa_to_port(ds
, i
)->bridge_dev
)
1156 dev_err(ds
->dev
, "p%d: hw VLAN %d already used by port %d in %s\n",
1158 netdev_name(dsa_to_port(ds
, i
)->bridge_dev
));
1162 } while (vlan
.vid
< vid_end
);
1165 mutex_unlock(&chip
->reg_lock
);
1170 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1171 bool vlan_filtering
)
1173 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1174 u16 mode
= vlan_filtering
? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE
:
1175 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
;
1178 if (!chip
->info
->max_vid
)
1181 mutex_lock(&chip
->reg_lock
);
1182 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
, mode
);
1183 mutex_unlock(&chip
->reg_lock
);
1189 mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1190 const struct switchdev_obj_port_vlan
*vlan
)
1192 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1195 if (!chip
->info
->max_vid
)
1198 /* If the requested port doesn't belong to the same bridge as the VLAN
1199 * members, do not support it (yet) and fallback to software VLAN.
1201 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1206 /* We don't need any dynamic resource from the kernel (yet),
1207 * so skip the prepare phase.
1212 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip
*chip
, int port
,
1213 const unsigned char *addr
, u16 vid
,
1216 struct mv88e6xxx_vtu_entry vlan
;
1217 struct mv88e6xxx_atu_entry entry
;
1220 /* Null VLAN ID corresponds to the port private database */
1222 err
= mv88e6xxx_port_get_fid(chip
, port
, &vlan
.fid
);
1224 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1228 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1229 ether_addr_copy(entry
.mac
, addr
);
1230 eth_addr_dec(entry
.mac
);
1232 err
= mv88e6xxx_g1_atu_getnext(chip
, vlan
.fid
, &entry
);
1236 /* Initialize a fresh ATU entry if it isn't found */
1237 if (entry
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
||
1238 !ether_addr_equal(entry
.mac
, addr
)) {
1239 memset(&entry
, 0, sizeof(entry
));
1240 ether_addr_copy(entry
.mac
, addr
);
1243 /* Purge the ATU entry only if no port is using it anymore */
1244 if (state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
) {
1245 entry
.portvec
&= ~BIT(port
);
1247 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1249 entry
.portvec
|= BIT(port
);
1250 entry
.state
= state
;
1253 return mv88e6xxx_g1_atu_loadpurge(chip
, vlan
.fid
, &entry
);
1256 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip
*chip
, int port
,
1259 const char broadcast
[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1260 u8 state
= MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
;
1262 return mv88e6xxx_port_db_load_purge(chip
, port
, broadcast
, vid
, state
);
1265 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip
*chip
, u16 vid
)
1270 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
1271 err
= mv88e6xxx_port_add_broadcast(chip
, port
, vid
);
1279 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip
*chip
, int port
,
1282 struct mv88e6xxx_vtu_entry vlan
;
1285 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, true);
1289 vlan
.member
[port
] = member
;
1291 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1295 return mv88e6xxx_broadcast_setup(chip
, vid
);
1298 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1299 const struct switchdev_obj_port_vlan
*vlan
)
1301 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1302 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1303 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1307 if (!chip
->info
->max_vid
)
1310 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1311 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED
;
1313 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED
;
1315 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED
;
1317 mutex_lock(&chip
->reg_lock
);
1319 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
1320 if (_mv88e6xxx_port_vlan_add(chip
, port
, vid
, member
))
1321 dev_err(ds
->dev
, "p%d: failed to add VLAN %d%c\n", port
,
1322 vid
, untagged
? 'u' : 't');
1324 if (pvid
&& mv88e6xxx_port_set_pvid(chip
, port
, vlan
->vid_end
))
1325 dev_err(ds
->dev
, "p%d: failed to set PVID %d\n", port
,
1328 mutex_unlock(&chip
->reg_lock
);
1331 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip
*chip
,
1334 struct mv88e6xxx_vtu_entry vlan
;
1337 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1341 /* Tell switchdev if this VLAN is handled in software */
1342 if (vlan
.member
[port
] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1345 vlan
.member
[port
] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1347 /* keep the VLAN unless all ports are excluded */
1349 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1350 if (vlan
.member
[i
] !=
1351 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
1357 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1361 return mv88e6xxx_g1_atu_remove(chip
, vlan
.fid
, port
, false);
1364 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
1365 const struct switchdev_obj_port_vlan
*vlan
)
1367 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1371 if (!chip
->info
->max_vid
)
1374 mutex_lock(&chip
->reg_lock
);
1376 err
= mv88e6xxx_port_get_pvid(chip
, port
, &pvid
);
1380 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1381 err
= _mv88e6xxx_port_vlan_del(chip
, port
, vid
);
1386 err
= mv88e6xxx_port_set_pvid(chip
, port
, 0);
1393 mutex_unlock(&chip
->reg_lock
);
1398 static int mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1399 const unsigned char *addr
, u16 vid
)
1401 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1404 mutex_lock(&chip
->reg_lock
);
1405 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1406 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1407 mutex_unlock(&chip
->reg_lock
);
1412 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1413 const unsigned char *addr
, u16 vid
)
1415 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1418 mutex_lock(&chip
->reg_lock
);
1419 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1420 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
1421 mutex_unlock(&chip
->reg_lock
);
1426 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip
*chip
,
1427 u16 fid
, u16 vid
, int port
,
1428 dsa_fdb_dump_cb_t
*cb
, void *data
)
1430 struct mv88e6xxx_atu_entry addr
;
1434 addr
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1435 eth_broadcast_addr(addr
.mac
);
1438 err
= mv88e6xxx_g1_atu_getnext(chip
, fid
, &addr
);
1442 if (addr
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
)
1445 if (addr
.trunk
|| (addr
.portvec
& BIT(port
)) == 0)
1448 if (!is_unicast_ether_addr(addr
.mac
))
1451 is_static
= (addr
.state
==
1452 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1453 err
= cb(addr
.mac
, vid
, is_static
, data
);
1456 } while (!is_broadcast_ether_addr(addr
.mac
));
1461 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip
*chip
, int port
,
1462 dsa_fdb_dump_cb_t
*cb
, void *data
)
1464 struct mv88e6xxx_vtu_entry vlan
= {
1465 .vid
= chip
->info
->max_vid
,
1470 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1471 err
= mv88e6xxx_port_get_fid(chip
, port
, &fid
);
1475 err
= mv88e6xxx_port_db_dump_fid(chip
, fid
, 0, port
, cb
, data
);
1479 /* Dump VLANs' Filtering Information Databases */
1481 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1488 err
= mv88e6xxx_port_db_dump_fid(chip
, vlan
.fid
, vlan
.vid
, port
,
1492 } while (vlan
.vid
< chip
->info
->max_vid
);
1497 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1498 dsa_fdb_dump_cb_t
*cb
, void *data
)
1500 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1503 mutex_lock(&chip
->reg_lock
);
1504 err
= mv88e6xxx_port_db_dump(chip
, port
, cb
, data
);
1505 mutex_unlock(&chip
->reg_lock
);
1510 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip
*chip
,
1511 struct net_device
*br
)
1513 struct dsa_switch
*ds
;
1518 /* Remap the Port VLAN of each local bridge group member */
1519 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); ++port
) {
1520 if (chip
->ds
->ports
[port
].bridge_dev
== br
) {
1521 err
= mv88e6xxx_port_vlan_map(chip
, port
);
1527 if (!mv88e6xxx_has_pvt(chip
))
1530 /* Remap the Port VLAN of each cross-chip bridge group member */
1531 for (dev
= 0; dev
< DSA_MAX_SWITCHES
; ++dev
) {
1532 ds
= chip
->ds
->dst
->ds
[dev
];
1536 for (port
= 0; port
< ds
->num_ports
; ++port
) {
1537 if (ds
->ports
[port
].bridge_dev
== br
) {
1538 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1548 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1549 struct net_device
*br
)
1551 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1554 mutex_lock(&chip
->reg_lock
);
1555 err
= mv88e6xxx_bridge_map(chip
, br
);
1556 mutex_unlock(&chip
->reg_lock
);
1561 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1562 struct net_device
*br
)
1564 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1566 mutex_lock(&chip
->reg_lock
);
1567 if (mv88e6xxx_bridge_map(chip
, br
) ||
1568 mv88e6xxx_port_vlan_map(chip
, port
))
1569 dev_err(ds
->dev
, "failed to remap in-chip Port VLAN\n");
1570 mutex_unlock(&chip
->reg_lock
);
1573 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch
*ds
, int dev
,
1574 int port
, struct net_device
*br
)
1576 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1579 if (!mv88e6xxx_has_pvt(chip
))
1582 mutex_lock(&chip
->reg_lock
);
1583 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1584 mutex_unlock(&chip
->reg_lock
);
1589 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch
*ds
, int dev
,
1590 int port
, struct net_device
*br
)
1592 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1594 if (!mv88e6xxx_has_pvt(chip
))
1597 mutex_lock(&chip
->reg_lock
);
1598 if (mv88e6xxx_pvt_map(chip
, dev
, port
))
1599 dev_err(ds
->dev
, "failed to remap cross-chip Port VLAN\n");
1600 mutex_unlock(&chip
->reg_lock
);
1603 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip
*chip
)
1605 if (chip
->info
->ops
->reset
)
1606 return chip
->info
->ops
->reset(chip
);
1611 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip
*chip
)
1613 struct gpio_desc
*gpiod
= chip
->reset
;
1615 /* If there is a GPIO connected to the reset pin, toggle it */
1617 gpiod_set_value_cansleep(gpiod
, 1);
1618 usleep_range(10000, 20000);
1619 gpiod_set_value_cansleep(gpiod
, 0);
1620 usleep_range(10000, 20000);
1624 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip
*chip
)
1628 /* Set all ports to the Disabled state */
1629 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
1630 err
= mv88e6xxx_port_set_state(chip
, i
, BR_STATE_DISABLED
);
1635 /* Wait for transmit queues to drain,
1636 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1638 usleep_range(2000, 4000);
1643 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip
*chip
)
1647 err
= mv88e6xxx_disable_ports(chip
);
1651 mv88e6xxx_hardware_reset(chip
);
1653 return mv88e6xxx_software_reset(chip
);
1656 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip
*chip
, int port
,
1657 enum mv88e6xxx_frame_mode frame
,
1658 enum mv88e6xxx_egress_mode egress
, u16 etype
)
1662 if (!chip
->info
->ops
->port_set_frame_mode
)
1665 err
= mv88e6xxx_port_set_egress_mode(chip
, port
, egress
);
1669 err
= chip
->info
->ops
->port_set_frame_mode(chip
, port
, frame
);
1673 if (chip
->info
->ops
->port_set_ether_type
)
1674 return chip
->info
->ops
->port_set_ether_type(chip
, port
, etype
);
1679 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip
*chip
, int port
)
1681 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_NORMAL
,
1682 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1683 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1686 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip
*chip
, int port
)
1688 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_DSA
,
1689 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1690 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1693 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip
*chip
, int port
)
1695 return mv88e6xxx_set_port_mode(chip
, port
,
1696 MV88E6XXX_FRAME_MODE_ETHERTYPE
,
1697 MV88E6XXX_EGRESS_MODE_ETHERTYPE
,
1701 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip
*chip
, int port
)
1703 if (dsa_is_dsa_port(chip
->ds
, port
))
1704 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1706 if (dsa_is_user_port(chip
->ds
, port
))
1707 return mv88e6xxx_set_port_mode_normal(chip
, port
);
1709 /* Setup CPU port mode depending on its supported tag format */
1710 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_DSA
)
1711 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1713 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
1714 return mv88e6xxx_set_port_mode_edsa(chip
, port
);
1719 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip
*chip
, int port
)
1721 bool message
= dsa_is_dsa_port(chip
->ds
, port
);
1723 return mv88e6xxx_port_set_message_port(chip
, port
, message
);
1726 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip
*chip
, int port
)
1728 struct dsa_switch
*ds
= chip
->ds
;
1731 /* Upstream ports flood frames with unknown unicast or multicast DA */
1732 flood
= dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
);
1733 if (chip
->info
->ops
->port_set_egress_floods
)
1734 return chip
->info
->ops
->port_set_egress_floods(chip
, port
,
1740 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip
*chip
, int port
,
1743 if (chip
->info
->ops
->serdes_power
)
1744 return chip
->info
->ops
->serdes_power(chip
, port
, on
);
1749 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip
*chip
, int port
)
1751 struct dsa_switch
*ds
= chip
->ds
;
1755 upstream_port
= dsa_upstream_port(ds
, port
);
1756 if (chip
->info
->ops
->port_set_upstream_port
) {
1757 err
= chip
->info
->ops
->port_set_upstream_port(chip
, port
,
1763 if (port
== upstream_port
) {
1764 if (chip
->info
->ops
->set_cpu_port
) {
1765 err
= chip
->info
->ops
->set_cpu_port(chip
,
1771 if (chip
->info
->ops
->set_egress_port
) {
1772 err
= chip
->info
->ops
->set_egress_port(chip
,
1782 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip
, int port
)
1784 struct dsa_switch
*ds
= chip
->ds
;
1788 /* MAC Forcing register: don't force link, speed, duplex or flow control
1789 * state to any particular values on physical ports, but force the CPU
1790 * port and all DSA ports to their maximum bandwidth and full duplex.
1792 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1793 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_FORCED_UP
,
1794 SPEED_MAX
, DUPLEX_FULL
,
1795 PHY_INTERFACE_MODE_NA
);
1797 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_UNFORCED
,
1798 SPEED_UNFORCED
, DUPLEX_UNFORCED
,
1799 PHY_INTERFACE_MODE_NA
);
1803 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1804 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1805 * tunneling, determine priority by looking at 802.1p and IP
1806 * priority fields (IP prio has precedence), and set STP state
1809 * If this is the CPU link, use DSA or EDSA tagging depending
1810 * on which tagging mode was configured.
1812 * If this is a link to another switch, use DSA tagging mode.
1814 * If this is the upstream port for this switch, enable
1815 * forwarding of unknown unicasts and multicasts.
1817 reg
= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP
|
1818 MV88E6185_PORT_CTL0_USE_TAG
| MV88E6185_PORT_CTL0_USE_IP
|
1819 MV88E6XXX_PORT_CTL0_STATE_FORWARDING
;
1820 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
1824 err
= mv88e6xxx_setup_port_mode(chip
, port
);
1828 err
= mv88e6xxx_setup_egress_floods(chip
, port
);
1832 /* Enable the SERDES interface for DSA and CPU ports. Normal
1833 * ports SERDES are enabled when the port is enabled, thus
1834 * saving a bit of power.
1836 if ((dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))) {
1837 err
= mv88e6xxx_serdes_power(chip
, port
, true);
1842 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1843 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1844 * untagged frames on this port, do a destination address lookup on all
1845 * received packets as usual, disable ARP mirroring and don't send a
1846 * copy of all transmitted/received frames on this port to the CPU.
1848 err
= mv88e6xxx_port_set_map_da(chip
, port
);
1852 err
= mv88e6xxx_setup_upstream_port(chip
, port
);
1856 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
,
1857 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
);
1861 if (chip
->info
->ops
->port_set_jumbo_size
) {
1862 err
= chip
->info
->ops
->port_set_jumbo_size(chip
, port
, 10240);
1867 /* Port Association Vector: when learning source addresses
1868 * of packets, add the address to the address database using
1869 * a port bitmap that has only the bit for this port set and
1870 * the other bits clear.
1873 /* Disable learning for CPU port */
1874 if (dsa_is_cpu_port(ds
, port
))
1877 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_ASSOC_VECTOR
,
1882 /* Egress rate control 2: disable egress rate control. */
1883 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_EGRESS_RATE_CTL2
,
1888 if (chip
->info
->ops
->port_pause_limit
) {
1889 err
= chip
->info
->ops
->port_pause_limit(chip
, port
, 0, 0);
1894 if (chip
->info
->ops
->port_disable_learn_limit
) {
1895 err
= chip
->info
->ops
->port_disable_learn_limit(chip
, port
);
1900 if (chip
->info
->ops
->port_disable_pri_override
) {
1901 err
= chip
->info
->ops
->port_disable_pri_override(chip
, port
);
1906 if (chip
->info
->ops
->port_tag_remap
) {
1907 err
= chip
->info
->ops
->port_tag_remap(chip
, port
);
1912 if (chip
->info
->ops
->port_egress_rate_limiting
) {
1913 err
= chip
->info
->ops
->port_egress_rate_limiting(chip
, port
);
1918 err
= mv88e6xxx_setup_message_port(chip
, port
);
1922 /* Port based VLAN map: give each port the same default address
1923 * database, and allow bidirectional communication between the
1924 * CPU and DSA port(s), and the other ports.
1926 err
= mv88e6xxx_port_set_fid(chip
, port
, 0);
1930 err
= mv88e6xxx_port_vlan_map(chip
, port
);
1934 /* Default VLAN ID and priority: don't set a default VLAN
1935 * ID, and set the default packet priority to zero.
1937 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
, 0);
1940 static int mv88e6xxx_port_enable(struct dsa_switch
*ds
, int port
,
1941 struct phy_device
*phydev
)
1943 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1946 mutex_lock(&chip
->reg_lock
);
1947 err
= mv88e6xxx_serdes_power(chip
, port
, true);
1948 mutex_unlock(&chip
->reg_lock
);
1953 static void mv88e6xxx_port_disable(struct dsa_switch
*ds
, int port
,
1954 struct phy_device
*phydev
)
1956 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1958 mutex_lock(&chip
->reg_lock
);
1959 if (mv88e6xxx_serdes_power(chip
, port
, false))
1960 dev_err(chip
->dev
, "failed to power off SERDES\n");
1961 mutex_unlock(&chip
->reg_lock
);
1964 static int mv88e6xxx_set_ageing_time(struct dsa_switch
*ds
,
1965 unsigned int ageing_time
)
1967 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1970 mutex_lock(&chip
->reg_lock
);
1971 err
= mv88e6xxx_g1_atu_set_age_time(chip
, ageing_time
);
1972 mutex_unlock(&chip
->reg_lock
);
1977 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip
*chip
)
1979 struct dsa_switch
*ds
= chip
->ds
;
1982 /* Disable remote management, and set the switch's DSA device number. */
1983 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL2
,
1984 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE
|
1985 (ds
->index
& 0x1f));
1989 /* Configure the IP ToS mapping registers. */
1990 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_0
, 0x0000);
1993 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_1
, 0x0000);
1996 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_2
, 0x5555);
1999 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_3
, 0x5555);
2002 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_4
, 0xaaaa);
2005 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_5
, 0xaaaa);
2008 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_6
, 0xffff);
2011 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_7
, 0xffff);
2015 /* Configure the IEEE 802.1p priority mapping register. */
2016 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IEEE_PRI
, 0xfa41);
2020 /* Initialize the statistics unit */
2021 err
= mv88e6xxx_stats_set_histogram(chip
);
2025 return mv88e6xxx_g1_stats_clear(chip
);
2028 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
2030 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2035 ds
->slave_mii_bus
= mv88e6xxx_default_mdio_bus(chip
);
2037 mutex_lock(&chip
->reg_lock
);
2039 /* Setup Switch Port Registers */
2040 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
2041 if (dsa_is_unused_port(ds
, i
))
2044 err
= mv88e6xxx_setup_port(chip
, i
);
2049 /* Setup Switch Global 1 Registers */
2050 err
= mv88e6xxx_g1_setup(chip
);
2054 /* Setup Switch Global 2 Registers */
2055 if (chip
->info
->global2_addr
) {
2056 err
= mv88e6xxx_g2_setup(chip
);
2061 err
= mv88e6xxx_irl_setup(chip
);
2065 err
= mv88e6xxx_mac_setup(chip
);
2069 err
= mv88e6xxx_phy_setup(chip
);
2073 err
= mv88e6xxx_vtu_setup(chip
);
2077 err
= mv88e6xxx_pvt_setup(chip
);
2081 err
= mv88e6xxx_atu_setup(chip
);
2085 err
= mv88e6xxx_broadcast_setup(chip
, 0);
2089 err
= mv88e6xxx_pot_setup(chip
);
2093 err
= mv88e6xxx_rsvd2cpu_setup(chip
);
2097 /* Setup PTP Hardware Clock and timestamping */
2098 if (chip
->info
->ptp_support
) {
2099 err
= mv88e6xxx_ptp_setup(chip
);
2103 err
= mv88e6xxx_hwtstamp_setup(chip
);
2109 mutex_unlock(&chip
->reg_lock
);
2114 static int mv88e6xxx_mdio_read(struct mii_bus
*bus
, int phy
, int reg
)
2116 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2117 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2121 if (!chip
->info
->ops
->phy_read
)
2124 mutex_lock(&chip
->reg_lock
);
2125 err
= chip
->info
->ops
->phy_read(chip
, bus
, phy
, reg
, &val
);
2126 mutex_unlock(&chip
->reg_lock
);
2128 if (reg
== MII_PHYSID2
) {
2129 /* Some internal PHYS don't have a model number. Use
2130 * the mv88e6390 family model number instead.
2133 val
|= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
>> 4;
2136 return err
? err
: val
;
2139 static int mv88e6xxx_mdio_write(struct mii_bus
*bus
, int phy
, int reg
, u16 val
)
2141 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2142 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2145 if (!chip
->info
->ops
->phy_write
)
2148 mutex_lock(&chip
->reg_lock
);
2149 err
= chip
->info
->ops
->phy_write(chip
, bus
, phy
, reg
, val
);
2150 mutex_unlock(&chip
->reg_lock
);
2155 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip
*chip
,
2156 struct device_node
*np
,
2160 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2161 struct mii_bus
*bus
;
2164 bus
= devm_mdiobus_alloc_size(chip
->dev
, sizeof(*mdio_bus
));
2168 mdio_bus
= bus
->priv
;
2169 mdio_bus
->bus
= bus
;
2170 mdio_bus
->chip
= chip
;
2171 INIT_LIST_HEAD(&mdio_bus
->list
);
2172 mdio_bus
->external
= external
;
2175 bus
->name
= np
->full_name
;
2176 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%pOF", np
);
2178 bus
->name
= "mv88e6xxx SMI";
2179 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "mv88e6xxx-%d", index
++);
2182 bus
->read
= mv88e6xxx_mdio_read
;
2183 bus
->write
= mv88e6xxx_mdio_write
;
2184 bus
->parent
= chip
->dev
;
2187 err
= of_mdiobus_register(bus
, np
);
2189 err
= mdiobus_register(bus
);
2191 dev_err(chip
->dev
, "Cannot register MDIO bus (%d)\n", err
);
2196 list_add_tail(&mdio_bus
->list
, &chip
->mdios
);
2198 list_add(&mdio_bus
->list
, &chip
->mdios
);
2203 static const struct of_device_id mv88e6xxx_mdio_external_match
[] = {
2204 { .compatible
= "marvell,mv88e6xxx-mdio-external",
2205 .data
= (void *)true },
2209 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip
*chip
)
2212 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2213 struct mii_bus
*bus
;
2215 list_for_each_entry(mdio_bus
, &chip
->mdios
, list
) {
2216 bus
= mdio_bus
->bus
;
2218 mdiobus_unregister(bus
);
2222 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip
*chip
,
2223 struct device_node
*np
)
2225 const struct of_device_id
*match
;
2226 struct device_node
*child
;
2229 /* Always register one mdio bus for the internal/default mdio
2230 * bus. This maybe represented in the device tree, but is
2233 child
= of_get_child_by_name(np
, "mdio");
2234 err
= mv88e6xxx_mdio_register(chip
, child
, false);
2238 /* Walk the device tree, and see if there are any other nodes
2239 * which say they are compatible with the external mdio
2242 for_each_available_child_of_node(np
, child
) {
2243 match
= of_match_node(mv88e6xxx_mdio_external_match
, child
);
2245 err
= mv88e6xxx_mdio_register(chip
, child
, true);
2247 mv88e6xxx_mdios_unregister(chip
);
2256 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
2258 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2260 return chip
->eeprom_len
;
2263 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
2264 struct ethtool_eeprom
*eeprom
, u8
*data
)
2266 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2269 if (!chip
->info
->ops
->get_eeprom
)
2272 mutex_lock(&chip
->reg_lock
);
2273 err
= chip
->info
->ops
->get_eeprom(chip
, eeprom
, data
);
2274 mutex_unlock(&chip
->reg_lock
);
2279 eeprom
->magic
= 0xc3ec4951;
2284 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
2285 struct ethtool_eeprom
*eeprom
, u8
*data
)
2287 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2290 if (!chip
->info
->ops
->set_eeprom
)
2293 if (eeprom
->magic
!= 0xc3ec4951)
2296 mutex_lock(&chip
->reg_lock
);
2297 err
= chip
->info
->ops
->set_eeprom(chip
, eeprom
, data
);
2298 mutex_unlock(&chip
->reg_lock
);
2303 static const struct mv88e6xxx_ops mv88e6085_ops
= {
2304 /* MV88E6XXX_FAMILY_6097 */
2305 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2306 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2307 .phy_read
= mv88e6185_phy_ppu_read
,
2308 .phy_write
= mv88e6185_phy_ppu_write
,
2309 .port_set_link
= mv88e6xxx_port_set_link
,
2310 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2311 .port_set_speed
= mv88e6185_port_set_speed
,
2312 .port_tag_remap
= mv88e6095_port_tag_remap
,
2313 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2314 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2315 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2316 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2317 .port_pause_limit
= mv88e6097_port_pause_limit
,
2318 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2319 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2320 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2321 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2322 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2323 .stats_get_strings
= mv88e6095_stats_get_strings
,
2324 .stats_get_stats
= mv88e6095_stats_get_stats
,
2325 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2326 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2327 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2328 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2329 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2330 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2331 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2332 .reset
= mv88e6185_g1_reset
,
2333 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2334 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2337 static const struct mv88e6xxx_ops mv88e6095_ops
= {
2338 /* MV88E6XXX_FAMILY_6095 */
2339 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2340 .phy_read
= mv88e6185_phy_ppu_read
,
2341 .phy_write
= mv88e6185_phy_ppu_write
,
2342 .port_set_link
= mv88e6xxx_port_set_link
,
2343 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2344 .port_set_speed
= mv88e6185_port_set_speed
,
2345 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2346 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2347 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2348 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2349 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2350 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2351 .stats_get_strings
= mv88e6095_stats_get_strings
,
2352 .stats_get_stats
= mv88e6095_stats_get_stats
,
2353 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2354 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2355 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2356 .reset
= mv88e6185_g1_reset
,
2357 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2358 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2361 static const struct mv88e6xxx_ops mv88e6097_ops
= {
2362 /* MV88E6XXX_FAMILY_6097 */
2363 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2364 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2365 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2366 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2367 .port_set_link
= mv88e6xxx_port_set_link
,
2368 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2369 .port_set_speed
= mv88e6185_port_set_speed
,
2370 .port_tag_remap
= mv88e6095_port_tag_remap
,
2371 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2372 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2373 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2374 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2375 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2376 .port_pause_limit
= mv88e6097_port_pause_limit
,
2377 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2378 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2379 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2380 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2381 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2382 .stats_get_strings
= mv88e6095_stats_get_strings
,
2383 .stats_get_stats
= mv88e6095_stats_get_stats
,
2384 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2385 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2386 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2387 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2388 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2389 .reset
= mv88e6352_g1_reset
,
2390 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2391 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2394 static const struct mv88e6xxx_ops mv88e6123_ops
= {
2395 /* MV88E6XXX_FAMILY_6165 */
2396 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2397 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2398 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2399 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2400 .port_set_link
= mv88e6xxx_port_set_link
,
2401 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2402 .port_set_speed
= mv88e6185_port_set_speed
,
2403 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2404 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2405 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2406 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2407 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2408 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2409 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2410 .stats_get_strings
= mv88e6095_stats_get_strings
,
2411 .stats_get_stats
= mv88e6095_stats_get_stats
,
2412 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2413 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2414 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2415 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2416 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2417 .reset
= mv88e6352_g1_reset
,
2418 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2419 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2422 static const struct mv88e6xxx_ops mv88e6131_ops
= {
2423 /* MV88E6XXX_FAMILY_6185 */
2424 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2425 .phy_read
= mv88e6185_phy_ppu_read
,
2426 .phy_write
= mv88e6185_phy_ppu_write
,
2427 .port_set_link
= mv88e6xxx_port_set_link
,
2428 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2429 .port_set_speed
= mv88e6185_port_set_speed
,
2430 .port_tag_remap
= mv88e6095_port_tag_remap
,
2431 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2432 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2433 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2434 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2435 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2436 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2437 .port_pause_limit
= mv88e6097_port_pause_limit
,
2438 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2439 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2440 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2441 .stats_get_strings
= mv88e6095_stats_get_strings
,
2442 .stats_get_stats
= mv88e6095_stats_get_stats
,
2443 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2444 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2445 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2446 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2447 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2448 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2449 .reset
= mv88e6185_g1_reset
,
2450 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2451 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2454 static const struct mv88e6xxx_ops mv88e6141_ops
= {
2455 /* MV88E6XXX_FAMILY_6341 */
2456 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2457 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2458 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2459 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2460 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2461 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2462 .port_set_link
= mv88e6xxx_port_set_link
,
2463 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2464 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2465 .port_set_speed
= mv88e6390_port_set_speed
,
2466 .port_tag_remap
= mv88e6095_port_tag_remap
,
2467 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2468 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2469 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2470 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2471 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2472 .port_pause_limit
= mv88e6097_port_pause_limit
,
2473 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2474 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2475 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2476 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2477 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2478 .stats_get_strings
= mv88e6320_stats_get_strings
,
2479 .stats_get_stats
= mv88e6390_stats_get_stats
,
2480 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2481 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2482 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2483 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2484 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2485 .reset
= mv88e6352_g1_reset
,
2486 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2487 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2488 .gpio_ops
= &mv88e6352_gpio_ops
,
2491 static const struct mv88e6xxx_ops mv88e6161_ops
= {
2492 /* MV88E6XXX_FAMILY_6165 */
2493 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2494 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2495 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2496 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2497 .port_set_link
= mv88e6xxx_port_set_link
,
2498 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2499 .port_set_speed
= mv88e6185_port_set_speed
,
2500 .port_tag_remap
= mv88e6095_port_tag_remap
,
2501 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2502 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2503 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2504 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2505 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2506 .port_pause_limit
= mv88e6097_port_pause_limit
,
2507 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2508 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2509 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2510 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2511 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2512 .stats_get_strings
= mv88e6095_stats_get_strings
,
2513 .stats_get_stats
= mv88e6095_stats_get_stats
,
2514 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2515 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2516 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2517 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2518 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2519 .reset
= mv88e6352_g1_reset
,
2520 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2521 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2524 static const struct mv88e6xxx_ops mv88e6165_ops
= {
2525 /* MV88E6XXX_FAMILY_6165 */
2526 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2527 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2528 .phy_read
= mv88e6165_phy_read
,
2529 .phy_write
= mv88e6165_phy_write
,
2530 .port_set_link
= mv88e6xxx_port_set_link
,
2531 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2532 .port_set_speed
= mv88e6185_port_set_speed
,
2533 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2534 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2535 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2536 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2537 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2538 .stats_get_strings
= mv88e6095_stats_get_strings
,
2539 .stats_get_stats
= mv88e6095_stats_get_stats
,
2540 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2541 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2542 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2543 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2544 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2545 .reset
= mv88e6352_g1_reset
,
2546 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2547 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2550 static const struct mv88e6xxx_ops mv88e6171_ops
= {
2551 /* MV88E6XXX_FAMILY_6351 */
2552 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2553 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2554 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2555 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2556 .port_set_link
= mv88e6xxx_port_set_link
,
2557 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2558 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2559 .port_set_speed
= mv88e6185_port_set_speed
,
2560 .port_tag_remap
= mv88e6095_port_tag_remap
,
2561 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2562 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2563 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2564 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2565 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2566 .port_pause_limit
= mv88e6097_port_pause_limit
,
2567 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2568 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2569 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2570 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2571 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2572 .stats_get_strings
= mv88e6095_stats_get_strings
,
2573 .stats_get_stats
= mv88e6095_stats_get_stats
,
2574 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2575 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2576 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2577 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2578 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2579 .reset
= mv88e6352_g1_reset
,
2580 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2581 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2584 static const struct mv88e6xxx_ops mv88e6172_ops
= {
2585 /* MV88E6XXX_FAMILY_6352 */
2586 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2587 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2588 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2589 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2590 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2591 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2592 .port_set_link
= mv88e6xxx_port_set_link
,
2593 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2594 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2595 .port_set_speed
= mv88e6352_port_set_speed
,
2596 .port_tag_remap
= mv88e6095_port_tag_remap
,
2597 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2598 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2599 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2600 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2601 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2602 .port_pause_limit
= mv88e6097_port_pause_limit
,
2603 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2604 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2605 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2606 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2607 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2608 .stats_get_strings
= mv88e6095_stats_get_strings
,
2609 .stats_get_stats
= mv88e6095_stats_get_stats
,
2610 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2611 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2612 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2613 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2614 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2615 .reset
= mv88e6352_g1_reset
,
2616 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2617 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2618 .serdes_power
= mv88e6352_serdes_power
,
2619 .gpio_ops
= &mv88e6352_gpio_ops
,
2622 static const struct mv88e6xxx_ops mv88e6175_ops
= {
2623 /* MV88E6XXX_FAMILY_6351 */
2624 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2625 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2626 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2627 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2628 .port_set_link
= mv88e6xxx_port_set_link
,
2629 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2630 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2631 .port_set_speed
= mv88e6185_port_set_speed
,
2632 .port_tag_remap
= mv88e6095_port_tag_remap
,
2633 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2634 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2635 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2636 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2637 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2638 .port_pause_limit
= mv88e6097_port_pause_limit
,
2639 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2640 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2641 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2642 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2643 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2644 .stats_get_strings
= mv88e6095_stats_get_strings
,
2645 .stats_get_stats
= mv88e6095_stats_get_stats
,
2646 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2647 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2648 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2649 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2650 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2651 .reset
= mv88e6352_g1_reset
,
2652 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2653 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2656 static const struct mv88e6xxx_ops mv88e6176_ops
= {
2657 /* MV88E6XXX_FAMILY_6352 */
2658 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2659 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2660 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2661 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2662 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2663 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2664 .port_set_link
= mv88e6xxx_port_set_link
,
2665 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2666 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2667 .port_set_speed
= mv88e6352_port_set_speed
,
2668 .port_tag_remap
= mv88e6095_port_tag_remap
,
2669 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2670 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2671 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2672 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2673 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2674 .port_pause_limit
= mv88e6097_port_pause_limit
,
2675 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2676 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2677 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2678 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2679 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2680 .stats_get_strings
= mv88e6095_stats_get_strings
,
2681 .stats_get_stats
= mv88e6095_stats_get_stats
,
2682 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2683 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2684 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2685 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2686 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2687 .reset
= mv88e6352_g1_reset
,
2688 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2689 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2690 .serdes_power
= mv88e6352_serdes_power
,
2691 .gpio_ops
= &mv88e6352_gpio_ops
,
2694 static const struct mv88e6xxx_ops mv88e6185_ops
= {
2695 /* MV88E6XXX_FAMILY_6185 */
2696 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2697 .phy_read
= mv88e6185_phy_ppu_read
,
2698 .phy_write
= mv88e6185_phy_ppu_write
,
2699 .port_set_link
= mv88e6xxx_port_set_link
,
2700 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2701 .port_set_speed
= mv88e6185_port_set_speed
,
2702 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2703 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2704 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2705 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2706 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2707 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2708 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2709 .stats_get_strings
= mv88e6095_stats_get_strings
,
2710 .stats_get_stats
= mv88e6095_stats_get_stats
,
2711 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2712 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2713 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2714 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2715 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2716 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2717 .reset
= mv88e6185_g1_reset
,
2718 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2719 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2722 static const struct mv88e6xxx_ops mv88e6190_ops
= {
2723 /* MV88E6XXX_FAMILY_6390 */
2724 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2725 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2726 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2727 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2728 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2729 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2730 .port_set_link
= mv88e6xxx_port_set_link
,
2731 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2732 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2733 .port_set_speed
= mv88e6390_port_set_speed
,
2734 .port_tag_remap
= mv88e6390_port_tag_remap
,
2735 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2736 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2737 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2738 .port_pause_limit
= mv88e6390_port_pause_limit
,
2739 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2740 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2741 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2742 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2743 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2744 .stats_get_strings
= mv88e6320_stats_get_strings
,
2745 .stats_get_stats
= mv88e6390_stats_get_stats
,
2746 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2747 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2748 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2749 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2750 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2751 .reset
= mv88e6352_g1_reset
,
2752 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2753 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2754 .serdes_power
= mv88e6390_serdes_power
,
2755 .gpio_ops
= &mv88e6352_gpio_ops
,
2758 static const struct mv88e6xxx_ops mv88e6190x_ops
= {
2759 /* MV88E6XXX_FAMILY_6390 */
2760 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2761 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2762 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2763 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2764 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2765 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2766 .port_set_link
= mv88e6xxx_port_set_link
,
2767 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2768 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2769 .port_set_speed
= mv88e6390x_port_set_speed
,
2770 .port_tag_remap
= mv88e6390_port_tag_remap
,
2771 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2772 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2773 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2774 .port_pause_limit
= mv88e6390_port_pause_limit
,
2775 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2776 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2777 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2778 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2779 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2780 .stats_get_strings
= mv88e6320_stats_get_strings
,
2781 .stats_get_stats
= mv88e6390_stats_get_stats
,
2782 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2783 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2784 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2785 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2786 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2787 .reset
= mv88e6352_g1_reset
,
2788 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2789 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2790 .serdes_power
= mv88e6390_serdes_power
,
2791 .gpio_ops
= &mv88e6352_gpio_ops
,
2794 static const struct mv88e6xxx_ops mv88e6191_ops
= {
2795 /* MV88E6XXX_FAMILY_6390 */
2796 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2797 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2798 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2799 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2800 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2801 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2802 .port_set_link
= mv88e6xxx_port_set_link
,
2803 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2804 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2805 .port_set_speed
= mv88e6390_port_set_speed
,
2806 .port_tag_remap
= mv88e6390_port_tag_remap
,
2807 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2808 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2809 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2810 .port_pause_limit
= mv88e6390_port_pause_limit
,
2811 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2812 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2813 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2814 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2815 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2816 .stats_get_strings
= mv88e6320_stats_get_strings
,
2817 .stats_get_stats
= mv88e6390_stats_get_stats
,
2818 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2819 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2820 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2821 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2822 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2823 .reset
= mv88e6352_g1_reset
,
2824 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2825 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2826 .serdes_power
= mv88e6390_serdes_power
,
2829 static const struct mv88e6xxx_ops mv88e6240_ops
= {
2830 /* MV88E6XXX_FAMILY_6352 */
2831 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2832 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2833 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2834 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2835 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2836 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2837 .port_set_link
= mv88e6xxx_port_set_link
,
2838 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2839 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2840 .port_set_speed
= mv88e6352_port_set_speed
,
2841 .port_tag_remap
= mv88e6095_port_tag_remap
,
2842 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2843 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2844 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2845 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2846 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2847 .port_pause_limit
= mv88e6097_port_pause_limit
,
2848 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2849 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2850 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2851 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2852 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2853 .stats_get_strings
= mv88e6095_stats_get_strings
,
2854 .stats_get_stats
= mv88e6095_stats_get_stats
,
2855 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2856 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2857 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2858 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2859 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2860 .reset
= mv88e6352_g1_reset
,
2861 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2862 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2863 .serdes_power
= mv88e6352_serdes_power
,
2864 .gpio_ops
= &mv88e6352_gpio_ops
,
2865 .avb_ops
= &mv88e6352_avb_ops
,
2868 static const struct mv88e6xxx_ops mv88e6290_ops
= {
2869 /* MV88E6XXX_FAMILY_6390 */
2870 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2871 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2872 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2873 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2874 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2875 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2876 .port_set_link
= mv88e6xxx_port_set_link
,
2877 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2878 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2879 .port_set_speed
= mv88e6390_port_set_speed
,
2880 .port_tag_remap
= mv88e6390_port_tag_remap
,
2881 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2882 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2883 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2884 .port_pause_limit
= mv88e6390_port_pause_limit
,
2885 .port_set_cmode
= mv88e6390x_port_set_cmode
,
2886 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2887 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2888 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2889 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2890 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2891 .stats_get_strings
= mv88e6320_stats_get_strings
,
2892 .stats_get_stats
= mv88e6390_stats_get_stats
,
2893 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2894 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2895 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2896 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2897 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2898 .reset
= mv88e6352_g1_reset
,
2899 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2900 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2901 .serdes_power
= mv88e6390_serdes_power
,
2902 .gpio_ops
= &mv88e6352_gpio_ops
,
2903 .avb_ops
= &mv88e6390_avb_ops
,
2906 static const struct mv88e6xxx_ops mv88e6320_ops
= {
2907 /* MV88E6XXX_FAMILY_6320 */
2908 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2909 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2910 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2911 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2912 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2913 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2914 .port_set_link
= mv88e6xxx_port_set_link
,
2915 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2916 .port_set_speed
= mv88e6185_port_set_speed
,
2917 .port_tag_remap
= mv88e6095_port_tag_remap
,
2918 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2919 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2920 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2921 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2922 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2923 .port_pause_limit
= mv88e6097_port_pause_limit
,
2924 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2925 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2926 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2927 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2928 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2929 .stats_get_strings
= mv88e6320_stats_get_strings
,
2930 .stats_get_stats
= mv88e6320_stats_get_stats
,
2931 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2932 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2933 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2934 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2935 .reset
= mv88e6352_g1_reset
,
2936 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2937 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2938 .gpio_ops
= &mv88e6352_gpio_ops
,
2939 .avb_ops
= &mv88e6352_avb_ops
,
2942 static const struct mv88e6xxx_ops mv88e6321_ops
= {
2943 /* MV88E6XXX_FAMILY_6320 */
2944 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2945 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2946 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2947 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2948 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2949 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2950 .port_set_link
= mv88e6xxx_port_set_link
,
2951 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2952 .port_set_speed
= mv88e6185_port_set_speed
,
2953 .port_tag_remap
= mv88e6095_port_tag_remap
,
2954 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2955 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2956 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2957 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2958 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2959 .port_pause_limit
= mv88e6097_port_pause_limit
,
2960 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2961 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2962 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2963 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2964 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2965 .stats_get_strings
= mv88e6320_stats_get_strings
,
2966 .stats_get_stats
= mv88e6320_stats_get_stats
,
2967 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2968 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2969 .reset
= mv88e6352_g1_reset
,
2970 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2971 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2972 .gpio_ops
= &mv88e6352_gpio_ops
,
2973 .avb_ops
= &mv88e6352_avb_ops
,
2976 static const struct mv88e6xxx_ops mv88e6341_ops
= {
2977 /* MV88E6XXX_FAMILY_6341 */
2978 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2979 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2980 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2981 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2982 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2983 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2984 .port_set_link
= mv88e6xxx_port_set_link
,
2985 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2986 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2987 .port_set_speed
= mv88e6390_port_set_speed
,
2988 .port_tag_remap
= mv88e6095_port_tag_remap
,
2989 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2990 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2991 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2992 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2993 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2994 .port_pause_limit
= mv88e6097_port_pause_limit
,
2995 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2996 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2997 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2998 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2999 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3000 .stats_get_strings
= mv88e6320_stats_get_strings
,
3001 .stats_get_stats
= mv88e6390_stats_get_stats
,
3002 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3003 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3004 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3005 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3006 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3007 .reset
= mv88e6352_g1_reset
,
3008 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3009 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3010 .gpio_ops
= &mv88e6352_gpio_ops
,
3011 .avb_ops
= &mv88e6390_avb_ops
,
3014 static const struct mv88e6xxx_ops mv88e6350_ops
= {
3015 /* MV88E6XXX_FAMILY_6351 */
3016 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3017 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3018 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3019 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3020 .port_set_link
= mv88e6xxx_port_set_link
,
3021 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3022 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3023 .port_set_speed
= mv88e6185_port_set_speed
,
3024 .port_tag_remap
= mv88e6095_port_tag_remap
,
3025 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3026 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3027 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3028 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3029 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3030 .port_pause_limit
= mv88e6097_port_pause_limit
,
3031 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3032 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3033 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3034 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3035 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3036 .stats_get_strings
= mv88e6095_stats_get_strings
,
3037 .stats_get_stats
= mv88e6095_stats_get_stats
,
3038 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3039 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3040 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3041 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3042 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3043 .reset
= mv88e6352_g1_reset
,
3044 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3045 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3048 static const struct mv88e6xxx_ops mv88e6351_ops
= {
3049 /* MV88E6XXX_FAMILY_6351 */
3050 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3051 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3052 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3053 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3054 .port_set_link
= mv88e6xxx_port_set_link
,
3055 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3056 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3057 .port_set_speed
= mv88e6185_port_set_speed
,
3058 .port_tag_remap
= mv88e6095_port_tag_remap
,
3059 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3060 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3061 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3062 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3063 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3064 .port_pause_limit
= mv88e6097_port_pause_limit
,
3065 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3066 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3067 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3068 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3069 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3070 .stats_get_strings
= mv88e6095_stats_get_strings
,
3071 .stats_get_stats
= mv88e6095_stats_get_stats
,
3072 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3073 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3074 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3075 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3076 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3077 .reset
= mv88e6352_g1_reset
,
3078 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3079 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3080 .avb_ops
= &mv88e6352_avb_ops
,
3083 static const struct mv88e6xxx_ops mv88e6352_ops
= {
3084 /* MV88E6XXX_FAMILY_6352 */
3085 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3086 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
3087 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
3088 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3089 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3090 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3091 .port_set_link
= mv88e6xxx_port_set_link
,
3092 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3093 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3094 .port_set_speed
= mv88e6352_port_set_speed
,
3095 .port_tag_remap
= mv88e6095_port_tag_remap
,
3096 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3097 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3098 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3099 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3100 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3101 .port_pause_limit
= mv88e6097_port_pause_limit
,
3102 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3103 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3104 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3105 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3106 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3107 .stats_get_strings
= mv88e6095_stats_get_strings
,
3108 .stats_get_stats
= mv88e6095_stats_get_stats
,
3109 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3110 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3111 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3112 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3113 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3114 .reset
= mv88e6352_g1_reset
,
3115 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3116 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3117 .serdes_power
= mv88e6352_serdes_power
,
3118 .gpio_ops
= &mv88e6352_gpio_ops
,
3119 .avb_ops
= &mv88e6352_avb_ops
,
3122 static const struct mv88e6xxx_ops mv88e6390_ops
= {
3123 /* MV88E6XXX_FAMILY_6390 */
3124 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3125 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3126 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3127 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3128 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3129 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3130 .port_set_link
= mv88e6xxx_port_set_link
,
3131 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3132 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3133 .port_set_speed
= mv88e6390_port_set_speed
,
3134 .port_tag_remap
= mv88e6390_port_tag_remap
,
3135 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3136 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3137 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3138 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3139 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3140 .port_pause_limit
= mv88e6390_port_pause_limit
,
3141 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3142 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3143 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3144 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3145 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3146 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3147 .stats_get_strings
= mv88e6320_stats_get_strings
,
3148 .stats_get_stats
= mv88e6390_stats_get_stats
,
3149 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3150 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3151 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3152 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3153 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3154 .reset
= mv88e6352_g1_reset
,
3155 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3156 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3157 .serdes_power
= mv88e6390_serdes_power
,
3158 .gpio_ops
= &mv88e6352_gpio_ops
,
3159 .avb_ops
= &mv88e6390_avb_ops
,
3162 static const struct mv88e6xxx_ops mv88e6390x_ops
= {
3163 /* MV88E6XXX_FAMILY_6390 */
3164 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3165 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3166 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3167 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3168 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3169 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3170 .port_set_link
= mv88e6xxx_port_set_link
,
3171 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3172 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3173 .port_set_speed
= mv88e6390x_port_set_speed
,
3174 .port_tag_remap
= mv88e6390_port_tag_remap
,
3175 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3176 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3177 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3178 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3179 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3180 .port_pause_limit
= mv88e6390_port_pause_limit
,
3181 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3182 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3183 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3184 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3185 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3186 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3187 .stats_get_strings
= mv88e6320_stats_get_strings
,
3188 .stats_get_stats
= mv88e6390_stats_get_stats
,
3189 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3190 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3191 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3192 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3193 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3194 .reset
= mv88e6352_g1_reset
,
3195 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3196 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3197 .serdes_power
= mv88e6390_serdes_power
,
3198 .gpio_ops
= &mv88e6352_gpio_ops
,
3199 .avb_ops
= &mv88e6390_avb_ops
,
3202 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3204 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6085
,
3205 .family
= MV88E6XXX_FAMILY_6097
,
3206 .name
= "Marvell 88E6085",
3207 .num_databases
= 4096,
3210 .port_base_addr
= 0x10,
3211 .global1_addr
= 0x1b,
3212 .global2_addr
= 0x1c,
3213 .age_time_coeff
= 15000,
3216 .atu_move_port_mask
= 0xf,
3219 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3220 .ops
= &mv88e6085_ops
,
3224 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6095
,
3225 .family
= MV88E6XXX_FAMILY_6095
,
3226 .name
= "Marvell 88E6095/88E6095F",
3227 .num_databases
= 256,
3230 .port_base_addr
= 0x10,
3231 .global1_addr
= 0x1b,
3232 .global2_addr
= 0x1c,
3233 .age_time_coeff
= 15000,
3235 .atu_move_port_mask
= 0xf,
3237 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3238 .ops
= &mv88e6095_ops
,
3242 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6097
,
3243 .family
= MV88E6XXX_FAMILY_6097
,
3244 .name
= "Marvell 88E6097/88E6097F",
3245 .num_databases
= 4096,
3248 .port_base_addr
= 0x10,
3249 .global1_addr
= 0x1b,
3250 .global2_addr
= 0x1c,
3251 .age_time_coeff
= 15000,
3254 .atu_move_port_mask
= 0xf,
3257 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3258 .ops
= &mv88e6097_ops
,
3262 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6123
,
3263 .family
= MV88E6XXX_FAMILY_6165
,
3264 .name
= "Marvell 88E6123",
3265 .num_databases
= 4096,
3268 .port_base_addr
= 0x10,
3269 .global1_addr
= 0x1b,
3270 .global2_addr
= 0x1c,
3271 .age_time_coeff
= 15000,
3274 .atu_move_port_mask
= 0xf,
3277 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3278 .ops
= &mv88e6123_ops
,
3282 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6131
,
3283 .family
= MV88E6XXX_FAMILY_6185
,
3284 .name
= "Marvell 88E6131",
3285 .num_databases
= 256,
3288 .port_base_addr
= 0x10,
3289 .global1_addr
= 0x1b,
3290 .global2_addr
= 0x1c,
3291 .age_time_coeff
= 15000,
3293 .atu_move_port_mask
= 0xf,
3295 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3296 .ops
= &mv88e6131_ops
,
3300 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6141
,
3301 .family
= MV88E6XXX_FAMILY_6341
,
3302 .name
= "Marvell 88E6341",
3303 .num_databases
= 4096,
3307 .port_base_addr
= 0x10,
3308 .global1_addr
= 0x1b,
3309 .global2_addr
= 0x1c,
3310 .age_time_coeff
= 3750,
3311 .atu_move_port_mask
= 0x1f,
3315 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3316 .ops
= &mv88e6141_ops
,
3320 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6161
,
3321 .family
= MV88E6XXX_FAMILY_6165
,
3322 .name
= "Marvell 88E6161",
3323 .num_databases
= 4096,
3326 .port_base_addr
= 0x10,
3327 .global1_addr
= 0x1b,
3328 .global2_addr
= 0x1c,
3329 .age_time_coeff
= 15000,
3332 .atu_move_port_mask
= 0xf,
3335 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3336 .ops
= &mv88e6161_ops
,
3340 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6165
,
3341 .family
= MV88E6XXX_FAMILY_6165
,
3342 .name
= "Marvell 88E6165",
3343 .num_databases
= 4096,
3346 .port_base_addr
= 0x10,
3347 .global1_addr
= 0x1b,
3348 .global2_addr
= 0x1c,
3349 .age_time_coeff
= 15000,
3352 .atu_move_port_mask
= 0xf,
3355 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3356 .ops
= &mv88e6165_ops
,
3360 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6171
,
3361 .family
= MV88E6XXX_FAMILY_6351
,
3362 .name
= "Marvell 88E6171",
3363 .num_databases
= 4096,
3366 .port_base_addr
= 0x10,
3367 .global1_addr
= 0x1b,
3368 .global2_addr
= 0x1c,
3369 .age_time_coeff
= 15000,
3372 .atu_move_port_mask
= 0xf,
3375 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3376 .ops
= &mv88e6171_ops
,
3380 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6172
,
3381 .family
= MV88E6XXX_FAMILY_6352
,
3382 .name
= "Marvell 88E6172",
3383 .num_databases
= 4096,
3387 .port_base_addr
= 0x10,
3388 .global1_addr
= 0x1b,
3389 .global2_addr
= 0x1c,
3390 .age_time_coeff
= 15000,
3393 .atu_move_port_mask
= 0xf,
3396 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3397 .ops
= &mv88e6172_ops
,
3401 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6175
,
3402 .family
= MV88E6XXX_FAMILY_6351
,
3403 .name
= "Marvell 88E6175",
3404 .num_databases
= 4096,
3407 .port_base_addr
= 0x10,
3408 .global1_addr
= 0x1b,
3409 .global2_addr
= 0x1c,
3410 .age_time_coeff
= 15000,
3413 .atu_move_port_mask
= 0xf,
3416 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3417 .ops
= &mv88e6175_ops
,
3421 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6176
,
3422 .family
= MV88E6XXX_FAMILY_6352
,
3423 .name
= "Marvell 88E6176",
3424 .num_databases
= 4096,
3428 .port_base_addr
= 0x10,
3429 .global1_addr
= 0x1b,
3430 .global2_addr
= 0x1c,
3431 .age_time_coeff
= 15000,
3434 .atu_move_port_mask
= 0xf,
3437 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3438 .ops
= &mv88e6176_ops
,
3442 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6185
,
3443 .family
= MV88E6XXX_FAMILY_6185
,
3444 .name
= "Marvell 88E6185",
3445 .num_databases
= 256,
3448 .port_base_addr
= 0x10,
3449 .global1_addr
= 0x1b,
3450 .global2_addr
= 0x1c,
3451 .age_time_coeff
= 15000,
3453 .atu_move_port_mask
= 0xf,
3455 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3456 .ops
= &mv88e6185_ops
,
3460 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190
,
3461 .family
= MV88E6XXX_FAMILY_6390
,
3462 .name
= "Marvell 88E6190",
3463 .num_databases
= 4096,
3464 .num_ports
= 11, /* 10 + Z80 */
3467 .port_base_addr
= 0x0,
3468 .global1_addr
= 0x1b,
3469 .global2_addr
= 0x1c,
3470 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3471 .age_time_coeff
= 3750,
3476 .atu_move_port_mask
= 0x1f,
3477 .ops
= &mv88e6190_ops
,
3481 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190X
,
3482 .family
= MV88E6XXX_FAMILY_6390
,
3483 .name
= "Marvell 88E6190X",
3484 .num_databases
= 4096,
3485 .num_ports
= 11, /* 10 + Z80 */
3488 .port_base_addr
= 0x0,
3489 .global1_addr
= 0x1b,
3490 .global2_addr
= 0x1c,
3491 .age_time_coeff
= 3750,
3494 .atu_move_port_mask
= 0x1f,
3497 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3498 .ops
= &mv88e6190x_ops
,
3502 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6191
,
3503 .family
= MV88E6XXX_FAMILY_6390
,
3504 .name
= "Marvell 88E6191",
3505 .num_databases
= 4096,
3506 .num_ports
= 11, /* 10 + Z80 */
3508 .port_base_addr
= 0x0,
3509 .global1_addr
= 0x1b,
3510 .global2_addr
= 0x1c,
3511 .age_time_coeff
= 3750,
3514 .atu_move_port_mask
= 0x1f,
3517 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3518 .ptp_support
= true,
3519 .ops
= &mv88e6191_ops
,
3523 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6240
,
3524 .family
= MV88E6XXX_FAMILY_6352
,
3525 .name
= "Marvell 88E6240",
3526 .num_databases
= 4096,
3530 .port_base_addr
= 0x10,
3531 .global1_addr
= 0x1b,
3532 .global2_addr
= 0x1c,
3533 .age_time_coeff
= 15000,
3536 .atu_move_port_mask
= 0xf,
3539 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3540 .ptp_support
= true,
3541 .ops
= &mv88e6240_ops
,
3545 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6290
,
3546 .family
= MV88E6XXX_FAMILY_6390
,
3547 .name
= "Marvell 88E6290",
3548 .num_databases
= 4096,
3549 .num_ports
= 11, /* 10 + Z80 */
3552 .port_base_addr
= 0x0,
3553 .global1_addr
= 0x1b,
3554 .global2_addr
= 0x1c,
3555 .age_time_coeff
= 3750,
3558 .atu_move_port_mask
= 0x1f,
3561 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3562 .ptp_support
= true,
3563 .ops
= &mv88e6290_ops
,
3567 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6320
,
3568 .family
= MV88E6XXX_FAMILY_6320
,
3569 .name
= "Marvell 88E6320",
3570 .num_databases
= 4096,
3574 .port_base_addr
= 0x10,
3575 .global1_addr
= 0x1b,
3576 .global2_addr
= 0x1c,
3577 .age_time_coeff
= 15000,
3579 .atu_move_port_mask
= 0xf,
3582 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3583 .ptp_support
= true,
3584 .ops
= &mv88e6320_ops
,
3588 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6321
,
3589 .family
= MV88E6XXX_FAMILY_6320
,
3590 .name
= "Marvell 88E6321",
3591 .num_databases
= 4096,
3595 .port_base_addr
= 0x10,
3596 .global1_addr
= 0x1b,
3597 .global2_addr
= 0x1c,
3598 .age_time_coeff
= 15000,
3600 .atu_move_port_mask
= 0xf,
3602 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3603 .ptp_support
= true,
3604 .ops
= &mv88e6321_ops
,
3608 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6341
,
3609 .family
= MV88E6XXX_FAMILY_6341
,
3610 .name
= "Marvell 88E6341",
3611 .num_databases
= 4096,
3615 .port_base_addr
= 0x10,
3616 .global1_addr
= 0x1b,
3617 .global2_addr
= 0x1c,
3618 .age_time_coeff
= 3750,
3619 .atu_move_port_mask
= 0x1f,
3623 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3624 .ptp_support
= true,
3625 .ops
= &mv88e6341_ops
,
3629 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6350
,
3630 .family
= MV88E6XXX_FAMILY_6351
,
3631 .name
= "Marvell 88E6350",
3632 .num_databases
= 4096,
3635 .port_base_addr
= 0x10,
3636 .global1_addr
= 0x1b,
3637 .global2_addr
= 0x1c,
3638 .age_time_coeff
= 15000,
3641 .atu_move_port_mask
= 0xf,
3644 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3645 .ops
= &mv88e6350_ops
,
3649 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6351
,
3650 .family
= MV88E6XXX_FAMILY_6351
,
3651 .name
= "Marvell 88E6351",
3652 .num_databases
= 4096,
3655 .port_base_addr
= 0x10,
3656 .global1_addr
= 0x1b,
3657 .global2_addr
= 0x1c,
3658 .age_time_coeff
= 15000,
3661 .atu_move_port_mask
= 0xf,
3664 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3665 .ops
= &mv88e6351_ops
,
3669 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6352
,
3670 .family
= MV88E6XXX_FAMILY_6352
,
3671 .name
= "Marvell 88E6352",
3672 .num_databases
= 4096,
3676 .port_base_addr
= 0x10,
3677 .global1_addr
= 0x1b,
3678 .global2_addr
= 0x1c,
3679 .age_time_coeff
= 15000,
3682 .atu_move_port_mask
= 0xf,
3685 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3686 .ptp_support
= true,
3687 .ops
= &mv88e6352_ops
,
3690 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
,
3691 .family
= MV88E6XXX_FAMILY_6390
,
3692 .name
= "Marvell 88E6390",
3693 .num_databases
= 4096,
3694 .num_ports
= 11, /* 10 + Z80 */
3697 .port_base_addr
= 0x0,
3698 .global1_addr
= 0x1b,
3699 .global2_addr
= 0x1c,
3700 .age_time_coeff
= 3750,
3703 .atu_move_port_mask
= 0x1f,
3706 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3707 .ptp_support
= true,
3708 .ops
= &mv88e6390_ops
,
3711 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390X
,
3712 .family
= MV88E6XXX_FAMILY_6390
,
3713 .name
= "Marvell 88E6390X",
3714 .num_databases
= 4096,
3715 .num_ports
= 11, /* 10 + Z80 */
3718 .port_base_addr
= 0x0,
3719 .global1_addr
= 0x1b,
3720 .global2_addr
= 0x1c,
3721 .age_time_coeff
= 3750,
3724 .atu_move_port_mask
= 0x1f,
3727 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3728 .ptp_support
= true,
3729 .ops
= &mv88e6390x_ops
,
3733 static const struct mv88e6xxx_info
*mv88e6xxx_lookup_info(unsigned int prod_num
)
3737 for (i
= 0; i
< ARRAY_SIZE(mv88e6xxx_table
); ++i
)
3738 if (mv88e6xxx_table
[i
].prod_num
== prod_num
)
3739 return &mv88e6xxx_table
[i
];
3744 static int mv88e6xxx_detect(struct mv88e6xxx_chip
*chip
)
3746 const struct mv88e6xxx_info
*info
;
3747 unsigned int prod_num
, rev
;
3751 mutex_lock(&chip
->reg_lock
);
3752 err
= mv88e6xxx_port_read(chip
, 0, MV88E6XXX_PORT_SWITCH_ID
, &id
);
3753 mutex_unlock(&chip
->reg_lock
);
3757 prod_num
= id
& MV88E6XXX_PORT_SWITCH_ID_PROD_MASK
;
3758 rev
= id
& MV88E6XXX_PORT_SWITCH_ID_REV_MASK
;
3760 info
= mv88e6xxx_lookup_info(prod_num
);
3764 /* Update the compatible info with the probed one */
3767 err
= mv88e6xxx_g2_require(chip
);
3771 dev_info(chip
->dev
, "switch 0x%x detected: %s, revision %u\n",
3772 chip
->info
->prod_num
, chip
->info
->name
, rev
);
3777 static struct mv88e6xxx_chip
*mv88e6xxx_alloc_chip(struct device
*dev
)
3779 struct mv88e6xxx_chip
*chip
;
3781 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
3787 mutex_init(&chip
->reg_lock
);
3788 INIT_LIST_HEAD(&chip
->mdios
);
3793 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip
*chip
,
3794 struct mii_bus
*bus
, int sw_addr
)
3797 chip
->smi_ops
= &mv88e6xxx_smi_single_chip_ops
;
3798 else if (chip
->info
->multi_chip
)
3799 chip
->smi_ops
= &mv88e6xxx_smi_multi_chip_ops
;
3804 chip
->sw_addr
= sw_addr
;
3809 static enum dsa_tag_protocol
mv88e6xxx_get_tag_protocol(struct dsa_switch
*ds
,
3812 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3814 return chip
->info
->tag_protocol
;
3817 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3818 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3819 struct device
*host_dev
, int sw_addr
,
3822 struct mv88e6xxx_chip
*chip
;
3823 struct mii_bus
*bus
;
3826 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3830 chip
= mv88e6xxx_alloc_chip(dsa_dev
);
3834 /* Legacy SMI probing will only support chips similar to 88E6085 */
3835 chip
->info
= &mv88e6xxx_table
[MV88E6085
];
3837 err
= mv88e6xxx_smi_init(chip
, bus
, sw_addr
);
3841 err
= mv88e6xxx_detect(chip
);
3845 mutex_lock(&chip
->reg_lock
);
3846 err
= mv88e6xxx_switch_reset(chip
);
3847 mutex_unlock(&chip
->reg_lock
);
3851 mv88e6xxx_phy_init(chip
);
3853 err
= mv88e6xxx_mdios_register(chip
, NULL
);
3859 return chip
->info
->name
;
3861 devm_kfree(dsa_dev
, chip
);
3867 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch
*ds
, int port
,
3868 const struct switchdev_obj_port_mdb
*mdb
)
3870 /* We don't need any dynamic resource from the kernel (yet),
3871 * so skip the prepare phase.
3877 static void mv88e6xxx_port_mdb_add(struct dsa_switch
*ds
, int port
,
3878 const struct switchdev_obj_port_mdb
*mdb
)
3880 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3882 mutex_lock(&chip
->reg_lock
);
3883 if (mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3884 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
))
3885 dev_err(ds
->dev
, "p%d: failed to load multicast MAC address\n",
3887 mutex_unlock(&chip
->reg_lock
);
3890 static int mv88e6xxx_port_mdb_del(struct dsa_switch
*ds
, int port
,
3891 const struct switchdev_obj_port_mdb
*mdb
)
3893 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3896 mutex_lock(&chip
->reg_lock
);
3897 err
= mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3898 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
3899 mutex_unlock(&chip
->reg_lock
);
3904 static const struct dsa_switch_ops mv88e6xxx_switch_ops
= {
3905 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3906 .probe
= mv88e6xxx_drv_probe
,
3908 .get_tag_protocol
= mv88e6xxx_get_tag_protocol
,
3909 .setup
= mv88e6xxx_setup
,
3910 .adjust_link
= mv88e6xxx_adjust_link
,
3911 .get_strings
= mv88e6xxx_get_strings
,
3912 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
3913 .get_sset_count
= mv88e6xxx_get_sset_count
,
3914 .port_enable
= mv88e6xxx_port_enable
,
3915 .port_disable
= mv88e6xxx_port_disable
,
3916 .get_mac_eee
= mv88e6xxx_get_mac_eee
,
3917 .set_mac_eee
= mv88e6xxx_set_mac_eee
,
3918 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
3919 .get_eeprom
= mv88e6xxx_get_eeprom
,
3920 .set_eeprom
= mv88e6xxx_set_eeprom
,
3921 .get_regs_len
= mv88e6xxx_get_regs_len
,
3922 .get_regs
= mv88e6xxx_get_regs
,
3923 .set_ageing_time
= mv88e6xxx_set_ageing_time
,
3924 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
3925 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
3926 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
3927 .port_fast_age
= mv88e6xxx_port_fast_age
,
3928 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
3929 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
3930 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
3931 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
3932 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
3933 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
3934 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
3935 .port_mdb_prepare
= mv88e6xxx_port_mdb_prepare
,
3936 .port_mdb_add
= mv88e6xxx_port_mdb_add
,
3937 .port_mdb_del
= mv88e6xxx_port_mdb_del
,
3938 .crosschip_bridge_join
= mv88e6xxx_crosschip_bridge_join
,
3939 .crosschip_bridge_leave
= mv88e6xxx_crosschip_bridge_leave
,
3940 .port_hwtstamp_set
= mv88e6xxx_port_hwtstamp_set
,
3941 .port_hwtstamp_get
= mv88e6xxx_port_hwtstamp_get
,
3942 .port_txtstamp
= mv88e6xxx_port_txtstamp
,
3943 .port_rxtstamp
= mv88e6xxx_port_rxtstamp
,
3944 .get_ts_info
= mv88e6xxx_get_ts_info
,
3947 static struct dsa_switch_driver mv88e6xxx_switch_drv
= {
3948 .ops
= &mv88e6xxx_switch_ops
,
3951 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip
*chip
)
3953 struct device
*dev
= chip
->dev
;
3954 struct dsa_switch
*ds
;
3956 ds
= dsa_switch_alloc(dev
, mv88e6xxx_num_ports(chip
));
3961 ds
->ops
= &mv88e6xxx_switch_ops
;
3962 ds
->ageing_time_min
= chip
->info
->age_time_coeff
;
3963 ds
->ageing_time_max
= chip
->info
->age_time_coeff
* U8_MAX
;
3965 dev_set_drvdata(dev
, ds
);
3967 return dsa_register_switch(ds
);
3970 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip
*chip
)
3972 dsa_unregister_switch(chip
->ds
);
3975 static int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
3977 struct device
*dev
= &mdiodev
->dev
;
3978 struct device_node
*np
= dev
->of_node
;
3979 const struct mv88e6xxx_info
*compat_info
;
3980 struct mv88e6xxx_chip
*chip
;
3984 compat_info
= of_device_get_match_data(dev
);
3988 chip
= mv88e6xxx_alloc_chip(dev
);
3992 chip
->info
= compat_info
;
3994 err
= mv88e6xxx_smi_init(chip
, mdiodev
->bus
, mdiodev
->addr
);
3998 chip
->reset
= devm_gpiod_get_optional(dev
, "reset", GPIOD_OUT_LOW
);
3999 if (IS_ERR(chip
->reset
))
4000 return PTR_ERR(chip
->reset
);
4002 err
= mv88e6xxx_detect(chip
);
4006 mv88e6xxx_phy_init(chip
);
4008 if (chip
->info
->ops
->get_eeprom
&&
4009 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
4010 chip
->eeprom_len
= eeprom_len
;
4012 mutex_lock(&chip
->reg_lock
);
4013 err
= mv88e6xxx_switch_reset(chip
);
4014 mutex_unlock(&chip
->reg_lock
);
4018 chip
->irq
= of_irq_get(np
, 0);
4019 if (chip
->irq
== -EPROBE_DEFER
) {
4024 if (chip
->irq
> 0) {
4025 /* Has to be performed before the MDIO bus is created,
4026 * because the PHYs will link there interrupts to these
4027 * interrupt controllers
4029 mutex_lock(&chip
->reg_lock
);
4030 err
= mv88e6xxx_g1_irq_setup(chip
);
4031 mutex_unlock(&chip
->reg_lock
);
4036 if (chip
->info
->g2_irqs
> 0) {
4037 err
= mv88e6xxx_g2_irq_setup(chip
);
4042 err
= mv88e6xxx_g1_atu_prob_irq_setup(chip
);
4046 err
= mv88e6xxx_g1_vtu_prob_irq_setup(chip
);
4048 goto out_g1_atu_prob_irq
;
4051 err
= mv88e6xxx_mdios_register(chip
, np
);
4053 goto out_g1_vtu_prob_irq
;
4055 err
= mv88e6xxx_register_switch(chip
);
4062 mv88e6xxx_mdios_unregister(chip
);
4063 out_g1_vtu_prob_irq
:
4065 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4066 out_g1_atu_prob_irq
:
4068 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4070 if (chip
->info
->g2_irqs
> 0 && chip
->irq
> 0)
4071 mv88e6xxx_g2_irq_free(chip
);
4073 if (chip
->irq
> 0) {
4074 mutex_lock(&chip
->reg_lock
);
4075 mv88e6xxx_g1_irq_free(chip
);
4076 mutex_unlock(&chip
->reg_lock
);
4082 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
4084 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
4085 struct mv88e6xxx_chip
*chip
= ds
->priv
;
4087 if (chip
->info
->ptp_support
) {
4088 mv88e6xxx_hwtstamp_free(chip
);
4089 mv88e6xxx_ptp_free(chip
);
4092 mv88e6xxx_phy_destroy(chip
);
4093 mv88e6xxx_unregister_switch(chip
);
4094 mv88e6xxx_mdios_unregister(chip
);
4096 if (chip
->irq
> 0) {
4097 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4098 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4099 if (chip
->info
->g2_irqs
> 0)
4100 mv88e6xxx_g2_irq_free(chip
);
4101 mutex_lock(&chip
->reg_lock
);
4102 mv88e6xxx_g1_irq_free(chip
);
4103 mutex_unlock(&chip
->reg_lock
);
4107 static const struct of_device_id mv88e6xxx_of_match
[] = {
4109 .compatible
= "marvell,mv88e6085",
4110 .data
= &mv88e6xxx_table
[MV88E6085
],
4113 .compatible
= "marvell,mv88e6190",
4114 .data
= &mv88e6xxx_table
[MV88E6190
],
4119 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
4121 static struct mdio_driver mv88e6xxx_driver
= {
4122 .probe
= mv88e6xxx_probe
,
4123 .remove
= mv88e6xxx_remove
,
4125 .name
= "mv88e6085",
4126 .of_match_table
= mv88e6xxx_of_match
,
4130 static int __init
mv88e6xxx_init(void)
4132 register_switch_driver(&mv88e6xxx_switch_drv
);
4133 return mdio_driver_register(&mv88e6xxx_driver
);
4135 module_init(mv88e6xxx_init
);
4137 static void __exit
mv88e6xxx_cleanup(void)
4139 mdio_driver_unregister(&mv88e6xxx_driver
);
4140 unregister_switch_driver(&mv88e6xxx_switch_drv
);
4142 module_exit(mv88e6xxx_cleanup
);
4144 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4145 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4146 MODULE_LICENSE("GPL");