2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
45 static void assert_reg_lock(struct mv88e6xxx_chip
*chip
)
47 if (unlikely(!mutex_is_locked(&chip
->reg_lock
))) {
48 dev_err(chip
->dev
, "Switch registers lock not held!\n");
53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip
*chip
,
66 int addr
, int reg
, u16
*val
)
71 return chip
->smi_ops
->read(chip
, addr
, reg
, val
);
74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip
*chip
,
75 int addr
, int reg
, u16 val
)
80 return chip
->smi_ops
->write(chip
, addr
, reg
, val
);
83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip
*chip
,
84 int addr
, int reg
, u16
*val
)
88 ret
= mdiobus_read_nested(chip
->bus
, addr
, reg
);
97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip
*chip
,
98 int addr
, int reg
, u16 val
)
102 ret
= mdiobus_write_nested(chip
->bus
, addr
, reg
, val
);
109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops
= {
110 .read
= mv88e6xxx_smi_single_chip_read
,
111 .write
= mv88e6xxx_smi_single_chip_write
,
114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip
*chip
)
119 for (i
= 0; i
< 16; i
++) {
120 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
);
124 if ((ret
& SMI_CMD_BUSY
) == 0)
131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip
*chip
,
132 int addr
, int reg
, u16
*val
)
136 /* Wait for the bus to become free. */
137 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
141 /* Transmit the read command. */
142 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
143 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
147 /* Wait for the read command to complete. */
148 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
153 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
);
162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip
*chip
,
163 int addr
, int reg
, u16 val
)
167 /* Wait for the bus to become free. */
168 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
172 /* Transmit the data to write. */
173 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
, val
);
177 /* Transmit the write command. */
178 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
179 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
183 /* Wait for the write command to complete. */
184 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops
= {
192 .read
= mv88e6xxx_smi_multi_chip_read
,
193 .write
= mv88e6xxx_smi_multi_chip_write
,
196 int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
)
200 assert_reg_lock(chip
);
202 err
= mv88e6xxx_smi_read(chip
, addr
, reg
, val
);
206 dev_dbg(chip
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
212 int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
)
216 assert_reg_lock(chip
);
218 err
= mv88e6xxx_smi_write(chip
, addr
, reg
, val
);
222 dev_dbg(chip
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
228 struct mii_bus
*mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip
*chip
)
230 struct mv88e6xxx_mdio_bus
*mdio_bus
;
232 mdio_bus
= list_first_entry(&chip
->mdios
, struct mv88e6xxx_mdio_bus
,
237 return mdio_bus
->bus
;
240 static void mv88e6xxx_g1_irq_mask(struct irq_data
*d
)
242 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
243 unsigned int n
= d
->hwirq
;
245 chip
->g1_irq
.masked
|= (1 << n
);
248 static void mv88e6xxx_g1_irq_unmask(struct irq_data
*d
)
250 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
251 unsigned int n
= d
->hwirq
;
253 chip
->g1_irq
.masked
&= ~(1 << n
);
256 static irqreturn_t
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip
*chip
)
258 unsigned int nhandled
= 0;
259 unsigned int sub_irq
;
264 mutex_lock(&chip
->reg_lock
);
265 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
266 mutex_unlock(&chip
->reg_lock
);
271 for (n
= 0; n
< chip
->g1_irq
.nirqs
; ++n
) {
272 if (reg
& (1 << n
)) {
273 sub_irq
= irq_find_mapping(chip
->g1_irq
.domain
, n
);
274 handle_nested_irq(sub_irq
);
279 return (nhandled
> 0 ? IRQ_HANDLED
: IRQ_NONE
);
282 static irqreturn_t
mv88e6xxx_g1_irq_thread_fn(int irq
, void *dev_id
)
284 struct mv88e6xxx_chip
*chip
= dev_id
;
286 return mv88e6xxx_g1_irq_thread_work(chip
);
289 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data
*d
)
291 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
293 mutex_lock(&chip
->reg_lock
);
296 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data
*d
)
298 struct mv88e6xxx_chip
*chip
= irq_data_get_irq_chip_data(d
);
299 u16 mask
= GENMASK(chip
->g1_irq
.nirqs
, 0);
303 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, ®
);
308 reg
|= (~chip
->g1_irq
.masked
& mask
);
310 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, reg
);
315 mutex_unlock(&chip
->reg_lock
);
318 static const struct irq_chip mv88e6xxx_g1_irq_chip
= {
319 .name
= "mv88e6xxx-g1",
320 .irq_mask
= mv88e6xxx_g1_irq_mask
,
321 .irq_unmask
= mv88e6xxx_g1_irq_unmask
,
322 .irq_bus_lock
= mv88e6xxx_g1_irq_bus_lock
,
323 .irq_bus_sync_unlock
= mv88e6xxx_g1_irq_bus_sync_unlock
,
326 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain
*d
,
328 irq_hw_number_t hwirq
)
330 struct mv88e6xxx_chip
*chip
= d
->host_data
;
332 irq_set_chip_data(irq
, d
->host_data
);
333 irq_set_chip_and_handler(irq
, &chip
->g1_irq
.chip
, handle_level_irq
);
334 irq_set_noprobe(irq
);
339 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops
= {
340 .map
= mv88e6xxx_g1_irq_domain_map
,
341 .xlate
= irq_domain_xlate_twocell
,
344 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip
*chip
)
349 mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
350 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
351 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
353 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++) {
354 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
355 irq_dispose_mapping(virq
);
358 irq_domain_remove(chip
->g1_irq
.domain
);
361 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip
*chip
)
363 mv88e6xxx_g1_irq_free_common(chip
);
365 free_irq(chip
->irq
, chip
);
368 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip
*chip
)
373 chip
->g1_irq
.nirqs
= chip
->info
->g1_irqs
;
374 chip
->g1_irq
.domain
= irq_domain_add_simple(
375 NULL
, chip
->g1_irq
.nirqs
, 0,
376 &mv88e6xxx_g1_irq_domain_ops
, chip
);
377 if (!chip
->g1_irq
.domain
)
380 for (irq
= 0; irq
< chip
->g1_irq
.nirqs
; irq
++)
381 irq_create_mapping(chip
->g1_irq
.domain
, irq
);
383 chip
->g1_irq
.chip
= mv88e6xxx_g1_irq_chip
;
384 chip
->g1_irq
.masked
= ~0;
386 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_CTL1
, &mask
);
390 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
392 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
396 /* Reading the interrupt status clears (most of) them */
397 err
= mv88e6xxx_g1_read(chip
, MV88E6XXX_G1_STS
, ®
);
404 mask
&= ~GENMASK(chip
->g1_irq
.nirqs
, 0);
405 mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL1
, mask
);
408 for (irq
= 0; irq
< 16; irq
++) {
409 virq
= irq_find_mapping(chip
->g1_irq
.domain
, irq
);
410 irq_dispose_mapping(virq
);
413 irq_domain_remove(chip
->g1_irq
.domain
);
418 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip
*chip
)
422 err
= mv88e6xxx_g1_irq_setup_common(chip
);
426 err
= request_threaded_irq(chip
->irq
, NULL
,
427 mv88e6xxx_g1_irq_thread_fn
,
428 IRQF_ONESHOT
| IRQF_TRIGGER_FALLING
,
429 dev_name(chip
->dev
), chip
);
431 mv88e6xxx_g1_irq_free_common(chip
);
436 static void mv88e6xxx_irq_poll(struct kthread_work
*work
)
438 struct mv88e6xxx_chip
*chip
= container_of(work
,
439 struct mv88e6xxx_chip
,
441 mv88e6xxx_g1_irq_thread_work(chip
);
443 kthread_queue_delayed_work(chip
->kworker
, &chip
->irq_poll_work
,
444 msecs_to_jiffies(100));
447 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip
*chip
)
451 err
= mv88e6xxx_g1_irq_setup_common(chip
);
455 kthread_init_delayed_work(&chip
->irq_poll_work
,
458 chip
->kworker
= kthread_create_worker(0, dev_name(chip
->dev
));
459 if (IS_ERR(chip
->kworker
))
460 return PTR_ERR(chip
->kworker
);
462 kthread_queue_delayed_work(chip
->kworker
, &chip
->irq_poll_work
,
463 msecs_to_jiffies(100));
468 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip
*chip
)
470 kthread_cancel_delayed_work_sync(&chip
->irq_poll_work
);
471 kthread_destroy_worker(chip
->kworker
);
474 int mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 mask
)
478 for (i
= 0; i
< 16; i
++) {
482 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
489 usleep_range(1000, 2000);
492 dev_err(chip
->dev
, "Timeout while waiting for switch\n");
496 /* Indirect write to single pointer-data register with an Update bit */
497 int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 update
)
502 /* Wait until the previous operation is completed */
503 err
= mv88e6xxx_wait(chip
, addr
, reg
, BIT(15));
507 /* Set the Update bit to trigger a write operation */
508 val
= BIT(15) | update
;
510 return mv88e6xxx_write(chip
, addr
, reg
, val
);
513 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip
*chip
, int port
,
514 int link
, int speed
, int duplex
,
515 phy_interface_t mode
)
519 if (!chip
->info
->ops
->port_set_link
)
522 /* Port's MAC control must not be changed unless the link is down */
523 err
= chip
->info
->ops
->port_set_link(chip
, port
, 0);
527 if (chip
->info
->ops
->port_set_speed
) {
528 err
= chip
->info
->ops
->port_set_speed(chip
, port
, speed
);
529 if (err
&& err
!= -EOPNOTSUPP
)
533 if (chip
->info
->ops
->port_set_duplex
) {
534 err
= chip
->info
->ops
->port_set_duplex(chip
, port
, duplex
);
535 if (err
&& err
!= -EOPNOTSUPP
)
539 if (chip
->info
->ops
->port_set_rgmii_delay
) {
540 err
= chip
->info
->ops
->port_set_rgmii_delay(chip
, port
, mode
);
541 if (err
&& err
!= -EOPNOTSUPP
)
545 if (chip
->info
->ops
->port_set_cmode
) {
546 err
= chip
->info
->ops
->port_set_cmode(chip
, port
, mode
);
547 if (err
&& err
!= -EOPNOTSUPP
)
553 if (chip
->info
->ops
->port_set_link(chip
, port
, link
))
554 dev_err(chip
->dev
, "p%d: failed to restore MAC's link\n", port
);
559 /* We expect the switch to perform auto negotiation if there is a real
560 * phy. However, in the case of a fixed link phy, we force the port
561 * settings from the fixed link settings.
563 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
564 struct phy_device
*phydev
)
566 struct mv88e6xxx_chip
*chip
= ds
->priv
;
569 if (!phy_is_pseudo_fixed_link(phydev
))
572 mutex_lock(&chip
->reg_lock
);
573 err
= mv88e6xxx_port_setup_mac(chip
, port
, phydev
->link
, phydev
->speed
,
574 phydev
->duplex
, phydev
->interface
);
575 mutex_unlock(&chip
->reg_lock
);
577 if (err
&& err
!= -EOPNOTSUPP
)
578 dev_err(ds
->dev
, "p%d: failed to configure MAC\n", port
);
581 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
)
583 if (!chip
->info
->ops
->stats_snapshot
)
586 return chip
->info
->ops
->stats_snapshot(chip
, port
);
589 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
590 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0
, },
591 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0
, },
592 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0
, },
593 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0
, },
594 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0
, },
595 { "in_pause", 4, 0x16, STATS_TYPE_BANK0
, },
596 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0
, },
597 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0
, },
598 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0
, },
599 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0
, },
600 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0
, },
601 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0
, },
602 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0
, },
603 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0
, },
604 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0
, },
605 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0
, },
606 { "out_pause", 4, 0x15, STATS_TYPE_BANK0
, },
607 { "excessive", 4, 0x11, STATS_TYPE_BANK0
, },
608 { "collisions", 4, 0x1e, STATS_TYPE_BANK0
, },
609 { "deferred", 4, 0x05, STATS_TYPE_BANK0
, },
610 { "single", 4, 0x14, STATS_TYPE_BANK0
, },
611 { "multiple", 4, 0x17, STATS_TYPE_BANK0
, },
612 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0
, },
613 { "late", 4, 0x1f, STATS_TYPE_BANK0
, },
614 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0
, },
615 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0
, },
616 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0
, },
617 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0
, },
618 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0
, },
619 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0
, },
620 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT
, },
621 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT
, },
622 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT
, },
623 { "in_discards", 4, 0x00, STATS_TYPE_BANK1
, },
624 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1
, },
625 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1
, },
626 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1
, },
627 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1
, },
628 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1
, },
629 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1
, },
630 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1
, },
631 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1
, },
632 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1
, },
633 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1
, },
634 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1
, },
635 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1
, },
636 { "in_management", 4, 0x0f, STATS_TYPE_BANK1
, },
637 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1
, },
638 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1
, },
639 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1
, },
640 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1
, },
641 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1
, },
642 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1
, },
643 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1
, },
644 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1
, },
645 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1
, },
646 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1
, },
647 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1
, },
648 { "out_management", 4, 0x1f, STATS_TYPE_BANK1
, },
651 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip
*chip
,
652 struct mv88e6xxx_hw_stat
*s
,
653 int port
, u16 bank1_select
,
663 case STATS_TYPE_PORT
:
664 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
, ®
);
670 err
= mv88e6xxx_port_read(chip
, port
, s
->reg
+ 1, ®
);
676 case STATS_TYPE_BANK1
:
679 case STATS_TYPE_BANK0
:
680 reg
|= s
->reg
| histogram
;
681 mv88e6xxx_g1_stats_read(chip
, reg
, &low
);
683 mv88e6xxx_g1_stats_read(chip
, reg
+ 1, &high
);
688 value
= (((u64
)high
) << 16) | low
;
692 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip
*chip
,
693 uint8_t *data
, int types
)
695 struct mv88e6xxx_hw_stat
*stat
;
698 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
699 stat
= &mv88e6xxx_hw_stats
[i
];
700 if (stat
->type
& types
) {
701 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
710 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip
*chip
,
713 return mv88e6xxx_stats_get_strings(chip
, data
,
714 STATS_TYPE_BANK0
| STATS_TYPE_PORT
);
717 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip
*chip
,
720 return mv88e6xxx_stats_get_strings(chip
, data
,
721 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
);
724 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
727 struct mv88e6xxx_chip
*chip
= ds
->priv
;
730 mutex_lock(&chip
->reg_lock
);
732 if (chip
->info
->ops
->stats_get_strings
)
733 count
= chip
->info
->ops
->stats_get_strings(chip
, data
);
735 if (chip
->info
->ops
->serdes_get_strings
) {
736 data
+= count
* ETH_GSTRING_LEN
;
737 chip
->info
->ops
->serdes_get_strings(chip
, port
, data
);
740 mutex_unlock(&chip
->reg_lock
);
743 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip
*chip
,
746 struct mv88e6xxx_hw_stat
*stat
;
749 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
750 stat
= &mv88e6xxx_hw_stats
[i
];
751 if (stat
->type
& types
)
757 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
759 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
763 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip
*chip
)
765 return mv88e6xxx_stats_get_sset_count(chip
, STATS_TYPE_BANK0
|
769 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
, int port
)
771 struct mv88e6xxx_chip
*chip
= ds
->priv
;
772 int serdes_count
= 0;
775 mutex_lock(&chip
->reg_lock
);
776 if (chip
->info
->ops
->stats_get_sset_count
)
777 count
= chip
->info
->ops
->stats_get_sset_count(chip
);
781 if (chip
->info
->ops
->serdes_get_sset_count
)
782 serdes_count
= chip
->info
->ops
->serdes_get_sset_count(chip
,
784 if (serdes_count
< 0)
785 count
= serdes_count
;
787 count
+= serdes_count
;
789 mutex_unlock(&chip
->reg_lock
);
794 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
795 uint64_t *data
, int types
,
796 u16 bank1_select
, u16 histogram
)
798 struct mv88e6xxx_hw_stat
*stat
;
801 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
802 stat
= &mv88e6xxx_hw_stats
[i
];
803 if (stat
->type
& types
) {
804 mutex_lock(&chip
->reg_lock
);
805 data
[j
] = _mv88e6xxx_get_ethtool_stat(chip
, stat
, port
,
808 mutex_unlock(&chip
->reg_lock
);
816 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
819 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
820 STATS_TYPE_BANK0
| STATS_TYPE_PORT
,
821 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
824 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
827 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
828 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
829 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9
,
830 MV88E6XXX_G1_STATS_OP_HIST_RX_TX
);
833 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
836 return mv88e6xxx_stats_get_stats(chip
, port
, data
,
837 STATS_TYPE_BANK0
| STATS_TYPE_BANK1
,
838 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10
,
842 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip
*chip
, int port
,
847 if (chip
->info
->ops
->stats_get_stats
)
848 count
= chip
->info
->ops
->stats_get_stats(chip
, port
, data
);
850 if (chip
->info
->ops
->serdes_get_stats
) {
852 mutex_lock(&chip
->reg_lock
);
853 chip
->info
->ops
->serdes_get_stats(chip
, port
, data
);
854 mutex_unlock(&chip
->reg_lock
);
858 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
861 struct mv88e6xxx_chip
*chip
= ds
->priv
;
864 mutex_lock(&chip
->reg_lock
);
866 ret
= mv88e6xxx_stats_snapshot(chip
, port
);
867 mutex_unlock(&chip
->reg_lock
);
872 mv88e6xxx_get_stats(chip
, port
, data
);
876 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip
*chip
)
878 if (chip
->info
->ops
->stats_set_histogram
)
879 return chip
->info
->ops
->stats_set_histogram(chip
);
884 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
886 return 32 * sizeof(u16
);
889 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
890 struct ethtool_regs
*regs
, void *_p
)
892 struct mv88e6xxx_chip
*chip
= ds
->priv
;
900 memset(p
, 0xff, 32 * sizeof(u16
));
902 mutex_lock(&chip
->reg_lock
);
904 for (i
= 0; i
< 32; i
++) {
906 err
= mv88e6xxx_port_read(chip
, port
, i
, ®
);
911 mutex_unlock(&chip
->reg_lock
);
914 static int mv88e6xxx_get_mac_eee(struct dsa_switch
*ds
, int port
,
915 struct ethtool_eee
*e
)
917 /* Nothing to do on the port's MAC */
921 static int mv88e6xxx_set_mac_eee(struct dsa_switch
*ds
, int port
,
922 struct ethtool_eee
*e
)
924 /* Nothing to do on the port's MAC */
928 static u16
mv88e6xxx_port_vlan(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
930 struct dsa_switch
*ds
= NULL
;
931 struct net_device
*br
;
935 if (dev
< DSA_MAX_SWITCHES
)
936 ds
= chip
->ds
->dst
->ds
[dev
];
938 /* Prevent frames from unknown switch or port */
939 if (!ds
|| port
>= ds
->num_ports
)
942 /* Frames from DSA links and CPU ports can egress any local port */
943 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
944 return mv88e6xxx_port_mask(chip
);
946 br
= ds
->ports
[port
].bridge_dev
;
949 /* Frames from user ports can egress any local DSA links and CPU ports,
950 * as well as any local member of their bridge group.
952 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
953 if (dsa_is_cpu_port(chip
->ds
, i
) ||
954 dsa_is_dsa_port(chip
->ds
, i
) ||
955 (br
&& dsa_to_port(chip
->ds
, i
)->bridge_dev
== br
))
961 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip
*chip
, int port
)
963 u16 output_ports
= mv88e6xxx_port_vlan(chip
, chip
->ds
->index
, port
);
965 /* prevent frames from going back out of the port they came in on */
966 output_ports
&= ~BIT(port
);
968 return mv88e6xxx_port_set_vlan_map(chip
, port
, output_ports
);
971 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
974 struct mv88e6xxx_chip
*chip
= ds
->priv
;
977 mutex_lock(&chip
->reg_lock
);
978 err
= mv88e6xxx_port_set_state(chip
, port
, state
);
979 mutex_unlock(&chip
->reg_lock
);
982 dev_err(ds
->dev
, "p%d: failed to update state\n", port
);
985 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip
*chip
)
987 if (chip
->info
->ops
->pot_clear
)
988 return chip
->info
->ops
->pot_clear(chip
);
993 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip
*chip
)
995 if (chip
->info
->ops
->mgmt_rsvd2cpu
)
996 return chip
->info
->ops
->mgmt_rsvd2cpu(chip
);
1001 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip
*chip
)
1005 err
= mv88e6xxx_g1_atu_flush(chip
, 0, true);
1009 err
= mv88e6xxx_g1_atu_set_learn2all(chip
, true);
1013 return mv88e6xxx_g1_atu_set_age_time(chip
, 300000);
1016 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip
*chip
)
1021 if (!chip
->info
->ops
->irl_init_all
)
1024 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
1025 /* Disable ingress rate limiting by resetting all per port
1026 * ingress rate limit resources to their initial state.
1028 err
= chip
->info
->ops
->irl_init_all(chip
, port
);
1036 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip
*chip
)
1038 if (chip
->info
->ops
->set_switch_mac
) {
1041 eth_random_addr(addr
);
1043 return chip
->info
->ops
->set_switch_mac(chip
, addr
);
1049 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip
*chip
, int dev
, int port
)
1053 if (!mv88e6xxx_has_pvt(chip
))
1056 /* Skip the local source device, which uses in-chip port VLAN */
1057 if (dev
!= chip
->ds
->index
)
1058 pvlan
= mv88e6xxx_port_vlan(chip
, dev
, port
);
1060 return mv88e6xxx_g2_pvt_write(chip
, dev
, port
, pvlan
);
1063 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip
*chip
)
1068 if (!mv88e6xxx_has_pvt(chip
))
1071 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1072 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1074 err
= mv88e6xxx_g2_misc_4_bit_port(chip
);
1078 for (dev
= 0; dev
< MV88E6XXX_MAX_PVT_SWITCHES
; ++dev
) {
1079 for (port
= 0; port
< MV88E6XXX_MAX_PVT_PORTS
; ++port
) {
1080 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1089 static void mv88e6xxx_port_fast_age(struct dsa_switch
*ds
, int port
)
1091 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1094 mutex_lock(&chip
->reg_lock
);
1095 err
= mv88e6xxx_g1_atu_remove(chip
, 0, port
, false);
1096 mutex_unlock(&chip
->reg_lock
);
1099 dev_err(ds
->dev
, "p%d: failed to flush ATU\n", port
);
1102 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip
*chip
)
1104 if (!chip
->info
->max_vid
)
1107 return mv88e6xxx_g1_vtu_flush(chip
);
1110 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip
*chip
,
1111 struct mv88e6xxx_vtu_entry
*entry
)
1113 if (!chip
->info
->ops
->vtu_getnext
)
1116 return chip
->info
->ops
->vtu_getnext(chip
, entry
);
1119 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
1120 struct mv88e6xxx_vtu_entry
*entry
)
1122 if (!chip
->info
->ops
->vtu_loadpurge
)
1125 return chip
->info
->ops
->vtu_loadpurge(chip
, entry
);
1128 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip
*chip
, u16
*fid
)
1130 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1131 struct mv88e6xxx_vtu_entry vlan
= {
1132 .vid
= chip
->info
->max_vid
,
1136 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1138 /* Set every FID bit used by the (un)bridged ports */
1139 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1140 err
= mv88e6xxx_port_get_fid(chip
, i
, fid
);
1144 set_bit(*fid
, fid_bitmap
);
1147 /* Set every FID bit used by the VLAN entries */
1149 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1156 set_bit(vlan
.fid
, fid_bitmap
);
1157 } while (vlan
.vid
< chip
->info
->max_vid
);
1159 /* The reset value 0x000 is used to indicate that multiple address
1160 * databases are not needed. Return the next positive available.
1162 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1163 if (unlikely(*fid
>= mv88e6xxx_num_databases(chip
)))
1166 /* Clear the database */
1167 return mv88e6xxx_g1_atu_flush(chip
, *fid
, true);
1170 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip
*chip
, u16 vid
,
1171 struct mv88e6xxx_vtu_entry
*entry
, bool new)
1178 entry
->vid
= vid
- 1;
1179 entry
->valid
= false;
1181 err
= mv88e6xxx_vtu_getnext(chip
, entry
);
1185 if (entry
->vid
== vid
&& entry
->valid
)
1191 /* Initialize a fresh VLAN entry */
1192 memset(entry
, 0, sizeof(*entry
));
1193 entry
->valid
= true;
1196 /* Exclude all ports */
1197 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
)
1199 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1201 return mv88e6xxx_atu_new(chip
, &entry
->fid
);
1204 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1208 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1209 u16 vid_begin
, u16 vid_end
)
1211 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1212 struct mv88e6xxx_vtu_entry vlan
= {
1213 .vid
= vid_begin
- 1,
1217 /* DSA and CPU ports have to be members of multiple vlans */
1218 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1224 mutex_lock(&chip
->reg_lock
);
1227 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1234 if (vlan
.vid
> vid_end
)
1237 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1238 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1241 if (!ds
->ports
[i
].slave
)
1244 if (vlan
.member
[i
] ==
1245 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1248 if (dsa_to_port(ds
, i
)->bridge_dev
==
1249 ds
->ports
[port
].bridge_dev
)
1250 break; /* same bridge, check next VLAN */
1252 if (!dsa_to_port(ds
, i
)->bridge_dev
)
1255 dev_err(ds
->dev
, "p%d: hw VLAN %d already used by port %d in %s\n",
1257 netdev_name(dsa_to_port(ds
, i
)->bridge_dev
));
1261 } while (vlan
.vid
< vid_end
);
1264 mutex_unlock(&chip
->reg_lock
);
1269 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1270 bool vlan_filtering
)
1272 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1273 u16 mode
= vlan_filtering
? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE
:
1274 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
;
1277 if (!chip
->info
->max_vid
)
1280 mutex_lock(&chip
->reg_lock
);
1281 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
, mode
);
1282 mutex_unlock(&chip
->reg_lock
);
1288 mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1289 const struct switchdev_obj_port_vlan
*vlan
)
1291 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1294 if (!chip
->info
->max_vid
)
1297 /* If the requested port doesn't belong to the same bridge as the VLAN
1298 * members, do not support it (yet) and fallback to software VLAN.
1300 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1305 /* We don't need any dynamic resource from the kernel (yet),
1306 * so skip the prepare phase.
1311 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip
*chip
, int port
,
1312 const unsigned char *addr
, u16 vid
,
1315 struct mv88e6xxx_vtu_entry vlan
;
1316 struct mv88e6xxx_atu_entry entry
;
1319 /* Null VLAN ID corresponds to the port private database */
1321 err
= mv88e6xxx_port_get_fid(chip
, port
, &vlan
.fid
);
1323 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1327 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1328 ether_addr_copy(entry
.mac
, addr
);
1329 eth_addr_dec(entry
.mac
);
1331 err
= mv88e6xxx_g1_atu_getnext(chip
, vlan
.fid
, &entry
);
1335 /* Initialize a fresh ATU entry if it isn't found */
1336 if (entry
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
||
1337 !ether_addr_equal(entry
.mac
, addr
)) {
1338 memset(&entry
, 0, sizeof(entry
));
1339 ether_addr_copy(entry
.mac
, addr
);
1342 /* Purge the ATU entry only if no port is using it anymore */
1343 if (state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
) {
1344 entry
.portvec
&= ~BIT(port
);
1346 entry
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1348 entry
.portvec
|= BIT(port
);
1349 entry
.state
= state
;
1352 return mv88e6xxx_g1_atu_loadpurge(chip
, vlan
.fid
, &entry
);
1355 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip
*chip
, int port
,
1358 const char broadcast
[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1359 u8 state
= MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
;
1361 return mv88e6xxx_port_db_load_purge(chip
, port
, broadcast
, vid
, state
);
1364 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip
*chip
, u16 vid
)
1369 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); port
++) {
1370 err
= mv88e6xxx_port_add_broadcast(chip
, port
, vid
);
1378 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip
*chip
, int port
,
1381 struct mv88e6xxx_vtu_entry vlan
;
1384 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, true);
1388 vlan
.member
[port
] = member
;
1390 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1394 return mv88e6xxx_broadcast_setup(chip
, vid
);
1397 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1398 const struct switchdev_obj_port_vlan
*vlan
)
1400 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1401 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1402 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1406 if (!chip
->info
->max_vid
)
1409 if (dsa_is_dsa_port(ds
, port
) || dsa_is_cpu_port(ds
, port
))
1410 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED
;
1412 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED
;
1414 member
= MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED
;
1416 mutex_lock(&chip
->reg_lock
);
1418 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
1419 if (_mv88e6xxx_port_vlan_add(chip
, port
, vid
, member
))
1420 dev_err(ds
->dev
, "p%d: failed to add VLAN %d%c\n", port
,
1421 vid
, untagged
? 'u' : 't');
1423 if (pvid
&& mv88e6xxx_port_set_pvid(chip
, port
, vlan
->vid_end
))
1424 dev_err(ds
->dev
, "p%d: failed to set PVID %d\n", port
,
1427 mutex_unlock(&chip
->reg_lock
);
1430 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip
*chip
,
1433 struct mv88e6xxx_vtu_entry vlan
;
1436 err
= mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1440 /* Tell switchdev if this VLAN is handled in software */
1441 if (vlan
.member
[port
] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1444 vlan
.member
[port
] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1446 /* keep the VLAN unless all ports are excluded */
1448 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); ++i
) {
1449 if (vlan
.member
[i
] !=
1450 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
1456 err
= mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1460 return mv88e6xxx_g1_atu_remove(chip
, vlan
.fid
, port
, false);
1463 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
1464 const struct switchdev_obj_port_vlan
*vlan
)
1466 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1470 if (!chip
->info
->max_vid
)
1473 mutex_lock(&chip
->reg_lock
);
1475 err
= mv88e6xxx_port_get_pvid(chip
, port
, &pvid
);
1479 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1480 err
= _mv88e6xxx_port_vlan_del(chip
, port
, vid
);
1485 err
= mv88e6xxx_port_set_pvid(chip
, port
, 0);
1492 mutex_unlock(&chip
->reg_lock
);
1497 static int mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1498 const unsigned char *addr
, u16 vid
)
1500 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1503 mutex_lock(&chip
->reg_lock
);
1504 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1505 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1506 mutex_unlock(&chip
->reg_lock
);
1511 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1512 const unsigned char *addr
, u16 vid
)
1514 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1517 mutex_lock(&chip
->reg_lock
);
1518 err
= mv88e6xxx_port_db_load_purge(chip
, port
, addr
, vid
,
1519 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
1520 mutex_unlock(&chip
->reg_lock
);
1525 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip
*chip
,
1526 u16 fid
, u16 vid
, int port
,
1527 dsa_fdb_dump_cb_t
*cb
, void *data
)
1529 struct mv88e6xxx_atu_entry addr
;
1533 addr
.state
= MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
;
1534 eth_broadcast_addr(addr
.mac
);
1537 mutex_lock(&chip
->reg_lock
);
1538 err
= mv88e6xxx_g1_atu_getnext(chip
, fid
, &addr
);
1539 mutex_unlock(&chip
->reg_lock
);
1543 if (addr
.state
== MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
)
1546 if (addr
.trunk
|| (addr
.portvec
& BIT(port
)) == 0)
1549 if (!is_unicast_ether_addr(addr
.mac
))
1552 is_static
= (addr
.state
==
1553 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC
);
1554 err
= cb(addr
.mac
, vid
, is_static
, data
);
1557 } while (!is_broadcast_ether_addr(addr
.mac
));
1562 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip
*chip
, int port
,
1563 dsa_fdb_dump_cb_t
*cb
, void *data
)
1565 struct mv88e6xxx_vtu_entry vlan
= {
1566 .vid
= chip
->info
->max_vid
,
1571 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1572 mutex_lock(&chip
->reg_lock
);
1573 err
= mv88e6xxx_port_get_fid(chip
, port
, &fid
);
1574 mutex_unlock(&chip
->reg_lock
);
1579 err
= mv88e6xxx_port_db_dump_fid(chip
, fid
, 0, port
, cb
, data
);
1583 /* Dump VLANs' Filtering Information Databases */
1585 mutex_lock(&chip
->reg_lock
);
1586 err
= mv88e6xxx_vtu_getnext(chip
, &vlan
);
1587 mutex_unlock(&chip
->reg_lock
);
1594 err
= mv88e6xxx_port_db_dump_fid(chip
, vlan
.fid
, vlan
.vid
, port
,
1598 } while (vlan
.vid
< chip
->info
->max_vid
);
1603 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1604 dsa_fdb_dump_cb_t
*cb
, void *data
)
1606 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1608 return mv88e6xxx_port_db_dump(chip
, port
, cb
, data
);
1611 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip
*chip
,
1612 struct net_device
*br
)
1614 struct dsa_switch
*ds
;
1619 /* Remap the Port VLAN of each local bridge group member */
1620 for (port
= 0; port
< mv88e6xxx_num_ports(chip
); ++port
) {
1621 if (chip
->ds
->ports
[port
].bridge_dev
== br
) {
1622 err
= mv88e6xxx_port_vlan_map(chip
, port
);
1628 if (!mv88e6xxx_has_pvt(chip
))
1631 /* Remap the Port VLAN of each cross-chip bridge group member */
1632 for (dev
= 0; dev
< DSA_MAX_SWITCHES
; ++dev
) {
1633 ds
= chip
->ds
->dst
->ds
[dev
];
1637 for (port
= 0; port
< ds
->num_ports
; ++port
) {
1638 if (ds
->ports
[port
].bridge_dev
== br
) {
1639 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1649 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1650 struct net_device
*br
)
1652 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1655 mutex_lock(&chip
->reg_lock
);
1656 err
= mv88e6xxx_bridge_map(chip
, br
);
1657 mutex_unlock(&chip
->reg_lock
);
1662 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
1663 struct net_device
*br
)
1665 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1667 mutex_lock(&chip
->reg_lock
);
1668 if (mv88e6xxx_bridge_map(chip
, br
) ||
1669 mv88e6xxx_port_vlan_map(chip
, port
))
1670 dev_err(ds
->dev
, "failed to remap in-chip Port VLAN\n");
1671 mutex_unlock(&chip
->reg_lock
);
1674 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch
*ds
, int dev
,
1675 int port
, struct net_device
*br
)
1677 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1680 if (!mv88e6xxx_has_pvt(chip
))
1683 mutex_lock(&chip
->reg_lock
);
1684 err
= mv88e6xxx_pvt_map(chip
, dev
, port
);
1685 mutex_unlock(&chip
->reg_lock
);
1690 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch
*ds
, int dev
,
1691 int port
, struct net_device
*br
)
1693 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1695 if (!mv88e6xxx_has_pvt(chip
))
1698 mutex_lock(&chip
->reg_lock
);
1699 if (mv88e6xxx_pvt_map(chip
, dev
, port
))
1700 dev_err(ds
->dev
, "failed to remap cross-chip Port VLAN\n");
1701 mutex_unlock(&chip
->reg_lock
);
1704 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip
*chip
)
1706 if (chip
->info
->ops
->reset
)
1707 return chip
->info
->ops
->reset(chip
);
1712 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip
*chip
)
1714 struct gpio_desc
*gpiod
= chip
->reset
;
1716 /* If there is a GPIO connected to the reset pin, toggle it */
1718 gpiod_set_value_cansleep(gpiod
, 1);
1719 usleep_range(10000, 20000);
1720 gpiod_set_value_cansleep(gpiod
, 0);
1721 usleep_range(10000, 20000);
1725 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip
*chip
)
1729 /* Set all ports to the Disabled state */
1730 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
1731 err
= mv88e6xxx_port_set_state(chip
, i
, BR_STATE_DISABLED
);
1736 /* Wait for transmit queues to drain,
1737 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1739 usleep_range(2000, 4000);
1744 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip
*chip
)
1748 err
= mv88e6xxx_disable_ports(chip
);
1752 mv88e6xxx_hardware_reset(chip
);
1754 return mv88e6xxx_software_reset(chip
);
1757 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip
*chip
, int port
,
1758 enum mv88e6xxx_frame_mode frame
,
1759 enum mv88e6xxx_egress_mode egress
, u16 etype
)
1763 if (!chip
->info
->ops
->port_set_frame_mode
)
1766 err
= mv88e6xxx_port_set_egress_mode(chip
, port
, egress
);
1770 err
= chip
->info
->ops
->port_set_frame_mode(chip
, port
, frame
);
1774 if (chip
->info
->ops
->port_set_ether_type
)
1775 return chip
->info
->ops
->port_set_ether_type(chip
, port
, etype
);
1780 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip
*chip
, int port
)
1782 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_NORMAL
,
1783 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1784 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1787 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip
*chip
, int port
)
1789 return mv88e6xxx_set_port_mode(chip
, port
, MV88E6XXX_FRAME_MODE_DSA
,
1790 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
1791 MV88E6XXX_PORT_ETH_TYPE_DEFAULT
);
1794 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip
*chip
, int port
)
1796 return mv88e6xxx_set_port_mode(chip
, port
,
1797 MV88E6XXX_FRAME_MODE_ETHERTYPE
,
1798 MV88E6XXX_EGRESS_MODE_ETHERTYPE
,
1802 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip
*chip
, int port
)
1804 if (dsa_is_dsa_port(chip
->ds
, port
))
1805 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1807 if (dsa_is_user_port(chip
->ds
, port
))
1808 return mv88e6xxx_set_port_mode_normal(chip
, port
);
1810 /* Setup CPU port mode depending on its supported tag format */
1811 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_DSA
)
1812 return mv88e6xxx_set_port_mode_dsa(chip
, port
);
1814 if (chip
->info
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
1815 return mv88e6xxx_set_port_mode_edsa(chip
, port
);
1820 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip
*chip
, int port
)
1822 bool message
= dsa_is_dsa_port(chip
->ds
, port
);
1824 return mv88e6xxx_port_set_message_port(chip
, port
, message
);
1827 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip
*chip
, int port
)
1829 struct dsa_switch
*ds
= chip
->ds
;
1832 /* Upstream ports flood frames with unknown unicast or multicast DA */
1833 flood
= dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
);
1834 if (chip
->info
->ops
->port_set_egress_floods
)
1835 return chip
->info
->ops
->port_set_egress_floods(chip
, port
,
1841 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip
*chip
, int port
,
1844 if (chip
->info
->ops
->serdes_power
)
1845 return chip
->info
->ops
->serdes_power(chip
, port
, on
);
1850 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip
*chip
, int port
)
1852 struct dsa_switch
*ds
= chip
->ds
;
1856 upstream_port
= dsa_upstream_port(ds
, port
);
1857 if (chip
->info
->ops
->port_set_upstream_port
) {
1858 err
= chip
->info
->ops
->port_set_upstream_port(chip
, port
,
1864 if (port
== upstream_port
) {
1865 if (chip
->info
->ops
->set_cpu_port
) {
1866 err
= chip
->info
->ops
->set_cpu_port(chip
,
1872 if (chip
->info
->ops
->set_egress_port
) {
1873 err
= chip
->info
->ops
->set_egress_port(chip
,
1883 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip
, int port
)
1885 struct dsa_switch
*ds
= chip
->ds
;
1889 /* MAC Forcing register: don't force link, speed, duplex or flow control
1890 * state to any particular values on physical ports, but force the CPU
1891 * port and all DSA ports to their maximum bandwidth and full duplex.
1893 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1894 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_FORCED_UP
,
1895 SPEED_MAX
, DUPLEX_FULL
,
1896 PHY_INTERFACE_MODE_NA
);
1898 err
= mv88e6xxx_port_setup_mac(chip
, port
, LINK_UNFORCED
,
1899 SPEED_UNFORCED
, DUPLEX_UNFORCED
,
1900 PHY_INTERFACE_MODE_NA
);
1904 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1905 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1906 * tunneling, determine priority by looking at 802.1p and IP
1907 * priority fields (IP prio has precedence), and set STP state
1910 * If this is the CPU link, use DSA or EDSA tagging depending
1911 * on which tagging mode was configured.
1913 * If this is a link to another switch, use DSA tagging mode.
1915 * If this is the upstream port for this switch, enable
1916 * forwarding of unknown unicasts and multicasts.
1918 reg
= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP
|
1919 MV88E6185_PORT_CTL0_USE_TAG
| MV88E6185_PORT_CTL0_USE_IP
|
1920 MV88E6XXX_PORT_CTL0_STATE_FORWARDING
;
1921 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
1925 err
= mv88e6xxx_setup_port_mode(chip
, port
);
1929 err
= mv88e6xxx_setup_egress_floods(chip
, port
);
1933 /* Enable the SERDES interface for DSA and CPU ports. Normal
1934 * ports SERDES are enabled when the port is enabled, thus
1935 * saving a bit of power.
1937 if ((dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))) {
1938 err
= mv88e6xxx_serdes_power(chip
, port
, true);
1943 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1944 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1945 * untagged frames on this port, do a destination address lookup on all
1946 * received packets as usual, disable ARP mirroring and don't send a
1947 * copy of all transmitted/received frames on this port to the CPU.
1949 err
= mv88e6xxx_port_set_map_da(chip
, port
);
1953 err
= mv88e6xxx_setup_upstream_port(chip
, port
);
1957 err
= mv88e6xxx_port_set_8021q_mode(chip
, port
,
1958 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
);
1962 if (chip
->info
->ops
->port_set_jumbo_size
) {
1963 err
= chip
->info
->ops
->port_set_jumbo_size(chip
, port
, 10240);
1968 /* Port Association Vector: when learning source addresses
1969 * of packets, add the address to the address database using
1970 * a port bitmap that has only the bit for this port set and
1971 * the other bits clear.
1974 /* Disable learning for CPU port */
1975 if (dsa_is_cpu_port(ds
, port
))
1978 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_ASSOC_VECTOR
,
1983 /* Egress rate control 2: disable egress rate control. */
1984 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_EGRESS_RATE_CTL2
,
1989 if (chip
->info
->ops
->port_pause_limit
) {
1990 err
= chip
->info
->ops
->port_pause_limit(chip
, port
, 0, 0);
1995 if (chip
->info
->ops
->port_disable_learn_limit
) {
1996 err
= chip
->info
->ops
->port_disable_learn_limit(chip
, port
);
2001 if (chip
->info
->ops
->port_disable_pri_override
) {
2002 err
= chip
->info
->ops
->port_disable_pri_override(chip
, port
);
2007 if (chip
->info
->ops
->port_tag_remap
) {
2008 err
= chip
->info
->ops
->port_tag_remap(chip
, port
);
2013 if (chip
->info
->ops
->port_egress_rate_limiting
) {
2014 err
= chip
->info
->ops
->port_egress_rate_limiting(chip
, port
);
2019 err
= mv88e6xxx_setup_message_port(chip
, port
);
2023 /* Port based VLAN map: give each port the same default address
2024 * database, and allow bidirectional communication between the
2025 * CPU and DSA port(s), and the other ports.
2027 err
= mv88e6xxx_port_set_fid(chip
, port
, 0);
2031 err
= mv88e6xxx_port_vlan_map(chip
, port
);
2035 /* Default VLAN ID and priority: don't set a default VLAN
2036 * ID, and set the default packet priority to zero.
2038 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
, 0);
2041 static int mv88e6xxx_port_enable(struct dsa_switch
*ds
, int port
,
2042 struct phy_device
*phydev
)
2044 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2047 mutex_lock(&chip
->reg_lock
);
2048 err
= mv88e6xxx_serdes_power(chip
, port
, true);
2049 mutex_unlock(&chip
->reg_lock
);
2054 static void mv88e6xxx_port_disable(struct dsa_switch
*ds
, int port
,
2055 struct phy_device
*phydev
)
2057 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2059 mutex_lock(&chip
->reg_lock
);
2060 if (mv88e6xxx_serdes_power(chip
, port
, false))
2061 dev_err(chip
->dev
, "failed to power off SERDES\n");
2062 mutex_unlock(&chip
->reg_lock
);
2065 static int mv88e6xxx_set_ageing_time(struct dsa_switch
*ds
,
2066 unsigned int ageing_time
)
2068 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2071 mutex_lock(&chip
->reg_lock
);
2072 err
= mv88e6xxx_g1_atu_set_age_time(chip
, ageing_time
);
2073 mutex_unlock(&chip
->reg_lock
);
2078 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip
*chip
)
2080 struct dsa_switch
*ds
= chip
->ds
;
2083 /* Disable remote management, and set the switch's DSA device number. */
2084 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_CTL2
,
2085 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE
|
2086 (ds
->index
& 0x1f));
2090 /* Configure the IP ToS mapping registers. */
2091 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_0
, 0x0000);
2094 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_1
, 0x0000);
2097 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_2
, 0x5555);
2100 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_3
, 0x5555);
2103 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_4
, 0xaaaa);
2106 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_5
, 0xaaaa);
2109 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_6
, 0xffff);
2112 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IP_PRI_7
, 0xffff);
2116 /* Configure the IEEE 802.1p priority mapping register. */
2117 err
= mv88e6xxx_g1_write(chip
, MV88E6XXX_G1_IEEE_PRI
, 0xfa41);
2121 /* Initialize the statistics unit */
2122 err
= mv88e6xxx_stats_set_histogram(chip
);
2126 return mv88e6xxx_g1_stats_clear(chip
);
2129 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
2131 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2136 ds
->slave_mii_bus
= mv88e6xxx_default_mdio_bus(chip
);
2138 mutex_lock(&chip
->reg_lock
);
2140 /* Setup Switch Port Registers */
2141 for (i
= 0; i
< mv88e6xxx_num_ports(chip
); i
++) {
2142 if (dsa_is_unused_port(ds
, i
))
2145 err
= mv88e6xxx_setup_port(chip
, i
);
2150 /* Setup Switch Global 1 Registers */
2151 err
= mv88e6xxx_g1_setup(chip
);
2155 /* Setup Switch Global 2 Registers */
2156 if (chip
->info
->global2_addr
) {
2157 err
= mv88e6xxx_g2_setup(chip
);
2162 err
= mv88e6xxx_irl_setup(chip
);
2166 err
= mv88e6xxx_mac_setup(chip
);
2170 err
= mv88e6xxx_phy_setup(chip
);
2174 err
= mv88e6xxx_vtu_setup(chip
);
2178 err
= mv88e6xxx_pvt_setup(chip
);
2182 err
= mv88e6xxx_atu_setup(chip
);
2186 err
= mv88e6xxx_broadcast_setup(chip
, 0);
2190 err
= mv88e6xxx_pot_setup(chip
);
2194 err
= mv88e6xxx_rsvd2cpu_setup(chip
);
2198 /* Setup PTP Hardware Clock and timestamping */
2199 if (chip
->info
->ptp_support
) {
2200 err
= mv88e6xxx_ptp_setup(chip
);
2204 err
= mv88e6xxx_hwtstamp_setup(chip
);
2210 mutex_unlock(&chip
->reg_lock
);
2215 static int mv88e6xxx_mdio_read(struct mii_bus
*bus
, int phy
, int reg
)
2217 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2218 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2222 if (!chip
->info
->ops
->phy_read
)
2225 mutex_lock(&chip
->reg_lock
);
2226 err
= chip
->info
->ops
->phy_read(chip
, bus
, phy
, reg
, &val
);
2227 mutex_unlock(&chip
->reg_lock
);
2229 if (reg
== MII_PHYSID2
) {
2230 /* Some internal PHYS don't have a model number. Use
2231 * the mv88e6390 family model number instead.
2234 val
|= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
>> 4;
2237 return err
? err
: val
;
2240 static int mv88e6xxx_mdio_write(struct mii_bus
*bus
, int phy
, int reg
, u16 val
)
2242 struct mv88e6xxx_mdio_bus
*mdio_bus
= bus
->priv
;
2243 struct mv88e6xxx_chip
*chip
= mdio_bus
->chip
;
2246 if (!chip
->info
->ops
->phy_write
)
2249 mutex_lock(&chip
->reg_lock
);
2250 err
= chip
->info
->ops
->phy_write(chip
, bus
, phy
, reg
, val
);
2251 mutex_unlock(&chip
->reg_lock
);
2256 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip
*chip
,
2257 struct device_node
*np
,
2261 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2262 struct mii_bus
*bus
;
2266 mutex_lock(&chip
->reg_lock
);
2267 err
= mv88e6xxx_g2_scratch_gpio_set_smi(chip
, true);
2268 mutex_unlock(&chip
->reg_lock
);
2274 bus
= devm_mdiobus_alloc_size(chip
->dev
, sizeof(*mdio_bus
));
2278 mdio_bus
= bus
->priv
;
2279 mdio_bus
->bus
= bus
;
2280 mdio_bus
->chip
= chip
;
2281 INIT_LIST_HEAD(&mdio_bus
->list
);
2282 mdio_bus
->external
= external
;
2285 bus
->name
= np
->full_name
;
2286 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%pOF", np
);
2288 bus
->name
= "mv88e6xxx SMI";
2289 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "mv88e6xxx-%d", index
++);
2292 bus
->read
= mv88e6xxx_mdio_read
;
2293 bus
->write
= mv88e6xxx_mdio_write
;
2294 bus
->parent
= chip
->dev
;
2297 err
= of_mdiobus_register(bus
, np
);
2299 err
= mdiobus_register(bus
);
2301 dev_err(chip
->dev
, "Cannot register MDIO bus (%d)\n", err
);
2306 list_add_tail(&mdio_bus
->list
, &chip
->mdios
);
2308 list_add(&mdio_bus
->list
, &chip
->mdios
);
2313 static const struct of_device_id mv88e6xxx_mdio_external_match
[] = {
2314 { .compatible
= "marvell,mv88e6xxx-mdio-external",
2315 .data
= (void *)true },
2319 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip
*chip
)
2322 struct mv88e6xxx_mdio_bus
*mdio_bus
;
2323 struct mii_bus
*bus
;
2325 list_for_each_entry(mdio_bus
, &chip
->mdios
, list
) {
2326 bus
= mdio_bus
->bus
;
2328 mdiobus_unregister(bus
);
2332 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip
*chip
,
2333 struct device_node
*np
)
2335 const struct of_device_id
*match
;
2336 struct device_node
*child
;
2339 /* Always register one mdio bus for the internal/default mdio
2340 * bus. This maybe represented in the device tree, but is
2343 child
= of_get_child_by_name(np
, "mdio");
2344 err
= mv88e6xxx_mdio_register(chip
, child
, false);
2348 /* Walk the device tree, and see if there are any other nodes
2349 * which say they are compatible with the external mdio
2352 for_each_available_child_of_node(np
, child
) {
2353 match
= of_match_node(mv88e6xxx_mdio_external_match
, child
);
2355 err
= mv88e6xxx_mdio_register(chip
, child
, true);
2357 mv88e6xxx_mdios_unregister(chip
);
2366 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
2368 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2370 return chip
->eeprom_len
;
2373 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
2374 struct ethtool_eeprom
*eeprom
, u8
*data
)
2376 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2379 if (!chip
->info
->ops
->get_eeprom
)
2382 mutex_lock(&chip
->reg_lock
);
2383 err
= chip
->info
->ops
->get_eeprom(chip
, eeprom
, data
);
2384 mutex_unlock(&chip
->reg_lock
);
2389 eeprom
->magic
= 0xc3ec4951;
2394 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
2395 struct ethtool_eeprom
*eeprom
, u8
*data
)
2397 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2400 if (!chip
->info
->ops
->set_eeprom
)
2403 if (eeprom
->magic
!= 0xc3ec4951)
2406 mutex_lock(&chip
->reg_lock
);
2407 err
= chip
->info
->ops
->set_eeprom(chip
, eeprom
, data
);
2408 mutex_unlock(&chip
->reg_lock
);
2413 static const struct mv88e6xxx_ops mv88e6085_ops
= {
2414 /* MV88E6XXX_FAMILY_6097 */
2415 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2416 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2417 .phy_read
= mv88e6185_phy_ppu_read
,
2418 .phy_write
= mv88e6185_phy_ppu_write
,
2419 .port_set_link
= mv88e6xxx_port_set_link
,
2420 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2421 .port_set_speed
= mv88e6185_port_set_speed
,
2422 .port_tag_remap
= mv88e6095_port_tag_remap
,
2423 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2424 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2425 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2426 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2427 .port_pause_limit
= mv88e6097_port_pause_limit
,
2428 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2429 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2430 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2431 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2432 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2433 .stats_get_strings
= mv88e6095_stats_get_strings
,
2434 .stats_get_stats
= mv88e6095_stats_get_stats
,
2435 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2436 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2437 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2438 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2439 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2440 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2441 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2442 .reset
= mv88e6185_g1_reset
,
2443 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2444 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2447 static const struct mv88e6xxx_ops mv88e6095_ops
= {
2448 /* MV88E6XXX_FAMILY_6095 */
2449 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2450 .phy_read
= mv88e6185_phy_ppu_read
,
2451 .phy_write
= mv88e6185_phy_ppu_write
,
2452 .port_set_link
= mv88e6xxx_port_set_link
,
2453 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2454 .port_set_speed
= mv88e6185_port_set_speed
,
2455 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2456 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2457 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2458 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2459 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2460 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2461 .stats_get_strings
= mv88e6095_stats_get_strings
,
2462 .stats_get_stats
= mv88e6095_stats_get_stats
,
2463 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2464 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2465 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2466 .reset
= mv88e6185_g1_reset
,
2467 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2468 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2471 static const struct mv88e6xxx_ops mv88e6097_ops
= {
2472 /* MV88E6XXX_FAMILY_6097 */
2473 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2474 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2475 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2476 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2477 .port_set_link
= mv88e6xxx_port_set_link
,
2478 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2479 .port_set_speed
= mv88e6185_port_set_speed
,
2480 .port_tag_remap
= mv88e6095_port_tag_remap
,
2481 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2482 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2483 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2484 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2485 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2486 .port_pause_limit
= mv88e6097_port_pause_limit
,
2487 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2488 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2489 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2490 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2491 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2492 .stats_get_strings
= mv88e6095_stats_get_strings
,
2493 .stats_get_stats
= mv88e6095_stats_get_stats
,
2494 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2495 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2496 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2497 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2498 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2499 .reset
= mv88e6352_g1_reset
,
2500 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2501 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2504 static const struct mv88e6xxx_ops mv88e6123_ops
= {
2505 /* MV88E6XXX_FAMILY_6165 */
2506 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2507 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2508 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2509 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2510 .port_set_link
= mv88e6xxx_port_set_link
,
2511 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2512 .port_set_speed
= mv88e6185_port_set_speed
,
2513 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2514 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2515 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2516 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2517 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2518 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2519 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2520 .stats_get_strings
= mv88e6095_stats_get_strings
,
2521 .stats_get_stats
= mv88e6095_stats_get_stats
,
2522 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2523 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2524 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2525 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2526 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2527 .reset
= mv88e6352_g1_reset
,
2528 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2529 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2532 static const struct mv88e6xxx_ops mv88e6131_ops
= {
2533 /* MV88E6XXX_FAMILY_6185 */
2534 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2535 .phy_read
= mv88e6185_phy_ppu_read
,
2536 .phy_write
= mv88e6185_phy_ppu_write
,
2537 .port_set_link
= mv88e6xxx_port_set_link
,
2538 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2539 .port_set_speed
= mv88e6185_port_set_speed
,
2540 .port_tag_remap
= mv88e6095_port_tag_remap
,
2541 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2542 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2543 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2544 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2545 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2546 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2547 .port_pause_limit
= mv88e6097_port_pause_limit
,
2548 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2549 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2550 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2551 .stats_get_strings
= mv88e6095_stats_get_strings
,
2552 .stats_get_stats
= mv88e6095_stats_get_stats
,
2553 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2554 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2555 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2556 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2557 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2558 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2559 .reset
= mv88e6185_g1_reset
,
2560 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2561 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2564 static const struct mv88e6xxx_ops mv88e6141_ops
= {
2565 /* MV88E6XXX_FAMILY_6341 */
2566 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2567 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2568 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2569 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2570 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2571 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2572 .port_set_link
= mv88e6xxx_port_set_link
,
2573 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2574 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2575 .port_set_speed
= mv88e6390_port_set_speed
,
2576 .port_tag_remap
= mv88e6095_port_tag_remap
,
2577 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2578 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2579 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2580 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2581 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2582 .port_pause_limit
= mv88e6097_port_pause_limit
,
2583 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2584 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2585 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2586 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2587 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2588 .stats_get_strings
= mv88e6320_stats_get_strings
,
2589 .stats_get_stats
= mv88e6390_stats_get_stats
,
2590 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2591 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2592 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2593 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2594 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2595 .reset
= mv88e6352_g1_reset
,
2596 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2597 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2598 .gpio_ops
= &mv88e6352_gpio_ops
,
2601 static const struct mv88e6xxx_ops mv88e6161_ops
= {
2602 /* MV88E6XXX_FAMILY_6165 */
2603 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2604 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2605 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2606 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2607 .port_set_link
= mv88e6xxx_port_set_link
,
2608 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2609 .port_set_speed
= mv88e6185_port_set_speed
,
2610 .port_tag_remap
= mv88e6095_port_tag_remap
,
2611 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2612 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2613 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2614 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2615 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2616 .port_pause_limit
= mv88e6097_port_pause_limit
,
2617 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2618 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2619 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2620 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2621 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2622 .stats_get_strings
= mv88e6095_stats_get_strings
,
2623 .stats_get_stats
= mv88e6095_stats_get_stats
,
2624 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2625 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2626 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2627 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2628 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2629 .reset
= mv88e6352_g1_reset
,
2630 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2631 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2634 static const struct mv88e6xxx_ops mv88e6165_ops
= {
2635 /* MV88E6XXX_FAMILY_6165 */
2636 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2637 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2638 .phy_read
= mv88e6165_phy_read
,
2639 .phy_write
= mv88e6165_phy_write
,
2640 .port_set_link
= mv88e6xxx_port_set_link
,
2641 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2642 .port_set_speed
= mv88e6185_port_set_speed
,
2643 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2644 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2645 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2646 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2647 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2648 .stats_get_strings
= mv88e6095_stats_get_strings
,
2649 .stats_get_stats
= mv88e6095_stats_get_stats
,
2650 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2651 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2652 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2653 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2654 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2655 .reset
= mv88e6352_g1_reset
,
2656 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2657 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2660 static const struct mv88e6xxx_ops mv88e6171_ops
= {
2661 /* MV88E6XXX_FAMILY_6351 */
2662 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2663 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2664 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2665 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2666 .port_set_link
= mv88e6xxx_port_set_link
,
2667 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2668 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2669 .port_set_speed
= mv88e6185_port_set_speed
,
2670 .port_tag_remap
= mv88e6095_port_tag_remap
,
2671 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2672 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2673 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2674 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2675 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2676 .port_pause_limit
= mv88e6097_port_pause_limit
,
2677 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2678 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2679 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2680 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2681 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2682 .stats_get_strings
= mv88e6095_stats_get_strings
,
2683 .stats_get_stats
= mv88e6095_stats_get_stats
,
2684 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2685 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2686 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2687 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2688 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2689 .reset
= mv88e6352_g1_reset
,
2690 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2691 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2694 static const struct mv88e6xxx_ops mv88e6172_ops
= {
2695 /* MV88E6XXX_FAMILY_6352 */
2696 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2697 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2698 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2699 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2700 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2701 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2702 .port_set_link
= mv88e6xxx_port_set_link
,
2703 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2704 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2705 .port_set_speed
= mv88e6352_port_set_speed
,
2706 .port_tag_remap
= mv88e6095_port_tag_remap
,
2707 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2708 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2709 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2710 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2711 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2712 .port_pause_limit
= mv88e6097_port_pause_limit
,
2713 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2714 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2715 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2716 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2717 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2718 .stats_get_strings
= mv88e6095_stats_get_strings
,
2719 .stats_get_stats
= mv88e6095_stats_get_stats
,
2720 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2721 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2722 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2723 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2724 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2725 .reset
= mv88e6352_g1_reset
,
2726 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2727 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2728 .serdes_power
= mv88e6352_serdes_power
,
2729 .gpio_ops
= &mv88e6352_gpio_ops
,
2732 static const struct mv88e6xxx_ops mv88e6175_ops
= {
2733 /* MV88E6XXX_FAMILY_6351 */
2734 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2735 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2736 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2737 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2738 .port_set_link
= mv88e6xxx_port_set_link
,
2739 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2740 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2741 .port_set_speed
= mv88e6185_port_set_speed
,
2742 .port_tag_remap
= mv88e6095_port_tag_remap
,
2743 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2744 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2745 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2746 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2747 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2748 .port_pause_limit
= mv88e6097_port_pause_limit
,
2749 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2750 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2751 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2752 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2753 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2754 .stats_get_strings
= mv88e6095_stats_get_strings
,
2755 .stats_get_stats
= mv88e6095_stats_get_stats
,
2756 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2757 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2758 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2759 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2760 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2761 .reset
= mv88e6352_g1_reset
,
2762 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2763 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2766 static const struct mv88e6xxx_ops mv88e6176_ops
= {
2767 /* MV88E6XXX_FAMILY_6352 */
2768 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2769 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2770 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2771 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2772 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2773 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2774 .port_set_link
= mv88e6xxx_port_set_link
,
2775 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2776 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2777 .port_set_speed
= mv88e6352_port_set_speed
,
2778 .port_tag_remap
= mv88e6095_port_tag_remap
,
2779 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2780 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2781 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2782 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2783 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2784 .port_pause_limit
= mv88e6097_port_pause_limit
,
2785 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2786 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2787 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2788 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2789 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2790 .stats_get_strings
= mv88e6095_stats_get_strings
,
2791 .stats_get_stats
= mv88e6095_stats_get_stats
,
2792 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2793 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2794 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2795 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2796 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2797 .reset
= mv88e6352_g1_reset
,
2798 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2799 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2800 .serdes_power
= mv88e6352_serdes_power
,
2801 .gpio_ops
= &mv88e6352_gpio_ops
,
2804 static const struct mv88e6xxx_ops mv88e6185_ops
= {
2805 /* MV88E6XXX_FAMILY_6185 */
2806 .set_switch_mac
= mv88e6xxx_g1_set_switch_mac
,
2807 .phy_read
= mv88e6185_phy_ppu_read
,
2808 .phy_write
= mv88e6185_phy_ppu_write
,
2809 .port_set_link
= mv88e6xxx_port_set_link
,
2810 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2811 .port_set_speed
= mv88e6185_port_set_speed
,
2812 .port_set_frame_mode
= mv88e6085_port_set_frame_mode
,
2813 .port_set_egress_floods
= mv88e6185_port_set_egress_floods
,
2814 .port_egress_rate_limiting
= mv88e6095_port_egress_rate_limiting
,
2815 .port_set_upstream_port
= mv88e6095_port_set_upstream_port
,
2816 .stats_snapshot
= mv88e6xxx_g1_stats_snapshot
,
2817 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2818 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2819 .stats_get_strings
= mv88e6095_stats_get_strings
,
2820 .stats_get_stats
= mv88e6095_stats_get_stats
,
2821 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2822 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2823 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2824 .mgmt_rsvd2cpu
= mv88e6185_g2_mgmt_rsvd2cpu
,
2825 .ppu_enable
= mv88e6185_g1_ppu_enable
,
2826 .ppu_disable
= mv88e6185_g1_ppu_disable
,
2827 .reset
= mv88e6185_g1_reset
,
2828 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
2829 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
2832 static const struct mv88e6xxx_ops mv88e6190_ops
= {
2833 /* MV88E6XXX_FAMILY_6390 */
2834 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2835 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2836 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2837 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2838 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2839 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2840 .port_set_link
= mv88e6xxx_port_set_link
,
2841 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2842 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2843 .port_set_speed
= mv88e6390_port_set_speed
,
2844 .port_tag_remap
= mv88e6390_port_tag_remap
,
2845 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2846 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2847 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2848 .port_pause_limit
= mv88e6390_port_pause_limit
,
2849 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2850 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2851 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2852 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2853 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2854 .stats_get_strings
= mv88e6320_stats_get_strings
,
2855 .stats_get_stats
= mv88e6390_stats_get_stats
,
2856 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2857 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2858 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2859 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2860 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2861 .reset
= mv88e6352_g1_reset
,
2862 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2863 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2864 .serdes_power
= mv88e6390_serdes_power
,
2865 .gpio_ops
= &mv88e6352_gpio_ops
,
2868 static const struct mv88e6xxx_ops mv88e6190x_ops
= {
2869 /* MV88E6XXX_FAMILY_6390 */
2870 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2871 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2872 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2873 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2874 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2875 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2876 .port_set_link
= mv88e6xxx_port_set_link
,
2877 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2878 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2879 .port_set_speed
= mv88e6390x_port_set_speed
,
2880 .port_tag_remap
= mv88e6390_port_tag_remap
,
2881 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2882 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2883 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2884 .port_pause_limit
= mv88e6390_port_pause_limit
,
2885 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2886 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2887 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2888 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2889 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2890 .stats_get_strings
= mv88e6320_stats_get_strings
,
2891 .stats_get_stats
= mv88e6390_stats_get_stats
,
2892 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2893 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2894 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2895 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2896 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2897 .reset
= mv88e6352_g1_reset
,
2898 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2899 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2900 .serdes_power
= mv88e6390_serdes_power
,
2901 .gpio_ops
= &mv88e6352_gpio_ops
,
2904 static const struct mv88e6xxx_ops mv88e6191_ops
= {
2905 /* MV88E6XXX_FAMILY_6390 */
2906 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2907 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2908 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2909 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2910 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2911 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2912 .port_set_link
= mv88e6xxx_port_set_link
,
2913 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2914 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2915 .port_set_speed
= mv88e6390_port_set_speed
,
2916 .port_tag_remap
= mv88e6390_port_tag_remap
,
2917 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2918 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2919 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2920 .port_pause_limit
= mv88e6390_port_pause_limit
,
2921 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2922 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2923 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2924 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
2925 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
2926 .stats_get_strings
= mv88e6320_stats_get_strings
,
2927 .stats_get_stats
= mv88e6390_stats_get_stats
,
2928 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
2929 .set_egress_port
= mv88e6390_g1_set_egress_port
,
2930 .watchdog_ops
= &mv88e6390_watchdog_ops
,
2931 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
2932 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2933 .reset
= mv88e6352_g1_reset
,
2934 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
2935 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
2936 .serdes_power
= mv88e6390_serdes_power
,
2939 static const struct mv88e6xxx_ops mv88e6240_ops
= {
2940 /* MV88E6XXX_FAMILY_6352 */
2941 .irl_init_all
= mv88e6352_g2_irl_init_all
,
2942 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
2943 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
2944 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2945 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2946 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2947 .port_set_link
= mv88e6xxx_port_set_link
,
2948 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2949 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
2950 .port_set_speed
= mv88e6352_port_set_speed
,
2951 .port_tag_remap
= mv88e6095_port_tag_remap
,
2952 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2953 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2954 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2955 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
2956 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
2957 .port_pause_limit
= mv88e6097_port_pause_limit
,
2958 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2959 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2960 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
2961 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
2962 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
2963 .stats_get_strings
= mv88e6095_stats_get_strings
,
2964 .stats_get_stats
= mv88e6095_stats_get_stats
,
2965 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
2966 .set_egress_port
= mv88e6095_g1_set_egress_port
,
2967 .watchdog_ops
= &mv88e6097_watchdog_ops
,
2968 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
2969 .pot_clear
= mv88e6xxx_g2_pot_clear
,
2970 .reset
= mv88e6352_g1_reset
,
2971 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
2972 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
2973 .serdes_power
= mv88e6352_serdes_power
,
2974 .gpio_ops
= &mv88e6352_gpio_ops
,
2975 .avb_ops
= &mv88e6352_avb_ops
,
2978 static const struct mv88e6xxx_ops mv88e6290_ops
= {
2979 /* MV88E6XXX_FAMILY_6390 */
2980 .irl_init_all
= mv88e6390_g2_irl_init_all
,
2981 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
2982 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
2983 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
2984 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
2985 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
2986 .port_set_link
= mv88e6xxx_port_set_link
,
2987 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
2988 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
2989 .port_set_speed
= mv88e6390_port_set_speed
,
2990 .port_tag_remap
= mv88e6390_port_tag_remap
,
2991 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
2992 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
2993 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
2994 .port_pause_limit
= mv88e6390_port_pause_limit
,
2995 .port_set_cmode
= mv88e6390x_port_set_cmode
,
2996 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
2997 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
2998 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
2999 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3000 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3001 .stats_get_strings
= mv88e6320_stats_get_strings
,
3002 .stats_get_stats
= mv88e6390_stats_get_stats
,
3003 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3004 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3005 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3006 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3007 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3008 .reset
= mv88e6352_g1_reset
,
3009 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3010 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3011 .serdes_power
= mv88e6390_serdes_power
,
3012 .gpio_ops
= &mv88e6352_gpio_ops
,
3013 .avb_ops
= &mv88e6390_avb_ops
,
3016 static const struct mv88e6xxx_ops mv88e6320_ops
= {
3017 /* MV88E6XXX_FAMILY_6320 */
3018 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3019 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
3020 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
3021 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3022 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3023 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3024 .port_set_link
= mv88e6xxx_port_set_link
,
3025 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3026 .port_set_speed
= mv88e6185_port_set_speed
,
3027 .port_tag_remap
= mv88e6095_port_tag_remap
,
3028 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3029 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3030 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3031 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3032 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3033 .port_pause_limit
= mv88e6097_port_pause_limit
,
3034 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3035 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3036 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3037 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3038 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3039 .stats_get_strings
= mv88e6320_stats_get_strings
,
3040 .stats_get_stats
= mv88e6320_stats_get_stats
,
3041 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3042 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3043 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3044 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3045 .reset
= mv88e6352_g1_reset
,
3046 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
3047 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
3048 .gpio_ops
= &mv88e6352_gpio_ops
,
3049 .avb_ops
= &mv88e6352_avb_ops
,
3052 static const struct mv88e6xxx_ops mv88e6321_ops
= {
3053 /* MV88E6XXX_FAMILY_6320 */
3054 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3055 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
3056 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
3057 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3058 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3059 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3060 .port_set_link
= mv88e6xxx_port_set_link
,
3061 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3062 .port_set_speed
= mv88e6185_port_set_speed
,
3063 .port_tag_remap
= mv88e6095_port_tag_remap
,
3064 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3065 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3066 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3067 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3068 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3069 .port_pause_limit
= mv88e6097_port_pause_limit
,
3070 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3071 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3072 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3073 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3074 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3075 .stats_get_strings
= mv88e6320_stats_get_strings
,
3076 .stats_get_stats
= mv88e6320_stats_get_stats
,
3077 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3078 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3079 .reset
= mv88e6352_g1_reset
,
3080 .vtu_getnext
= mv88e6185_g1_vtu_getnext
,
3081 .vtu_loadpurge
= mv88e6185_g1_vtu_loadpurge
,
3082 .gpio_ops
= &mv88e6352_gpio_ops
,
3083 .avb_ops
= &mv88e6352_avb_ops
,
3086 static const struct mv88e6xxx_ops mv88e6341_ops
= {
3087 /* MV88E6XXX_FAMILY_6341 */
3088 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3089 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3090 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3091 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3092 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3093 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3094 .port_set_link
= mv88e6xxx_port_set_link
,
3095 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3096 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3097 .port_set_speed
= mv88e6390_port_set_speed
,
3098 .port_tag_remap
= mv88e6095_port_tag_remap
,
3099 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3100 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3101 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3102 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3103 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3104 .port_pause_limit
= mv88e6097_port_pause_limit
,
3105 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3106 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3107 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3108 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3109 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3110 .stats_get_strings
= mv88e6320_stats_get_strings
,
3111 .stats_get_stats
= mv88e6390_stats_get_stats
,
3112 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3113 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3114 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3115 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3116 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3117 .reset
= mv88e6352_g1_reset
,
3118 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3119 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3120 .gpio_ops
= &mv88e6352_gpio_ops
,
3121 .avb_ops
= &mv88e6390_avb_ops
,
3124 static const struct mv88e6xxx_ops mv88e6350_ops
= {
3125 /* MV88E6XXX_FAMILY_6351 */
3126 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3127 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3128 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3129 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3130 .port_set_link
= mv88e6xxx_port_set_link
,
3131 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3132 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3133 .port_set_speed
= mv88e6185_port_set_speed
,
3134 .port_tag_remap
= mv88e6095_port_tag_remap
,
3135 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3136 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3137 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3138 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3139 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3140 .port_pause_limit
= mv88e6097_port_pause_limit
,
3141 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3142 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3143 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3144 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3145 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3146 .stats_get_strings
= mv88e6095_stats_get_strings
,
3147 .stats_get_stats
= mv88e6095_stats_get_stats
,
3148 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3149 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3150 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3151 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3152 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3153 .reset
= mv88e6352_g1_reset
,
3154 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3155 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3158 static const struct mv88e6xxx_ops mv88e6351_ops
= {
3159 /* MV88E6XXX_FAMILY_6351 */
3160 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3161 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3162 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3163 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3164 .port_set_link
= mv88e6xxx_port_set_link
,
3165 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3166 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3167 .port_set_speed
= mv88e6185_port_set_speed
,
3168 .port_tag_remap
= mv88e6095_port_tag_remap
,
3169 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3170 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3171 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3172 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3173 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3174 .port_pause_limit
= mv88e6097_port_pause_limit
,
3175 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3176 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3177 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3178 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3179 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3180 .stats_get_strings
= mv88e6095_stats_get_strings
,
3181 .stats_get_stats
= mv88e6095_stats_get_stats
,
3182 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3183 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3184 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3185 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3186 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3187 .reset
= mv88e6352_g1_reset
,
3188 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3189 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3190 .avb_ops
= &mv88e6352_avb_ops
,
3193 static const struct mv88e6xxx_ops mv88e6352_ops
= {
3194 /* MV88E6XXX_FAMILY_6352 */
3195 .irl_init_all
= mv88e6352_g2_irl_init_all
,
3196 .get_eeprom
= mv88e6xxx_g2_get_eeprom16
,
3197 .set_eeprom
= mv88e6xxx_g2_set_eeprom16
,
3198 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3199 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3200 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3201 .port_set_link
= mv88e6xxx_port_set_link
,
3202 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3203 .port_set_rgmii_delay
= mv88e6352_port_set_rgmii_delay
,
3204 .port_set_speed
= mv88e6352_port_set_speed
,
3205 .port_tag_remap
= mv88e6095_port_tag_remap
,
3206 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3207 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3208 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3209 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3210 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3211 .port_pause_limit
= mv88e6097_port_pause_limit
,
3212 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3213 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3214 .stats_snapshot
= mv88e6320_g1_stats_snapshot
,
3215 .stats_set_histogram
= mv88e6095_g1_stats_set_histogram
,
3216 .stats_get_sset_count
= mv88e6095_stats_get_sset_count
,
3217 .stats_get_strings
= mv88e6095_stats_get_strings
,
3218 .stats_get_stats
= mv88e6095_stats_get_stats
,
3219 .set_cpu_port
= mv88e6095_g1_set_cpu_port
,
3220 .set_egress_port
= mv88e6095_g1_set_egress_port
,
3221 .watchdog_ops
= &mv88e6097_watchdog_ops
,
3222 .mgmt_rsvd2cpu
= mv88e6352_g2_mgmt_rsvd2cpu
,
3223 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3224 .reset
= mv88e6352_g1_reset
,
3225 .vtu_getnext
= mv88e6352_g1_vtu_getnext
,
3226 .vtu_loadpurge
= mv88e6352_g1_vtu_loadpurge
,
3227 .serdes_power
= mv88e6352_serdes_power
,
3228 .gpio_ops
= &mv88e6352_gpio_ops
,
3229 .avb_ops
= &mv88e6352_avb_ops
,
3230 .serdes_get_sset_count
= mv88e6352_serdes_get_sset_count
,
3231 .serdes_get_strings
= mv88e6352_serdes_get_strings
,
3232 .serdes_get_stats
= mv88e6352_serdes_get_stats
,
3235 static const struct mv88e6xxx_ops mv88e6390_ops
= {
3236 /* MV88E6XXX_FAMILY_6390 */
3237 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3238 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3239 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3240 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3241 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3242 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3243 .port_set_link
= mv88e6xxx_port_set_link
,
3244 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3245 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3246 .port_set_speed
= mv88e6390_port_set_speed
,
3247 .port_tag_remap
= mv88e6390_port_tag_remap
,
3248 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3249 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3250 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3251 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3252 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3253 .port_pause_limit
= mv88e6390_port_pause_limit
,
3254 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3255 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3256 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3257 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3258 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3259 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3260 .stats_get_strings
= mv88e6320_stats_get_strings
,
3261 .stats_get_stats
= mv88e6390_stats_get_stats
,
3262 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3263 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3264 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3265 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3266 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3267 .reset
= mv88e6352_g1_reset
,
3268 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3269 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3270 .serdes_power
= mv88e6390_serdes_power
,
3271 .gpio_ops
= &mv88e6352_gpio_ops
,
3272 .avb_ops
= &mv88e6390_avb_ops
,
3275 static const struct mv88e6xxx_ops mv88e6390x_ops
= {
3276 /* MV88E6XXX_FAMILY_6390 */
3277 .irl_init_all
= mv88e6390_g2_irl_init_all
,
3278 .get_eeprom
= mv88e6xxx_g2_get_eeprom8
,
3279 .set_eeprom
= mv88e6xxx_g2_set_eeprom8
,
3280 .set_switch_mac
= mv88e6xxx_g2_set_switch_mac
,
3281 .phy_read
= mv88e6xxx_g2_smi_phy_read
,
3282 .phy_write
= mv88e6xxx_g2_smi_phy_write
,
3283 .port_set_link
= mv88e6xxx_port_set_link
,
3284 .port_set_duplex
= mv88e6xxx_port_set_duplex
,
3285 .port_set_rgmii_delay
= mv88e6390_port_set_rgmii_delay
,
3286 .port_set_speed
= mv88e6390x_port_set_speed
,
3287 .port_tag_remap
= mv88e6390_port_tag_remap
,
3288 .port_set_frame_mode
= mv88e6351_port_set_frame_mode
,
3289 .port_set_egress_floods
= mv88e6352_port_set_egress_floods
,
3290 .port_set_ether_type
= mv88e6351_port_set_ether_type
,
3291 .port_set_jumbo_size
= mv88e6165_port_set_jumbo_size
,
3292 .port_egress_rate_limiting
= mv88e6097_port_egress_rate_limiting
,
3293 .port_pause_limit
= mv88e6390_port_pause_limit
,
3294 .port_set_cmode
= mv88e6390x_port_set_cmode
,
3295 .port_disable_learn_limit
= mv88e6xxx_port_disable_learn_limit
,
3296 .port_disable_pri_override
= mv88e6xxx_port_disable_pri_override
,
3297 .stats_snapshot
= mv88e6390_g1_stats_snapshot
,
3298 .stats_set_histogram
= mv88e6390_g1_stats_set_histogram
,
3299 .stats_get_sset_count
= mv88e6320_stats_get_sset_count
,
3300 .stats_get_strings
= mv88e6320_stats_get_strings
,
3301 .stats_get_stats
= mv88e6390_stats_get_stats
,
3302 .set_cpu_port
= mv88e6390_g1_set_cpu_port
,
3303 .set_egress_port
= mv88e6390_g1_set_egress_port
,
3304 .watchdog_ops
= &mv88e6390_watchdog_ops
,
3305 .mgmt_rsvd2cpu
= mv88e6390_g1_mgmt_rsvd2cpu
,
3306 .pot_clear
= mv88e6xxx_g2_pot_clear
,
3307 .reset
= mv88e6352_g1_reset
,
3308 .vtu_getnext
= mv88e6390_g1_vtu_getnext
,
3309 .vtu_loadpurge
= mv88e6390_g1_vtu_loadpurge
,
3310 .serdes_power
= mv88e6390_serdes_power
,
3311 .gpio_ops
= &mv88e6352_gpio_ops
,
3312 .avb_ops
= &mv88e6390_avb_ops
,
3315 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3317 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6085
,
3318 .family
= MV88E6XXX_FAMILY_6097
,
3319 .name
= "Marvell 88E6085",
3320 .num_databases
= 4096,
3323 .port_base_addr
= 0x10,
3324 .global1_addr
= 0x1b,
3325 .global2_addr
= 0x1c,
3326 .age_time_coeff
= 15000,
3329 .atu_move_port_mask
= 0xf,
3332 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3333 .ops
= &mv88e6085_ops
,
3337 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6095
,
3338 .family
= MV88E6XXX_FAMILY_6095
,
3339 .name
= "Marvell 88E6095/88E6095F",
3340 .num_databases
= 256,
3343 .port_base_addr
= 0x10,
3344 .global1_addr
= 0x1b,
3345 .global2_addr
= 0x1c,
3346 .age_time_coeff
= 15000,
3348 .atu_move_port_mask
= 0xf,
3350 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3351 .ops
= &mv88e6095_ops
,
3355 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6097
,
3356 .family
= MV88E6XXX_FAMILY_6097
,
3357 .name
= "Marvell 88E6097/88E6097F",
3358 .num_databases
= 4096,
3361 .port_base_addr
= 0x10,
3362 .global1_addr
= 0x1b,
3363 .global2_addr
= 0x1c,
3364 .age_time_coeff
= 15000,
3367 .atu_move_port_mask
= 0xf,
3370 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3371 .ops
= &mv88e6097_ops
,
3375 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6123
,
3376 .family
= MV88E6XXX_FAMILY_6165
,
3377 .name
= "Marvell 88E6123",
3378 .num_databases
= 4096,
3381 .port_base_addr
= 0x10,
3382 .global1_addr
= 0x1b,
3383 .global2_addr
= 0x1c,
3384 .age_time_coeff
= 15000,
3387 .atu_move_port_mask
= 0xf,
3390 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3391 .ops
= &mv88e6123_ops
,
3395 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6131
,
3396 .family
= MV88E6XXX_FAMILY_6185
,
3397 .name
= "Marvell 88E6131",
3398 .num_databases
= 256,
3401 .port_base_addr
= 0x10,
3402 .global1_addr
= 0x1b,
3403 .global2_addr
= 0x1c,
3404 .age_time_coeff
= 15000,
3406 .atu_move_port_mask
= 0xf,
3408 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3409 .ops
= &mv88e6131_ops
,
3413 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6141
,
3414 .family
= MV88E6XXX_FAMILY_6341
,
3415 .name
= "Marvell 88E6341",
3416 .num_databases
= 4096,
3420 .port_base_addr
= 0x10,
3421 .global1_addr
= 0x1b,
3422 .global2_addr
= 0x1c,
3423 .age_time_coeff
= 3750,
3424 .atu_move_port_mask
= 0x1f,
3429 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3430 .ops
= &mv88e6141_ops
,
3434 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6161
,
3435 .family
= MV88E6XXX_FAMILY_6165
,
3436 .name
= "Marvell 88E6161",
3437 .num_databases
= 4096,
3440 .port_base_addr
= 0x10,
3441 .global1_addr
= 0x1b,
3442 .global2_addr
= 0x1c,
3443 .age_time_coeff
= 15000,
3446 .atu_move_port_mask
= 0xf,
3449 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3450 .ops
= &mv88e6161_ops
,
3454 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6165
,
3455 .family
= MV88E6XXX_FAMILY_6165
,
3456 .name
= "Marvell 88E6165",
3457 .num_databases
= 4096,
3460 .port_base_addr
= 0x10,
3461 .global1_addr
= 0x1b,
3462 .global2_addr
= 0x1c,
3463 .age_time_coeff
= 15000,
3466 .atu_move_port_mask
= 0xf,
3469 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3470 .ops
= &mv88e6165_ops
,
3474 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6171
,
3475 .family
= MV88E6XXX_FAMILY_6351
,
3476 .name
= "Marvell 88E6171",
3477 .num_databases
= 4096,
3480 .port_base_addr
= 0x10,
3481 .global1_addr
= 0x1b,
3482 .global2_addr
= 0x1c,
3483 .age_time_coeff
= 15000,
3486 .atu_move_port_mask
= 0xf,
3489 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3490 .ops
= &mv88e6171_ops
,
3494 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6172
,
3495 .family
= MV88E6XXX_FAMILY_6352
,
3496 .name
= "Marvell 88E6172",
3497 .num_databases
= 4096,
3501 .port_base_addr
= 0x10,
3502 .global1_addr
= 0x1b,
3503 .global2_addr
= 0x1c,
3504 .age_time_coeff
= 15000,
3507 .atu_move_port_mask
= 0xf,
3510 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3511 .ops
= &mv88e6172_ops
,
3515 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6175
,
3516 .family
= MV88E6XXX_FAMILY_6351
,
3517 .name
= "Marvell 88E6175",
3518 .num_databases
= 4096,
3521 .port_base_addr
= 0x10,
3522 .global1_addr
= 0x1b,
3523 .global2_addr
= 0x1c,
3524 .age_time_coeff
= 15000,
3527 .atu_move_port_mask
= 0xf,
3530 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3531 .ops
= &mv88e6175_ops
,
3535 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6176
,
3536 .family
= MV88E6XXX_FAMILY_6352
,
3537 .name
= "Marvell 88E6176",
3538 .num_databases
= 4096,
3542 .port_base_addr
= 0x10,
3543 .global1_addr
= 0x1b,
3544 .global2_addr
= 0x1c,
3545 .age_time_coeff
= 15000,
3548 .atu_move_port_mask
= 0xf,
3551 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3552 .ops
= &mv88e6176_ops
,
3556 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6185
,
3557 .family
= MV88E6XXX_FAMILY_6185
,
3558 .name
= "Marvell 88E6185",
3559 .num_databases
= 256,
3562 .port_base_addr
= 0x10,
3563 .global1_addr
= 0x1b,
3564 .global2_addr
= 0x1c,
3565 .age_time_coeff
= 15000,
3567 .atu_move_port_mask
= 0xf,
3569 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3570 .ops
= &mv88e6185_ops
,
3574 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190
,
3575 .family
= MV88E6XXX_FAMILY_6390
,
3576 .name
= "Marvell 88E6190",
3577 .num_databases
= 4096,
3578 .num_ports
= 11, /* 10 + Z80 */
3581 .port_base_addr
= 0x0,
3582 .global1_addr
= 0x1b,
3583 .global2_addr
= 0x1c,
3584 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3585 .age_time_coeff
= 3750,
3590 .atu_move_port_mask
= 0x1f,
3591 .ops
= &mv88e6190_ops
,
3595 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6190X
,
3596 .family
= MV88E6XXX_FAMILY_6390
,
3597 .name
= "Marvell 88E6190X",
3598 .num_databases
= 4096,
3599 .num_ports
= 11, /* 10 + Z80 */
3602 .port_base_addr
= 0x0,
3603 .global1_addr
= 0x1b,
3604 .global2_addr
= 0x1c,
3605 .age_time_coeff
= 3750,
3608 .atu_move_port_mask
= 0x1f,
3611 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3612 .ops
= &mv88e6190x_ops
,
3616 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6191
,
3617 .family
= MV88E6XXX_FAMILY_6390
,
3618 .name
= "Marvell 88E6191",
3619 .num_databases
= 4096,
3620 .num_ports
= 11, /* 10 + Z80 */
3622 .port_base_addr
= 0x0,
3623 .global1_addr
= 0x1b,
3624 .global2_addr
= 0x1c,
3625 .age_time_coeff
= 3750,
3628 .atu_move_port_mask
= 0x1f,
3631 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3632 .ptp_support
= true,
3633 .ops
= &mv88e6191_ops
,
3637 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6240
,
3638 .family
= MV88E6XXX_FAMILY_6352
,
3639 .name
= "Marvell 88E6240",
3640 .num_databases
= 4096,
3644 .port_base_addr
= 0x10,
3645 .global1_addr
= 0x1b,
3646 .global2_addr
= 0x1c,
3647 .age_time_coeff
= 15000,
3650 .atu_move_port_mask
= 0xf,
3653 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3654 .ptp_support
= true,
3655 .ops
= &mv88e6240_ops
,
3659 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6290
,
3660 .family
= MV88E6XXX_FAMILY_6390
,
3661 .name
= "Marvell 88E6290",
3662 .num_databases
= 4096,
3663 .num_ports
= 11, /* 10 + Z80 */
3666 .port_base_addr
= 0x0,
3667 .global1_addr
= 0x1b,
3668 .global2_addr
= 0x1c,
3669 .age_time_coeff
= 3750,
3672 .atu_move_port_mask
= 0x1f,
3675 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3676 .ptp_support
= true,
3677 .ops
= &mv88e6290_ops
,
3681 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6320
,
3682 .family
= MV88E6XXX_FAMILY_6320
,
3683 .name
= "Marvell 88E6320",
3684 .num_databases
= 4096,
3688 .port_base_addr
= 0x10,
3689 .global1_addr
= 0x1b,
3690 .global2_addr
= 0x1c,
3691 .age_time_coeff
= 15000,
3693 .atu_move_port_mask
= 0xf,
3696 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3697 .ptp_support
= true,
3698 .ops
= &mv88e6320_ops
,
3702 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6321
,
3703 .family
= MV88E6XXX_FAMILY_6320
,
3704 .name
= "Marvell 88E6321",
3705 .num_databases
= 4096,
3709 .port_base_addr
= 0x10,
3710 .global1_addr
= 0x1b,
3711 .global2_addr
= 0x1c,
3712 .age_time_coeff
= 15000,
3714 .atu_move_port_mask
= 0xf,
3716 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3717 .ptp_support
= true,
3718 .ops
= &mv88e6321_ops
,
3722 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6341
,
3723 .family
= MV88E6XXX_FAMILY_6341
,
3724 .name
= "Marvell 88E6341",
3725 .num_databases
= 4096,
3729 .port_base_addr
= 0x10,
3730 .global1_addr
= 0x1b,
3731 .global2_addr
= 0x1c,
3732 .age_time_coeff
= 3750,
3733 .atu_move_port_mask
= 0x1f,
3738 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3739 .ptp_support
= true,
3740 .ops
= &mv88e6341_ops
,
3744 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6350
,
3745 .family
= MV88E6XXX_FAMILY_6351
,
3746 .name
= "Marvell 88E6350",
3747 .num_databases
= 4096,
3750 .port_base_addr
= 0x10,
3751 .global1_addr
= 0x1b,
3752 .global2_addr
= 0x1c,
3753 .age_time_coeff
= 15000,
3756 .atu_move_port_mask
= 0xf,
3759 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3760 .ops
= &mv88e6350_ops
,
3764 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6351
,
3765 .family
= MV88E6XXX_FAMILY_6351
,
3766 .name
= "Marvell 88E6351",
3767 .num_databases
= 4096,
3770 .port_base_addr
= 0x10,
3771 .global1_addr
= 0x1b,
3772 .global2_addr
= 0x1c,
3773 .age_time_coeff
= 15000,
3776 .atu_move_port_mask
= 0xf,
3779 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3780 .ops
= &mv88e6351_ops
,
3784 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6352
,
3785 .family
= MV88E6XXX_FAMILY_6352
,
3786 .name
= "Marvell 88E6352",
3787 .num_databases
= 4096,
3791 .port_base_addr
= 0x10,
3792 .global1_addr
= 0x1b,
3793 .global2_addr
= 0x1c,
3794 .age_time_coeff
= 15000,
3797 .atu_move_port_mask
= 0xf,
3800 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3801 .ptp_support
= true,
3802 .ops
= &mv88e6352_ops
,
3805 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390
,
3806 .family
= MV88E6XXX_FAMILY_6390
,
3807 .name
= "Marvell 88E6390",
3808 .num_databases
= 4096,
3809 .num_ports
= 11, /* 10 + Z80 */
3812 .port_base_addr
= 0x0,
3813 .global1_addr
= 0x1b,
3814 .global2_addr
= 0x1c,
3815 .age_time_coeff
= 3750,
3818 .atu_move_port_mask
= 0x1f,
3821 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3822 .ptp_support
= true,
3823 .ops
= &mv88e6390_ops
,
3826 .prod_num
= MV88E6XXX_PORT_SWITCH_ID_PROD_6390X
,
3827 .family
= MV88E6XXX_FAMILY_6390
,
3828 .name
= "Marvell 88E6390X",
3829 .num_databases
= 4096,
3830 .num_ports
= 11, /* 10 + Z80 */
3833 .port_base_addr
= 0x0,
3834 .global1_addr
= 0x1b,
3835 .global2_addr
= 0x1c,
3836 .age_time_coeff
= 3750,
3839 .atu_move_port_mask
= 0x1f,
3842 .tag_protocol
= DSA_TAG_PROTO_DSA
,
3843 .ptp_support
= true,
3844 .ops
= &mv88e6390x_ops
,
3848 static const struct mv88e6xxx_info
*mv88e6xxx_lookup_info(unsigned int prod_num
)
3852 for (i
= 0; i
< ARRAY_SIZE(mv88e6xxx_table
); ++i
)
3853 if (mv88e6xxx_table
[i
].prod_num
== prod_num
)
3854 return &mv88e6xxx_table
[i
];
3859 static int mv88e6xxx_detect(struct mv88e6xxx_chip
*chip
)
3861 const struct mv88e6xxx_info
*info
;
3862 unsigned int prod_num
, rev
;
3866 mutex_lock(&chip
->reg_lock
);
3867 err
= mv88e6xxx_port_read(chip
, 0, MV88E6XXX_PORT_SWITCH_ID
, &id
);
3868 mutex_unlock(&chip
->reg_lock
);
3872 prod_num
= id
& MV88E6XXX_PORT_SWITCH_ID_PROD_MASK
;
3873 rev
= id
& MV88E6XXX_PORT_SWITCH_ID_REV_MASK
;
3875 info
= mv88e6xxx_lookup_info(prod_num
);
3879 /* Update the compatible info with the probed one */
3882 err
= mv88e6xxx_g2_require(chip
);
3886 dev_info(chip
->dev
, "switch 0x%x detected: %s, revision %u\n",
3887 chip
->info
->prod_num
, chip
->info
->name
, rev
);
3892 static struct mv88e6xxx_chip
*mv88e6xxx_alloc_chip(struct device
*dev
)
3894 struct mv88e6xxx_chip
*chip
;
3896 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
3902 mutex_init(&chip
->reg_lock
);
3903 INIT_LIST_HEAD(&chip
->mdios
);
3908 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip
*chip
,
3909 struct mii_bus
*bus
, int sw_addr
)
3912 chip
->smi_ops
= &mv88e6xxx_smi_single_chip_ops
;
3913 else if (chip
->info
->multi_chip
)
3914 chip
->smi_ops
= &mv88e6xxx_smi_multi_chip_ops
;
3919 chip
->sw_addr
= sw_addr
;
3924 static enum dsa_tag_protocol
mv88e6xxx_get_tag_protocol(struct dsa_switch
*ds
,
3927 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3929 return chip
->info
->tag_protocol
;
3932 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3933 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3934 struct device
*host_dev
, int sw_addr
,
3937 struct mv88e6xxx_chip
*chip
;
3938 struct mii_bus
*bus
;
3941 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3945 chip
= mv88e6xxx_alloc_chip(dsa_dev
);
3949 /* Legacy SMI probing will only support chips similar to 88E6085 */
3950 chip
->info
= &mv88e6xxx_table
[MV88E6085
];
3952 err
= mv88e6xxx_smi_init(chip
, bus
, sw_addr
);
3956 err
= mv88e6xxx_detect(chip
);
3960 mutex_lock(&chip
->reg_lock
);
3961 err
= mv88e6xxx_switch_reset(chip
);
3962 mutex_unlock(&chip
->reg_lock
);
3966 mv88e6xxx_phy_init(chip
);
3968 err
= mv88e6xxx_mdios_register(chip
, NULL
);
3974 return chip
->info
->name
;
3976 devm_kfree(dsa_dev
, chip
);
3982 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch
*ds
, int port
,
3983 const struct switchdev_obj_port_mdb
*mdb
)
3985 /* We don't need any dynamic resource from the kernel (yet),
3986 * so skip the prepare phase.
3992 static void mv88e6xxx_port_mdb_add(struct dsa_switch
*ds
, int port
,
3993 const struct switchdev_obj_port_mdb
*mdb
)
3995 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3997 mutex_lock(&chip
->reg_lock
);
3998 if (mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3999 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC
))
4000 dev_err(ds
->dev
, "p%d: failed to load multicast MAC address\n",
4002 mutex_unlock(&chip
->reg_lock
);
4005 static int mv88e6xxx_port_mdb_del(struct dsa_switch
*ds
, int port
,
4006 const struct switchdev_obj_port_mdb
*mdb
)
4008 struct mv88e6xxx_chip
*chip
= ds
->priv
;
4011 mutex_lock(&chip
->reg_lock
);
4012 err
= mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
4013 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED
);
4014 mutex_unlock(&chip
->reg_lock
);
4019 static const struct dsa_switch_ops mv88e6xxx_switch_ops
= {
4020 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4021 .probe
= mv88e6xxx_drv_probe
,
4023 .get_tag_protocol
= mv88e6xxx_get_tag_protocol
,
4024 .setup
= mv88e6xxx_setup
,
4025 .adjust_link
= mv88e6xxx_adjust_link
,
4026 .get_strings
= mv88e6xxx_get_strings
,
4027 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
4028 .get_sset_count
= mv88e6xxx_get_sset_count
,
4029 .port_enable
= mv88e6xxx_port_enable
,
4030 .port_disable
= mv88e6xxx_port_disable
,
4031 .get_mac_eee
= mv88e6xxx_get_mac_eee
,
4032 .set_mac_eee
= mv88e6xxx_set_mac_eee
,
4033 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
4034 .get_eeprom
= mv88e6xxx_get_eeprom
,
4035 .set_eeprom
= mv88e6xxx_set_eeprom
,
4036 .get_regs_len
= mv88e6xxx_get_regs_len
,
4037 .get_regs
= mv88e6xxx_get_regs
,
4038 .set_ageing_time
= mv88e6xxx_set_ageing_time
,
4039 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
4040 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
4041 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
4042 .port_fast_age
= mv88e6xxx_port_fast_age
,
4043 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
4044 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
4045 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
4046 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
4047 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
4048 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
4049 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
4050 .port_mdb_prepare
= mv88e6xxx_port_mdb_prepare
,
4051 .port_mdb_add
= mv88e6xxx_port_mdb_add
,
4052 .port_mdb_del
= mv88e6xxx_port_mdb_del
,
4053 .crosschip_bridge_join
= mv88e6xxx_crosschip_bridge_join
,
4054 .crosschip_bridge_leave
= mv88e6xxx_crosschip_bridge_leave
,
4055 .port_hwtstamp_set
= mv88e6xxx_port_hwtstamp_set
,
4056 .port_hwtstamp_get
= mv88e6xxx_port_hwtstamp_get
,
4057 .port_txtstamp
= mv88e6xxx_port_txtstamp
,
4058 .port_rxtstamp
= mv88e6xxx_port_rxtstamp
,
4059 .get_ts_info
= mv88e6xxx_get_ts_info
,
4062 static struct dsa_switch_driver mv88e6xxx_switch_drv
= {
4063 .ops
= &mv88e6xxx_switch_ops
,
4066 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip
*chip
)
4068 struct device
*dev
= chip
->dev
;
4069 struct dsa_switch
*ds
;
4071 ds
= dsa_switch_alloc(dev
, mv88e6xxx_num_ports(chip
));
4076 ds
->ops
= &mv88e6xxx_switch_ops
;
4077 ds
->ageing_time_min
= chip
->info
->age_time_coeff
;
4078 ds
->ageing_time_max
= chip
->info
->age_time_coeff
* U8_MAX
;
4080 dev_set_drvdata(dev
, ds
);
4082 return dsa_register_switch(ds
);
4085 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip
*chip
)
4087 dsa_unregister_switch(chip
->ds
);
4090 static int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
4092 struct device
*dev
= &mdiodev
->dev
;
4093 struct device_node
*np
= dev
->of_node
;
4094 const struct mv88e6xxx_info
*compat_info
;
4095 struct mv88e6xxx_chip
*chip
;
4099 compat_info
= of_device_get_match_data(dev
);
4103 chip
= mv88e6xxx_alloc_chip(dev
);
4107 chip
->info
= compat_info
;
4109 err
= mv88e6xxx_smi_init(chip
, mdiodev
->bus
, mdiodev
->addr
);
4113 chip
->reset
= devm_gpiod_get_optional(dev
, "reset", GPIOD_OUT_LOW
);
4114 if (IS_ERR(chip
->reset
))
4115 return PTR_ERR(chip
->reset
);
4117 err
= mv88e6xxx_detect(chip
);
4121 mv88e6xxx_phy_init(chip
);
4123 if (chip
->info
->ops
->get_eeprom
&&
4124 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
4125 chip
->eeprom_len
= eeprom_len
;
4127 mutex_lock(&chip
->reg_lock
);
4128 err
= mv88e6xxx_switch_reset(chip
);
4129 mutex_unlock(&chip
->reg_lock
);
4133 chip
->irq
= of_irq_get(np
, 0);
4134 if (chip
->irq
== -EPROBE_DEFER
) {
4139 /* Has to be performed before the MDIO bus is created, because
4140 * the PHYs will link there interrupts to these interrupt
4143 mutex_lock(&chip
->reg_lock
);
4145 err
= mv88e6xxx_g1_irq_setup(chip
);
4147 err
= mv88e6xxx_irq_poll_setup(chip
);
4148 mutex_unlock(&chip
->reg_lock
);
4153 if (chip
->info
->g2_irqs
> 0) {
4154 err
= mv88e6xxx_g2_irq_setup(chip
);
4159 err
= mv88e6xxx_g1_atu_prob_irq_setup(chip
);
4163 err
= mv88e6xxx_g1_vtu_prob_irq_setup(chip
);
4165 goto out_g1_atu_prob_irq
;
4167 err
= mv88e6xxx_mdios_register(chip
, np
);
4169 goto out_g1_vtu_prob_irq
;
4171 err
= mv88e6xxx_register_switch(chip
);
4178 mv88e6xxx_mdios_unregister(chip
);
4179 out_g1_vtu_prob_irq
:
4180 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4181 out_g1_atu_prob_irq
:
4182 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4184 if (chip
->info
->g2_irqs
> 0)
4185 mv88e6xxx_g2_irq_free(chip
);
4187 mutex_lock(&chip
->reg_lock
);
4189 mv88e6xxx_g1_irq_free(chip
);
4191 mv88e6xxx_irq_poll_free(chip
);
4192 mutex_unlock(&chip
->reg_lock
);
4197 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
4199 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
4200 struct mv88e6xxx_chip
*chip
= ds
->priv
;
4202 if (chip
->info
->ptp_support
) {
4203 mv88e6xxx_hwtstamp_free(chip
);
4204 mv88e6xxx_ptp_free(chip
);
4207 mv88e6xxx_phy_destroy(chip
);
4208 mv88e6xxx_unregister_switch(chip
);
4209 mv88e6xxx_mdios_unregister(chip
);
4211 mv88e6xxx_g1_vtu_prob_irq_free(chip
);
4212 mv88e6xxx_g1_atu_prob_irq_free(chip
);
4214 if (chip
->info
->g2_irqs
> 0)
4215 mv88e6xxx_g2_irq_free(chip
);
4217 mutex_lock(&chip
->reg_lock
);
4219 mv88e6xxx_g1_irq_free(chip
);
4221 mv88e6xxx_irq_poll_free(chip
);
4222 mutex_unlock(&chip
->reg_lock
);
4225 static const struct of_device_id mv88e6xxx_of_match
[] = {
4227 .compatible
= "marvell,mv88e6085",
4228 .data
= &mv88e6xxx_table
[MV88E6085
],
4231 .compatible
= "marvell,mv88e6190",
4232 .data
= &mv88e6xxx_table
[MV88E6190
],
4237 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
4239 static struct mdio_driver mv88e6xxx_driver
= {
4240 .probe
= mv88e6xxx_probe
,
4241 .remove
= mv88e6xxx_remove
,
4243 .name
= "mv88e6085",
4244 .of_match_table
= mv88e6xxx_of_match
,
4248 static int __init
mv88e6xxx_init(void)
4250 register_switch_driver(&mv88e6xxx_switch_drv
);
4251 return mdio_driver_register(&mv88e6xxx_driver
);
4253 module_init(mv88e6xxx_init
);
4255 static void __exit
mv88e6xxx_cleanup(void)
4257 mdio_driver_unregister(&mv88e6xxx_driver
);
4258 unregister_switch_driver(&mv88e6xxx_switch_drv
);
4260 module_exit(mv88e6xxx_cleanup
);
4262 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4263 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4264 MODULE_LICENSE("GPL");