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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/net/dsa/mv88e6xxx/global1.h
2 * Marvell 88E6xxx Switch Global (1) Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #ifndef _MV88E6XXX_GLOBAL1_H
16 #define _MV88E6XXX_GLOBAL1_H
20 /* Offset 0x00: Switch Global Status Register */
21 #define MV88E6XXX_G1_STS 0x00
22 #define MV88E6352_G1_STS_PPU_STATE 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
24 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
25 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
26 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
27 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
28 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
29 #define MV88E6XXX_G1_STS_IRQ_AVB 8
30 #define MV88E6XXX_G1_STS_IRQ_DEVICE 7
31 #define MV88E6XXX_G1_STS_IRQ_STATS 6
32 #define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5
33 #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
34 #define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3
35 #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
36 #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
37 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
39 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
40 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
41 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
43 #define MV88E6XXX_G1_MAC_01 0x01
44 #define MV88E6XXX_G1_MAC_23 0x02
45 #define MV88E6XXX_G1_MAC_45 0x03
47 /* Offset 0x01: ATU FID Register */
48 #define MV88E6352_G1_ATU_FID 0x01
50 /* Offset 0x02: VTU FID Register */
51 #define MV88E6352_G1_VTU_FID 0x02
52 #define MV88E6352_G1_VTU_FID_MASK 0x0fff
54 /* Offset 0x03: VTU SID Register */
55 #define MV88E6352_G1_VTU_SID 0x03
56 #define MV88E6352_G1_VTU_SID_MASK 0x3f
58 /* Offset 0x04: Switch Global Control Register */
59 #define MV88E6XXX_G1_CTL1 0x04
60 #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
61 #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
62 #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
63 #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
64 #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
65 #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
66 #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
67 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
68 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
69 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
70 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
71 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
72 #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
73 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
75 /* Offset 0x05: VTU Operation Register */
76 #define MV88E6XXX_G1_VTU_OP 0x05
77 #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
78 #define MV88E6XXX_G1_VTU_OP_MASK 0x7000
79 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
80 #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
81 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
82 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
83 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
84 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
85 #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
86 #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)
87 #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)
88 #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
90 /* Offset 0x06: VTU VID Register */
91 #define MV88E6XXX_G1_VTU_VID 0x06
92 #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
93 #define MV88E6390_G1_VTU_VID_PAGE 0x2000
94 #define MV88E6XXX_G1_VTU_VID_VALID 0x1000
96 /* Offset 0x07: VTU/STU Data Register 1
97 * Offset 0x08: VTU/STU Data Register 2
98 * Offset 0x09: VTU/STU Data Register 3
100 #define MV88E6XXX_G1_VTU_DATA1 0x07
101 #define MV88E6XXX_G1_VTU_DATA2 0x08
102 #define MV88E6XXX_G1_VTU_DATA3 0x09
103 #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
104 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
105 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
106 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
107 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
108 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
109 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
110 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
111 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
113 /* Offset 0x0A: ATU Control Register */
114 #define MV88E6XXX_G1_ATU_CTL 0x0a
115 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
117 /* Offset 0x0B: ATU Operation Register */
118 #define MV88E6XXX_G1_ATU_OP 0x0b
119 #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
120 #define MV88E6XXX_G1_ATU_OP_MASK 0x7000
121 #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
124 #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
125 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
126 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
127 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
128 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
129 #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7)
130 #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6)
131 #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5)
132 #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4)
134 /* Offset 0x0C: ATU Data Register */
135 #define MV88E6XXX_G1_ATU_DATA 0x0c
136 #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
137 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
138 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
139 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
140 #define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000
141 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d
142 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
143 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER 0x000f
144 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE 0x0005
145 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
146 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT 0x000e
147 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER 0x000f
149 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
150 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
151 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
153 #define MV88E6XXX_G1_ATU_MAC01 0x0d
154 #define MV88E6XXX_G1_ATU_MAC23 0x0e
155 #define MV88E6XXX_G1_ATU_MAC45 0x0f
157 /* Offset 0x10: IP-PRI Mapping Register 0
158 * Offset 0x11: IP-PRI Mapping Register 1
159 * Offset 0x12: IP-PRI Mapping Register 2
160 * Offset 0x13: IP-PRI Mapping Register 3
161 * Offset 0x14: IP-PRI Mapping Register 4
162 * Offset 0x15: IP-PRI Mapping Register 5
163 * Offset 0x16: IP-PRI Mapping Register 6
164 * Offset 0x17: IP-PRI Mapping Register 7
166 #define MV88E6XXX_G1_IP_PRI_0 0x10
167 #define MV88E6XXX_G1_IP_PRI_1 0x11
168 #define MV88E6XXX_G1_IP_PRI_2 0x12
169 #define MV88E6XXX_G1_IP_PRI_3 0x13
170 #define MV88E6XXX_G1_IP_PRI_4 0x14
171 #define MV88E6XXX_G1_IP_PRI_5 0x15
172 #define MV88E6XXX_G1_IP_PRI_6 0x16
173 #define MV88E6XXX_G1_IP_PRI_7 0x17
175 /* Offset 0x18: IEEE-PRI Register */
176 #define MV88E6XXX_G1_IEEE_PRI 0x18
178 /* Offset 0x19: Core Tag Type */
179 #define MV88E6185_G1_CORE_TAG_TYPE 0x19
181 /* Offset 0x1A: Monitor Control */
182 #define MV88E6185_G1_MONITOR_CTL 0x1a
183 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
184 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
185 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
186 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
187 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
189 /* Offset 0x1A: Monitor & MGMT Control Register */
190 #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
191 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
192 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
193 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
194 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
195 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO 0x0200
196 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI 0x0300
197 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
198 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
199 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
200 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
202 /* Offset 0x1C: Global Control 2 */
203 #define MV88E6XXX_G1_CTL2 0x1c
204 #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
205 #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
206 #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
207 #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000
208 #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000
209 #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000
210 #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000
211 #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
212 #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
213 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
214 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
215 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
216 #define MV88E6085_G1_CTL2_DA_CHECK 0x4000
217 #define MV88E6085_G1_CTL2_P10RM 0x2000
218 #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
219 #define MV88E6352_G1_CTL2_DA_CHECK 0x0800
220 #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
221 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
222 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
223 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
224 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
225 #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
226 #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
227 #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0
228 #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040
229 #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080
230 #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060
231 #define MV88E6390_G1_CTL2_CTR_MODE 0x0020
232 #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
234 /* Offset 0x1D: Stats Operation Register */
235 #define MV88E6XXX_G1_STATS_OP 0x1d
236 #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
237 #define MV88E6XXX_G1_STATS_OP_NOP 0x0000
238 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
239 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
240 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
241 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
242 #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
243 #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
244 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
245 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
246 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
248 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
249 * Offset 0x1F: Stats Counter Register Bytes 1 & 0
251 #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
252 #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
254 int mv88e6xxx_g1_read(struct mv88e6xxx_chip
*chip
, int reg
, u16
*val
);
255 int mv88e6xxx_g1_write(struct mv88e6xxx_chip
*chip
, int reg
, u16 val
);
256 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip
*chip
, int reg
, u16 mask
);
258 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip
*chip
, u8
*addr
);
260 int mv88e6185_g1_reset(struct mv88e6xxx_chip
*chip
);
261 int mv88e6352_g1_reset(struct mv88e6xxx_chip
*chip
);
263 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip
*chip
);
264 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip
*chip
);
266 int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip
*chip
);
267 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
);
268 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
);
269 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
);
270 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip
*chip
);
271 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip
*chip
);
272 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip
*chip
, int stat
, u32
*val
);
273 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip
*chip
);
274 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip
*chip
, int port
);
275 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip
*chip
, int port
);
276 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip
*chip
, int port
);
277 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip
*chip
, int port
);
278 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip
*chip
);
280 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip
*chip
);
281 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip
*chip
);
283 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip
*chip
, int port
);
285 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip
*chip
);
286 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip
*chip
);
287 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip
*chip
);
289 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip
*chip
, int index
);
291 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip
*chip
, bool learn2all
);
292 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip
*chip
,
294 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip
*chip
, u16 fid
,
295 struct mv88e6xxx_atu_entry
*entry
);
296 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip
*chip
, u16 fid
,
297 struct mv88e6xxx_atu_entry
*entry
);
298 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip
*chip
, u16 fid
, bool all
);
299 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip
*chip
, u16 fid
, int port
,
301 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip
*chip
);
302 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip
*chip
);
304 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip
*chip
,
305 struct mv88e6xxx_vtu_entry
*entry
);
306 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
307 struct mv88e6xxx_vtu_entry
*entry
);
308 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip
*chip
,
309 struct mv88e6xxx_vtu_entry
*entry
);
310 int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
311 struct mv88e6xxx_vtu_entry
*entry
);
312 int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip
*chip
,
313 struct mv88e6xxx_vtu_entry
*entry
);
314 int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
315 struct mv88e6xxx_vtu_entry
*entry
);
316 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip
*chip
);
317 int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip
*chip
);
318 void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip
*chip
);
320 #endif /* _MV88E6XXX_GLOBAL1_H */