2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/phy.h>
20 int mv88e6xxx_port_read(struct mv88e6xxx_chip
*chip
, int port
, int reg
,
23 int addr
= chip
->info
->port_base_addr
+ port
;
25 return mv88e6xxx_read(chip
, addr
, reg
, val
);
28 int mv88e6xxx_port_write(struct mv88e6xxx_chip
*chip
, int port
, int reg
,
31 int addr
= chip
->info
->port_base_addr
+ port
;
33 return mv88e6xxx_write(chip
, addr
, reg
, val
);
36 /* Offset 0x01: MAC (or PCS or Physical) Control Register
38 * Link, Duplex and Flow Control have one force bit, one value bit.
40 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
41 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
42 * Newer chips need a ForcedSpd bit 13 set to consider the value.
45 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
51 err
= mv88e6xxx_port_read(chip
, port
, PORT_PCS_CTRL
, ®
);
55 reg
&= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
56 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
59 case PHY_INTERFACE_MODE_RGMII_RXID
:
60 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
62 case PHY_INTERFACE_MODE_RGMII_TXID
:
63 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
65 case PHY_INTERFACE_MODE_RGMII_ID
:
66 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
67 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
69 case PHY_INTERFACE_MODE_RGMII
:
75 err
= mv88e6xxx_port_write(chip
, port
, PORT_PCS_CTRL
, reg
);
79 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "delay RXCLK %s, TXCLK %s\n",
80 reg
& PORT_PCS_CTRL_RGMII_DELAY_RXCLK
? "yes" : "no",
81 reg
& PORT_PCS_CTRL_RGMII_DELAY_TXCLK
? "yes" : "no");
86 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
92 return mv88e6xxx_port_set_rgmii_delay(chip
, port
, mode
);
95 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
101 return mv88e6xxx_port_set_rgmii_delay(chip
, port
, mode
);
104 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip
*chip
, int port
, int link
)
109 err
= mv88e6xxx_port_read(chip
, port
, PORT_PCS_CTRL
, ®
);
113 reg
&= ~(PORT_PCS_CTRL_FORCE_LINK
| PORT_PCS_CTRL_LINK_UP
);
116 case LINK_FORCED_DOWN
:
117 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
120 reg
|= PORT_PCS_CTRL_FORCE_LINK
| PORT_PCS_CTRL_LINK_UP
;
123 /* normal link detection */
129 err
= mv88e6xxx_port_write(chip
, port
, PORT_PCS_CTRL
, reg
);
133 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "%s link %s\n",
134 reg
& PORT_PCS_CTRL_FORCE_LINK
? "Force" : "Unforce",
135 reg
& PORT_PCS_CTRL_LINK_UP
? "up" : "down");
140 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip
*chip
, int port
, int dup
)
145 err
= mv88e6xxx_port_read(chip
, port
, PORT_PCS_CTRL
, ®
);
149 reg
&= ~(PORT_PCS_CTRL_FORCE_DUPLEX
| PORT_PCS_CTRL_DUPLEX_FULL
);
153 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
156 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
| PORT_PCS_CTRL_DUPLEX_FULL
;
158 case DUPLEX_UNFORCED
:
159 /* normal duplex detection */
165 err
= mv88e6xxx_port_write(chip
, port
, PORT_PCS_CTRL
, reg
);
169 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "%s %s duplex\n",
170 reg
& PORT_PCS_CTRL_FORCE_DUPLEX
? "Force" : "Unforce",
171 reg
& PORT_PCS_CTRL_DUPLEX_FULL
? "full" : "half");
176 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
,
177 int speed
, bool alt_bit
, bool force_bit
)
184 ctrl
= PORT_PCS_CTRL_SPEED_10
;
187 ctrl
= PORT_PCS_CTRL_SPEED_100
;
191 ctrl
= PORT_PCS_CTRL_SPEED_100
| PORT_PCS_CTRL_ALTSPEED
;
193 ctrl
= PORT_PCS_CTRL_SPEED_200
;
196 ctrl
= PORT_PCS_CTRL_SPEED_1000
;
199 ctrl
= PORT_PCS_CTRL_SPEED_10000
| PORT_PCS_CTRL_ALTSPEED
;
202 /* all bits set, fall through... */
204 ctrl
= PORT_PCS_CTRL_SPEED_UNFORCED
;
210 err
= mv88e6xxx_port_read(chip
, port
, PORT_PCS_CTRL
, ®
);
214 reg
&= ~PORT_PCS_CTRL_SPEED_MASK
;
216 reg
&= ~PORT_PCS_CTRL_ALTSPEED
;
218 reg
&= ~PORT_PCS_CTRL_FORCE_SPEED
;
219 if (speed
!= SPEED_UNFORCED
)
220 ctrl
|= PORT_PCS_CTRL_FORCE_SPEED
;
224 err
= mv88e6xxx_port_write(chip
, port
, PORT_PCS_CTRL
, reg
);
229 netdev_dbg(chip
->ds
->ports
[port
].netdev
,
230 "Speed set to %d Mbps\n", speed
);
232 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "Speed unforced\n");
237 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
238 int mv88e6065_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
240 if (speed
== SPEED_MAX
)
246 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
247 return mv88e6xxx_port_set_speed(chip
, port
, speed
, false, false);
250 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
251 int mv88e6185_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
253 if (speed
== SPEED_MAX
)
256 if (speed
== 200 || speed
> 1000)
259 return mv88e6xxx_port_set_speed(chip
, port
, speed
, false, false);
262 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
263 int mv88e6352_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
265 if (speed
== SPEED_MAX
)
271 if (speed
== 200 && port
< 5)
274 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, false);
277 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
278 int mv88e6390_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
280 if (speed
== SPEED_MAX
)
281 speed
= port
< 9 ? 1000 : 2500;
286 if (speed
== 200 && port
!= 0)
289 if (speed
== 2500 && port
< 9)
292 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, true);
295 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
296 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
298 if (speed
== SPEED_MAX
)
299 speed
= port
< 9 ? 1000 : 10000;
301 if (speed
== 200 && port
!= 0)
304 if (speed
>= 2500 && port
< 9)
307 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, true);
310 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip
*chip
, int port
,
311 phy_interface_t mode
)
317 if (mode
== PHY_INTERFACE_MODE_NA
)
320 if (port
!= 9 && port
!= 10)
324 case PHY_INTERFACE_MODE_1000BASEX
:
325 cmode
= PORT_STATUS_CMODE_1000BASE_X
;
327 case PHY_INTERFACE_MODE_SGMII
:
328 cmode
= PORT_STATUS_CMODE_SGMII
;
330 case PHY_INTERFACE_MODE_2500BASEX
:
331 cmode
= PORT_STATUS_CMODE_2500BASEX
;
333 case PHY_INTERFACE_MODE_XGMII
:
334 cmode
= PORT_STATUS_CMODE_XAUI
;
336 case PHY_INTERFACE_MODE_RXAUI
:
337 cmode
= PORT_STATUS_CMODE_RXAUI
;
344 err
= mv88e6xxx_port_read(chip
, port
, PORT_STATUS
, ®
);
348 reg
&= ~PORT_STATUS_CMODE_MASK
;
351 err
= mv88e6xxx_port_write(chip
, port
, PORT_STATUS
, reg
);
359 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip
*chip
, int port
, u8
*cmode
)
364 err
= mv88e6xxx_port_read(chip
, port
, PORT_STATUS
, ®
);
368 *cmode
= reg
& PORT_STATUS_CMODE_MASK
;
373 /* Offset 0x02: Pause Control
375 * Do not limit the period of time that this port can be paused for by
376 * the remote end or the period of time that this port can pause the
379 int mv88e6097_port_pause_config(struct mv88e6xxx_chip
*chip
, int port
)
381 return mv88e6xxx_port_write(chip
, port
, PORT_PAUSE_CTRL
, 0x0000);
384 int mv88e6390_port_pause_config(struct mv88e6xxx_chip
*chip
, int port
)
388 err
= mv88e6xxx_port_write(chip
, port
, PORT_PAUSE_CTRL
,
389 PORT_FLOW_CTRL_LIMIT_IN
| 0);
393 return mv88e6xxx_port_write(chip
, port
, PORT_PAUSE_CTRL
,
394 PORT_FLOW_CTRL_LIMIT_OUT
| 0);
397 /* Offset 0x04: Port Control Register */
399 static const char * const mv88e6xxx_port_state_names
[] = {
400 [PORT_CONTROL_STATE_DISABLED
] = "Disabled",
401 [PORT_CONTROL_STATE_BLOCKING
] = "Blocking/Listening",
402 [PORT_CONTROL_STATE_LEARNING
] = "Learning",
403 [PORT_CONTROL_STATE_FORWARDING
] = "Forwarding",
406 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip
*chip
, int port
, u8 state
)
411 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
415 reg
&= ~PORT_CONTROL_STATE_MASK
;
418 err
= mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
422 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "PortState set to %s\n",
423 mv88e6xxx_port_state_names
[state
]);
428 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip
*chip
, int port
,
434 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
438 reg
&= ~PORT_CONTROL_EGRESS_MASK
;
441 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
444 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip
*chip
, int port
,
445 enum mv88e6xxx_frame_mode mode
)
450 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
454 reg
&= ~PORT_CONTROL_FRAME_MASK
;
457 case MV88E6XXX_FRAME_MODE_NORMAL
:
458 reg
|= PORT_CONTROL_FRAME_MODE_NORMAL
;
460 case MV88E6XXX_FRAME_MODE_DSA
:
461 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
467 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
470 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip
*chip
, int port
,
471 enum mv88e6xxx_frame_mode mode
)
476 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
480 reg
&= ~PORT_CONTROL_FRAME_MASK
;
483 case MV88E6XXX_FRAME_MODE_NORMAL
:
484 reg
|= PORT_CONTROL_FRAME_MODE_NORMAL
;
486 case MV88E6XXX_FRAME_MODE_DSA
:
487 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
489 case MV88E6XXX_FRAME_MODE_PROVIDER
:
490 reg
|= PORT_CONTROL_FRAME_MODE_PROVIDER
;
492 case MV88E6XXX_FRAME_MODE_ETHERTYPE
:
493 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
;
499 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
502 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip
*chip
,
503 int port
, bool unicast
)
508 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
513 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
;
515 reg
&= ~PORT_CONTROL_FORWARD_UNKNOWN
;
517 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
520 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip
*chip
, int port
,
521 bool unicast
, bool multicast
)
526 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL
, ®
);
530 reg
&= ~PORT_CONTROL_EGRESS_FLOODS_MASK
;
532 if (unicast
&& multicast
)
533 reg
|= PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA
;
535 reg
|= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA
;
537 reg
|= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA
;
539 reg
|= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA
;
541 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL
, reg
);
544 /* Offset 0x05: Port Control 1 */
546 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip
*chip
, int port
,
552 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_1
, &val
);
557 val
|= PORT_CONTROL_1_MESSAGE_PORT
;
559 val
&= ~PORT_CONTROL_1_MESSAGE_PORT
;
561 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_1
, val
);
564 /* Offset 0x06: Port Based VLAN Map */
566 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip
*chip
, int port
, u16 map
)
568 const u16 mask
= mv88e6xxx_port_mask(chip
);
572 err
= mv88e6xxx_port_read(chip
, port
, PORT_BASE_VLAN
, ®
);
579 err
= mv88e6xxx_port_write(chip
, port
, PORT_BASE_VLAN
, reg
);
583 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "VLANTable set to %.3x\n",
589 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip
*chip
, int port
, u16
*fid
)
591 const u16 upper_mask
= (mv88e6xxx_num_databases(chip
) - 1) >> 4;
595 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
596 err
= mv88e6xxx_port_read(chip
, port
, PORT_BASE_VLAN
, ®
);
600 *fid
= (reg
& 0xf000) >> 12;
602 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
604 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_1
, ®
);
608 *fid
|= (reg
& upper_mask
) << 4;
614 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip
*chip
, int port
, u16 fid
)
616 const u16 upper_mask
= (mv88e6xxx_num_databases(chip
) - 1) >> 4;
620 if (fid
>= mv88e6xxx_num_databases(chip
))
623 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
624 err
= mv88e6xxx_port_read(chip
, port
, PORT_BASE_VLAN
, ®
);
629 reg
|= (fid
& 0x000f) << 12;
631 err
= mv88e6xxx_port_write(chip
, port
, PORT_BASE_VLAN
, reg
);
635 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
637 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_1
, ®
);
642 reg
|= (fid
>> 4) & upper_mask
;
644 err
= mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_1
, reg
);
649 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "FID set to %u\n", fid
);
654 /* Offset 0x07: Default Port VLAN ID & Priority */
656 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip
*chip
, int port
, u16
*pvid
)
661 err
= mv88e6xxx_port_read(chip
, port
, PORT_DEFAULT_VLAN
, ®
);
665 *pvid
= reg
& PORT_DEFAULT_VLAN_MASK
;
670 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip
*chip
, int port
, u16 pvid
)
675 err
= mv88e6xxx_port_read(chip
, port
, PORT_DEFAULT_VLAN
, ®
);
679 reg
&= ~PORT_DEFAULT_VLAN_MASK
;
680 reg
|= pvid
& PORT_DEFAULT_VLAN_MASK
;
682 err
= mv88e6xxx_port_write(chip
, port
, PORT_DEFAULT_VLAN
, reg
);
686 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "DefaultVID set to %u\n",
692 /* Offset 0x08: Port Control 2 Register */
694 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
695 [PORT_CONTROL_2_8021Q_DISABLED
] = "Disabled",
696 [PORT_CONTROL_2_8021Q_FALLBACK
] = "Fallback",
697 [PORT_CONTROL_2_8021Q_CHECK
] = "Check",
698 [PORT_CONTROL_2_8021Q_SECURE
] = "Secure",
701 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip
*chip
,
702 int port
, bool multicast
)
707 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_2
, ®
);
712 reg
|= PORT_CONTROL_2_DEFAULT_FORWARD
;
714 reg
&= ~PORT_CONTROL_2_DEFAULT_FORWARD
;
716 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_2
, reg
);
719 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip
*chip
, int port
,
720 bool unicast
, bool multicast
)
724 err
= mv88e6185_port_set_forward_unknown(chip
, port
, unicast
);
728 return mv88e6185_port_set_default_forward(chip
, port
, multicast
);
731 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip
*chip
, int port
,
737 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_2
, ®
);
741 reg
&= ~PORT_CONTROL_2_UPSTREAM_MASK
;
742 reg
|= upstream_port
;
744 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_2
, reg
);
747 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip
*chip
, int port
,
753 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_2
, ®
);
757 reg
&= ~PORT_CONTROL_2_8021Q_MASK
;
758 reg
|= mode
& PORT_CONTROL_2_8021Q_MASK
;
760 err
= mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_2
, reg
);
764 netdev_dbg(chip
->ds
->ports
[port
].netdev
, "802.1QMode set to %s\n",
765 mv88e6xxx_port_8021q_mode_names
[mode
]);
770 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip
*chip
, int port
)
775 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_2
, ®
);
779 reg
|= PORT_CONTROL_2_MAP_DA
;
781 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_2
, reg
);
784 int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip
*chip
, int port
)
789 err
= mv88e6xxx_port_read(chip
, port
, PORT_CONTROL_2
, ®
);
793 reg
|= PORT_CONTROL_2_JUMBO_10240
;
795 return mv88e6xxx_port_write(chip
, port
, PORT_CONTROL_2
, reg
);
798 /* Offset 0x09: Port Rate Control */
800 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip
*chip
, int port
)
802 return mv88e6xxx_port_write(chip
, port
, PORT_RATE_CONTROL
, 0x0000);
805 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip
*chip
, int port
)
807 return mv88e6xxx_port_write(chip
, port
, PORT_RATE_CONTROL
, 0x0001);
810 /* Offset 0x0C: Port ATU Control */
812 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip
*chip
, int port
)
814 return mv88e6xxx_port_write(chip
, port
, PORT_ATU_CONTROL
, 0);
817 /* Offset 0x0D: (Priority) Override Register */
819 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip
*chip
, int port
)
821 return mv88e6xxx_port_write(chip
, port
, PORT_PRI_OVERRIDE
, 0);
824 /* Offset 0x0f: Port Ether type */
826 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip
*chip
, int port
,
829 return mv88e6xxx_port_write(chip
, port
, PORT_ETH_TYPE
, etype
);
832 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
833 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
836 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip
*chip
, int port
)
840 /* Use a direct priority mapping for all IEEE tagged frames */
841 err
= mv88e6xxx_port_write(chip
, port
, PORT_TAG_REGMAP_0123
, 0x3210);
845 return mv88e6xxx_port_write(chip
, port
, PORT_TAG_REGMAP_4567
, 0x7654);
848 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip
*chip
,
850 u8 pointer
, u16 data
)
854 reg
= PORT_IEEE_PRIO_MAP_TABLE_UPDATE
|
856 (pointer
<< PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT
) |
859 return mv88e6xxx_port_write(chip
, port
, PORT_IEEE_PRIO_MAP_TABLE
, reg
);
862 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip
*chip
, int port
)
866 for (i
= 0; i
<= 7; i
++) {
867 err
= mv88e6xxx_port_ieeepmt_write(
868 chip
, port
, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP
,
873 err
= mv88e6xxx_port_ieeepmt_write(
874 chip
, port
, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP
,
879 err
= mv88e6xxx_port_ieeepmt_write(
880 chip
, port
, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP
,
885 err
= mv88e6xxx_port_ieeepmt_write(
886 chip
, port
, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP
,