drivers/net/dsa/mv88e6xxx/port.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Marvell 88E6xxx Switch Port Registers support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   8  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   9  */
  10
  11 #ifndef _MV88E6XXX_PORT_H
  12 #define _MV88E6XXX_PORT_H
  13
  14 #include "chip.h"
  15
  16 /* Offset 0x00: Port Status Register */
  17 #define MV88E6XXX_PORT_STS                      0x00
  18 #define MV88E6XXX_PORT_STS_PAUSE_EN             0x8000
  19 #define MV88E6XXX_PORT_STS_MY_PAUSE             0x4000
  20 #define MV88E6XXX_PORT_STS_HD_FLOW              0x2000
  21 #define MV88E6XXX_PORT_STS_PHY_DETECT           0x1000
  22 #define MV88E6250_PORT_STS_LINK                         0x1000
  23 #define MV88E6250_PORT_STS_PORTMODE_MASK                0x0f00
  24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF         0x0800
  25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF        0x0900
  26 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL         0x0a00
  27 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL        0x0b00
  28 #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF         0x0c00
  29 #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF        0x0d00
  30 #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL         0x0e00
  31 #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL        0x0f00
  32 #define MV88E6XXX_PORT_STS_LINK                 0x0800
  33 #define MV88E6XXX_PORT_STS_DUPLEX               0x0400
  34 #define MV88E6XXX_PORT_STS_SPEED_MASK           0x0300
  35 #define MV88E6XXX_PORT_STS_SPEED_10             0x0000
  36 #define MV88E6XXX_PORT_STS_SPEED_100            0x0100
  37 #define MV88E6XXX_PORT_STS_SPEED_1000           0x0200
  38 #define MV88E6XXX_PORT_STS_SPEED_10000          0x0300
  39 #define MV88E6352_PORT_STS_EEE                  0x0040
  40 #define MV88E6165_PORT_STS_AM_DIS               0x0040
  41 #define MV88E6185_PORT_STS_MGMII                0x0040
  42 #define MV88E6XXX_PORT_STS_TX_PAUSED            0x0020
  43 #define MV88E6XXX_PORT_STS_FLOW_CTL             0x0010
  44 #define MV88E6XXX_PORT_STS_CMODE_MASK           0x000f
  45 #define MV88E6XXX_PORT_STS_CMODE_RGMII          0x0007
  46 #define MV88E6XXX_PORT_STS_CMODE_100BASEX       0x0008
  47 #define MV88E6XXX_PORT_STS_CMODE_1000BASEX      0x0009
  48 #define MV88E6XXX_PORT_STS_CMODE_SGMII          0x000a
  49 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX      0x000b
  50 #define MV88E6XXX_PORT_STS_CMODE_XAUI           0x000c
  51 #define MV88E6XXX_PORT_STS_CMODE_RXAUI          0x000d
  52 #define MV88E6185_PORT_STS_CDUPLEX              0x0008
  53 #define MV88E6185_PORT_STS_CMODE_MASK           0x0007
  54 #define MV88E6185_PORT_STS_CMODE_GMII_FD        0x0000
  55 #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS  0x0001
  56 #define MV88E6185_PORT_STS_CMODE_MII_100        0x0002
  57 #define MV88E6185_PORT_STS_CMODE_MII_10         0x0003
  58 #define MV88E6185_PORT_STS_CMODE_SERDES         0x0004
  59 #define MV88E6185_PORT_STS_CMODE_1000BASE_X     0x0005
  60 #define MV88E6185_PORT_STS_CMODE_PHY            0x0006
  61 #define MV88E6185_PORT_STS_CMODE_DISABLED       0x0007
  62
  63 /* Offset 0x01: MAC (or PCS or Physical) Control Register */
  64 #define MV88E6XXX_PORT_MAC_CTL                          0x01
  65 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK        0x8000
  66 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK        0x4000
  67 #define MV88E6185_PORT_MAC_CTL_SYNC_OK                  0x4000
  68 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED              0x2000
  69 #define MV88E6390_PORT_MAC_CTL_ALTSPEED                 0x1000
  70 #define MV88E6352_PORT_MAC_CTL_200BASE                  0x1000
  71 #define MV88E6185_PORT_MAC_CTL_AN_EN                    0x0400
  72 #define MV88E6185_PORT_MAC_CTL_AN_RESTART               0x0200
  73 #define MV88E6185_PORT_MAC_CTL_AN_DONE                  0x0100
  74 #define MV88E6XXX_PORT_MAC_CTL_FC                       0x0080
  75 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC                 0x0040
  76 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP                  0x0020
  77 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK               0x0010
  78 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL              0x0008
  79 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX             0x0004
  80 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK               0x0003
  81 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10                 0x0000
  82 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100                0x0001
  83 #define MV88E6065_PORT_MAC_CTL_SPEED_200                0x0002
  84 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000               0x0002
  85 #define MV88E6390_PORT_MAC_CTL_SPEED_10000              0x0003
  86 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED           0x0003
  87
  88 /* Offset 0x02: Jamming Control Register */
  89 #define MV88E6097_PORT_JAM_CTL                  0x02
  90 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK   0xff00
  91 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK    0x00ff
  92
  93 /* Offset 0x02: Flow Control Register */
  94 #define MV88E6390_PORT_FLOW_CTL                 0x02
  95 #define MV88E6390_PORT_FLOW_CTL_UPDATE          0x8000
  96 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK        0x7f00
  97 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN        0x0000
  98 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT       0x0100
  99 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK       0x00ff
 100
 101 /* Offset 0x03: Switch Identifier Register */
 102 #define MV88E6XXX_PORT_SWITCH_ID                0x03
 103 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK      0xfff0
 104 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085      0x04a0
 105 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095      0x0950
 106 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097      0x0990
 107 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X     0x0a00
 108 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X     0x0a10
 109 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131      0x1060
 110 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320      0x1150
 111 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123      0x1210
 112 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161      0x1610
 113 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165      0x1650
 114 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171      0x1710
 115 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172      0x1720
 116 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175      0x1750
 117 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176      0x1760
 118 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190      0x1900
 119 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191      0x1910
 120 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185      0x1a70
 121 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220      0x2200
 122 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240      0x2400
 123 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250      0x2500
 124 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290      0x2900
 125 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321      0x3100
 126 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141      0x3400
 127 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341      0x3410
 128 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352      0x3520
 129 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350      0x3710
 130 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351      0x3750
 131 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390      0x3900
 132 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK       0x000f
 133
 134 /* Offset 0x04: Port Control Register */
 135 #define MV88E6XXX_PORT_CTL0                                     0x04
 136 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG                        0x8000
 137 #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK                        0x4000
 138 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK                    0x3000
 139 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED              0x0000
 140 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED                0x1000
 141 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED                  0x2000
 142 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA          0x3000
 143 #define MV88E6XXX_PORT_CTL0_HEADER                              0x0800
 144 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP                      0x0400
 145 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG                          0x0200
 146 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK                     0x0300
 147 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL                   0x0000
 148 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA                      0x0100
 149 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER                 0x0200
 150 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA           0x0300
 151 #define MV88E6XXX_PORT_CTL0_DSA_TAG                             0x0100
 152 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL                         0x0080
 153 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH                         0x0040
 154 #define MV88E6185_PORT_CTL0_USE_IP                              0x0020
 155 #define MV88E6185_PORT_CTL0_USE_TAG                             0x0010
 156 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN                     0x0004
 157 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK                  0x000c
 158 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA         0x0000
 159 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA      0x0004
 160 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA      0x0008
 161 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA        0x000c
 162 #define MV88E6XXX_PORT_CTL0_STATE_MASK                          0x0003
 163 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED                      0x0000
 164 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING                      0x0001
 165 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING                      0x0002
 166 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING                    0x0003
 167
 168 /* Offset 0x05: Port Control 1 */
 169 #define MV88E6XXX_PORT_CTL1                     0x05
 170 #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT        0x8000
 171 #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK       0x00ff
 172
 173 /* Offset 0x06: Port Based VLAN Map */
 174 #define MV88E6XXX_PORT_BASE_VLAN                0x06
 175 #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK   0xf000
 176
 177 /* Offset 0x07: Default Port VLAN ID & Priority */
 178 #define MV88E6XXX_PORT_DEFAULT_VLAN             0x07
 179 #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK        0x0fff
 180
 181 /* Offset 0x08: Port Control 2 Register */
 182 #define MV88E6XXX_PORT_CTL2                             0x08
 183 #define MV88E6XXX_PORT_CTL2_IGNORE_FCS                  0x8000
 184 #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE            0x4000
 185 #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE            0x2000
 186 #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE            0x1000
 187 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK             0x3000
 188 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522             0x0000
 189 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048             0x1000
 190 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240            0x2000
 191 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK             0x0c00
 192 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED         0x0000
 193 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK         0x0400
 194 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK            0x0800
 195 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE           0x0c00
 196 #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED              0x0200
 197 #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED            0x0100
 198 #define MV88E6XXX_PORT_CTL2_MAP_DA                      0x0080
 199 #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD             0x0040
 200 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR              0x0020
 201 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR             0x0010
 202 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK               0x000f
 203
 204 /* Offset 0x09: Egress Rate Control */
 205 #define MV88E6XXX_PORT_EGRESS_RATE_CTL1         0x09
 206
 207 /* Offset 0x0A: Egress Rate Control 2 */
 208 #define MV88E6XXX_PORT_EGRESS_RATE_CTL2         0x0a
 209
 210 /* Offset 0x0B: Port Association Vector */
 211 #define MV88E6XXX_PORT_ASSOC_VECTOR                     0x0b
 212 #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1           0x8000
 213 #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT         0x4000
 214 #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT         0x2000
 215 #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG        0x1000
 216 #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED      0x0800
 217
 218 /* Offset 0x0C: Port ATU Control */
 219 #define MV88E6XXX_PORT_ATU_CTL          0x0c
 220
 221 /* Offset 0x0D: Priority Override Register */
 222 #define MV88E6XXX_PORT_PRI_OVERRIDE     0x0d
 223
 224 /* Offset 0x0E: Policy Control Register */
 225 #define MV88E6XXX_PORT_POLICY_CTL               0x0e
 226 #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK       0xc000
 227 #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK       0x3000
 228 #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK      0x0c00
 229 #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK    0x0300
 230 #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK    0x00c0
 231 #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK     0x0030
 232 #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK    0x000c
 233 #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK      0x0003
 234 #define MV88E6XXX_PORT_POLICY_CTL_NORMAL        0x0000
 235 #define MV88E6XXX_PORT_POLICY_CTL_MIRROR        0x0001
 236 #define MV88E6XXX_PORT_POLICY_CTL_TRAP          0x0002
 237 #define MV88E6XXX_PORT_POLICY_CTL_DISCARD       0x0003
 238
 239 /* Offset 0x0F: Port Special Ether Type */
 240 #define MV88E6XXX_PORT_ETH_TYPE         0x0f
 241 #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
 242
 243 /* Offset 0x10: InDiscards Low Counter */
 244 #define MV88E6XXX_PORT_IN_DISCARD_LO    0x10
 245
 246 /* Offset 0x11: InDiscards High Counter */
 247 #define MV88E6XXX_PORT_IN_DISCARD_HI    0x11
 248
 249 /* Offset 0x12: InFiltered Counter */
 250 #define MV88E6XXX_PORT_IN_FILTERED      0x12
 251
 252 /* Offset 0x13: OutFiltered Counter */
 253 #define MV88E6XXX_PORT_OUT_FILTERED     0x13
 254
 255 /* Offset 0x18: IEEE Priority Mapping Table */
 256 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE                      0x18
 257 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE               0x8000
 258 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK                 0x7000
 259 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP          0x0000
 260 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP     0x1000
 261 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP    0x2000
 262 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP       0x3000
 263 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP    0x5000
 264 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP   0x6000
 265 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP      0x7000
 266 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK             0x0e00
 267 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK            0x01ff
 268
 269 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
 270 #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123     0x18
 271
 272 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
 273 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567     0x19
 274
 275 /* Offset 0x1a: Magic undocumented errata register */
 276 #define MV88E6XXX_PORT_RESERVED_1A              0x1a
 277 #define MV88E6XXX_PORT_RESERVED_1A_BUSY         0x8000
 278 #define MV88E6XXX_PORT_RESERVED_1A_WRITE        0x4000
 279 #define MV88E6XXX_PORT_RESERVED_1A_READ         0x0000
 280 #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT   5
 281 #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT  10
 282 #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT    0x04
 283 #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT    0x05
 284 #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE  0x8000
 285 #define MV88E6341_PORT_RESERVED_1A_SGMII_AN     0x2000
 286
 287 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
 288                         u16 *val);
 289 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
 290                          u16 val);
 291
 292 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
 293                              int pause);
 294 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 295                                    phy_interface_t mode);
 296 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 297                                    phy_interface_t mode);
 298
 299 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
 300
 301 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
 302
 303 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 304 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 305 int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 306 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 307 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 308 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 309 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 310
 311 phy_interface_t mv88e6341_port_max_speed_mode(int port);
 312 phy_interface_t mv88e6390_port_max_speed_mode(int port);
 313 phy_interface_t mv88e6390x_port_max_speed_mode(int port);
 314
 315 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
 316
 317 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
 318
 319 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
 320 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
 321
 322 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
 323 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
 324
 325 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
 326                                   u16 mode);
 327 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
 328 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
 329 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
 330                                    enum mv88e6xxx_egress_mode mode);
 331 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 332                                   enum mv88e6xxx_frame_mode mode);
 333 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 334                                   enum mv88e6xxx_frame_mode mode);
 335 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 336                                      bool unicast, bool multicast);
 337 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 338                                      bool unicast, bool multicast);
 339 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
 340                               enum mv88e6xxx_policy_mapping mapping,
 341                               enum mv88e6xxx_policy_action action);
 342 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
 343                                   u16 etype);
 344 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
 345                                     bool message_port);
 346 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
 347                                   size_t size);
 348 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
 349 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
 350 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 351                                u8 out);
 352 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 353                                u8 out);
 354 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 355                              phy_interface_t mode);
 356 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 357                              phy_interface_t mode);
 358 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 359                               phy_interface_t mode);
 360 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 361 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 362 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
 363                               struct phylink_link_state *state);
 364 int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
 365                               struct phylink_link_state *state);
 366 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
 367                               struct phylink_link_state *state);
 368 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
 369 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
 370                                      int upstream_port);
 371 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
 372                               enum mv88e6xxx_egress_direction direction,
 373                               bool mirror);
 374
 375 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
 376 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
 377
 378 int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,
 379                                 int port, int reg, u16 val);
 380 int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);
 381 int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,
 382                                int reg, u16 *val);
 383
 384 #endif /* _MV88E6XXX_PORT_H */