2 * Marvell 88E6xxx Switch PTP support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2017 National Instruments
7 * Erik Hons <erik.hons@ni.com>
8 * Brandon Streiff <brandon.streiff@ni.com>
9 * Dane Wagner <dane.wagner@ni.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
22 /* Raw timestamps are in units of 8-ns clock periods. */
24 #define CC_MULT (8 << CC_SHIFT)
25 #define CC_MULT_NUM (1 << 9)
26 #define CC_MULT_DEM 15625ULL
28 #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)
30 #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
31 #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
33 #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
36 static int mv88e6xxx_tai_read(struct mv88e6xxx_chip
*chip
, int addr
,
39 if (!chip
->info
->ops
->avb_ops
->tai_read
)
42 return chip
->info
->ops
->avb_ops
->tai_read(chip
, addr
, data
, len
);
45 static int mv88e6xxx_tai_write(struct mv88e6xxx_chip
*chip
, int addr
, u16 data
)
47 if (!chip
->info
->ops
->avb_ops
->tai_write
)
50 return chip
->info
->ops
->avb_ops
->tai_write(chip
, addr
, data
);
53 /* TODO: places where this are called should be using pinctrl */
54 static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip
*chip
, int pin
,
59 if (!chip
->info
->ops
->gpio_ops
)
62 err
= chip
->info
->ops
->gpio_ops
->set_dir(chip
, pin
, input
);
66 return chip
->info
->ops
->gpio_ops
->set_pctl(chip
, pin
, func
);
69 static u64
mv88e6352_ptp_clock_read(const struct cyclecounter
*cc
)
71 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
75 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_TAI_TIME_LO
, phc_time
,
76 ARRAY_SIZE(phc_time
));
80 return ((u32
)phc_time
[1] << 16) | phc_time
[0];
83 static u64
mv88e6165_ptp_clock_read(const struct cyclecounter
*cc
)
85 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
89 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_PTP_GC_TIME_LO
, phc_time
,
90 ARRAY_SIZE(phc_time
));
94 return ((u32
)phc_time
[1] << 16) | phc_time
[0];
97 /* mv88e6352_config_eventcap - configure TAI event capture
98 * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
99 * @rising: zero for falling-edge trigger, else rising-edge trigger
101 * This will also reset the capture sequence counter.
103 static int mv88e6352_config_eventcap(struct mv88e6xxx_chip
*chip
, int event
,
110 chip
->evcap_config
= MV88E6XXX_TAI_CFG_CAP_OVERWRITE
|
111 MV88E6XXX_TAI_CFG_CAP_CTR_START
;
113 chip
->evcap_config
|= MV88E6XXX_TAI_CFG_EVREQ_FALLING
;
115 global_config
= (chip
->evcap_config
| chip
->trig_config
);
116 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_CFG
, global_config
);
120 if (event
== PTP_CLOCK_PPS
) {
121 cap_config
= MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG
;
122 } else if (event
== PTP_CLOCK_EXTTS
) {
123 /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
129 /* Write the capture config; this also clears the capture counter */
130 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_EVENT_STATUS
,
136 static void mv88e6352_tai_event_work(struct work_struct
*ugly
)
138 struct delayed_work
*dw
= to_delayed_work(ugly
);
139 struct mv88e6xxx_chip
*chip
= dw_tai_event_to_chip(dw
);
140 struct ptp_clock_event ev
;
145 mutex_lock(&chip
->reg_lock
);
146 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_TAI_EVENT_STATUS
,
147 status
, ARRAY_SIZE(status
));
148 mutex_unlock(&chip
->reg_lock
);
151 dev_err(chip
->dev
, "failed to read TAI status register\n");
154 if (status
[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR
) {
155 dev_warn(chip
->dev
, "missed event capture\n");
158 if (!(status
[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID
))
161 raw_ts
= ((u32
)status
[2] << 16) | status
[1];
163 /* Clear the valid bit so the next timestamp can come in */
164 status
[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID
;
165 mutex_lock(&chip
->reg_lock
);
166 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_EVENT_STATUS
, status
[0]);
167 mutex_unlock(&chip
->reg_lock
);
169 /* This is an external timestamp */
170 ev
.type
= PTP_CLOCK_EXTTS
;
172 /* We only have one timestamping channel. */
174 mutex_lock(&chip
->reg_lock
);
175 ev
.timestamp
= timecounter_cyc2time(&chip
->tstamp_tc
, raw_ts
);
176 mutex_unlock(&chip
->reg_lock
);
178 ptp_clock_event(chip
->ptp_clock
, &ev
);
180 schedule_delayed_work(&chip
->tai_event_work
, TAI_EVENT_WORK_INTERVAL
);
183 static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info
*ptp
, long scaled_ppm
)
185 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
190 if (scaled_ppm
< 0) {
192 scaled_ppm
= -scaled_ppm
;
197 diff
= div_u64(adj
, CC_MULT_DEM
);
199 mutex_lock(&chip
->reg_lock
);
201 timecounter_read(&chip
->tstamp_tc
);
202 chip
->tstamp_cc
.mult
= neg_adj
? mult
- diff
: mult
+ diff
;
204 mutex_unlock(&chip
->reg_lock
);
209 static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
211 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
213 mutex_lock(&chip
->reg_lock
);
214 timecounter_adjtime(&chip
->tstamp_tc
, delta
);
215 mutex_unlock(&chip
->reg_lock
);
220 static int mv88e6xxx_ptp_gettime(struct ptp_clock_info
*ptp
,
221 struct timespec64
*ts
)
223 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
226 mutex_lock(&chip
->reg_lock
);
227 ns
= timecounter_read(&chip
->tstamp_tc
);
228 mutex_unlock(&chip
->reg_lock
);
230 *ts
= ns_to_timespec64(ns
);
235 static int mv88e6xxx_ptp_settime(struct ptp_clock_info
*ptp
,
236 const struct timespec64
*ts
)
238 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
241 ns
= timespec64_to_ns(ts
);
243 mutex_lock(&chip
->reg_lock
);
244 timecounter_init(&chip
->tstamp_tc
, &chip
->tstamp_cc
, ns
);
245 mutex_unlock(&chip
->reg_lock
);
250 static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip
*chip
,
251 struct ptp_clock_request
*rq
, int on
)
253 int rising
= (rq
->extts
.flags
& PTP_RISING_EDGE
);
258 pin
= ptp_find_pin(chip
->ptp_clock
, PTP_PF_EXTTS
, rq
->extts
.index
);
263 mutex_lock(&chip
->reg_lock
);
266 func
= MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ
;
268 err
= mv88e6352_set_gpio_func(chip
, pin
, func
, true);
272 schedule_delayed_work(&chip
->tai_event_work
,
273 TAI_EVENT_WORK_INTERVAL
);
275 err
= mv88e6352_config_eventcap(chip
, PTP_CLOCK_EXTTS
, rising
);
277 func
= MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO
;
279 err
= mv88e6352_set_gpio_func(chip
, pin
, func
, true);
281 cancel_delayed_work_sync(&chip
->tai_event_work
);
285 mutex_unlock(&chip
->reg_lock
);
290 static int mv88e6352_ptp_enable(struct ptp_clock_info
*ptp
,
291 struct ptp_clock_request
*rq
, int on
)
293 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
296 case PTP_CLK_REQ_EXTTS
:
297 return mv88e6352_ptp_enable_extts(chip
, rq
, on
);
303 static int mv88e6352_ptp_verify(struct ptp_clock_info
*ptp
, unsigned int pin
,
304 enum ptp_pin_function func
, unsigned int chan
)
317 const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops
= {
318 .clock_read
= mv88e6352_ptp_clock_read
,
319 .ptp_enable
= mv88e6352_ptp_enable
,
320 .ptp_verify
= mv88e6352_ptp_verify
,
321 .event_work
= mv88e6352_tai_event_work
,
322 .port_enable
= mv88e6352_hwtstamp_port_enable
,
323 .port_disable
= mv88e6352_hwtstamp_port_disable
,
325 .arr0_sts_reg
= MV88E6XXX_PORT_PTP_ARR0_STS
,
326 .arr1_sts_reg
= MV88E6XXX_PORT_PTP_ARR1_STS
,
327 .dep_sts_reg
= MV88E6XXX_PORT_PTP_DEP_STS
,
330 const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops
= {
331 .clock_read
= mv88e6165_ptp_clock_read
,
334 static u64
mv88e6xxx_ptp_clock_read(const struct cyclecounter
*cc
)
336 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
338 if (chip
->info
->ops
->ptp_ops
->clock_read
)
339 return chip
->info
->ops
->ptp_ops
->clock_read(cc
);
344 /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
345 * seconds; this task forces periodic reads so that we don't miss any.
347 #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
348 static void mv88e6xxx_ptp_overflow_check(struct work_struct
*work
)
350 struct delayed_work
*dw
= to_delayed_work(work
);
351 struct mv88e6xxx_chip
*chip
= dw_overflow_to_chip(dw
);
352 struct timespec64 ts
;
354 mv88e6xxx_ptp_gettime(&chip
->ptp_clock_info
, &ts
);
356 schedule_delayed_work(&chip
->overflow_work
,
357 MV88E6XXX_TAI_OVERFLOW_PERIOD
);
360 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip
*chip
)
362 const struct mv88e6xxx_ptp_ops
*ptp_ops
= chip
->info
->ops
->ptp_ops
;
365 /* Set up the cycle counter */
366 memset(&chip
->tstamp_cc
, 0, sizeof(chip
->tstamp_cc
));
367 chip
->tstamp_cc
.read
= mv88e6xxx_ptp_clock_read
;
368 chip
->tstamp_cc
.mask
= CYCLECOUNTER_MASK(32);
369 chip
->tstamp_cc
.mult
= CC_MULT
;
370 chip
->tstamp_cc
.shift
= CC_SHIFT
;
372 timecounter_init(&chip
->tstamp_tc
, &chip
->tstamp_cc
,
373 ktime_to_ns(ktime_get_real()));
375 INIT_DELAYED_WORK(&chip
->overflow_work
, mv88e6xxx_ptp_overflow_check
);
376 if (ptp_ops
->event_work
)
377 INIT_DELAYED_WORK(&chip
->tai_event_work
, ptp_ops
->event_work
);
379 chip
->ptp_clock_info
.owner
= THIS_MODULE
;
380 snprintf(chip
->ptp_clock_info
.name
, sizeof(chip
->ptp_clock_info
.name
),
381 dev_name(chip
->dev
));
382 chip
->ptp_clock_info
.max_adj
= 1000000;
384 chip
->ptp_clock_info
.n_ext_ts
= ptp_ops
->n_ext_ts
;
385 chip
->ptp_clock_info
.n_per_out
= 0;
386 chip
->ptp_clock_info
.n_pins
= mv88e6xxx_num_gpio(chip
);
387 chip
->ptp_clock_info
.pps
= 0;
389 for (i
= 0; i
< chip
->ptp_clock_info
.n_pins
; ++i
) {
390 struct ptp_pin_desc
*ppd
= &chip
->pin_config
[i
];
392 snprintf(ppd
->name
, sizeof(ppd
->name
), "mv88e6xxx_gpio%d", i
);
394 ppd
->func
= PTP_PF_NONE
;
396 chip
->ptp_clock_info
.pin_config
= chip
->pin_config
;
398 chip
->ptp_clock_info
.adjfine
= mv88e6xxx_ptp_adjfine
;
399 chip
->ptp_clock_info
.adjtime
= mv88e6xxx_ptp_adjtime
;
400 chip
->ptp_clock_info
.gettime64
= mv88e6xxx_ptp_gettime
;
401 chip
->ptp_clock_info
.settime64
= mv88e6xxx_ptp_settime
;
402 chip
->ptp_clock_info
.enable
= ptp_ops
->ptp_enable
;
403 chip
->ptp_clock_info
.verify
= ptp_ops
->ptp_verify
;
404 chip
->ptp_clock_info
.do_aux_work
= mv88e6xxx_hwtstamp_work
;
406 chip
->ptp_clock
= ptp_clock_register(&chip
->ptp_clock_info
, chip
->dev
);
407 if (IS_ERR(chip
->ptp_clock
))
408 return PTR_ERR(chip
->ptp_clock
);
410 schedule_delayed_work(&chip
->overflow_work
,
411 MV88E6XXX_TAI_OVERFLOW_PERIOD
);
416 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip
*chip
)
418 if (chip
->ptp_clock
) {
419 cancel_delayed_work_sync(&chip
->overflow_work
);
420 if (chip
->info
->ops
->ptp_ops
->event_work
)
421 cancel_delayed_work_sync(&chip
->tai_event_work
);
423 ptp_clock_unregister(chip
->ptp_clock
);
424 chip
->ptp_clock
= NULL
;