1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch PTP support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2017 National Instruments
8 * Erik Hons <erik.hons@ni.com>
9 * Brandon Streiff <brandon.streiff@ni.com>
10 * Dane Wagner <dane.wagner@ni.com>
18 /* Raw timestamps are in units of 8-ns clock periods. */
20 #define CC_MULT (8 << CC_SHIFT)
21 #define CC_MULT_NUM (1 << 9)
22 #define CC_MULT_DEM 15625ULL
24 #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)
26 #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
27 #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
29 #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
32 static int mv88e6xxx_tai_read(struct mv88e6xxx_chip
*chip
, int addr
,
35 if (!chip
->info
->ops
->avb_ops
->tai_read
)
38 return chip
->info
->ops
->avb_ops
->tai_read(chip
, addr
, data
, len
);
41 static int mv88e6xxx_tai_write(struct mv88e6xxx_chip
*chip
, int addr
, u16 data
)
43 if (!chip
->info
->ops
->avb_ops
->tai_write
)
46 return chip
->info
->ops
->avb_ops
->tai_write(chip
, addr
, data
);
49 /* TODO: places where this are called should be using pinctrl */
50 static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip
*chip
, int pin
,
55 if (!chip
->info
->ops
->gpio_ops
)
58 err
= chip
->info
->ops
->gpio_ops
->set_dir(chip
, pin
, input
);
62 return chip
->info
->ops
->gpio_ops
->set_pctl(chip
, pin
, func
);
65 static u64
mv88e6352_ptp_clock_read(const struct cyclecounter
*cc
)
67 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
71 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_TAI_TIME_LO
, phc_time
,
72 ARRAY_SIZE(phc_time
));
76 return ((u32
)phc_time
[1] << 16) | phc_time
[0];
79 static u64
mv88e6165_ptp_clock_read(const struct cyclecounter
*cc
)
81 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
85 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_PTP_GC_TIME_LO
, phc_time
,
86 ARRAY_SIZE(phc_time
));
90 return ((u32
)phc_time
[1] << 16) | phc_time
[0];
93 /* mv88e6352_config_eventcap - configure TAI event capture
94 * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
95 * @rising: zero for falling-edge trigger, else rising-edge trigger
97 * This will also reset the capture sequence counter.
99 static int mv88e6352_config_eventcap(struct mv88e6xxx_chip
*chip
, int event
,
106 chip
->evcap_config
= MV88E6XXX_TAI_CFG_CAP_OVERWRITE
|
107 MV88E6XXX_TAI_CFG_CAP_CTR_START
;
109 chip
->evcap_config
|= MV88E6XXX_TAI_CFG_EVREQ_FALLING
;
111 global_config
= (chip
->evcap_config
| chip
->trig_config
);
112 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_CFG
, global_config
);
116 if (event
== PTP_CLOCK_PPS
) {
117 cap_config
= MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG
;
118 } else if (event
== PTP_CLOCK_EXTTS
) {
119 /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
125 /* Write the capture config; this also clears the capture counter */
126 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_EVENT_STATUS
,
132 static void mv88e6352_tai_event_work(struct work_struct
*ugly
)
134 struct delayed_work
*dw
= to_delayed_work(ugly
);
135 struct mv88e6xxx_chip
*chip
= dw_tai_event_to_chip(dw
);
136 struct ptp_clock_event ev
;
141 mutex_lock(&chip
->reg_lock
);
142 err
= mv88e6xxx_tai_read(chip
, MV88E6XXX_TAI_EVENT_STATUS
,
143 status
, ARRAY_SIZE(status
));
144 mutex_unlock(&chip
->reg_lock
);
147 dev_err(chip
->dev
, "failed to read TAI status register\n");
150 if (status
[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR
) {
151 dev_warn(chip
->dev
, "missed event capture\n");
154 if (!(status
[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID
))
157 raw_ts
= ((u32
)status
[2] << 16) | status
[1];
159 /* Clear the valid bit so the next timestamp can come in */
160 status
[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID
;
161 mutex_lock(&chip
->reg_lock
);
162 err
= mv88e6xxx_tai_write(chip
, MV88E6XXX_TAI_EVENT_STATUS
, status
[0]);
163 mutex_unlock(&chip
->reg_lock
);
165 /* This is an external timestamp */
166 ev
.type
= PTP_CLOCK_EXTTS
;
168 /* We only have one timestamping channel. */
170 mutex_lock(&chip
->reg_lock
);
171 ev
.timestamp
= timecounter_cyc2time(&chip
->tstamp_tc
, raw_ts
);
172 mutex_unlock(&chip
->reg_lock
);
174 ptp_clock_event(chip
->ptp_clock
, &ev
);
176 schedule_delayed_work(&chip
->tai_event_work
, TAI_EVENT_WORK_INTERVAL
);
179 static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info
*ptp
, long scaled_ppm
)
181 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
186 if (scaled_ppm
< 0) {
188 scaled_ppm
= -scaled_ppm
;
193 diff
= div_u64(adj
, CC_MULT_DEM
);
195 mutex_lock(&chip
->reg_lock
);
197 timecounter_read(&chip
->tstamp_tc
);
198 chip
->tstamp_cc
.mult
= neg_adj
? mult
- diff
: mult
+ diff
;
200 mutex_unlock(&chip
->reg_lock
);
205 static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
207 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
209 mutex_lock(&chip
->reg_lock
);
210 timecounter_adjtime(&chip
->tstamp_tc
, delta
);
211 mutex_unlock(&chip
->reg_lock
);
216 static int mv88e6xxx_ptp_gettime(struct ptp_clock_info
*ptp
,
217 struct timespec64
*ts
)
219 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
222 mutex_lock(&chip
->reg_lock
);
223 ns
= timecounter_read(&chip
->tstamp_tc
);
224 mutex_unlock(&chip
->reg_lock
);
226 *ts
= ns_to_timespec64(ns
);
231 static int mv88e6xxx_ptp_settime(struct ptp_clock_info
*ptp
,
232 const struct timespec64
*ts
)
234 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
237 ns
= timespec64_to_ns(ts
);
239 mutex_lock(&chip
->reg_lock
);
240 timecounter_init(&chip
->tstamp_tc
, &chip
->tstamp_cc
, ns
);
241 mutex_unlock(&chip
->reg_lock
);
246 static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip
*chip
,
247 struct ptp_clock_request
*rq
, int on
)
249 int rising
= (rq
->extts
.flags
& PTP_RISING_EDGE
);
254 pin
= ptp_find_pin(chip
->ptp_clock
, PTP_PF_EXTTS
, rq
->extts
.index
);
259 mutex_lock(&chip
->reg_lock
);
262 func
= MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ
;
264 err
= mv88e6352_set_gpio_func(chip
, pin
, func
, true);
268 schedule_delayed_work(&chip
->tai_event_work
,
269 TAI_EVENT_WORK_INTERVAL
);
271 err
= mv88e6352_config_eventcap(chip
, PTP_CLOCK_EXTTS
, rising
);
273 func
= MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO
;
275 err
= mv88e6352_set_gpio_func(chip
, pin
, func
, true);
277 cancel_delayed_work_sync(&chip
->tai_event_work
);
281 mutex_unlock(&chip
->reg_lock
);
286 static int mv88e6352_ptp_enable(struct ptp_clock_info
*ptp
,
287 struct ptp_clock_request
*rq
, int on
)
289 struct mv88e6xxx_chip
*chip
= ptp_to_chip(ptp
);
292 case PTP_CLK_REQ_EXTTS
:
293 return mv88e6352_ptp_enable_extts(chip
, rq
, on
);
299 static int mv88e6352_ptp_verify(struct ptp_clock_info
*ptp
, unsigned int pin
,
300 enum ptp_pin_function func
, unsigned int chan
)
313 const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops
= {
314 .clock_read
= mv88e6352_ptp_clock_read
,
315 .ptp_enable
= mv88e6352_ptp_enable
,
316 .ptp_verify
= mv88e6352_ptp_verify
,
317 .event_work
= mv88e6352_tai_event_work
,
318 .port_enable
= mv88e6352_hwtstamp_port_enable
,
319 .port_disable
= mv88e6352_hwtstamp_port_disable
,
321 .arr0_sts_reg
= MV88E6XXX_PORT_PTP_ARR0_STS
,
322 .arr1_sts_reg
= MV88E6XXX_PORT_PTP_ARR1_STS
,
323 .dep_sts_reg
= MV88E6XXX_PORT_PTP_DEP_STS
,
324 .rx_filters
= (1 << HWTSTAMP_FILTER_NONE
) |
325 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT
) |
326 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC
) |
327 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
) |
328 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT
) |
329 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC
) |
330 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
) |
331 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
) |
332 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC
) |
333 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
),
336 const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops
= {
337 .clock_read
= mv88e6165_ptp_clock_read
,
338 .global_enable
= mv88e6165_global_enable
,
339 .global_disable
= mv88e6165_global_disable
,
340 .arr0_sts_reg
= MV88E6165_PORT_PTP_ARR0_STS
,
341 .arr1_sts_reg
= MV88E6165_PORT_PTP_ARR1_STS
,
342 .dep_sts_reg
= MV88E6165_PORT_PTP_DEP_STS
,
343 .rx_filters
= (1 << HWTSTAMP_FILTER_NONE
) |
344 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT
) |
345 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC
) |
346 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
) |
347 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
) |
348 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC
) |
349 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
),
352 static u64
mv88e6xxx_ptp_clock_read(const struct cyclecounter
*cc
)
354 struct mv88e6xxx_chip
*chip
= cc_to_chip(cc
);
356 if (chip
->info
->ops
->ptp_ops
->clock_read
)
357 return chip
->info
->ops
->ptp_ops
->clock_read(cc
);
362 /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
363 * seconds; this task forces periodic reads so that we don't miss any.
365 #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
366 static void mv88e6xxx_ptp_overflow_check(struct work_struct
*work
)
368 struct delayed_work
*dw
= to_delayed_work(work
);
369 struct mv88e6xxx_chip
*chip
= dw_overflow_to_chip(dw
);
370 struct timespec64 ts
;
372 mv88e6xxx_ptp_gettime(&chip
->ptp_clock_info
, &ts
);
374 schedule_delayed_work(&chip
->overflow_work
,
375 MV88E6XXX_TAI_OVERFLOW_PERIOD
);
378 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip
*chip
)
380 const struct mv88e6xxx_ptp_ops
*ptp_ops
= chip
->info
->ops
->ptp_ops
;
383 /* Set up the cycle counter */
384 memset(&chip
->tstamp_cc
, 0, sizeof(chip
->tstamp_cc
));
385 chip
->tstamp_cc
.read
= mv88e6xxx_ptp_clock_read
;
386 chip
->tstamp_cc
.mask
= CYCLECOUNTER_MASK(32);
387 chip
->tstamp_cc
.mult
= CC_MULT
;
388 chip
->tstamp_cc
.shift
= CC_SHIFT
;
390 timecounter_init(&chip
->tstamp_tc
, &chip
->tstamp_cc
,
391 ktime_to_ns(ktime_get_real()));
393 INIT_DELAYED_WORK(&chip
->overflow_work
, mv88e6xxx_ptp_overflow_check
);
394 if (ptp_ops
->event_work
)
395 INIT_DELAYED_WORK(&chip
->tai_event_work
, ptp_ops
->event_work
);
397 chip
->ptp_clock_info
.owner
= THIS_MODULE
;
398 snprintf(chip
->ptp_clock_info
.name
, sizeof(chip
->ptp_clock_info
.name
),
399 "%s", dev_name(chip
->dev
));
400 chip
->ptp_clock_info
.max_adj
= 1000000;
402 chip
->ptp_clock_info
.n_ext_ts
= ptp_ops
->n_ext_ts
;
403 chip
->ptp_clock_info
.n_per_out
= 0;
404 chip
->ptp_clock_info
.n_pins
= mv88e6xxx_num_gpio(chip
);
405 chip
->ptp_clock_info
.pps
= 0;
407 for (i
= 0; i
< chip
->ptp_clock_info
.n_pins
; ++i
) {
408 struct ptp_pin_desc
*ppd
= &chip
->pin_config
[i
];
410 snprintf(ppd
->name
, sizeof(ppd
->name
), "mv88e6xxx_gpio%d", i
);
412 ppd
->func
= PTP_PF_NONE
;
414 chip
->ptp_clock_info
.pin_config
= chip
->pin_config
;
416 chip
->ptp_clock_info
.adjfine
= mv88e6xxx_ptp_adjfine
;
417 chip
->ptp_clock_info
.adjtime
= mv88e6xxx_ptp_adjtime
;
418 chip
->ptp_clock_info
.gettime64
= mv88e6xxx_ptp_gettime
;
419 chip
->ptp_clock_info
.settime64
= mv88e6xxx_ptp_settime
;
420 chip
->ptp_clock_info
.enable
= ptp_ops
->ptp_enable
;
421 chip
->ptp_clock_info
.verify
= ptp_ops
->ptp_verify
;
422 chip
->ptp_clock_info
.do_aux_work
= mv88e6xxx_hwtstamp_work
;
424 chip
->ptp_clock
= ptp_clock_register(&chip
->ptp_clock_info
, chip
->dev
);
425 if (IS_ERR(chip
->ptp_clock
))
426 return PTR_ERR(chip
->ptp_clock
);
428 schedule_delayed_work(&chip
->overflow_work
,
429 MV88E6XXX_TAI_OVERFLOW_PERIOD
);
434 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip
*chip
)
436 if (chip
->ptp_clock
) {
437 cancel_delayed_work_sync(&chip
->overflow_work
);
438 if (chip
->info
->ops
->ptp_ops
->event_work
)
439 cancel_delayed_work_sync(&chip
->tai_event_work
);
441 ptp_clock_unregister(chip
->ptp_clock
);
442 chip
->ptp_clock
= NULL
;