2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/delay.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_bridge.h>
20 #include <linux/jiffies.h>
21 #include <linux/list.h>
22 #include <linux/mdio.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/phy.h>
28 #include <net/switchdev.h>
29 #include "mv88e6xxx.h"
31 static void assert_smi_lock(struct mv88e6xxx_priv_state
*ps
)
33 if (unlikely(!mutex_is_locked(&ps
->smi_mutex
))) {
34 dev_err(ps
->dev
, "SMI lock not held!\n");
39 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
40 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
41 * will be directly accessible on some {device address,register address}
42 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
43 * will only respond to SMI transactions to that specific address, and
44 * an indirect addressing mechanism needs to be used to access its
47 static int mv88e6xxx_reg_wait_ready(struct mii_bus
*bus
, int sw_addr
)
52 for (i
= 0; i
< 16; i
++) {
53 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_CMD
);
57 if ((ret
& SMI_CMD_BUSY
) == 0)
64 static int __mv88e6xxx_reg_read(struct mii_bus
*bus
, int sw_addr
, int addr
,
70 return mdiobus_read_nested(bus
, addr
, reg
);
72 /* Wait for the bus to become free. */
73 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
77 /* Transmit the read command. */
78 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
79 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
83 /* Wait for the read command to complete. */
84 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
89 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_DATA
);
96 static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state
*ps
,
103 ret
= __mv88e6xxx_reg_read(ps
->bus
, ps
->sw_addr
, addr
, reg
);
107 dev_dbg(ps
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
113 int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state
*ps
, int addr
, int reg
)
117 mutex_lock(&ps
->smi_mutex
);
118 ret
= _mv88e6xxx_reg_read(ps
, addr
, reg
);
119 mutex_unlock(&ps
->smi_mutex
);
124 static int __mv88e6xxx_reg_write(struct mii_bus
*bus
, int sw_addr
, int addr
,
130 return mdiobus_write_nested(bus
, addr
, reg
, val
);
132 /* Wait for the bus to become free. */
133 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
137 /* Transmit the data to write. */
138 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_DATA
, val
);
142 /* Transmit the write command. */
143 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
144 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
148 /* Wait for the write command to complete. */
149 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
156 static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
161 dev_dbg(ps
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
164 return __mv88e6xxx_reg_write(ps
->bus
, ps
->sw_addr
, addr
, reg
, val
);
167 int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
172 mutex_lock(&ps
->smi_mutex
);
173 ret
= _mv88e6xxx_reg_write(ps
, addr
, reg
, val
);
174 mutex_unlock(&ps
->smi_mutex
);
179 static int mv88e6xxx_set_addr_direct(struct dsa_switch
*ds
, u8
*addr
)
181 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
184 err
= mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_01
,
185 (addr
[0] << 8) | addr
[1]);
189 err
= mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_23
,
190 (addr
[2] << 8) | addr
[3]);
194 return mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_45
,
195 (addr
[4] << 8) | addr
[5]);
198 static int mv88e6xxx_set_addr_indirect(struct dsa_switch
*ds
, u8
*addr
)
200 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
204 for (i
= 0; i
< 6; i
++) {
207 /* Write the MAC address byte. */
208 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SWITCH_MAC
,
209 GLOBAL2_SWITCH_MAC_BUSY
|
214 /* Wait for the write to complete. */
215 for (j
= 0; j
< 16; j
++) {
216 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
,
221 if ((ret
& GLOBAL2_SWITCH_MAC_BUSY
) == 0)
231 int mv88e6xxx_set_addr(struct dsa_switch
*ds
, u8
*addr
)
233 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
235 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SWITCH_MAC
))
236 return mv88e6xxx_set_addr_indirect(ds
, addr
);
238 return mv88e6xxx_set_addr_direct(ds
, addr
);
241 static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state
*ps
, int addr
,
245 return _mv88e6xxx_reg_read(ps
, addr
, regnum
);
249 static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
253 return _mv88e6xxx_reg_write(ps
, addr
, regnum
, val
);
257 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state
*ps
)
260 unsigned long timeout
;
262 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_CONTROL
);
266 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL
,
267 ret
& ~GLOBAL_CONTROL_PPU_ENABLE
);
271 timeout
= jiffies
+ 1 * HZ
;
272 while (time_before(jiffies
, timeout
)) {
273 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATUS
);
277 usleep_range(1000, 2000);
278 if ((ret
& GLOBAL_STATUS_PPU_MASK
) !=
279 GLOBAL_STATUS_PPU_POLLING
)
286 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state
*ps
)
289 unsigned long timeout
;
291 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_CONTROL
);
295 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL
,
296 ret
| GLOBAL_CONTROL_PPU_ENABLE
);
300 timeout
= jiffies
+ 1 * HZ
;
301 while (time_before(jiffies
, timeout
)) {
302 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATUS
);
306 usleep_range(1000, 2000);
307 if ((ret
& GLOBAL_STATUS_PPU_MASK
) ==
308 GLOBAL_STATUS_PPU_POLLING
)
315 static void mv88e6xxx_ppu_reenable_work(struct work_struct
*ugly
)
317 struct mv88e6xxx_priv_state
*ps
;
319 ps
= container_of(ugly
, struct mv88e6xxx_priv_state
, ppu_work
);
321 mutex_lock(&ps
->smi_mutex
);
323 if (mutex_trylock(&ps
->ppu_mutex
)) {
324 if (mv88e6xxx_ppu_enable(ps
) == 0)
325 ps
->ppu_disabled
= 0;
326 mutex_unlock(&ps
->ppu_mutex
);
329 mutex_unlock(&ps
->smi_mutex
);
332 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps
)
334 struct mv88e6xxx_priv_state
*ps
= (void *)_ps
;
336 schedule_work(&ps
->ppu_work
);
339 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state
*ps
)
343 mutex_lock(&ps
->ppu_mutex
);
345 /* If the PHY polling unit is enabled, disable it so that
346 * we can access the PHY registers. If it was already
347 * disabled, cancel the timer that is going to re-enable
350 if (!ps
->ppu_disabled
) {
351 ret
= mv88e6xxx_ppu_disable(ps
);
353 mutex_unlock(&ps
->ppu_mutex
);
356 ps
->ppu_disabled
= 1;
358 del_timer(&ps
->ppu_timer
);
365 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state
*ps
)
367 /* Schedule a timer to re-enable the PHY polling unit. */
368 mod_timer(&ps
->ppu_timer
, jiffies
+ msecs_to_jiffies(10));
369 mutex_unlock(&ps
->ppu_mutex
);
372 void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state
*ps
)
374 mutex_init(&ps
->ppu_mutex
);
375 INIT_WORK(&ps
->ppu_work
, mv88e6xxx_ppu_reenable_work
);
376 init_timer(&ps
->ppu_timer
);
377 ps
->ppu_timer
.data
= (unsigned long)ps
;
378 ps
->ppu_timer
.function
= mv88e6xxx_ppu_reenable_timer
;
381 static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state
*ps
, int addr
,
386 ret
= mv88e6xxx_ppu_access_get(ps
);
388 ret
= _mv88e6xxx_reg_read(ps
, addr
, regnum
);
389 mv88e6xxx_ppu_access_put(ps
);
395 static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state
*ps
, int addr
,
400 ret
= mv88e6xxx_ppu_access_get(ps
);
402 ret
= _mv88e6xxx_reg_write(ps
, addr
, regnum
, val
);
403 mv88e6xxx_ppu_access_put(ps
);
409 static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state
*ps
)
411 return ps
->info
->family
== MV88E6XXX_FAMILY_6065
;
414 static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state
*ps
)
416 return ps
->info
->family
== MV88E6XXX_FAMILY_6095
;
419 static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state
*ps
)
421 return ps
->info
->family
== MV88E6XXX_FAMILY_6097
;
424 static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state
*ps
)
426 return ps
->info
->family
== MV88E6XXX_FAMILY_6165
;
429 static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state
*ps
)
431 return ps
->info
->family
== MV88E6XXX_FAMILY_6185
;
434 static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state
*ps
)
436 return ps
->info
->family
== MV88E6XXX_FAMILY_6320
;
439 static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state
*ps
)
441 return ps
->info
->family
== MV88E6XXX_FAMILY_6351
;
444 static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state
*ps
)
446 return ps
->info
->family
== MV88E6XXX_FAMILY_6352
;
449 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state
*ps
)
451 return ps
->info
->num_databases
;
454 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state
*ps
)
456 /* Does the device have dedicated FID registers for ATU and VTU ops? */
457 if (mv88e6xxx_6097_family(ps
) || mv88e6xxx_6165_family(ps
) ||
458 mv88e6xxx_6351_family(ps
) || mv88e6xxx_6352_family(ps
))
464 /* We expect the switch to perform auto negotiation if there is a real
465 * phy. However, in the case of a fixed link phy, we force the port
466 * settings from the fixed link settings.
468 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
469 struct phy_device
*phydev
)
471 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
475 if (!phy_is_pseudo_fixed_link(phydev
))
478 mutex_lock(&ps
->smi_mutex
);
480 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_PCS_CTRL
);
484 reg
= ret
& ~(PORT_PCS_CTRL_LINK_UP
|
485 PORT_PCS_CTRL_FORCE_LINK
|
486 PORT_PCS_CTRL_DUPLEX_FULL
|
487 PORT_PCS_CTRL_FORCE_DUPLEX
|
488 PORT_PCS_CTRL_UNFORCED
);
490 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
492 reg
|= PORT_PCS_CTRL_LINK_UP
;
494 if (mv88e6xxx_6065_family(ps
) && phydev
->speed
> SPEED_100
)
497 switch (phydev
->speed
) {
499 reg
|= PORT_PCS_CTRL_1000
;
502 reg
|= PORT_PCS_CTRL_100
;
505 reg
|= PORT_PCS_CTRL_10
;
508 pr_info("Unknown speed");
512 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
513 if (phydev
->duplex
== DUPLEX_FULL
)
514 reg
|= PORT_PCS_CTRL_DUPLEX_FULL
;
516 if ((mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
)) &&
517 (port
>= ps
->info
->num_ports
- 2)) {
518 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
519 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
520 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
521 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
522 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
523 reg
|= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
524 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
526 _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_PCS_CTRL
, reg
);
529 mutex_unlock(&ps
->smi_mutex
);
532 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state
*ps
)
537 for (i
= 0; i
< 10; i
++) {
538 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
);
539 if ((ret
& GLOBAL_STATS_OP_BUSY
) == 0)
546 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state
*ps
,
551 if (mv88e6xxx_6320_family(ps
) || mv88e6xxx_6352_family(ps
))
552 port
= (port
+ 1) << 5;
554 /* Snapshot the hardware statistics counters for this port. */
555 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
556 GLOBAL_STATS_OP_CAPTURE_PORT
|
557 GLOBAL_STATS_OP_HIST_RX_TX
| port
);
561 /* Wait for the snapshotting to complete. */
562 ret
= _mv88e6xxx_stats_wait(ps
);
569 static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state
*ps
,
577 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
578 GLOBAL_STATS_OP_READ_CAPTURED
|
579 GLOBAL_STATS_OP_HIST_RX_TX
| stat
);
583 ret
= _mv88e6xxx_stats_wait(ps
);
587 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_32
);
593 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_01
);
600 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
601 { "in_good_octets", 8, 0x00, BANK0
, },
602 { "in_bad_octets", 4, 0x02, BANK0
, },
603 { "in_unicast", 4, 0x04, BANK0
, },
604 { "in_broadcasts", 4, 0x06, BANK0
, },
605 { "in_multicasts", 4, 0x07, BANK0
, },
606 { "in_pause", 4, 0x16, BANK0
, },
607 { "in_undersize", 4, 0x18, BANK0
, },
608 { "in_fragments", 4, 0x19, BANK0
, },
609 { "in_oversize", 4, 0x1a, BANK0
, },
610 { "in_jabber", 4, 0x1b, BANK0
, },
611 { "in_rx_error", 4, 0x1c, BANK0
, },
612 { "in_fcs_error", 4, 0x1d, BANK0
, },
613 { "out_octets", 8, 0x0e, BANK0
, },
614 { "out_unicast", 4, 0x10, BANK0
, },
615 { "out_broadcasts", 4, 0x13, BANK0
, },
616 { "out_multicasts", 4, 0x12, BANK0
, },
617 { "out_pause", 4, 0x15, BANK0
, },
618 { "excessive", 4, 0x11, BANK0
, },
619 { "collisions", 4, 0x1e, BANK0
, },
620 { "deferred", 4, 0x05, BANK0
, },
621 { "single", 4, 0x14, BANK0
, },
622 { "multiple", 4, 0x17, BANK0
, },
623 { "out_fcs_error", 4, 0x03, BANK0
, },
624 { "late", 4, 0x1f, BANK0
, },
625 { "hist_64bytes", 4, 0x08, BANK0
, },
626 { "hist_65_127bytes", 4, 0x09, BANK0
, },
627 { "hist_128_255bytes", 4, 0x0a, BANK0
, },
628 { "hist_256_511bytes", 4, 0x0b, BANK0
, },
629 { "hist_512_1023bytes", 4, 0x0c, BANK0
, },
630 { "hist_1024_max_bytes", 4, 0x0d, BANK0
, },
631 { "sw_in_discards", 4, 0x10, PORT
, },
632 { "sw_in_filtered", 2, 0x12, PORT
, },
633 { "sw_out_filtered", 2, 0x13, PORT
, },
634 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
635 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
636 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
637 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
638 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
639 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
640 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
641 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
642 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
643 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
644 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
645 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
646 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
647 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
648 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
649 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
650 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
651 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
652 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
653 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
654 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
655 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
656 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
657 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
658 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
659 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
662 static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state
*ps
,
663 struct mv88e6xxx_hw_stat
*stat
)
665 switch (stat
->type
) {
669 return mv88e6xxx_6320_family(ps
);
671 return mv88e6xxx_6095_family(ps
) ||
672 mv88e6xxx_6185_family(ps
) ||
673 mv88e6xxx_6097_family(ps
) ||
674 mv88e6xxx_6165_family(ps
) ||
675 mv88e6xxx_6351_family(ps
) ||
676 mv88e6xxx_6352_family(ps
);
681 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state
*ps
,
682 struct mv88e6xxx_hw_stat
*s
,
692 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), s
->reg
);
697 if (s
->sizeof_stat
== 4) {
698 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
),
707 _mv88e6xxx_stats_read(ps
, s
->reg
, &low
);
708 if (s
->sizeof_stat
== 8)
709 _mv88e6xxx_stats_read(ps
, s
->reg
+ 1, &high
);
711 value
= (((u64
)high
) << 16) | low
;
715 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
718 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
719 struct mv88e6xxx_hw_stat
*stat
;
722 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
723 stat
= &mv88e6xxx_hw_stats
[i
];
724 if (mv88e6xxx_has_stat(ps
, stat
)) {
725 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
732 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
734 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
735 struct mv88e6xxx_hw_stat
*stat
;
738 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
739 stat
= &mv88e6xxx_hw_stats
[i
];
740 if (mv88e6xxx_has_stat(ps
, stat
))
746 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
749 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
750 struct mv88e6xxx_hw_stat
*stat
;
754 mutex_lock(&ps
->smi_mutex
);
756 ret
= _mv88e6xxx_stats_snapshot(ps
, port
);
758 mutex_unlock(&ps
->smi_mutex
);
761 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
762 stat
= &mv88e6xxx_hw_stats
[i
];
763 if (mv88e6xxx_has_stat(ps
, stat
)) {
764 data
[j
] = _mv88e6xxx_get_ethtool_stat(ps
, stat
, port
);
769 mutex_unlock(&ps
->smi_mutex
);
772 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
774 return 32 * sizeof(u16
);
777 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
778 struct ethtool_regs
*regs
, void *_p
)
780 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
786 memset(p
, 0xff, 32 * sizeof(u16
));
788 mutex_lock(&ps
->smi_mutex
);
790 for (i
= 0; i
< 32; i
++) {
793 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), i
);
798 mutex_unlock(&ps
->smi_mutex
);
801 static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state
*ps
, int reg
, int offset
,
804 unsigned long timeout
= jiffies
+ HZ
/ 10;
806 while (time_before(jiffies
, timeout
)) {
809 ret
= _mv88e6xxx_reg_read(ps
, reg
, offset
);
815 usleep_range(1000, 2000);
820 static int mv88e6xxx_wait(struct mv88e6xxx_priv_state
*ps
, int reg
,
821 int offset
, u16 mask
)
825 mutex_lock(&ps
->smi_mutex
);
826 ret
= _mv88e6xxx_wait(ps
, reg
, offset
, mask
);
827 mutex_unlock(&ps
->smi_mutex
);
832 static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state
*ps
)
834 return _mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
835 GLOBAL2_SMI_OP_BUSY
);
838 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch
*ds
)
840 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
842 return mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
843 GLOBAL2_EEPROM_OP_LOAD
);
846 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch
*ds
)
848 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
850 return mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
851 GLOBAL2_EEPROM_OP_BUSY
);
854 static int mv88e6xxx_read_eeprom_word(struct dsa_switch
*ds
, int addr
)
856 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
859 mutex_lock(&ps
->eeprom_mutex
);
861 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
862 GLOBAL2_EEPROM_OP_READ
|
863 (addr
& GLOBAL2_EEPROM_OP_ADDR_MASK
));
867 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
871 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
);
873 mutex_unlock(&ps
->eeprom_mutex
);
877 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
879 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
881 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
882 return ps
->eeprom_len
;
887 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
888 struct ethtool_eeprom
*eeprom
, u8
*data
)
890 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
895 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
898 offset
= eeprom
->offset
;
902 eeprom
->magic
= 0xc3ec4951;
904 ret
= mv88e6xxx_eeprom_load_wait(ds
);
911 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
915 *data
++ = (word
>> 8) & 0xff;
925 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
929 *data
++ = word
& 0xff;
930 *data
++ = (word
>> 8) & 0xff;
940 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
944 *data
++ = word
& 0xff;
954 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch
*ds
)
956 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
959 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
);
963 if (!(ret
& GLOBAL2_EEPROM_OP_WRITE_EN
))
969 static int mv88e6xxx_write_eeprom_word(struct dsa_switch
*ds
, int addr
,
972 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
975 mutex_lock(&ps
->eeprom_mutex
);
977 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
, data
);
981 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
982 GLOBAL2_EEPROM_OP_WRITE
|
983 (addr
& GLOBAL2_EEPROM_OP_ADDR_MASK
));
987 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
989 mutex_unlock(&ps
->eeprom_mutex
);
993 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
994 struct ethtool_eeprom
*eeprom
, u8
*data
)
996 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1001 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
1004 if (eeprom
->magic
!= 0xc3ec4951)
1007 ret
= mv88e6xxx_eeprom_is_readonly(ds
);
1011 offset
= eeprom
->offset
;
1015 ret
= mv88e6xxx_eeprom_load_wait(ds
);
1022 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
1026 word
= (*data
++ << 8) | (word
& 0xff);
1028 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1041 word
|= *data
++ << 8;
1043 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1055 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
1059 word
= (word
& 0xff00) | *data
++;
1061 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1073 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state
*ps
)
1075 return _mv88e6xxx_wait(ps
, REG_GLOBAL
, GLOBAL_ATU_OP
,
1076 GLOBAL_ATU_OP_BUSY
);
1079 static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state
*ps
,
1080 int addr
, int regnum
)
1084 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
1085 GLOBAL2_SMI_OP_22_READ
| (addr
<< 5) |
1090 ret
= _mv88e6xxx_phy_wait(ps
);
1094 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
);
1099 static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state
*ps
,
1100 int addr
, int regnum
, u16 val
)
1104 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
, val
);
1108 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
1109 GLOBAL2_SMI_OP_22_WRITE
| (addr
<< 5) |
1112 return _mv88e6xxx_phy_wait(ps
);
1115 static int mv88e6xxx_get_eee(struct dsa_switch
*ds
, int port
,
1116 struct ethtool_eee
*e
)
1118 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1121 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEE
))
1124 mutex_lock(&ps
->smi_mutex
);
1126 reg
= _mv88e6xxx_phy_read_indirect(ps
, port
, 16);
1130 e
->eee_enabled
= !!(reg
& 0x0200);
1131 e
->tx_lpi_enabled
= !!(reg
& 0x0100);
1133 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_STATUS
);
1137 e
->eee_active
= !!(reg
& PORT_STATUS_EEE
);
1141 mutex_unlock(&ps
->smi_mutex
);
1145 static int mv88e6xxx_set_eee(struct dsa_switch
*ds
, int port
,
1146 struct phy_device
*phydev
, struct ethtool_eee
*e
)
1148 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1152 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEE
))
1155 mutex_lock(&ps
->smi_mutex
);
1157 ret
= _mv88e6xxx_phy_read_indirect(ps
, port
, 16);
1161 reg
= ret
& ~0x0300;
1164 if (e
->tx_lpi_enabled
)
1167 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 16, reg
);
1169 mutex_unlock(&ps
->smi_mutex
);
1174 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state
*ps
, u16 fid
, u16 cmd
)
1178 if (mv88e6xxx_has_fid_reg(ps
)) {
1179 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_FID
, fid
);
1182 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1183 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1184 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
);
1188 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
1190 ((fid
<< 8) & 0xf000));
1194 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1198 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_OP
, cmd
);
1202 return _mv88e6xxx_atu_wait(ps
);
1205 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state
*ps
,
1206 struct mv88e6xxx_atu_entry
*entry
)
1208 u16 data
= entry
->state
& GLOBAL_ATU_DATA_STATE_MASK
;
1210 if (entry
->state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
1211 unsigned int mask
, shift
;
1214 data
|= GLOBAL_ATU_DATA_TRUNK
;
1215 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
1216 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
1218 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
1219 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
1222 data
|= (entry
->portv_trunkid
<< shift
) & mask
;
1225 return _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_DATA
, data
);
1228 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state
*ps
,
1229 struct mv88e6xxx_atu_entry
*entry
,
1235 err
= _mv88e6xxx_atu_wait(ps
);
1239 err
= _mv88e6xxx_atu_data_write(ps
, entry
);
1244 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB
:
1245 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB
;
1247 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL
:
1248 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC
;
1251 return _mv88e6xxx_atu_cmd(ps
, entry
->fid
, op
);
1254 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state
*ps
,
1255 u16 fid
, bool static_too
)
1257 struct mv88e6xxx_atu_entry entry
= {
1259 .state
= 0, /* EntryState bits must be 0 */
1262 return _mv88e6xxx_atu_flush_move(ps
, &entry
, static_too
);
1265 static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
1266 int from_port
, int to_port
, bool static_too
)
1268 struct mv88e6xxx_atu_entry entry
= {
1273 /* EntryState bits must be 0xF */
1274 entry
.state
= GLOBAL_ATU_DATA_STATE_MASK
;
1276 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1277 entry
.portv_trunkid
= (to_port
& 0x0f) << 4;
1278 entry
.portv_trunkid
|= from_port
& 0x0f;
1280 return _mv88e6xxx_atu_flush_move(ps
, &entry
, static_too
);
1283 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
1284 int port
, bool static_too
)
1286 /* Destination port 0xF means remove the entries */
1287 return _mv88e6xxx_atu_move(ps
, fid
, port
, 0x0f, static_too
);
1290 static const char * const mv88e6xxx_port_state_names
[] = {
1291 [PORT_CONTROL_STATE_DISABLED
] = "Disabled",
1292 [PORT_CONTROL_STATE_BLOCKING
] = "Blocking/Listening",
1293 [PORT_CONTROL_STATE_LEARNING
] = "Learning",
1294 [PORT_CONTROL_STATE_FORWARDING
] = "Forwarding",
1297 static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state
*ps
, int port
,
1300 struct dsa_switch
*ds
= ps
->ds
;
1304 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL
);
1308 oldstate
= reg
& PORT_CONTROL_STATE_MASK
;
1310 if (oldstate
!= state
) {
1311 /* Flush forwarding database if we're moving a port
1312 * from Learning or Forwarding state to Disabled or
1313 * Blocking or Listening state.
1315 if ((oldstate
== PORT_CONTROL_STATE_LEARNING
||
1316 oldstate
== PORT_CONTROL_STATE_FORWARDING
)
1317 && (state
== PORT_CONTROL_STATE_DISABLED
||
1318 state
== PORT_CONTROL_STATE_BLOCKING
)) {
1319 ret
= _mv88e6xxx_atu_remove(ps
, 0, port
, false);
1324 reg
= (reg
& ~PORT_CONTROL_STATE_MASK
) | state
;
1325 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL
,
1330 netdev_dbg(ds
->ports
[port
].netdev
, "PortState %s (was %s)\n",
1331 mv88e6xxx_port_state_names
[state
],
1332 mv88e6xxx_port_state_names
[oldstate
]);
1338 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state
*ps
,
1341 struct net_device
*bridge
= ps
->ports
[port
].bridge_dev
;
1342 const u16 mask
= (1 << ps
->info
->num_ports
) - 1;
1343 struct dsa_switch
*ds
= ps
->ds
;
1344 u16 output_ports
= 0;
1348 /* allow CPU port or DSA link(s) to send frames to every port */
1349 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
1350 output_ports
= mask
;
1352 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1353 /* allow sending frames to every group member */
1354 if (bridge
&& ps
->ports
[i
].bridge_dev
== bridge
)
1355 output_ports
|= BIT(i
);
1357 /* allow sending frames to CPU port and DSA link(s) */
1358 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1359 output_ports
|= BIT(i
);
1363 /* prevent frames from going back out of the port they came in on */
1364 output_ports
&= ~BIT(port
);
1366 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_BASE_VLAN
);
1371 reg
|= output_ports
& mask
;
1373 return _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_BASE_VLAN
, reg
);
1376 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
1379 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1383 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PORTSTATE
))
1387 case BR_STATE_DISABLED
:
1388 stp_state
= PORT_CONTROL_STATE_DISABLED
;
1390 case BR_STATE_BLOCKING
:
1391 case BR_STATE_LISTENING
:
1392 stp_state
= PORT_CONTROL_STATE_BLOCKING
;
1394 case BR_STATE_LEARNING
:
1395 stp_state
= PORT_CONTROL_STATE_LEARNING
;
1397 case BR_STATE_FORWARDING
:
1399 stp_state
= PORT_CONTROL_STATE_FORWARDING
;
1403 mutex_lock(&ps
->smi_mutex
);
1404 err
= _mv88e6xxx_port_state(ps
, port
, stp_state
);
1405 mutex_unlock(&ps
->smi_mutex
);
1408 netdev_err(ds
->ports
[port
].netdev
,
1409 "failed to update state to %s\n",
1410 mv88e6xxx_port_state_names
[stp_state
]);
1413 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state
*ps
, int port
,
1416 struct dsa_switch
*ds
= ps
->ds
;
1420 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1424 pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1427 ret
&= ~PORT_DEFAULT_VLAN_MASK
;
1428 ret
|= *new & PORT_DEFAULT_VLAN_MASK
;
1430 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
1431 PORT_DEFAULT_VLAN
, ret
);
1435 netdev_dbg(ds
->ports
[port
].netdev
,
1436 "DefaultVID %d (was %d)\n", *new, pvid
);
1445 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state
*ps
,
1446 int port
, u16
*pvid
)
1448 return _mv88e6xxx_port_pvid(ps
, port
, NULL
, pvid
);
1451 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state
*ps
,
1454 return _mv88e6xxx_port_pvid(ps
, port
, &pvid
, NULL
);
1457 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state
*ps
)
1459 return _mv88e6xxx_wait(ps
, REG_GLOBAL
, GLOBAL_VTU_OP
,
1460 GLOBAL_VTU_OP_BUSY
);
1463 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state
*ps
, u16 op
)
1467 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_OP
, op
);
1471 return _mv88e6xxx_vtu_wait(ps
);
1474 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state
*ps
)
1478 ret
= _mv88e6xxx_vtu_wait(ps
);
1482 return _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_FLUSH_ALL
);
1485 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state
*ps
,
1486 struct mv88e6xxx_vtu_stu_entry
*entry
,
1487 unsigned int nibble_offset
)
1493 for (i
= 0; i
< 3; ++i
) {
1494 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1495 GLOBAL_VTU_DATA_0_3
+ i
);
1502 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1503 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1504 u16 reg
= regs
[i
/ 4];
1506 entry
->data
[i
] = (reg
>> shift
) & GLOBAL_VTU_STU_DATA_MASK
;
1512 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state
*ps
,
1513 struct mv88e6xxx_vtu_stu_entry
*entry
)
1515 return _mv88e6xxx_vtu_stu_data_read(ps
, entry
, 0);
1518 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state
*ps
,
1519 struct mv88e6xxx_vtu_stu_entry
*entry
)
1521 return _mv88e6xxx_vtu_stu_data_read(ps
, entry
, 2);
1524 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state
*ps
,
1525 struct mv88e6xxx_vtu_stu_entry
*entry
,
1526 unsigned int nibble_offset
)
1528 u16 regs
[3] = { 0 };
1532 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1533 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1534 u8 data
= entry
->data
[i
];
1536 regs
[i
/ 4] |= (data
& GLOBAL_VTU_STU_DATA_MASK
) << shift
;
1539 for (i
= 0; i
< 3; ++i
) {
1540 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
,
1541 GLOBAL_VTU_DATA_0_3
+ i
, regs
[i
]);
1549 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state
*ps
,
1550 struct mv88e6xxx_vtu_stu_entry
*entry
)
1552 return _mv88e6xxx_vtu_stu_data_write(ps
, entry
, 0);
1555 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state
*ps
,
1556 struct mv88e6xxx_vtu_stu_entry
*entry
)
1558 return _mv88e6xxx_vtu_stu_data_write(ps
, entry
, 2);
1561 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state
*ps
, u16 vid
)
1563 return _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
,
1564 vid
& GLOBAL_VTU_VID_MASK
);
1567 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state
*ps
,
1568 struct mv88e6xxx_vtu_stu_entry
*entry
)
1570 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1573 ret
= _mv88e6xxx_vtu_wait(ps
);
1577 ret
= _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_VTU_GET_NEXT
);
1581 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1585 next
.vid
= ret
& GLOBAL_VTU_VID_MASK
;
1586 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1589 ret
= mv88e6xxx_vtu_data_read(ps
, &next
);
1593 if (mv88e6xxx_has_fid_reg(ps
)) {
1594 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1599 next
.fid
= ret
& GLOBAL_VTU_FID_MASK
;
1600 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1601 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1602 * VTU DBNum[3:0] are located in VTU Operation 3:0
1604 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1609 next
.fid
= (ret
& 0xf00) >> 4;
1610 next
.fid
|= ret
& 0xf;
1613 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_STU
)) {
1614 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1619 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1627 static int mv88e6xxx_port_vlan_dump(struct dsa_switch
*ds
, int port
,
1628 struct switchdev_obj_port_vlan
*vlan
,
1629 int (*cb
)(struct switchdev_obj
*obj
))
1631 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1632 struct mv88e6xxx_vtu_stu_entry next
;
1636 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VTU
))
1639 mutex_lock(&ps
->smi_mutex
);
1641 err
= _mv88e6xxx_port_pvid_get(ps
, port
, &pvid
);
1645 err
= _mv88e6xxx_vtu_vid_write(ps
, GLOBAL_VTU_VID_MASK
);
1650 err
= _mv88e6xxx_vtu_getnext(ps
, &next
);
1657 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1660 /* reinit and dump this VLAN obj */
1661 vlan
->vid_begin
= vlan
->vid_end
= next
.vid
;
1664 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1665 vlan
->flags
|= BRIDGE_VLAN_INFO_UNTAGGED
;
1667 if (next
.vid
== pvid
)
1668 vlan
->flags
|= BRIDGE_VLAN_INFO_PVID
;
1670 err
= cb(&vlan
->obj
);
1673 } while (next
.vid
< GLOBAL_VTU_VID_MASK
);
1676 mutex_unlock(&ps
->smi_mutex
);
1681 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state
*ps
,
1682 struct mv88e6xxx_vtu_stu_entry
*entry
)
1684 u16 op
= GLOBAL_VTU_OP_VTU_LOAD_PURGE
;
1688 ret
= _mv88e6xxx_vtu_wait(ps
);
1695 /* Write port member tags */
1696 ret
= mv88e6xxx_vtu_data_write(ps
, entry
);
1700 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_STU
)) {
1701 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1702 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1707 if (mv88e6xxx_has_fid_reg(ps
)) {
1708 reg
= entry
->fid
& GLOBAL_VTU_FID_MASK
;
1709 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_FID
, reg
);
1712 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1713 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1714 * VTU DBNum[3:0] are located in VTU Operation 3:0
1716 op
|= (entry
->fid
& 0xf0) << 8;
1717 op
|= entry
->fid
& 0xf;
1720 reg
= GLOBAL_VTU_VID_VALID
;
1722 reg
|= entry
->vid
& GLOBAL_VTU_VID_MASK
;
1723 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1727 return _mv88e6xxx_vtu_cmd(ps
, op
);
1730 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state
*ps
, u8 sid
,
1731 struct mv88e6xxx_vtu_stu_entry
*entry
)
1733 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1736 ret
= _mv88e6xxx_vtu_wait(ps
);
1740 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1741 sid
& GLOBAL_VTU_SID_MASK
);
1745 ret
= _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_STU_GET_NEXT
);
1749 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
);
1753 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1755 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1759 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1762 ret
= mv88e6xxx_stu_data_read(ps
, &next
);
1771 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state
*ps
,
1772 struct mv88e6xxx_vtu_stu_entry
*entry
)
1777 ret
= _mv88e6xxx_vtu_wait(ps
);
1784 /* Write port states */
1785 ret
= mv88e6xxx_stu_data_write(ps
, entry
);
1789 reg
= GLOBAL_VTU_VID_VALID
;
1791 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1795 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1796 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1800 return _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_STU_LOAD_PURGE
);
1803 static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state
*ps
, int port
,
1806 struct dsa_switch
*ds
= ps
->ds
;
1811 if (mv88e6xxx_num_databases(ps
) == 4096)
1813 else if (mv88e6xxx_num_databases(ps
) == 256)
1818 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1819 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_BASE_VLAN
);
1823 fid
= (ret
& PORT_BASE_VLAN_FID_3_0_MASK
) >> 12;
1826 ret
&= ~PORT_BASE_VLAN_FID_3_0_MASK
;
1827 ret
|= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK
;
1829 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_BASE_VLAN
,
1835 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1836 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL_1
);
1840 fid
|= (ret
& upper_mask
) << 4;
1844 ret
|= (*new >> 4) & upper_mask
;
1846 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_1
,
1851 netdev_dbg(ds
->ports
[port
].netdev
,
1852 "FID %d (was %d)\n", *new, fid
);
1861 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state
*ps
,
1864 return _mv88e6xxx_port_fid(ps
, port
, NULL
, fid
);
1867 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state
*ps
,
1870 return _mv88e6xxx_port_fid(ps
, port
, &fid
, NULL
);
1873 static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state
*ps
, u16
*fid
)
1875 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1876 struct mv88e6xxx_vtu_stu_entry vlan
;
1879 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1881 /* Set every FID bit used by the (un)bridged ports */
1882 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1883 err
= _mv88e6xxx_port_fid_get(ps
, i
, fid
);
1887 set_bit(*fid
, fid_bitmap
);
1890 /* Set every FID bit used by the VLAN entries */
1891 err
= _mv88e6xxx_vtu_vid_write(ps
, GLOBAL_VTU_VID_MASK
);
1896 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
1903 set_bit(vlan
.fid
, fid_bitmap
);
1904 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
1906 /* The reset value 0x000 is used to indicate that multiple address
1907 * databases are not needed. Return the next positive available.
1909 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1910 if (unlikely(*fid
>= mv88e6xxx_num_databases(ps
)))
1913 /* Clear the database */
1914 return _mv88e6xxx_atu_flush(ps
, *fid
, true);
1917 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state
*ps
, u16 vid
,
1918 struct mv88e6xxx_vtu_stu_entry
*entry
)
1920 struct dsa_switch
*ds
= ps
->ds
;
1921 struct mv88e6xxx_vtu_stu_entry vlan
= {
1927 err
= _mv88e6xxx_fid_new(ps
, &vlan
.fid
);
1931 /* exclude all ports except the CPU and DSA ports */
1932 for (i
= 0; i
< ps
->info
->num_ports
; ++i
)
1933 vlan
.data
[i
] = dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
)
1934 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1935 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1937 if (mv88e6xxx_6097_family(ps
) || mv88e6xxx_6165_family(ps
) ||
1938 mv88e6xxx_6351_family(ps
) || mv88e6xxx_6352_family(ps
)) {
1939 struct mv88e6xxx_vtu_stu_entry vstp
;
1941 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1942 * implemented, only one STU entry is needed to cover all VTU
1943 * entries. Thus, validate the SID 0.
1946 err
= _mv88e6xxx_stu_getnext(ps
, GLOBAL_VTU_SID_MASK
, &vstp
);
1950 if (vstp
.sid
!= vlan
.sid
|| !vstp
.valid
) {
1951 memset(&vstp
, 0, sizeof(vstp
));
1953 vstp
.sid
= vlan
.sid
;
1955 err
= _mv88e6xxx_stu_loadpurge(ps
, &vstp
);
1965 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state
*ps
, u16 vid
,
1966 struct mv88e6xxx_vtu_stu_entry
*entry
, bool creat
)
1973 err
= _mv88e6xxx_vtu_vid_write(ps
, vid
- 1);
1977 err
= _mv88e6xxx_vtu_getnext(ps
, entry
);
1981 if (entry
->vid
!= vid
|| !entry
->valid
) {
1984 /* -ENOENT would've been more appropriate, but switchdev expects
1985 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1988 err
= _mv88e6xxx_vtu_new(ps
, vid
, entry
);
1994 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1995 u16 vid_begin
, u16 vid_end
)
1997 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1998 struct mv88e6xxx_vtu_stu_entry vlan
;
2004 mutex_lock(&ps
->smi_mutex
);
2006 err
= _mv88e6xxx_vtu_vid_write(ps
, vid_begin
- 1);
2011 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
2018 if (vlan
.vid
> vid_end
)
2021 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
2022 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
2026 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
2029 if (ps
->ports
[i
].bridge_dev
==
2030 ps
->ports
[port
].bridge_dev
)
2031 break; /* same bridge, check next VLAN */
2033 netdev_warn(ds
->ports
[port
].netdev
,
2034 "hardware VLAN %d already used by %s\n",
2036 netdev_name(ps
->ports
[i
].bridge_dev
));
2040 } while (vlan
.vid
< vid_end
);
2043 mutex_unlock(&ps
->smi_mutex
);
2048 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
2049 [PORT_CONTROL_2_8021Q_DISABLED
] = "Disabled",
2050 [PORT_CONTROL_2_8021Q_FALLBACK
] = "Fallback",
2051 [PORT_CONTROL_2_8021Q_CHECK
] = "Check",
2052 [PORT_CONTROL_2_8021Q_SECURE
] = "Secure",
2055 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
2056 bool vlan_filtering
)
2058 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2059 u16 old
, new = vlan_filtering
? PORT_CONTROL_2_8021Q_SECURE
:
2060 PORT_CONTROL_2_8021Q_DISABLED
;
2063 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VTU
))
2066 mutex_lock(&ps
->smi_mutex
);
2068 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL_2
);
2072 old
= ret
& PORT_CONTROL_2_8021Q_MASK
;
2075 ret
&= ~PORT_CONTROL_2_8021Q_MASK
;
2076 ret
|= new & PORT_CONTROL_2_8021Q_MASK
;
2078 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_2
,
2083 netdev_dbg(ds
->ports
[port
].netdev
, "802.1Q Mode %s (was %s)\n",
2084 mv88e6xxx_port_8021q_mode_names
[new],
2085 mv88e6xxx_port_8021q_mode_names
[old
]);
2090 mutex_unlock(&ps
->smi_mutex
);
2095 static int mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
2096 const struct switchdev_obj_port_vlan
*vlan
,
2097 struct switchdev_trans
*trans
)
2099 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2102 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VTU
))
2105 /* If the requested port doesn't belong to the same bridge as the VLAN
2106 * members, do not support it (yet) and fallback to software VLAN.
2108 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
2113 /* We don't need any dynamic resource from the kernel (yet),
2114 * so skip the prepare phase.
2119 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state
*ps
, int port
,
2120 u16 vid
, bool untagged
)
2122 struct mv88e6xxx_vtu_stu_entry vlan
;
2125 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, true);
2129 vlan
.data
[port
] = untagged
?
2130 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
:
2131 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
;
2133 return _mv88e6xxx_vtu_loadpurge(ps
, &vlan
);
2136 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
2137 const struct switchdev_obj_port_vlan
*vlan
,
2138 struct switchdev_trans
*trans
)
2140 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2141 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
2142 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
2145 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VTU
))
2148 mutex_lock(&ps
->smi_mutex
);
2150 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
2151 if (_mv88e6xxx_port_vlan_add(ps
, port
, vid
, untagged
))
2152 netdev_err(ds
->ports
[port
].netdev
,
2153 "failed to add VLAN %d%c\n",
2154 vid
, untagged
? 'u' : 't');
2156 if (pvid
&& _mv88e6xxx_port_pvid_set(ps
, port
, vlan
->vid_end
))
2157 netdev_err(ds
->ports
[port
].netdev
, "failed to set PVID %d\n",
2160 mutex_unlock(&ps
->smi_mutex
);
2163 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state
*ps
,
2166 struct dsa_switch
*ds
= ps
->ds
;
2167 struct mv88e6xxx_vtu_stu_entry vlan
;
2170 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, false);
2174 /* Tell switchdev if this VLAN is handled in software */
2175 if (vlan
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
2178 vlan
.data
[port
] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
2180 /* keep the VLAN unless all ports are excluded */
2182 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
2183 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
2186 if (vlan
.data
[i
] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
2192 err
= _mv88e6xxx_vtu_loadpurge(ps
, &vlan
);
2196 return _mv88e6xxx_atu_remove(ps
, vlan
.fid
, port
, false);
2199 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
2200 const struct switchdev_obj_port_vlan
*vlan
)
2202 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2206 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VTU
))
2209 mutex_lock(&ps
->smi_mutex
);
2211 err
= _mv88e6xxx_port_pvid_get(ps
, port
, &pvid
);
2215 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
2216 err
= _mv88e6xxx_port_vlan_del(ps
, port
, vid
);
2221 err
= _mv88e6xxx_port_pvid_set(ps
, port
, 0);
2228 mutex_unlock(&ps
->smi_mutex
);
2233 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state
*ps
,
2234 const unsigned char *addr
)
2238 for (i
= 0; i
< 3; i
++) {
2239 ret
= _mv88e6xxx_reg_write(
2240 ps
, REG_GLOBAL
, GLOBAL_ATU_MAC_01
+ i
,
2241 (addr
[i
* 2] << 8) | addr
[i
* 2 + 1]);
2249 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state
*ps
,
2250 unsigned char *addr
)
2254 for (i
= 0; i
< 3; i
++) {
2255 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
2256 GLOBAL_ATU_MAC_01
+ i
);
2259 addr
[i
* 2] = ret
>> 8;
2260 addr
[i
* 2 + 1] = ret
& 0xff;
2266 static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state
*ps
,
2267 struct mv88e6xxx_atu_entry
*entry
)
2271 ret
= _mv88e6xxx_atu_wait(ps
);
2275 ret
= _mv88e6xxx_atu_mac_write(ps
, entry
->mac
);
2279 ret
= _mv88e6xxx_atu_data_write(ps
, entry
);
2283 return _mv88e6xxx_atu_cmd(ps
, entry
->fid
, GLOBAL_ATU_OP_LOAD_DB
);
2286 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state
*ps
, int port
,
2287 const unsigned char *addr
, u16 vid
,
2290 struct mv88e6xxx_atu_entry entry
= { 0 };
2291 struct mv88e6xxx_vtu_stu_entry vlan
;
2294 /* Null VLAN ID corresponds to the port private database */
2296 err
= _mv88e6xxx_port_fid_get(ps
, port
, &vlan
.fid
);
2298 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, false);
2302 entry
.fid
= vlan
.fid
;
2303 entry
.state
= state
;
2304 ether_addr_copy(entry
.mac
, addr
);
2305 if (state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2306 entry
.trunk
= false;
2307 entry
.portv_trunkid
= BIT(port
);
2310 return _mv88e6xxx_atu_load(ps
, &entry
);
2313 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
2314 const struct switchdev_obj_port_fdb
*fdb
,
2315 struct switchdev_trans
*trans
)
2317 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2319 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_ATU
))
2322 /* We don't need any dynamic resource from the kernel (yet),
2323 * so skip the prepare phase.
2328 static void mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
2329 const struct switchdev_obj_port_fdb
*fdb
,
2330 struct switchdev_trans
*trans
)
2332 int state
= is_multicast_ether_addr(fdb
->addr
) ?
2333 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2334 GLOBAL_ATU_DATA_STATE_UC_STATIC
;
2335 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2337 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_ATU
))
2340 mutex_lock(&ps
->smi_mutex
);
2341 if (_mv88e6xxx_port_fdb_load(ps
, port
, fdb
->addr
, fdb
->vid
, state
))
2342 netdev_err(ds
->ports
[port
].netdev
,
2343 "failed to load MAC address\n");
2344 mutex_unlock(&ps
->smi_mutex
);
2347 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
2348 const struct switchdev_obj_port_fdb
*fdb
)
2350 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2353 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_ATU
))
2356 mutex_lock(&ps
->smi_mutex
);
2357 ret
= _mv88e6xxx_port_fdb_load(ps
, port
, fdb
->addr
, fdb
->vid
,
2358 GLOBAL_ATU_DATA_STATE_UNUSED
);
2359 mutex_unlock(&ps
->smi_mutex
);
2364 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
2365 struct mv88e6xxx_atu_entry
*entry
)
2367 struct mv88e6xxx_atu_entry next
= { 0 };
2372 ret
= _mv88e6xxx_atu_wait(ps
);
2376 ret
= _mv88e6xxx_atu_cmd(ps
, fid
, GLOBAL_ATU_OP_GET_NEXT_DB
);
2380 ret
= _mv88e6xxx_atu_mac_read(ps
, next
.mac
);
2384 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_ATU_DATA
);
2388 next
.state
= ret
& GLOBAL_ATU_DATA_STATE_MASK
;
2389 if (next
.state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2390 unsigned int mask
, shift
;
2392 if (ret
& GLOBAL_ATU_DATA_TRUNK
) {
2394 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
2395 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
2398 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
2399 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
2402 next
.portv_trunkid
= (ret
& mask
) >> shift
;
2409 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state
*ps
,
2410 u16 fid
, u16 vid
, int port
,
2411 struct switchdev_obj_port_fdb
*fdb
,
2412 int (*cb
)(struct switchdev_obj
*obj
))
2414 struct mv88e6xxx_atu_entry addr
= {
2415 .mac
= { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2419 err
= _mv88e6xxx_atu_mac_write(ps
, addr
.mac
);
2424 err
= _mv88e6xxx_atu_getnext(ps
, fid
, &addr
);
2428 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UNUSED
)
2431 if (!addr
.trunk
&& addr
.portv_trunkid
& BIT(port
)) {
2432 bool is_static
= addr
.state
==
2433 (is_multicast_ether_addr(addr
.mac
) ?
2434 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2435 GLOBAL_ATU_DATA_STATE_UC_STATIC
);
2438 ether_addr_copy(fdb
->addr
, addr
.mac
);
2439 fdb
->ndm_state
= is_static
? NUD_NOARP
: NUD_REACHABLE
;
2441 err
= cb(&fdb
->obj
);
2445 } while (!is_broadcast_ether_addr(addr
.mac
));
2450 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
2451 struct switchdev_obj_port_fdb
*fdb
,
2452 int (*cb
)(struct switchdev_obj
*obj
))
2454 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2455 struct mv88e6xxx_vtu_stu_entry vlan
= {
2456 .vid
= GLOBAL_VTU_VID_MASK
, /* all ones */
2461 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_ATU
))
2464 mutex_lock(&ps
->smi_mutex
);
2466 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2467 err
= _mv88e6xxx_port_fid_get(ps
, port
, &fid
);
2471 err
= _mv88e6xxx_port_fdb_dump_one(ps
, fid
, 0, port
, fdb
, cb
);
2475 /* Dump VLANs' Filtering Information Databases */
2476 err
= _mv88e6xxx_vtu_vid_write(ps
, vlan
.vid
);
2481 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
2488 err
= _mv88e6xxx_port_fdb_dump_one(ps
, vlan
.fid
, vlan
.vid
, port
,
2492 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
2495 mutex_unlock(&ps
->smi_mutex
);
2500 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
2501 struct net_device
*bridge
)
2503 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2506 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VLANTABLE
))
2509 mutex_lock(&ps
->smi_mutex
);
2511 /* Assign the bridge and remap each port's VLANTable */
2512 ps
->ports
[port
].bridge_dev
= bridge
;
2514 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
2515 if (ps
->ports
[i
].bridge_dev
== bridge
) {
2516 err
= _mv88e6xxx_port_based_vlan_map(ps
, i
);
2522 mutex_unlock(&ps
->smi_mutex
);
2527 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
)
2529 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2530 struct net_device
*bridge
= ps
->ports
[port
].bridge_dev
;
2533 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_VLANTABLE
))
2536 mutex_lock(&ps
->smi_mutex
);
2538 /* Unassign the bridge and remap each port's VLANTable */
2539 ps
->ports
[port
].bridge_dev
= NULL
;
2541 for (i
= 0; i
< ps
->info
->num_ports
; ++i
)
2542 if (i
== port
|| ps
->ports
[i
].bridge_dev
== bridge
)
2543 if (_mv88e6xxx_port_based_vlan_map(ps
, i
))
2544 netdev_warn(ds
->ports
[i
].netdev
,
2545 "failed to remap\n");
2547 mutex_unlock(&ps
->smi_mutex
);
2550 static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state
*ps
,
2551 int port
, int page
, int reg
, int val
)
2555 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, page
);
2557 goto restore_page_0
;
2559 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, reg
, val
);
2561 _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, 0x0);
2566 static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state
*ps
,
2567 int port
, int page
, int reg
)
2571 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, page
);
2573 goto restore_page_0
;
2575 ret
= _mv88e6xxx_phy_read_indirect(ps
, port
, reg
);
2577 _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, 0x0);
2582 static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state
*ps
)
2584 bool ppu_active
= mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU_ACTIVE
);
2585 u16 is_reset
= (ppu_active
? 0x8800 : 0xc800);
2586 struct gpio_desc
*gpiod
= ps
->reset
;
2587 unsigned long timeout
;
2591 /* Set all ports to the disabled state. */
2592 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
2593 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(i
), PORT_CONTROL
);
2597 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(i
), PORT_CONTROL
,
2603 /* Wait for transmit queues to drain. */
2604 usleep_range(2000, 4000);
2606 /* If there is a gpio connected to the reset pin, toggle it */
2608 gpiod_set_value_cansleep(gpiod
, 1);
2609 usleep_range(10000, 20000);
2610 gpiod_set_value_cansleep(gpiod
, 0);
2611 usleep_range(10000, 20000);
2614 /* Reset the switch. Keep the PPU active if requested. The PPU
2615 * needs to be active to support indirect phy register access
2616 * through global registers 0x18 and 0x19.
2619 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, 0x04, 0xc000);
2621 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, 0x04, 0xc400);
2625 /* Wait up to one second for reset to complete. */
2626 timeout
= jiffies
+ 1 * HZ
;
2627 while (time_before(jiffies
, timeout
)) {
2628 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, 0x00);
2632 if ((ret
& is_reset
) == is_reset
)
2634 usleep_range(1000, 2000);
2636 if (time_after(jiffies
, timeout
))
2644 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state
*ps
)
2648 ret
= _mv88e6xxx_phy_page_read(ps
, REG_FIBER_SERDES
, PAGE_FIBER_SERDES
,
2653 if (ret
& BMCR_PDOWN
) {
2655 ret
= _mv88e6xxx_phy_page_write(ps
, REG_FIBER_SERDES
,
2656 PAGE_FIBER_SERDES
, MII_BMCR
,
2663 static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state
*ps
, int port
)
2665 struct dsa_switch
*ds
= ps
->ds
;
2669 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2670 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2671 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
2672 mv88e6xxx_6065_family(ps
) || mv88e6xxx_6320_family(ps
)) {
2673 /* MAC Forcing register: don't force link, speed,
2674 * duplex or flow control state to any particular
2675 * values on physical ports, but force the CPU port
2676 * and all DSA ports to their maximum bandwidth and
2679 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_PCS_CTRL
);
2680 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
2681 reg
&= ~PORT_PCS_CTRL_UNFORCED
;
2682 reg
|= PORT_PCS_CTRL_FORCE_LINK
|
2683 PORT_PCS_CTRL_LINK_UP
|
2684 PORT_PCS_CTRL_DUPLEX_FULL
|
2685 PORT_PCS_CTRL_FORCE_DUPLEX
;
2686 if (mv88e6xxx_6065_family(ps
))
2687 reg
|= PORT_PCS_CTRL_100
;
2689 reg
|= PORT_PCS_CTRL_1000
;
2691 reg
|= PORT_PCS_CTRL_UNFORCED
;
2694 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2695 PORT_PCS_CTRL
, reg
);
2700 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2701 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2702 * tunneling, determine priority by looking at 802.1p and IP
2703 * priority fields (IP prio has precedence), and set STP state
2706 * If this is the CPU link, use DSA or EDSA tagging depending
2707 * on which tagging mode was configured.
2709 * If this is a link to another switch, use DSA tagging mode.
2711 * If this is the upstream port for this switch, enable
2712 * forwarding of unknown unicasts and multicasts.
2715 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2716 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2717 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6065_family(ps
) ||
2718 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6320_family(ps
))
2719 reg
= PORT_CONTROL_IGMP_MLD_SNOOP
|
2720 PORT_CONTROL_USE_TAG
| PORT_CONTROL_USE_IP
|
2721 PORT_CONTROL_STATE_FORWARDING
;
2722 if (dsa_is_cpu_port(ds
, port
)) {
2723 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
))
2724 reg
|= PORT_CONTROL_DSA_TAG
;
2725 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2726 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2727 mv88e6xxx_6320_family(ps
)) {
2728 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2729 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
;
2731 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2732 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2733 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2736 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2737 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2738 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6065_family(ps
) ||
2739 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6320_family(ps
)) {
2740 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2741 reg
|= PORT_CONTROL_EGRESS_ADD_TAG
;
2744 if (dsa_is_dsa_port(ds
, port
)) {
2745 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
))
2746 reg
|= PORT_CONTROL_DSA_TAG
;
2747 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2748 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2749 mv88e6xxx_6320_family(ps
)) {
2750 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2753 if (port
== dsa_upstream_port(ds
))
2754 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2755 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2758 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2764 /* If this port is connected to a SerDes, make sure the SerDes is not
2767 if (mv88e6xxx_6352_family(ps
)) {
2768 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_STATUS
);
2771 ret
&= PORT_STATUS_CMODE_MASK
;
2772 if ((ret
== PORT_STATUS_CMODE_100BASE_X
) ||
2773 (ret
== PORT_STATUS_CMODE_1000BASE_X
) ||
2774 (ret
== PORT_STATUS_CMODE_SGMII
)) {
2775 ret
= mv88e6xxx_power_on_serdes(ps
);
2781 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2782 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2783 * untagged frames on this port, do a destination address lookup on all
2784 * received packets as usual, disable ARP mirroring and don't send a
2785 * copy of all transmitted/received frames on this port to the CPU.
2788 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2789 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2790 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6320_family(ps
) ||
2791 mv88e6xxx_6185_family(ps
))
2792 reg
= PORT_CONTROL_2_MAP_DA
;
2794 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2795 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6320_family(ps
))
2796 reg
|= PORT_CONTROL_2_JUMBO_10240
;
2798 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
)) {
2799 /* Set the upstream port this port should use */
2800 reg
|= dsa_upstream_port(ds
);
2801 /* enable forwarding of unknown multicast addresses to
2804 if (port
== dsa_upstream_port(ds
))
2805 reg
|= PORT_CONTROL_2_FORWARD_UNKNOWN
;
2808 reg
|= PORT_CONTROL_2_8021Q_DISABLED
;
2811 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2812 PORT_CONTROL_2
, reg
);
2817 /* Port Association Vector: when learning source addresses
2818 * of packets, add the address to the address database using
2819 * a port bitmap that has only the bit for this port set and
2820 * the other bits clear.
2823 /* Disable learning for CPU port */
2824 if (dsa_is_cpu_port(ds
, port
))
2827 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_ASSOC_VECTOR
, reg
);
2831 /* Egress rate control 2: disable egress rate control. */
2832 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_RATE_CONTROL_2
,
2837 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2838 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2839 mv88e6xxx_6320_family(ps
)) {
2840 /* Do not limit the period of time that this port can
2841 * be paused for by the remote end or the period of
2842 * time that this port can pause the remote end.
2844 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2845 PORT_PAUSE_CTRL
, 0x0000);
2849 /* Port ATU control: disable limiting the number of
2850 * address database entries that this port is allowed
2853 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2854 PORT_ATU_CONTROL
, 0x0000);
2855 /* Priority Override: disable DA, SA and VTU priority
2858 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2859 PORT_PRI_OVERRIDE
, 0x0000);
2863 /* Port Ethertype: use the Ethertype DSA Ethertype
2866 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2867 PORT_ETH_TYPE
, ETH_P_EDSA
);
2870 /* Tag Remap: use an identity 802.1p prio -> switch
2873 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2874 PORT_TAG_REGMAP_0123
, 0x3210);
2878 /* Tag Remap 2: use an identity 802.1p prio -> switch
2881 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2882 PORT_TAG_REGMAP_4567
, 0x7654);
2887 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2888 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2889 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
2890 mv88e6xxx_6320_family(ps
)) {
2891 /* Rate Control: disable ingress rate limiting. */
2892 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2893 PORT_RATE_CONTROL
, 0x0001);
2898 /* Port Control 1: disable trunking, disable sending
2899 * learning messages to this port.
2901 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_1
, 0x0000);
2905 /* Port based VLAN map: give each port the same default address
2906 * database, and allow bidirectional communication between the
2907 * CPU and DSA port(s), and the other ports.
2909 ret
= _mv88e6xxx_port_fid_set(ps
, port
, 0);
2913 ret
= _mv88e6xxx_port_based_vlan_map(ps
, port
);
2917 /* Default VLAN ID and priority: don't set a default VLAN
2918 * ID, and set the default packet priority to zero.
2920 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
2928 static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state
*ps
)
2930 struct dsa_switch
*ds
= ps
->ds
;
2931 u32 upstream_port
= dsa_upstream_port(ds
);
2936 /* Enable the PHY Polling Unit if present, don't discard any packets,
2937 * and mask all interrupt sources.
2940 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
) ||
2941 mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU_ACTIVE
))
2942 reg
|= GLOBAL_CONTROL_PPU_ENABLE
;
2944 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL
, reg
);
2948 /* Configure the upstream port, and configure it as the port to which
2949 * ingress and egress and ARP monitor frames are to be sent.
2951 reg
= upstream_port
<< GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT
|
2952 upstream_port
<< GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT
|
2953 upstream_port
<< GLOBAL_MONITOR_CONTROL_ARP_SHIFT
;
2954 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MONITOR_CONTROL
, reg
);
2958 /* Disable remote management, and set the switch's DSA device number. */
2959 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL_2
,
2960 GLOBAL_CONTROL_2_MULTIPLE_CASCADE
|
2961 (ds
->index
& 0x1f));
2965 /* Set the default address aging time to 5 minutes, and
2966 * enable address learn messages to be sent to all message
2969 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
2970 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL
);
2974 /* Configure the IP ToS mapping registers. */
2975 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_0
, 0x0000);
2978 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_1
, 0x0000);
2981 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_2
, 0x5555);
2984 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_3
, 0x5555);
2987 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_4
, 0xaaaa);
2990 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_5
, 0xaaaa);
2993 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_6
, 0xffff);
2996 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_7
, 0xffff);
3000 /* Configure the IEEE 802.1p priority mapping register. */
3001 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IEEE_PRI
, 0xfa41);
3005 /* Send all frames with destination addresses matching
3006 * 01:80:c2:00:00:0x to the CPU port.
3008 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_MGMT_EN_0X
, 0xffff);
3012 /* Ignore removed tag data on doubly tagged packets, disable
3013 * flow control messages, force flow control priority to the
3014 * highest, and send all special multicast frames to the CPU
3015 * port at the highest priority.
3017 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SWITCH_MGMT
,
3018 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU
| 0x70 |
3019 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI
);
3023 /* Program the DSA routing table. */
3024 for (i
= 0; i
< 32; i
++) {
3027 if (i
!= ds
->index
&& i
< DSA_MAX_SWITCHES
)
3028 nexthop
= ds
->rtable
[i
] & 0x1f;
3030 err
= _mv88e6xxx_reg_write(
3032 GLOBAL2_DEVICE_MAPPING
,
3033 GLOBAL2_DEVICE_MAPPING_UPDATE
|
3034 (i
<< GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT
) | nexthop
);
3039 /* Clear all trunk masks. */
3040 for (i
= 0; i
< 8; i
++) {
3041 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_TRUNK_MASK
,
3043 (i
<< GLOBAL2_TRUNK_MASK_NUM_SHIFT
) |
3044 ((1 << ps
->info
->num_ports
) - 1));
3049 /* Clear all trunk mappings. */
3050 for (i
= 0; i
< 16; i
++) {
3051 err
= _mv88e6xxx_reg_write(
3053 GLOBAL2_TRUNK_MAPPING
,
3054 GLOBAL2_TRUNK_MAPPING_UPDATE
|
3055 (i
<< GLOBAL2_TRUNK_MAPPING_ID_SHIFT
));
3060 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
3061 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
3062 mv88e6xxx_6320_family(ps
)) {
3063 /* Send all frames with destination addresses matching
3064 * 01:80:c2:00:00:2x to the CPU port.
3066 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
3067 GLOBAL2_MGMT_EN_2X
, 0xffff);
3071 /* Initialise cross-chip port VLAN table to reset
3074 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
3075 GLOBAL2_PVT_ADDR
, 0x9000);
3079 /* Clear the priority override table. */
3080 for (i
= 0; i
< 16; i
++) {
3081 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
3082 GLOBAL2_PRIO_OVERRIDE
,
3089 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
3090 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
3091 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
3092 mv88e6xxx_6320_family(ps
)) {
3093 /* Disable ingress rate limiting by resetting all
3094 * ingress rate limit registers to their initial
3097 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
3098 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
3106 /* Clear the statistics counters for all ports */
3107 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
3108 GLOBAL_STATS_OP_FLUSH_ALL
);
3112 /* Wait for the flush to complete. */
3113 err
= _mv88e6xxx_stats_wait(ps
);
3117 /* Clear all ATU entries */
3118 err
= _mv88e6xxx_atu_flush(ps
, 0, true);
3122 /* Clear all the VTU and STU entries */
3123 err
= _mv88e6xxx_vtu_stu_flush(ps
);
3130 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
3132 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3138 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
3139 mutex_init(&ps
->eeprom_mutex
);
3141 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
3142 mv88e6xxx_ppu_state_init(ps
);
3144 mutex_lock(&ps
->smi_mutex
);
3146 err
= mv88e6xxx_switch_reset(ps
);
3150 err
= mv88e6xxx_setup_global(ps
);
3154 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
3155 err
= mv88e6xxx_setup_port(ps
, i
);
3161 mutex_unlock(&ps
->smi_mutex
);
3166 int mv88e6xxx_phy_page_read(struct dsa_switch
*ds
, int port
, int page
, int reg
)
3168 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3171 mutex_lock(&ps
->smi_mutex
);
3172 ret
= _mv88e6xxx_phy_page_read(ps
, port
, page
, reg
);
3173 mutex_unlock(&ps
->smi_mutex
);
3178 int mv88e6xxx_phy_page_write(struct dsa_switch
*ds
, int port
, int page
,
3181 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3184 mutex_lock(&ps
->smi_mutex
);
3185 ret
= _mv88e6xxx_phy_page_write(ps
, port
, page
, reg
, val
);
3186 mutex_unlock(&ps
->smi_mutex
);
3191 static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state
*ps
,
3194 if (port
>= 0 && port
< ps
->info
->num_ports
)
3199 static int mv88e6xxx_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
3201 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3202 int addr
= mv88e6xxx_port_to_phy_addr(ps
, port
);
3208 mutex_lock(&ps
->smi_mutex
);
3210 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
3211 ret
= mv88e6xxx_phy_read_ppu(ps
, addr
, regnum
);
3212 else if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SMI_PHY
))
3213 ret
= _mv88e6xxx_phy_read_indirect(ps
, addr
, regnum
);
3215 ret
= _mv88e6xxx_phy_read(ps
, addr
, regnum
);
3217 mutex_unlock(&ps
->smi_mutex
);
3221 static int mv88e6xxx_phy_write(struct dsa_switch
*ds
, int port
, int regnum
,
3224 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3225 int addr
= mv88e6xxx_port_to_phy_addr(ps
, port
);
3231 mutex_lock(&ps
->smi_mutex
);
3233 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
3234 ret
= mv88e6xxx_phy_write_ppu(ps
, addr
, regnum
, val
);
3235 else if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SMI_PHY
))
3236 ret
= _mv88e6xxx_phy_write_indirect(ps
, addr
, regnum
, val
);
3238 ret
= _mv88e6xxx_phy_write(ps
, addr
, regnum
, val
);
3240 mutex_unlock(&ps
->smi_mutex
);
3244 #ifdef CONFIG_NET_DSA_HWMON
3246 static int mv88e61xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3248 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3254 mutex_lock(&ps
->smi_mutex
);
3256 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x16, 0x6);
3260 /* Enable temperature sensor */
3261 ret
= _mv88e6xxx_phy_read(ps
, 0x0, 0x1a);
3265 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x1a, ret
| (1 << 5));
3269 /* Wait for temperature to stabilize */
3270 usleep_range(10000, 12000);
3272 val
= _mv88e6xxx_phy_read(ps
, 0x0, 0x1a);
3278 /* Disable temperature sensor */
3279 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x1a, ret
& ~(1 << 5));
3283 *temp
= ((val
& 0x1f) - 5) * 5;
3286 _mv88e6xxx_phy_write(ps
, 0x0, 0x16, 0x0);
3287 mutex_unlock(&ps
->smi_mutex
);
3291 static int mv88e63xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3293 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3294 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3299 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 27);
3303 *temp
= (ret
& 0xff) - 25;
3308 static int mv88e6xxx_get_temp(struct dsa_switch
*ds
, int *temp
)
3310 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3312 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP
))
3315 if (mv88e6xxx_6320_family(ps
) || mv88e6xxx_6352_family(ps
))
3316 return mv88e63xx_get_temp(ds
, temp
);
3318 return mv88e61xx_get_temp(ds
, temp
);
3321 static int mv88e6xxx_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
3323 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3324 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3327 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3332 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3336 *temp
= (((ret
>> 8) & 0x1f) * 5) - 25;
3341 static int mv88e6xxx_set_temp_limit(struct dsa_switch
*ds
, int temp
)
3343 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3344 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3347 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3350 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3353 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
3354 return mv88e6xxx_phy_page_write(ds
, phy
, 6, 26,
3355 (ret
& 0xe0ff) | (temp
<< 8));
3358 static int mv88e6xxx_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
3360 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3361 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3364 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3369 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3373 *alarm
= !!(ret
& 0x40);
3377 #endif /* CONFIG_NET_DSA_HWMON */
3379 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3381 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6085
,
3382 .family
= MV88E6XXX_FAMILY_6097
,
3383 .name
= "Marvell 88E6085",
3384 .num_databases
= 4096,
3386 .flags
= MV88E6XXX_FLAGS_FAMILY_6097
,
3390 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6095
,
3391 .family
= MV88E6XXX_FAMILY_6095
,
3392 .name
= "Marvell 88E6095/88E6095F",
3393 .num_databases
= 256,
3395 .flags
= MV88E6XXX_FLAGS_FAMILY_6095
,
3399 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6123
,
3400 .family
= MV88E6XXX_FAMILY_6165
,
3401 .name
= "Marvell 88E6123",
3402 .num_databases
= 4096,
3404 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3408 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6131
,
3409 .family
= MV88E6XXX_FAMILY_6185
,
3410 .name
= "Marvell 88E6131",
3411 .num_databases
= 256,
3413 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3417 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6161
,
3418 .family
= MV88E6XXX_FAMILY_6165
,
3419 .name
= "Marvell 88E6161",
3420 .num_databases
= 4096,
3422 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3426 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6165
,
3427 .family
= MV88E6XXX_FAMILY_6165
,
3428 .name
= "Marvell 88E6165",
3429 .num_databases
= 4096,
3431 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3435 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6171
,
3436 .family
= MV88E6XXX_FAMILY_6351
,
3437 .name
= "Marvell 88E6171",
3438 .num_databases
= 4096,
3440 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3444 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6172
,
3445 .family
= MV88E6XXX_FAMILY_6352
,
3446 .name
= "Marvell 88E6172",
3447 .num_databases
= 4096,
3449 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3453 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6175
,
3454 .family
= MV88E6XXX_FAMILY_6351
,
3455 .name
= "Marvell 88E6175",
3456 .num_databases
= 4096,
3458 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3462 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6176
,
3463 .family
= MV88E6XXX_FAMILY_6352
,
3464 .name
= "Marvell 88E6176",
3465 .num_databases
= 4096,
3467 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3471 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6185
,
3472 .family
= MV88E6XXX_FAMILY_6185
,
3473 .name
= "Marvell 88E6185",
3474 .num_databases
= 256,
3476 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3480 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6240
,
3481 .family
= MV88E6XXX_FAMILY_6352
,
3482 .name
= "Marvell 88E6240",
3483 .num_databases
= 4096,
3485 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3489 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6320
,
3490 .family
= MV88E6XXX_FAMILY_6320
,
3491 .name
= "Marvell 88E6320",
3492 .num_databases
= 4096,
3494 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3498 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6321
,
3499 .family
= MV88E6XXX_FAMILY_6320
,
3500 .name
= "Marvell 88E6321",
3501 .num_databases
= 4096,
3503 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3507 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6350
,
3508 .family
= MV88E6XXX_FAMILY_6351
,
3509 .name
= "Marvell 88E6350",
3510 .num_databases
= 4096,
3512 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3516 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6351
,
3517 .family
= MV88E6XXX_FAMILY_6351
,
3518 .name
= "Marvell 88E6351",
3519 .num_databases
= 4096,
3521 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3525 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6352
,
3526 .family
= MV88E6XXX_FAMILY_6352
,
3527 .name
= "Marvell 88E6352",
3528 .num_databases
= 4096,
3530 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3534 static const struct mv88e6xxx_info
*
3535 mv88e6xxx_lookup_info(unsigned int prod_num
, const struct mv88e6xxx_info
*table
,
3540 for (i
= 0; i
< num
; ++i
)
3541 if (table
[i
].prod_num
== prod_num
)
3547 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3548 struct device
*host_dev
, int sw_addr
,
3551 const struct mv88e6xxx_info
*info
;
3552 struct mv88e6xxx_priv_state
*ps
;
3553 struct mii_bus
*bus
;
3555 int id
, prod_num
, rev
;
3557 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3561 id
= __mv88e6xxx_reg_read(bus
, sw_addr
, REG_PORT(0), PORT_SWITCH_ID
);
3565 prod_num
= (id
& 0xfff0) >> 4;
3568 info
= mv88e6xxx_lookup_info(prod_num
, mv88e6xxx_table
,
3569 ARRAY_SIZE(mv88e6xxx_table
));
3575 ps
= devm_kzalloc(dsa_dev
, sizeof(*ps
), GFP_KERNEL
);
3580 ps
->sw_addr
= sw_addr
;
3582 mutex_init(&ps
->smi_mutex
);
3586 dev_info(&ps
->bus
->dev
, "switch 0x%x probed: %s, revision %u\n",
3587 prod_num
, name
, rev
);
3592 struct dsa_switch_driver mv88e6xxx_switch_driver
= {
3593 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3594 .probe
= mv88e6xxx_drv_probe
,
3595 .setup
= mv88e6xxx_setup
,
3596 .set_addr
= mv88e6xxx_set_addr
,
3597 .phy_read
= mv88e6xxx_phy_read
,
3598 .phy_write
= mv88e6xxx_phy_write
,
3599 .adjust_link
= mv88e6xxx_adjust_link
,
3600 .get_strings
= mv88e6xxx_get_strings
,
3601 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
3602 .get_sset_count
= mv88e6xxx_get_sset_count
,
3603 .set_eee
= mv88e6xxx_set_eee
,
3604 .get_eee
= mv88e6xxx_get_eee
,
3605 #ifdef CONFIG_NET_DSA_HWMON
3606 .get_temp
= mv88e6xxx_get_temp
,
3607 .get_temp_limit
= mv88e6xxx_get_temp_limit
,
3608 .set_temp_limit
= mv88e6xxx_set_temp_limit
,
3609 .get_temp_alarm
= mv88e6xxx_get_temp_alarm
,
3611 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
3612 .get_eeprom
= mv88e6xxx_get_eeprom
,
3613 .set_eeprom
= mv88e6xxx_set_eeprom
,
3614 .get_regs_len
= mv88e6xxx_get_regs_len
,
3615 .get_regs
= mv88e6xxx_get_regs
,
3616 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
3617 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
3618 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
3619 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
3620 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
3621 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
3622 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
3623 .port_vlan_dump
= mv88e6xxx_port_vlan_dump
,
3624 .port_fdb_prepare
= mv88e6xxx_port_fdb_prepare
,
3625 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
3626 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
3627 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
3630 int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
3632 struct device
*dev
= &mdiodev
->dev
;
3633 struct device_node
*np
= dev
->of_node
;
3634 struct mv88e6xxx_priv_state
*ps
;
3635 int id
, prod_num
, rev
;
3636 struct dsa_switch
*ds
;
3640 ds
= devm_kzalloc(dev
, sizeof(*ds
) + sizeof(*ps
), GFP_KERNEL
);
3644 ps
= (struct mv88e6xxx_priv_state
*)(ds
+ 1);
3649 ps
->bus
= mdiodev
->bus
;
3650 ps
->sw_addr
= mdiodev
->addr
;
3651 mutex_init(&ps
->smi_mutex
);
3653 get_device(&ps
->bus
->dev
);
3655 ds
->drv
= &mv88e6xxx_switch_driver
;
3657 id
= mv88e6xxx_reg_read(ps
, REG_PORT(0), PORT_SWITCH_ID
);
3661 prod_num
= (id
& 0xfff0) >> 4;
3664 ps
->info
= mv88e6xxx_lookup_info(prod_num
, mv88e6xxx_table
,
3665 ARRAY_SIZE(mv88e6xxx_table
));
3669 ps
->reset
= devm_gpiod_get(&mdiodev
->dev
, "reset", GPIOD_ASIS
);
3670 if (IS_ERR(ps
->reset
)) {
3671 err
= PTR_ERR(ps
->reset
);
3672 if (err
== -ENOENT
) {
3673 /* Optional, so not an error */
3680 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
) &&
3681 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
3682 ps
->eeprom_len
= eeprom_len
;
3684 dev_set_drvdata(dev
, ds
);
3686 dev_info(dev
, "switch 0x%x probed: %s, revision %u\n",
3687 prod_num
, ps
->info
->name
, rev
);
3692 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
3694 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
3695 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3697 put_device(&ps
->bus
->dev
);
3700 static const struct of_device_id mv88e6xxx_of_match
[] = {
3701 { .compatible
= "marvell,mv88e6085" },
3705 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
3707 static struct mdio_driver mv88e6xxx_driver
= {
3708 .probe
= mv88e6xxx_probe
,
3709 .remove
= mv88e6xxx_remove
,
3711 .name
= "mv88e6085",
3712 .of_match_table
= mv88e6xxx_of_match
,
3716 static int __init
mv88e6xxx_init(void)
3718 register_switch_driver(&mv88e6xxx_switch_driver
);
3719 return mdio_driver_register(&mv88e6xxx_driver
);
3721 module_init(mv88e6xxx_init
);
3723 static void __exit
mv88e6xxx_cleanup(void)
3725 mdio_driver_unregister(&mv88e6xxx_driver
);
3726 unregister_switch_driver(&mv88e6xxx_switch_driver
);
3728 module_exit(mv88e6xxx_cleanup
);
3730 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3731 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3732 MODULE_LICENSE("GPL");