2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch
*ds
)
30 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
32 if (unlikely(!mutex_is_locked(&ps
->smi_mutex
))) {
33 dev_err(ds
->master_dev
, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus
*bus
, int sw_addr
)
51 for (i
= 0; i
< 16; i
++) {
52 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_CMD
);
56 if ((ret
& SMI_CMD_BUSY
) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus
*bus
, int sw_addr
, int addr
,
69 return mdiobus_read_nested(bus
, addr
, reg
);
71 /* Wait for the bus to become free. */
72 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
76 /* Transmit the read command. */
77 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
78 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
82 /* Wait for the read command to complete. */
83 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
88 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_DATA
);
95 static int _mv88e6xxx_reg_read(struct dsa_switch
*ds
, int addr
, int reg
)
97 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(ds
->master_dev
);
105 ret
= __mv88e6xxx_reg_read(bus
, ds
->pd
->sw_addr
, addr
, reg
);
109 dev_dbg(ds
->master_dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch
*ds
, int addr
, int reg
)
117 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
120 mutex_lock(&ps
->smi_mutex
);
121 ret
= _mv88e6xxx_reg_read(ds
, addr
, reg
);
122 mutex_unlock(&ps
->smi_mutex
);
127 static int __mv88e6xxx_reg_write(struct mii_bus
*bus
, int sw_addr
, int addr
,
133 return mdiobus_write_nested(bus
, addr
, reg
, val
);
135 /* Wait for the bus to become free. */
136 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
140 /* Transmit the data to write. */
141 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_DATA
, val
);
145 /* Transmit the write command. */
146 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
147 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
151 /* Wait for the write command to complete. */
152 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
159 static int _mv88e6xxx_reg_write(struct dsa_switch
*ds
, int addr
, int reg
,
162 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(ds
->master_dev
);
169 dev_dbg(ds
->master_dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus
, ds
->pd
->sw_addr
, addr
, reg
, val
);
175 int mv88e6xxx_reg_write(struct dsa_switch
*ds
, int addr
, int reg
, u16 val
)
177 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
180 mutex_lock(&ps
->smi_mutex
);
181 ret
= _mv88e6xxx_reg_write(ds
, addr
, reg
, val
);
182 mutex_unlock(&ps
->smi_mutex
);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch
*ds
, u8
*addr
)
189 REG_WRITE(REG_GLOBAL
, GLOBAL_MAC_01
, (addr
[0] << 8) | addr
[1]);
190 REG_WRITE(REG_GLOBAL
, GLOBAL_MAC_23
, (addr
[2] << 8) | addr
[3]);
191 REG_WRITE(REG_GLOBAL
, GLOBAL_MAC_45
, (addr
[4] << 8) | addr
[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch
*ds
, u8
*addr
)
201 for (i
= 0; i
< 6; i
++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2
, GLOBAL2_SWITCH_MAC
,
206 GLOBAL2_SWITCH_MAC_BUSY
| (i
<< 8) | addr
[i
]);
208 /* Wait for the write to complete. */
209 for (j
= 0; j
< 16; j
++) {
210 ret
= REG_READ(REG_GLOBAL2
, GLOBAL2_SWITCH_MAC
);
211 if ((ret
& GLOBAL2_SWITCH_MAC_BUSY
) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch
*ds
, int addr
, int regnum
)
224 return _mv88e6xxx_reg_read(ds
, addr
, regnum
);
228 static int _mv88e6xxx_phy_write(struct dsa_switch
*ds
, int addr
, int regnum
,
232 return _mv88e6xxx_reg_write(ds
, addr
, regnum
, val
);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch
*ds
)
240 unsigned long timeout
;
242 ret
= REG_READ(REG_GLOBAL
, GLOBAL_CONTROL
);
243 REG_WRITE(REG_GLOBAL
, GLOBAL_CONTROL
,
244 ret
& ~GLOBAL_CONTROL_PPU_ENABLE
);
246 timeout
= jiffies
+ 1 * HZ
;
247 while (time_before(jiffies
, timeout
)) {
248 ret
= REG_READ(REG_GLOBAL
, GLOBAL_STATUS
);
249 usleep_range(1000, 2000);
250 if ((ret
& GLOBAL_STATUS_PPU_MASK
) !=
251 GLOBAL_STATUS_PPU_POLLING
)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch
*ds
)
261 unsigned long timeout
;
263 ret
= REG_READ(REG_GLOBAL
, GLOBAL_CONTROL
);
264 REG_WRITE(REG_GLOBAL
, GLOBAL_CONTROL
, ret
| GLOBAL_CONTROL_PPU_ENABLE
);
266 timeout
= jiffies
+ 1 * HZ
;
267 while (time_before(jiffies
, timeout
)) {
268 ret
= REG_READ(REG_GLOBAL
, GLOBAL_STATUS
);
269 usleep_range(1000, 2000);
270 if ((ret
& GLOBAL_STATUS_PPU_MASK
) ==
271 GLOBAL_STATUS_PPU_POLLING
)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct
*ugly
)
280 struct mv88e6xxx_priv_state
*ps
;
282 ps
= container_of(ugly
, struct mv88e6xxx_priv_state
, ppu_work
);
283 if (mutex_trylock(&ps
->ppu_mutex
)) {
284 struct dsa_switch
*ds
= ((struct dsa_switch
*)ps
) - 1;
286 if (mv88e6xxx_ppu_enable(ds
) == 0)
287 ps
->ppu_disabled
= 0;
288 mutex_unlock(&ps
->ppu_mutex
);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps
)
294 struct mv88e6xxx_priv_state
*ps
= (void *)_ps
;
296 schedule_work(&ps
->ppu_work
);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch
*ds
)
301 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
304 mutex_lock(&ps
->ppu_mutex
);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps
->ppu_disabled
) {
312 ret
= mv88e6xxx_ppu_disable(ds
);
314 mutex_unlock(&ps
->ppu_mutex
);
317 ps
->ppu_disabled
= 1;
319 del_timer(&ps
->ppu_timer
);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch
*ds
)
328 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps
->ppu_timer
, jiffies
+ msecs_to_jiffies(10));
332 mutex_unlock(&ps
->ppu_mutex
);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch
*ds
)
337 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
339 mutex_init(&ps
->ppu_mutex
);
340 INIT_WORK(&ps
->ppu_work
, mv88e6xxx_ppu_reenable_work
);
341 init_timer(&ps
->ppu_timer
);
342 ps
->ppu_timer
.data
= (unsigned long)ps
;
343 ps
->ppu_timer
.function
= mv88e6xxx_ppu_reenable_timer
;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch
*ds
, int addr
, int regnum
)
350 ret
= mv88e6xxx_ppu_access_get(ds
);
352 ret
= mv88e6xxx_reg_read(ds
, addr
, regnum
);
353 mv88e6xxx_ppu_access_put(ds
);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch
*ds
, int addr
,
364 ret
= mv88e6xxx_ppu_access_get(ds
);
366 ret
= mv88e6xxx_reg_write(ds
, addr
, regnum
, val
);
367 mv88e6xxx_ppu_access_put(ds
);
374 static bool mv88e6xxx_6065_family(struct dsa_switch
*ds
)
376 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
379 case PORT_SWITCH_ID_6031
:
380 case PORT_SWITCH_ID_6061
:
381 case PORT_SWITCH_ID_6035
:
382 case PORT_SWITCH_ID_6065
:
388 static bool mv88e6xxx_6095_family(struct dsa_switch
*ds
)
390 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
393 case PORT_SWITCH_ID_6092
:
394 case PORT_SWITCH_ID_6095
:
400 static bool mv88e6xxx_6097_family(struct dsa_switch
*ds
)
402 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
405 case PORT_SWITCH_ID_6046
:
406 case PORT_SWITCH_ID_6085
:
407 case PORT_SWITCH_ID_6096
:
408 case PORT_SWITCH_ID_6097
:
414 static bool mv88e6xxx_6165_family(struct dsa_switch
*ds
)
416 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
419 case PORT_SWITCH_ID_6123
:
420 case PORT_SWITCH_ID_6161
:
421 case PORT_SWITCH_ID_6165
:
427 static bool mv88e6xxx_6185_family(struct dsa_switch
*ds
)
429 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
432 case PORT_SWITCH_ID_6121
:
433 case PORT_SWITCH_ID_6122
:
434 case PORT_SWITCH_ID_6152
:
435 case PORT_SWITCH_ID_6155
:
436 case PORT_SWITCH_ID_6182
:
437 case PORT_SWITCH_ID_6185
:
438 case PORT_SWITCH_ID_6108
:
439 case PORT_SWITCH_ID_6131
:
445 static bool mv88e6xxx_6320_family(struct dsa_switch
*ds
)
447 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
450 case PORT_SWITCH_ID_6320
:
451 case PORT_SWITCH_ID_6321
:
457 static bool mv88e6xxx_6351_family(struct dsa_switch
*ds
)
459 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
462 case PORT_SWITCH_ID_6171
:
463 case PORT_SWITCH_ID_6175
:
464 case PORT_SWITCH_ID_6350
:
465 case PORT_SWITCH_ID_6351
:
471 static bool mv88e6xxx_6352_family(struct dsa_switch
*ds
)
473 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
476 case PORT_SWITCH_ID_6172
:
477 case PORT_SWITCH_ID_6176
:
478 case PORT_SWITCH_ID_6240
:
479 case PORT_SWITCH_ID_6352
:
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
489 void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
490 struct phy_device
*phydev
)
492 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
496 if (!phy_is_pseudo_fixed_link(phydev
))
499 mutex_lock(&ps
->smi_mutex
);
501 ret
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_PCS_CTRL
);
505 reg
= ret
& ~(PORT_PCS_CTRL_LINK_UP
|
506 PORT_PCS_CTRL_FORCE_LINK
|
507 PORT_PCS_CTRL_DUPLEX_FULL
|
508 PORT_PCS_CTRL_FORCE_DUPLEX
|
509 PORT_PCS_CTRL_UNFORCED
);
511 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
513 reg
|= PORT_PCS_CTRL_LINK_UP
;
515 if (mv88e6xxx_6065_family(ds
) && phydev
->speed
> SPEED_100
)
518 switch (phydev
->speed
) {
520 reg
|= PORT_PCS_CTRL_1000
;
523 reg
|= PORT_PCS_CTRL_100
;
526 reg
|= PORT_PCS_CTRL_10
;
529 pr_info("Unknown speed");
533 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
534 if (phydev
->duplex
== DUPLEX_FULL
)
535 reg
|= PORT_PCS_CTRL_DUPLEX_FULL
;
537 if ((mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
)) &&
538 (port
>= ps
->num_ports
- 2)) {
539 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
540 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
541 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
542 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
543 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
544 reg
|= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
547 _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_PCS_CTRL
, reg
);
550 mutex_unlock(&ps
->smi_mutex
);
553 static int _mv88e6xxx_stats_wait(struct dsa_switch
*ds
)
558 for (i
= 0; i
< 10; i
++) {
559 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_STATS_OP
);
560 if ((ret
& GLOBAL_STATS_OP_BUSY
) == 0)
567 static int _mv88e6xxx_stats_snapshot(struct dsa_switch
*ds
, int port
)
571 if (mv88e6xxx_6320_family(ds
) || mv88e6xxx_6352_family(ds
))
572 port
= (port
+ 1) << 5;
574 /* Snapshot the hardware statistics counters for this port. */
575 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_STATS_OP
,
576 GLOBAL_STATS_OP_CAPTURE_PORT
|
577 GLOBAL_STATS_OP_HIST_RX_TX
| port
);
581 /* Wait for the snapshotting to complete. */
582 ret
= _mv88e6xxx_stats_wait(ds
);
589 static void _mv88e6xxx_stats_read(struct dsa_switch
*ds
, int stat
, u32
*val
)
596 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_STATS_OP
,
597 GLOBAL_STATS_OP_READ_CAPTURED
|
598 GLOBAL_STATS_OP_HIST_RX_TX
| stat
);
602 ret
= _mv88e6xxx_stats_wait(ds
);
606 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_32
);
612 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_01
);
619 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
620 { "in_good_octets", 8, 0x00, BANK0
, },
621 { "in_bad_octets", 4, 0x02, BANK0
, },
622 { "in_unicast", 4, 0x04, BANK0
, },
623 { "in_broadcasts", 4, 0x06, BANK0
, },
624 { "in_multicasts", 4, 0x07, BANK0
, },
625 { "in_pause", 4, 0x16, BANK0
, },
626 { "in_undersize", 4, 0x18, BANK0
, },
627 { "in_fragments", 4, 0x19, BANK0
, },
628 { "in_oversize", 4, 0x1a, BANK0
, },
629 { "in_jabber", 4, 0x1b, BANK0
, },
630 { "in_rx_error", 4, 0x1c, BANK0
, },
631 { "in_fcs_error", 4, 0x1d, BANK0
, },
632 { "out_octets", 8, 0x0e, BANK0
, },
633 { "out_unicast", 4, 0x10, BANK0
, },
634 { "out_broadcasts", 4, 0x13, BANK0
, },
635 { "out_multicasts", 4, 0x12, BANK0
, },
636 { "out_pause", 4, 0x15, BANK0
, },
637 { "excessive", 4, 0x11, BANK0
, },
638 { "collisions", 4, 0x1e, BANK0
, },
639 { "deferred", 4, 0x05, BANK0
, },
640 { "single", 4, 0x14, BANK0
, },
641 { "multiple", 4, 0x17, BANK0
, },
642 { "out_fcs_error", 4, 0x03, BANK0
, },
643 { "late", 4, 0x1f, BANK0
, },
644 { "hist_64bytes", 4, 0x08, BANK0
, },
645 { "hist_65_127bytes", 4, 0x09, BANK0
, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0
, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0
, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0
, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0
, },
650 { "sw_in_discards", 4, 0x10, PORT
, },
651 { "sw_in_filtered", 2, 0x12, PORT
, },
652 { "sw_out_filtered", 2, 0x13, PORT
, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
681 static bool mv88e6xxx_has_stat(struct dsa_switch
*ds
,
682 struct mv88e6xxx_hw_stat
*stat
)
684 switch (stat
->type
) {
688 return mv88e6xxx_6320_family(ds
);
690 return mv88e6xxx_6095_family(ds
) ||
691 mv88e6xxx_6185_family(ds
) ||
692 mv88e6xxx_6097_family(ds
) ||
693 mv88e6xxx_6165_family(ds
) ||
694 mv88e6xxx_6351_family(ds
) ||
695 mv88e6xxx_6352_family(ds
);
700 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch
*ds
,
701 struct mv88e6xxx_hw_stat
*s
,
711 ret
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), s
->reg
);
716 if (s
->sizeof_stat
== 4) {
717 ret
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
),
726 _mv88e6xxx_stats_read(ds
, s
->reg
, &low
);
727 if (s
->sizeof_stat
== 8)
728 _mv88e6xxx_stats_read(ds
, s
->reg
+ 1, &high
);
730 value
= (((u64
)high
) << 16) | low
;
734 void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
736 struct mv88e6xxx_hw_stat
*stat
;
739 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
740 stat
= &mv88e6xxx_hw_stats
[i
];
741 if (mv88e6xxx_has_stat(ds
, stat
)) {
742 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
749 int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
751 struct mv88e6xxx_hw_stat
*stat
;
754 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
755 stat
= &mv88e6xxx_hw_stats
[i
];
756 if (mv88e6xxx_has_stat(ds
, stat
))
763 mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
,
764 int port
, uint64_t *data
)
766 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
767 struct mv88e6xxx_hw_stat
*stat
;
771 mutex_lock(&ps
->smi_mutex
);
773 ret
= _mv88e6xxx_stats_snapshot(ds
, port
);
775 mutex_unlock(&ps
->smi_mutex
);
778 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
779 stat
= &mv88e6xxx_hw_stats
[i
];
780 if (mv88e6xxx_has_stat(ds
, stat
)) {
781 data
[j
] = _mv88e6xxx_get_ethtool_stat(ds
, stat
, port
);
786 mutex_unlock(&ps
->smi_mutex
);
789 int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
791 return 32 * sizeof(u16
);
794 void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
795 struct ethtool_regs
*regs
, void *_p
)
802 memset(p
, 0xff, 32 * sizeof(u16
));
804 for (i
= 0; i
< 32; i
++) {
807 ret
= mv88e6xxx_reg_read(ds
, REG_PORT(port
), i
);
813 static int _mv88e6xxx_wait(struct dsa_switch
*ds
, int reg
, int offset
,
816 unsigned long timeout
= jiffies
+ HZ
/ 10;
818 while (time_before(jiffies
, timeout
)) {
821 ret
= _mv88e6xxx_reg_read(ds
, reg
, offset
);
827 usleep_range(1000, 2000);
832 static int mv88e6xxx_wait(struct dsa_switch
*ds
, int reg
, int offset
, u16 mask
)
834 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
837 mutex_lock(&ps
->smi_mutex
);
838 ret
= _mv88e6xxx_wait(ds
, reg
, offset
, mask
);
839 mutex_unlock(&ps
->smi_mutex
);
844 static int _mv88e6xxx_phy_wait(struct dsa_switch
*ds
)
846 return _mv88e6xxx_wait(ds
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
847 GLOBAL2_SMI_OP_BUSY
);
850 int mv88e6xxx_eeprom_load_wait(struct dsa_switch
*ds
)
852 return mv88e6xxx_wait(ds
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
853 GLOBAL2_EEPROM_OP_LOAD
);
856 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch
*ds
)
858 return mv88e6xxx_wait(ds
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
859 GLOBAL2_EEPROM_OP_BUSY
);
862 static int _mv88e6xxx_atu_wait(struct dsa_switch
*ds
)
864 return _mv88e6xxx_wait(ds
, REG_GLOBAL
, GLOBAL_ATU_OP
,
868 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch
*ds
, int addr
,
873 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
874 GLOBAL2_SMI_OP_22_READ
| (addr
<< 5) |
879 ret
= _mv88e6xxx_phy_wait(ds
);
883 return _mv88e6xxx_reg_read(ds
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
);
886 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch
*ds
, int addr
,
891 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
, val
);
895 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
896 GLOBAL2_SMI_OP_22_WRITE
| (addr
<< 5) |
899 return _mv88e6xxx_phy_wait(ds
);
902 int mv88e6xxx_get_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
904 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
907 mutex_lock(&ps
->smi_mutex
);
909 reg
= _mv88e6xxx_phy_read_indirect(ds
, port
, 16);
913 e
->eee_enabled
= !!(reg
& 0x0200);
914 e
->tx_lpi_enabled
= !!(reg
& 0x0100);
916 reg
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_STATUS
);
920 e
->eee_active
= !!(reg
& PORT_STATUS_EEE
);
924 mutex_unlock(&ps
->smi_mutex
);
928 int mv88e6xxx_set_eee(struct dsa_switch
*ds
, int port
,
929 struct phy_device
*phydev
, struct ethtool_eee
*e
)
931 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
935 mutex_lock(&ps
->smi_mutex
);
937 ret
= _mv88e6xxx_phy_read_indirect(ds
, port
, 16);
944 if (e
->tx_lpi_enabled
)
947 ret
= _mv88e6xxx_phy_write_indirect(ds
, port
, 16, reg
);
949 mutex_unlock(&ps
->smi_mutex
);
954 static int _mv88e6xxx_atu_cmd(struct dsa_switch
*ds
, u16 cmd
)
958 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_ATU_OP
, cmd
);
962 return _mv88e6xxx_atu_wait(ds
);
965 static int _mv88e6xxx_atu_data_write(struct dsa_switch
*ds
,
966 struct mv88e6xxx_atu_entry
*entry
)
968 u16 data
= entry
->state
& GLOBAL_ATU_DATA_STATE_MASK
;
970 if (entry
->state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
971 unsigned int mask
, shift
;
974 data
|= GLOBAL_ATU_DATA_TRUNK
;
975 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
976 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
978 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
979 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
982 data
|= (entry
->portv_trunkid
<< shift
) & mask
;
985 return _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_ATU_DATA
, data
);
988 static int _mv88e6xxx_atu_flush_move(struct dsa_switch
*ds
,
989 struct mv88e6xxx_atu_entry
*entry
,
995 err
= _mv88e6xxx_atu_wait(ds
);
999 err
= _mv88e6xxx_atu_data_write(ds
, entry
);
1004 err
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_ATU_FID
,
1009 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB
:
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB
;
1012 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL
:
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC
;
1016 return _mv88e6xxx_atu_cmd(ds
, op
);
1019 static int _mv88e6xxx_atu_flush(struct dsa_switch
*ds
, u16 fid
, bool static_too
)
1021 struct mv88e6xxx_atu_entry entry
= {
1023 .state
= 0, /* EntryState bits must be 0 */
1026 return _mv88e6xxx_atu_flush_move(ds
, &entry
, static_too
);
1029 static int _mv88e6xxx_atu_move(struct dsa_switch
*ds
, u16 fid
, int from_port
,
1030 int to_port
, bool static_too
)
1032 struct mv88e6xxx_atu_entry entry
= {
1037 /* EntryState bits must be 0xF */
1038 entry
.state
= GLOBAL_ATU_DATA_STATE_MASK
;
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry
.portv_trunkid
= (to_port
& 0x0f) << 4;
1042 entry
.portv_trunkid
|= from_port
& 0x0f;
1044 return _mv88e6xxx_atu_flush_move(ds
, &entry
, static_too
);
1047 static int _mv88e6xxx_atu_remove(struct dsa_switch
*ds
, u16 fid
, int port
,
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds
, fid
, port
, 0x0f, static_too
);
1054 static int mv88e6xxx_set_port_state(struct dsa_switch
*ds
, int port
, u8 state
)
1056 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1060 mutex_lock(&ps
->smi_mutex
);
1062 reg
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_CONTROL
);
1068 oldstate
= reg
& PORT_CONTROL_STATE_MASK
;
1069 if (oldstate
!= state
) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1074 if (oldstate
>= PORT_CONTROL_STATE_LEARNING
&&
1075 state
<= PORT_CONTROL_STATE_BLOCKING
) {
1076 ret
= _mv88e6xxx_atu_remove(ds
, 0, port
, false);
1080 reg
= (reg
& ~PORT_CONTROL_STATE_MASK
) | state
;
1081 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_CONTROL
,
1086 mutex_unlock(&ps
->smi_mutex
);
1090 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch
*ds
, int port
,
1093 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1094 const u16 mask
= (1 << ps
->num_ports
) - 1;
1097 reg
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_BASE_VLAN
);
1102 reg
|= output_ports
& mask
;
1104 return _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_BASE_VLAN
, reg
);
1107 int mv88e6xxx_port_stp_update(struct dsa_switch
*ds
, int port
, u8 state
)
1109 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1113 case BR_STATE_DISABLED
:
1114 stp_state
= PORT_CONTROL_STATE_DISABLED
;
1116 case BR_STATE_BLOCKING
:
1117 case BR_STATE_LISTENING
:
1118 stp_state
= PORT_CONTROL_STATE_BLOCKING
;
1120 case BR_STATE_LEARNING
:
1121 stp_state
= PORT_CONTROL_STATE_LEARNING
;
1123 case BR_STATE_FORWARDING
:
1125 stp_state
= PORT_CONTROL_STATE_FORWARDING
;
1129 netdev_dbg(ds
->ports
[port
], "port state %d [%d]\n", state
, stp_state
);
1131 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1132 * so we can not update the port state directly but need to schedule it.
1134 ps
->ports
[port
].state
= stp_state
;
1135 set_bit(port
, &ps
->port_state_update_mask
);
1136 schedule_work(&ps
->bridge_work
);
1141 static int _mv88e6xxx_port_pvid_get(struct dsa_switch
*ds
, int port
, u16
*pvid
)
1145 ret
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1149 *pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1154 int mv88e6xxx_port_pvid_get(struct dsa_switch
*ds
, int port
, u16
*pvid
)
1158 ret
= mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1162 *pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1167 static int _mv88e6xxx_port_pvid_set(struct dsa_switch
*ds
, int port
, u16 pvid
)
1169 return _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
1170 pvid
& PORT_DEFAULT_VLAN_MASK
);
1173 static int _mv88e6xxx_vtu_wait(struct dsa_switch
*ds
)
1175 return _mv88e6xxx_wait(ds
, REG_GLOBAL
, GLOBAL_VTU_OP
,
1176 GLOBAL_VTU_OP_BUSY
);
1179 static int _mv88e6xxx_vtu_cmd(struct dsa_switch
*ds
, u16 op
)
1183 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_OP
, op
);
1187 return _mv88e6xxx_vtu_wait(ds
);
1190 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch
*ds
)
1194 ret
= _mv88e6xxx_vtu_wait(ds
);
1198 return _mv88e6xxx_vtu_cmd(ds
, GLOBAL_VTU_OP_FLUSH_ALL
);
1201 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch
*ds
,
1202 struct mv88e6xxx_vtu_stu_entry
*entry
,
1203 unsigned int nibble_offset
)
1205 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1210 for (i
= 0; i
< 3; ++i
) {
1211 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
,
1212 GLOBAL_VTU_DATA_0_3
+ i
);
1219 for (i
= 0; i
< ps
->num_ports
; ++i
) {
1220 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1221 u16 reg
= regs
[i
/ 4];
1223 entry
->data
[i
] = (reg
>> shift
) & GLOBAL_VTU_STU_DATA_MASK
;
1229 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch
*ds
,
1230 struct mv88e6xxx_vtu_stu_entry
*entry
,
1231 unsigned int nibble_offset
)
1233 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1234 u16 regs
[3] = { 0 };
1238 for (i
= 0; i
< ps
->num_ports
; ++i
) {
1239 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1240 u8 data
= entry
->data
[i
];
1242 regs
[i
/ 4] |= (data
& GLOBAL_VTU_STU_DATA_MASK
) << shift
;
1245 for (i
= 0; i
< 3; ++i
) {
1246 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
,
1247 GLOBAL_VTU_DATA_0_3
+ i
, regs
[i
]);
1255 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch
*ds
, u16 vid
)
1257 return _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_VID
,
1258 vid
& GLOBAL_VTU_VID_MASK
);
1261 static int _mv88e6xxx_vtu_getnext(struct dsa_switch
*ds
,
1262 struct mv88e6xxx_vtu_stu_entry
*entry
)
1264 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1267 ret
= _mv88e6xxx_vtu_wait(ds
);
1271 ret
= _mv88e6xxx_vtu_cmd(ds
, GLOBAL_VTU_OP_VTU_GET_NEXT
);
1275 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1279 next
.vid
= ret
& GLOBAL_VTU_VID_MASK
;
1280 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1283 ret
= _mv88e6xxx_vtu_stu_data_read(ds
, &next
, 0);
1287 if (mv88e6xxx_6097_family(ds
) || mv88e6xxx_6165_family(ds
) ||
1288 mv88e6xxx_6351_family(ds
) || mv88e6xxx_6352_family(ds
)) {
1289 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
,
1294 next
.fid
= ret
& GLOBAL_VTU_FID_MASK
;
1296 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
,
1301 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1309 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch
*ds
,
1310 struct mv88e6xxx_vtu_stu_entry
*entry
)
1315 ret
= _mv88e6xxx_vtu_wait(ds
);
1322 /* Write port member tags */
1323 ret
= _mv88e6xxx_vtu_stu_data_write(ds
, entry
, 0);
1327 if (mv88e6xxx_6097_family(ds
) || mv88e6xxx_6165_family(ds
) ||
1328 mv88e6xxx_6351_family(ds
) || mv88e6xxx_6352_family(ds
)) {
1329 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1330 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1334 reg
= entry
->fid
& GLOBAL_VTU_FID_MASK
;
1335 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_FID
, reg
);
1340 reg
= GLOBAL_VTU_VID_VALID
;
1342 reg
|= entry
->vid
& GLOBAL_VTU_VID_MASK
;
1343 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1347 return _mv88e6xxx_vtu_cmd(ds
, GLOBAL_VTU_OP_VTU_LOAD_PURGE
);
1350 static int _mv88e6xxx_stu_getnext(struct dsa_switch
*ds
, u8 sid
,
1351 struct mv88e6xxx_vtu_stu_entry
*entry
)
1353 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1356 ret
= _mv88e6xxx_vtu_wait(ds
);
1360 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1361 sid
& GLOBAL_VTU_SID_MASK
);
1365 ret
= _mv88e6xxx_vtu_cmd(ds
, GLOBAL_VTU_OP_STU_GET_NEXT
);
1369 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_VTU_SID
);
1373 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1375 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1379 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1382 ret
= _mv88e6xxx_vtu_stu_data_read(ds
, &next
, 2);
1391 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch
*ds
,
1392 struct mv88e6xxx_vtu_stu_entry
*entry
)
1397 ret
= _mv88e6xxx_vtu_wait(ds
);
1404 /* Write port states */
1405 ret
= _mv88e6xxx_vtu_stu_data_write(ds
, entry
, 2);
1409 reg
= GLOBAL_VTU_VID_VALID
;
1411 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1415 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1416 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1420 return _mv88e6xxx_vtu_cmd(ds
, GLOBAL_VTU_OP_STU_LOAD_PURGE
);
1423 static int _mv88e6xxx_vlan_init(struct dsa_switch
*ds
, u16 vid
,
1424 struct mv88e6xxx_vtu_stu_entry
*entry
)
1426 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1427 struct mv88e6xxx_vtu_stu_entry vlan
= {
1430 .fid
= vid
, /* We use one FID per VLAN */
1434 /* exclude all ports except the CPU and DSA ports */
1435 for (i
= 0; i
< ps
->num_ports
; ++i
)
1436 vlan
.data
[i
] = dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
)
1437 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1438 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1440 if (mv88e6xxx_6097_family(ds
) || mv88e6xxx_6165_family(ds
) ||
1441 mv88e6xxx_6351_family(ds
) || mv88e6xxx_6352_family(ds
)) {
1442 struct mv88e6xxx_vtu_stu_entry vstp
;
1445 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1446 * implemented, only one STU entry is needed to cover all VTU
1447 * entries. Thus, validate the SID 0.
1450 err
= _mv88e6xxx_stu_getnext(ds
, GLOBAL_VTU_SID_MASK
, &vstp
);
1454 if (vstp
.sid
!= vlan
.sid
|| !vstp
.valid
) {
1455 memset(&vstp
, 0, sizeof(vstp
));
1457 vstp
.sid
= vlan
.sid
;
1459 err
= _mv88e6xxx_stu_loadpurge(ds
, &vstp
);
1464 /* Clear all MAC addresses from the new database */
1465 err
= _mv88e6xxx_atu_flush(ds
, vlan
.fid
, true);
1474 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1475 u16 vid_begin
, u16 vid_end
)
1477 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1478 struct mv88e6xxx_vtu_stu_entry vlan
;
1484 mutex_lock(&ps
->smi_mutex
);
1486 err
= _mv88e6xxx_vtu_vid_write(ds
, vid_begin
- 1);
1491 err
= _mv88e6xxx_vtu_getnext(ds
, &vlan
);
1498 if (vlan
.vid
> vid_end
)
1501 for (i
= 0; i
< ps
->num_ports
; ++i
) {
1502 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1506 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1509 if (ps
->ports
[i
].bridge_dev
==
1510 ps
->ports
[port
].bridge_dev
)
1511 break; /* same bridge, check next VLAN */
1513 netdev_warn(ds
->ports
[port
],
1514 "hardware VLAN %d already used by %s\n",
1516 netdev_name(ps
->ports
[i
].bridge_dev
));
1520 } while (vlan
.vid
< vid_end
);
1523 mutex_unlock(&ps
->smi_mutex
);
1528 int mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1529 const struct switchdev_obj_port_vlan
*vlan
,
1530 struct switchdev_trans
*trans
)
1534 /* We reserve a few VLANs to isolate unbridged ports */
1535 if (vlan
->vid_end
>= 4000)
1538 /* If the requested port doesn't belong to the same bridge as the VLAN
1539 * members, do not support it (yet) and fallback to software VLAN.
1541 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1546 /* We don't need any dynamic resource from the kernel (yet),
1547 * so skip the prepare phase.
1552 static int _mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
, u16 vid
,
1555 struct mv88e6xxx_vtu_stu_entry vlan
;
1558 err
= _mv88e6xxx_vtu_vid_write(ds
, vid
- 1);
1562 err
= _mv88e6xxx_vtu_getnext(ds
, &vlan
);
1566 if (vlan
.vid
!= vid
|| !vlan
.valid
) {
1567 err
= _mv88e6xxx_vlan_init(ds
, vid
, &vlan
);
1572 vlan
.data
[port
] = untagged
?
1573 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
:
1574 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
;
1576 return _mv88e6xxx_vtu_loadpurge(ds
, &vlan
);
1579 int mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1580 const struct switchdev_obj_port_vlan
*vlan
,
1581 struct switchdev_trans
*trans
)
1583 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1584 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1585 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1589 mutex_lock(&ps
->smi_mutex
);
1591 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1592 err
= _mv88e6xxx_port_vlan_add(ds
, port
, vid
, untagged
);
1597 /* no PVID with ranges, otherwise it's a bug */
1599 err
= _mv88e6xxx_port_pvid_set(ds
, port
, vlan
->vid_end
);
1601 mutex_unlock(&ps
->smi_mutex
);
1606 static int _mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
, u16 vid
)
1608 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1609 struct mv88e6xxx_vtu_stu_entry vlan
;
1612 err
= _mv88e6xxx_vtu_vid_write(ds
, vid
- 1);
1616 err
= _mv88e6xxx_vtu_getnext(ds
, &vlan
);
1620 if (vlan
.vid
!= vid
|| !vlan
.valid
||
1621 vlan
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1624 vlan
.data
[port
] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1626 /* keep the VLAN unless all ports are excluded */
1628 for (i
= 0; i
< ps
->num_ports
; ++i
) {
1629 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1632 if (vlan
.data
[i
] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
1638 err
= _mv88e6xxx_vtu_loadpurge(ds
, &vlan
);
1642 return _mv88e6xxx_atu_remove(ds
, vlan
.fid
, port
, false);
1645 int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
1646 const struct switchdev_obj_port_vlan
*vlan
)
1648 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1649 const u16 defpvid
= 4000 + ds
->index
* DSA_MAX_PORTS
+ port
;
1653 mutex_lock(&ps
->smi_mutex
);
1655 err
= _mv88e6xxx_port_pvid_get(ds
, port
, &pvid
);
1659 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1660 err
= _mv88e6xxx_port_vlan_del(ds
, port
, vid
);
1665 /* restore reserved VLAN ID */
1666 err
= _mv88e6xxx_port_pvid_set(ds
, port
, defpvid
);
1673 mutex_unlock(&ps
->smi_mutex
);
1678 int mv88e6xxx_vlan_getnext(struct dsa_switch
*ds
, u16
*vid
,
1679 unsigned long *ports
, unsigned long *untagged
)
1681 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1682 struct mv88e6xxx_vtu_stu_entry next
;
1689 mutex_lock(&ps
->smi_mutex
);
1690 err
= _mv88e6xxx_vtu_vid_write(ds
, *vid
);
1694 err
= _mv88e6xxx_vtu_getnext(ds
, &next
);
1696 mutex_unlock(&ps
->smi_mutex
);
1706 for (port
= 0; port
< ps
->num_ports
; ++port
) {
1707 clear_bit(port
, ports
);
1708 clear_bit(port
, untagged
);
1710 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1713 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
||
1714 next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1715 set_bit(port
, ports
);
1717 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1718 set_bit(port
, untagged
);
1724 static int _mv88e6xxx_atu_mac_write(struct dsa_switch
*ds
,
1725 const unsigned char *addr
)
1729 for (i
= 0; i
< 3; i
++) {
1730 ret
= _mv88e6xxx_reg_write(
1731 ds
, REG_GLOBAL
, GLOBAL_ATU_MAC_01
+ i
,
1732 (addr
[i
* 2] << 8) | addr
[i
* 2 + 1]);
1740 static int _mv88e6xxx_atu_mac_read(struct dsa_switch
*ds
, unsigned char *addr
)
1744 for (i
= 0; i
< 3; i
++) {
1745 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
,
1746 GLOBAL_ATU_MAC_01
+ i
);
1749 addr
[i
* 2] = ret
>> 8;
1750 addr
[i
* 2 + 1] = ret
& 0xff;
1756 static int _mv88e6xxx_atu_load(struct dsa_switch
*ds
,
1757 struct mv88e6xxx_atu_entry
*entry
)
1761 ret
= _mv88e6xxx_atu_wait(ds
);
1765 ret
= _mv88e6xxx_atu_mac_write(ds
, entry
->mac
);
1769 ret
= _mv88e6xxx_atu_data_write(ds
, entry
);
1773 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_ATU_FID
, entry
->fid
);
1777 return _mv88e6xxx_atu_cmd(ds
, GLOBAL_ATU_OP_LOAD_DB
);
1780 static int _mv88e6xxx_port_fdb_load(struct dsa_switch
*ds
, int port
,
1781 const unsigned char *addr
, u16 vid
,
1784 struct mv88e6xxx_atu_entry entry
= { 0 };
1786 entry
.fid
= vid
; /* We use one FID per VLAN */
1787 entry
.state
= state
;
1788 ether_addr_copy(entry
.mac
, addr
);
1789 if (state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
1790 entry
.trunk
= false;
1791 entry
.portv_trunkid
= BIT(port
);
1794 return _mv88e6xxx_atu_load(ds
, &entry
);
1797 int mv88e6xxx_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
1798 const struct switchdev_obj_port_fdb
*fdb
,
1799 struct switchdev_trans
*trans
)
1801 /* We don't use per-port FDB */
1805 /* We don't need any dynamic resource from the kernel (yet),
1806 * so skip the prepare phase.
1811 int mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1812 const struct switchdev_obj_port_fdb
*fdb
,
1813 struct switchdev_trans
*trans
)
1815 int state
= is_multicast_ether_addr(fdb
->addr
) ?
1816 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
1817 GLOBAL_ATU_DATA_STATE_UC_STATIC
;
1818 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1821 mutex_lock(&ps
->smi_mutex
);
1822 ret
= _mv88e6xxx_port_fdb_load(ds
, port
, fdb
->addr
, fdb
->vid
, state
);
1823 mutex_unlock(&ps
->smi_mutex
);
1828 int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1829 const struct switchdev_obj_port_fdb
*fdb
)
1831 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1834 mutex_lock(&ps
->smi_mutex
);
1835 ret
= _mv88e6xxx_port_fdb_load(ds
, port
, fdb
->addr
, fdb
->vid
,
1836 GLOBAL_ATU_DATA_STATE_UNUSED
);
1837 mutex_unlock(&ps
->smi_mutex
);
1842 static int _mv88e6xxx_atu_getnext(struct dsa_switch
*ds
, u16 fid
,
1843 struct mv88e6xxx_atu_entry
*entry
)
1845 struct mv88e6xxx_atu_entry next
= { 0 };
1850 ret
= _mv88e6xxx_atu_wait(ds
);
1854 ret
= _mv88e6xxx_reg_write(ds
, REG_GLOBAL
, GLOBAL_ATU_FID
, fid
);
1858 ret
= _mv88e6xxx_atu_cmd(ds
, GLOBAL_ATU_OP_GET_NEXT_DB
);
1862 ret
= _mv88e6xxx_atu_mac_read(ds
, next
.mac
);
1866 ret
= _mv88e6xxx_reg_read(ds
, REG_GLOBAL
, GLOBAL_ATU_DATA
);
1870 next
.state
= ret
& GLOBAL_ATU_DATA_STATE_MASK
;
1871 if (next
.state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
1872 unsigned int mask
, shift
;
1874 if (ret
& GLOBAL_ATU_DATA_TRUNK
) {
1876 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
1877 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
1880 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
1881 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
1884 next
.portv_trunkid
= (ret
& mask
) >> shift
;
1891 int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1892 struct switchdev_obj_port_fdb
*fdb
,
1893 int (*cb
)(struct switchdev_obj
*obj
))
1895 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1896 struct mv88e6xxx_vtu_stu_entry vlan
= {
1897 .vid
= GLOBAL_VTU_VID_MASK
, /* all ones */
1901 mutex_lock(&ps
->smi_mutex
);
1903 err
= _mv88e6xxx_vtu_vid_write(ds
, vlan
.vid
);
1908 struct mv88e6xxx_atu_entry addr
= {
1909 .mac
= { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1912 err
= _mv88e6xxx_vtu_getnext(ds
, &vlan
);
1919 err
= _mv88e6xxx_atu_mac_write(ds
, addr
.mac
);
1924 err
= _mv88e6xxx_atu_getnext(ds
, vlan
.fid
, &addr
);
1928 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UNUSED
)
1931 if (!addr
.trunk
&& addr
.portv_trunkid
& BIT(port
)) {
1932 bool is_static
= addr
.state
==
1933 (is_multicast_ether_addr(addr
.mac
) ?
1934 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
1935 GLOBAL_ATU_DATA_STATE_UC_STATIC
);
1937 fdb
->vid
= vlan
.vid
;
1938 ether_addr_copy(fdb
->addr
, addr
.mac
);
1939 fdb
->ndm_state
= is_static
? NUD_NOARP
:
1942 err
= cb(&fdb
->obj
);
1946 } while (!is_broadcast_ether_addr(addr
.mac
));
1948 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
1951 mutex_unlock(&ps
->smi_mutex
);
1956 int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
1957 struct net_device
*bridge
)
1959 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1961 ps
->ports
[port
].bridge_dev
= bridge
;
1966 int mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
)
1968 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1970 ps
->ports
[port
].bridge_dev
= NULL
;
1975 static int mv88e6xxx_setup_port_default_vlan(struct dsa_switch
*ds
, int port
)
1977 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1978 const u16 pvid
= 4000 + ds
->index
* DSA_MAX_PORTS
+ port
;
1981 mutex_lock(&ps
->smi_mutex
);
1982 err
= _mv88e6xxx_port_vlan_add(ds
, port
, pvid
, true);
1984 err
= _mv88e6xxx_port_pvid_set(ds
, port
, pvid
);
1985 mutex_unlock(&ps
->smi_mutex
);
1989 static void mv88e6xxx_bridge_work(struct work_struct
*work
)
1991 struct mv88e6xxx_priv_state
*ps
;
1992 struct dsa_switch
*ds
;
1995 ps
= container_of(work
, struct mv88e6xxx_priv_state
, bridge_work
);
1996 ds
= ((struct dsa_switch
*)ps
) - 1;
1998 while (ps
->port_state_update_mask
) {
1999 port
= __ffs(ps
->port_state_update_mask
);
2000 clear_bit(port
, &ps
->port_state_update_mask
);
2001 mv88e6xxx_set_port_state(ds
, port
, ps
->ports
[port
].state
);
2005 static int mv88e6xxx_setup_port(struct dsa_switch
*ds
, int port
)
2007 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2011 mutex_lock(&ps
->smi_mutex
);
2013 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2014 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2015 mv88e6xxx_6185_family(ds
) || mv88e6xxx_6095_family(ds
) ||
2016 mv88e6xxx_6065_family(ds
) || mv88e6xxx_6320_family(ds
)) {
2017 /* MAC Forcing register: don't force link, speed,
2018 * duplex or flow control state to any particular
2019 * values on physical ports, but force the CPU port
2020 * and all DSA ports to their maximum bandwidth and
2023 reg
= _mv88e6xxx_reg_read(ds
, REG_PORT(port
), PORT_PCS_CTRL
);
2024 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
2025 reg
&= ~PORT_PCS_CTRL_UNFORCED
;
2026 reg
|= PORT_PCS_CTRL_FORCE_LINK
|
2027 PORT_PCS_CTRL_LINK_UP
|
2028 PORT_PCS_CTRL_DUPLEX_FULL
|
2029 PORT_PCS_CTRL_FORCE_DUPLEX
;
2030 if (mv88e6xxx_6065_family(ds
))
2031 reg
|= PORT_PCS_CTRL_100
;
2033 reg
|= PORT_PCS_CTRL_1000
;
2035 reg
|= PORT_PCS_CTRL_UNFORCED
;
2038 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2039 PORT_PCS_CTRL
, reg
);
2044 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2045 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2046 * tunneling, determine priority by looking at 802.1p and IP
2047 * priority fields (IP prio has precedence), and set STP state
2050 * If this is the CPU link, use DSA or EDSA tagging depending
2051 * on which tagging mode was configured.
2053 * If this is a link to another switch, use DSA tagging mode.
2055 * If this is the upstream port for this switch, enable
2056 * forwarding of unknown unicasts and multicasts.
2059 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2060 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2061 mv88e6xxx_6095_family(ds
) || mv88e6xxx_6065_family(ds
) ||
2062 mv88e6xxx_6185_family(ds
) || mv88e6xxx_6320_family(ds
))
2063 reg
= PORT_CONTROL_IGMP_MLD_SNOOP
|
2064 PORT_CONTROL_USE_TAG
| PORT_CONTROL_USE_IP
|
2065 PORT_CONTROL_STATE_FORWARDING
;
2066 if (dsa_is_cpu_port(ds
, port
)) {
2067 if (mv88e6xxx_6095_family(ds
) || mv88e6xxx_6185_family(ds
))
2068 reg
|= PORT_CONTROL_DSA_TAG
;
2069 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2070 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2071 mv88e6xxx_6320_family(ds
)) {
2072 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2073 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
;
2075 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2076 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2077 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2080 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2081 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2082 mv88e6xxx_6095_family(ds
) || mv88e6xxx_6065_family(ds
) ||
2083 mv88e6xxx_6185_family(ds
) || mv88e6xxx_6320_family(ds
)) {
2084 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2085 reg
|= PORT_CONTROL_EGRESS_ADD_TAG
;
2088 if (dsa_is_dsa_port(ds
, port
)) {
2089 if (mv88e6xxx_6095_family(ds
) || mv88e6xxx_6185_family(ds
))
2090 reg
|= PORT_CONTROL_DSA_TAG
;
2091 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2092 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2093 mv88e6xxx_6320_family(ds
)) {
2094 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2097 if (port
== dsa_upstream_port(ds
))
2098 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2099 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2102 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2108 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2109 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2110 * untagged frames on this port, do a destination address lookup on all
2111 * received packets as usual, disable ARP mirroring and don't send a
2112 * copy of all transmitted/received frames on this port to the CPU.
2115 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2116 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2117 mv88e6xxx_6095_family(ds
) || mv88e6xxx_6320_family(ds
))
2118 reg
= PORT_CONTROL_2_MAP_DA
;
2120 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2121 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6320_family(ds
))
2122 reg
|= PORT_CONTROL_2_JUMBO_10240
;
2124 if (mv88e6xxx_6095_family(ds
) || mv88e6xxx_6185_family(ds
)) {
2125 /* Set the upstream port this port should use */
2126 reg
|= dsa_upstream_port(ds
);
2127 /* enable forwarding of unknown multicast addresses to
2130 if (port
== dsa_upstream_port(ds
))
2131 reg
|= PORT_CONTROL_2_FORWARD_UNKNOWN
;
2134 reg
|= PORT_CONTROL_2_8021Q_SECURE
;
2137 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2138 PORT_CONTROL_2
, reg
);
2143 /* Port Association Vector: when learning source addresses
2144 * of packets, add the address to the address database using
2145 * a port bitmap that has only the bit for this port set and
2146 * the other bits clear.
2149 /* Disable learning for DSA and CPU ports */
2150 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
2151 reg
= PORT_ASSOC_VECTOR_LOCKED_PORT
;
2153 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_ASSOC_VECTOR
, reg
);
2157 /* Egress rate control 2: disable egress rate control. */
2158 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_RATE_CONTROL_2
,
2163 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2164 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2165 mv88e6xxx_6320_family(ds
)) {
2166 /* Do not limit the period of time that this port can
2167 * be paused for by the remote end or the period of
2168 * time that this port can pause the remote end.
2170 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2171 PORT_PAUSE_CTRL
, 0x0000);
2175 /* Port ATU control: disable limiting the number of
2176 * address database entries that this port is allowed
2179 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2180 PORT_ATU_CONTROL
, 0x0000);
2181 /* Priority Override: disable DA, SA and VTU priority
2184 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2185 PORT_PRI_OVERRIDE
, 0x0000);
2189 /* Port Ethertype: use the Ethertype DSA Ethertype
2192 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2193 PORT_ETH_TYPE
, ETH_P_EDSA
);
2196 /* Tag Remap: use an identity 802.1p prio -> switch
2199 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2200 PORT_TAG_REGMAP_0123
, 0x3210);
2204 /* Tag Remap 2: use an identity 802.1p prio -> switch
2207 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2208 PORT_TAG_REGMAP_4567
, 0x7654);
2213 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2214 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2215 mv88e6xxx_6185_family(ds
) || mv88e6xxx_6095_family(ds
) ||
2216 mv88e6xxx_6320_family(ds
)) {
2217 /* Rate Control: disable ingress rate limiting. */
2218 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
),
2219 PORT_RATE_CONTROL
, 0x0001);
2224 /* Port Control 1: disable trunking, disable sending
2225 * learning messages to this port.
2227 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_CONTROL_1
, 0x0000);
2231 /* Port based VLAN map: do not give each port its own address
2232 * database, and allow every port to egress frames on all other ports.
2234 reg
= BIT(ps
->num_ports
) - 1; /* all ports */
2235 reg
&= ~BIT(port
); /* except itself */
2236 ret
= _mv88e6xxx_port_vlan_map_set(ds
, port
, reg
);
2240 /* Default VLAN ID and priority: don't set a default VLAN
2241 * ID, and set the default packet priority to zero.
2243 ret
= _mv88e6xxx_reg_write(ds
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
2246 mutex_unlock(&ps
->smi_mutex
);
2250 int mv88e6xxx_setup_ports(struct dsa_switch
*ds
)
2252 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2256 for (i
= 0; i
< ps
->num_ports
; i
++) {
2257 ret
= mv88e6xxx_setup_port(ds
, i
);
2261 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
2264 ret
= mv88e6xxx_setup_port_default_vlan(ds
, i
);
2271 int mv88e6xxx_setup_common(struct dsa_switch
*ds
)
2273 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2275 mutex_init(&ps
->smi_mutex
);
2277 ps
->id
= REG_READ(REG_PORT(0), PORT_SWITCH_ID
) & 0xfff0;
2279 INIT_WORK(&ps
->bridge_work
, mv88e6xxx_bridge_work
);
2284 int mv88e6xxx_setup_global(struct dsa_switch
*ds
)
2286 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2290 /* Set the default address aging time to 5 minutes, and
2291 * enable address learn messages to be sent to all message
2294 REG_WRITE(REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
2295 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL
);
2297 /* Configure the IP ToS mapping registers. */
2298 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_0
, 0x0000);
2299 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_1
, 0x0000);
2300 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_2
, 0x5555);
2301 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_3
, 0x5555);
2302 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_4
, 0xaaaa);
2303 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_5
, 0xaaaa);
2304 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_6
, 0xffff);
2305 REG_WRITE(REG_GLOBAL
, GLOBAL_IP_PRI_7
, 0xffff);
2307 /* Configure the IEEE 802.1p priority mapping register. */
2308 REG_WRITE(REG_GLOBAL
, GLOBAL_IEEE_PRI
, 0xfa41);
2310 /* Send all frames with destination addresses matching
2311 * 01:80:c2:00:00:0x to the CPU port.
2313 REG_WRITE(REG_GLOBAL2
, GLOBAL2_MGMT_EN_0X
, 0xffff);
2315 /* Ignore removed tag data on doubly tagged packets, disable
2316 * flow control messages, force flow control priority to the
2317 * highest, and send all special multicast frames to the CPU
2318 * port at the highest priority.
2320 REG_WRITE(REG_GLOBAL2
, GLOBAL2_SWITCH_MGMT
,
2321 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU
| 0x70 |
2322 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI
);
2324 /* Program the DSA routing table. */
2325 for (i
= 0; i
< 32; i
++) {
2328 if (ds
->pd
->rtable
&&
2329 i
!= ds
->index
&& i
< ds
->dst
->pd
->nr_chips
)
2330 nexthop
= ds
->pd
->rtable
[i
] & 0x1f;
2332 REG_WRITE(REG_GLOBAL2
, GLOBAL2_DEVICE_MAPPING
,
2333 GLOBAL2_DEVICE_MAPPING_UPDATE
|
2334 (i
<< GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT
) |
2338 /* Clear all trunk masks. */
2339 for (i
= 0; i
< 8; i
++)
2340 REG_WRITE(REG_GLOBAL2
, GLOBAL2_TRUNK_MASK
,
2341 0x8000 | (i
<< GLOBAL2_TRUNK_MASK_NUM_SHIFT
) |
2342 ((1 << ps
->num_ports
) - 1));
2344 /* Clear all trunk mappings. */
2345 for (i
= 0; i
< 16; i
++)
2346 REG_WRITE(REG_GLOBAL2
, GLOBAL2_TRUNK_MAPPING
,
2347 GLOBAL2_TRUNK_MAPPING_UPDATE
|
2348 (i
<< GLOBAL2_TRUNK_MAPPING_ID_SHIFT
));
2350 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2351 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2352 mv88e6xxx_6320_family(ds
)) {
2353 /* Send all frames with destination addresses matching
2354 * 01:80:c2:00:00:2x to the CPU port.
2356 REG_WRITE(REG_GLOBAL2
, GLOBAL2_MGMT_EN_2X
, 0xffff);
2358 /* Initialise cross-chip port VLAN table to reset
2361 REG_WRITE(REG_GLOBAL2
, GLOBAL2_PVT_ADDR
, 0x9000);
2363 /* Clear the priority override table. */
2364 for (i
= 0; i
< 16; i
++)
2365 REG_WRITE(REG_GLOBAL2
, GLOBAL2_PRIO_OVERRIDE
,
2369 if (mv88e6xxx_6352_family(ds
) || mv88e6xxx_6351_family(ds
) ||
2370 mv88e6xxx_6165_family(ds
) || mv88e6xxx_6097_family(ds
) ||
2371 mv88e6xxx_6185_family(ds
) || mv88e6xxx_6095_family(ds
) ||
2372 mv88e6xxx_6320_family(ds
)) {
2373 /* Disable ingress rate limiting by resetting all
2374 * ingress rate limit registers to their initial
2377 for (i
= 0; i
< ps
->num_ports
; i
++)
2378 REG_WRITE(REG_GLOBAL2
, GLOBAL2_INGRESS_OP
,
2382 /* Clear the statistics counters for all ports */
2383 REG_WRITE(REG_GLOBAL
, GLOBAL_STATS_OP
, GLOBAL_STATS_OP_FLUSH_ALL
);
2385 /* Wait for the flush to complete. */
2386 mutex_lock(&ps
->smi_mutex
);
2387 ret
= _mv88e6xxx_stats_wait(ds
);
2391 /* Clear all ATU entries */
2392 ret
= _mv88e6xxx_atu_flush(ds
, 0, true);
2396 /* Clear all the VTU and STU entries */
2397 ret
= _mv88e6xxx_vtu_stu_flush(ds
);
2399 mutex_unlock(&ps
->smi_mutex
);
2404 int mv88e6xxx_switch_reset(struct dsa_switch
*ds
, bool ppu_active
)
2406 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2407 u16 is_reset
= (ppu_active
? 0x8800 : 0xc800);
2408 struct gpio_desc
*gpiod
= ds
->pd
->reset
;
2409 unsigned long timeout
;
2413 /* Set all ports to the disabled state. */
2414 for (i
= 0; i
< ps
->num_ports
; i
++) {
2415 ret
= REG_READ(REG_PORT(i
), PORT_CONTROL
);
2416 REG_WRITE(REG_PORT(i
), PORT_CONTROL
, ret
& 0xfffc);
2419 /* Wait for transmit queues to drain. */
2420 usleep_range(2000, 4000);
2422 /* If there is a gpio connected to the reset pin, toggle it */
2424 gpiod_set_value_cansleep(gpiod
, 1);
2425 usleep_range(10000, 20000);
2426 gpiod_set_value_cansleep(gpiod
, 0);
2427 usleep_range(10000, 20000);
2430 /* Reset the switch. Keep the PPU active if requested. The PPU
2431 * needs to be active to support indirect phy register access
2432 * through global registers 0x18 and 0x19.
2435 REG_WRITE(REG_GLOBAL
, 0x04, 0xc000);
2437 REG_WRITE(REG_GLOBAL
, 0x04, 0xc400);
2439 /* Wait up to one second for reset to complete. */
2440 timeout
= jiffies
+ 1 * HZ
;
2441 while (time_before(jiffies
, timeout
)) {
2442 ret
= REG_READ(REG_GLOBAL
, 0x00);
2443 if ((ret
& is_reset
) == is_reset
)
2445 usleep_range(1000, 2000);
2447 if (time_after(jiffies
, timeout
))
2453 int mv88e6xxx_phy_page_read(struct dsa_switch
*ds
, int port
, int page
, int reg
)
2455 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2458 mutex_lock(&ps
->smi_mutex
);
2459 ret
= _mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, page
);
2462 ret
= _mv88e6xxx_phy_read_indirect(ds
, port
, reg
);
2464 _mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, 0x0);
2465 mutex_unlock(&ps
->smi_mutex
);
2469 int mv88e6xxx_phy_page_write(struct dsa_switch
*ds
, int port
, int page
,
2472 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2475 mutex_lock(&ps
->smi_mutex
);
2476 ret
= _mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, page
);
2480 ret
= _mv88e6xxx_phy_write_indirect(ds
, port
, reg
, val
);
2482 _mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, 0x0);
2483 mutex_unlock(&ps
->smi_mutex
);
2487 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch
*ds
, int port
)
2489 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2491 if (port
>= 0 && port
< ps
->num_ports
)
2497 mv88e6xxx_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
2499 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2500 int addr
= mv88e6xxx_port_to_phy_addr(ds
, port
);
2506 mutex_lock(&ps
->smi_mutex
);
2507 ret
= _mv88e6xxx_phy_read(ds
, addr
, regnum
);
2508 mutex_unlock(&ps
->smi_mutex
);
2513 mv88e6xxx_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
2515 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2516 int addr
= mv88e6xxx_port_to_phy_addr(ds
, port
);
2522 mutex_lock(&ps
->smi_mutex
);
2523 ret
= _mv88e6xxx_phy_write(ds
, addr
, regnum
, val
);
2524 mutex_unlock(&ps
->smi_mutex
);
2529 mv88e6xxx_phy_read_indirect(struct dsa_switch
*ds
, int port
, int regnum
)
2531 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2532 int addr
= mv88e6xxx_port_to_phy_addr(ds
, port
);
2538 mutex_lock(&ps
->smi_mutex
);
2539 ret
= _mv88e6xxx_phy_read_indirect(ds
, addr
, regnum
);
2540 mutex_unlock(&ps
->smi_mutex
);
2545 mv88e6xxx_phy_write_indirect(struct dsa_switch
*ds
, int port
, int regnum
,
2548 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2549 int addr
= mv88e6xxx_port_to_phy_addr(ds
, port
);
2555 mutex_lock(&ps
->smi_mutex
);
2556 ret
= _mv88e6xxx_phy_write_indirect(ds
, addr
, regnum
, val
);
2557 mutex_unlock(&ps
->smi_mutex
);
2561 #ifdef CONFIG_NET_DSA_HWMON
2563 static int mv88e61xx_get_temp(struct dsa_switch
*ds
, int *temp
)
2565 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2571 mutex_lock(&ps
->smi_mutex
);
2573 ret
= _mv88e6xxx_phy_write(ds
, 0x0, 0x16, 0x6);
2577 /* Enable temperature sensor */
2578 ret
= _mv88e6xxx_phy_read(ds
, 0x0, 0x1a);
2582 ret
= _mv88e6xxx_phy_write(ds
, 0x0, 0x1a, ret
| (1 << 5));
2586 /* Wait for temperature to stabilize */
2587 usleep_range(10000, 12000);
2589 val
= _mv88e6xxx_phy_read(ds
, 0x0, 0x1a);
2595 /* Disable temperature sensor */
2596 ret
= _mv88e6xxx_phy_write(ds
, 0x0, 0x1a, ret
& ~(1 << 5));
2600 *temp
= ((val
& 0x1f) - 5) * 5;
2603 _mv88e6xxx_phy_write(ds
, 0x0, 0x16, 0x0);
2604 mutex_unlock(&ps
->smi_mutex
);
2608 static int mv88e63xx_get_temp(struct dsa_switch
*ds
, int *temp
)
2610 int phy
= mv88e6xxx_6320_family(ds
) ? 3 : 0;
2615 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 27);
2619 *temp
= (ret
& 0xff) - 25;
2624 int mv88e6xxx_get_temp(struct dsa_switch
*ds
, int *temp
)
2626 if (mv88e6xxx_6320_family(ds
) || mv88e6xxx_6352_family(ds
))
2627 return mv88e63xx_get_temp(ds
, temp
);
2629 return mv88e61xx_get_temp(ds
, temp
);
2632 int mv88e6xxx_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
2634 int phy
= mv88e6xxx_6320_family(ds
) ? 3 : 0;
2637 if (!mv88e6xxx_6320_family(ds
) && !mv88e6xxx_6352_family(ds
))
2642 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
2646 *temp
= (((ret
>> 8) & 0x1f) * 5) - 25;
2651 int mv88e6xxx_set_temp_limit(struct dsa_switch
*ds
, int temp
)
2653 int phy
= mv88e6xxx_6320_family(ds
) ? 3 : 0;
2656 if (!mv88e6xxx_6320_family(ds
) && !mv88e6xxx_6352_family(ds
))
2659 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
2662 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
2663 return mv88e6xxx_phy_page_write(ds
, phy
, 6, 26,
2664 (ret
& 0xe0ff) | (temp
<< 8));
2667 int mv88e6xxx_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
2669 int phy
= mv88e6xxx_6320_family(ds
) ? 3 : 0;
2672 if (!mv88e6xxx_6320_family(ds
) && !mv88e6xxx_6352_family(ds
))
2677 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
2681 *alarm
= !!(ret
& 0x40);
2685 #endif /* CONFIG_NET_DSA_HWMON */
2687 char *mv88e6xxx_lookup_name(struct device
*host_dev
, int sw_addr
,
2688 const struct mv88e6xxx_switch_id
*table
,
2691 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(host_dev
);
2697 ret
= __mv88e6xxx_reg_read(bus
, sw_addr
, REG_PORT(0), PORT_SWITCH_ID
);
2701 /* Look up the exact switch ID */
2702 for (i
= 0; i
< num
; ++i
)
2703 if (table
[i
].id
== ret
)
2704 return table
[i
].name
;
2706 /* Look up only the product number */
2707 for (i
= 0; i
< num
; ++i
) {
2708 if (table
[i
].id
== (ret
& PORT_SWITCH_ID_PROD_NUM_MASK
)) {
2709 dev_warn(host_dev
, "unknown revision %d, using base switch 0x%x\n",
2710 ret
& PORT_SWITCH_ID_REV_MASK
,
2711 ret
& PORT_SWITCH_ID_PROD_NUM_MASK
);
2712 return table
[i
].name
;
2719 static int __init
mv88e6xxx_init(void)
2721 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2722 register_switch_driver(&mv88e6131_switch_driver
);
2724 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2725 register_switch_driver(&mv88e6123_61_65_switch_driver
);
2727 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2728 register_switch_driver(&mv88e6352_switch_driver
);
2730 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2731 register_switch_driver(&mv88e6171_switch_driver
);
2735 module_init(mv88e6xxx_init
);
2737 static void __exit
mv88e6xxx_cleanup(void)
2739 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2740 unregister_switch_driver(&mv88e6171_switch_driver
);
2742 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2743 unregister_switch_driver(&mv88e6352_switch_driver
);
2745 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2746 unregister_switch_driver(&mv88e6123_61_65_switch_driver
);
2748 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2749 unregister_switch_driver(&mv88e6131_switch_driver
);
2752 module_exit(mv88e6xxx_cleanup
);
2754 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2755 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2756 MODULE_LICENSE("GPL");