2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct mv88e6xxx_priv_state
*ps
)
30 if (unlikely(!mutex_is_locked(&ps
->smi_mutex
))) {
31 dev_err(ps
->dev
, "SMI lock not held!\n");
36 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
37 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
38 * will be directly accessible on some {device address,register address}
39 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
40 * will only respond to SMI transactions to that specific address, and
41 * an indirect addressing mechanism needs to be used to access its
44 static int mv88e6xxx_reg_wait_ready(struct mii_bus
*bus
, int sw_addr
)
49 for (i
= 0; i
< 16; i
++) {
50 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_CMD
);
54 if ((ret
& SMI_CMD_BUSY
) == 0)
61 static int __mv88e6xxx_reg_read(struct mii_bus
*bus
, int sw_addr
, int addr
,
67 return mdiobus_read_nested(bus
, addr
, reg
);
69 /* Wait for the bus to become free. */
70 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
74 /* Transmit the read command. */
75 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
76 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
80 /* Wait for the read command to complete. */
81 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
86 ret
= mdiobus_read_nested(bus
, sw_addr
, SMI_DATA
);
93 static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state
*ps
,
100 ret
= __mv88e6xxx_reg_read(ps
->bus
, ps
->sw_addr
, addr
, reg
);
104 dev_dbg(ps
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state
*ps
, int addr
, int reg
)
114 mutex_lock(&ps
->smi_mutex
);
115 ret
= _mv88e6xxx_reg_read(ps
, addr
, reg
);
116 mutex_unlock(&ps
->smi_mutex
);
121 static int __mv88e6xxx_reg_write(struct mii_bus
*bus
, int sw_addr
, int addr
,
127 return mdiobus_write_nested(bus
, addr
, reg
, val
);
129 /* Wait for the bus to become free. */
130 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
134 /* Transmit the data to write. */
135 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_DATA
, val
);
139 /* Transmit the write command. */
140 ret
= mdiobus_write_nested(bus
, sw_addr
, SMI_CMD
,
141 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
145 /* Wait for the write command to complete. */
146 ret
= mv88e6xxx_reg_wait_ready(bus
, sw_addr
);
153 static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
158 dev_dbg(ps
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
161 return __mv88e6xxx_reg_write(ps
->bus
, ps
->sw_addr
, addr
, reg
, val
);
164 int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
169 mutex_lock(&ps
->smi_mutex
);
170 ret
= _mv88e6xxx_reg_write(ps
, addr
, reg
, val
);
171 mutex_unlock(&ps
->smi_mutex
);
176 static int mv88e6xxx_set_addr_direct(struct dsa_switch
*ds
, u8
*addr
)
178 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
181 err
= mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_01
,
182 (addr
[0] << 8) | addr
[1]);
186 err
= mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_23
,
187 (addr
[2] << 8) | addr
[3]);
191 return mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_MAC_45
,
192 (addr
[4] << 8) | addr
[5]);
195 static int mv88e6xxx_set_addr_indirect(struct dsa_switch
*ds
, u8
*addr
)
197 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
201 for (i
= 0; i
< 6; i
++) {
204 /* Write the MAC address byte. */
205 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SWITCH_MAC
,
206 GLOBAL2_SWITCH_MAC_BUSY
|
211 /* Wait for the write to complete. */
212 for (j
= 0; j
< 16; j
++) {
213 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
,
218 if ((ret
& GLOBAL2_SWITCH_MAC_BUSY
) == 0)
228 int mv88e6xxx_set_addr(struct dsa_switch
*ds
, u8
*addr
)
230 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
232 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SWITCH_MAC
))
233 return mv88e6xxx_set_addr_indirect(ds
, addr
);
235 return mv88e6xxx_set_addr_direct(ds
, addr
);
238 static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state
*ps
, int addr
,
242 return _mv88e6xxx_reg_read(ps
, addr
, regnum
);
246 static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state
*ps
, int addr
,
250 return _mv88e6xxx_reg_write(ps
, addr
, regnum
, val
);
254 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state
*ps
)
257 unsigned long timeout
;
259 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_CONTROL
);
263 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL
,
264 ret
& ~GLOBAL_CONTROL_PPU_ENABLE
);
268 timeout
= jiffies
+ 1 * HZ
;
269 while (time_before(jiffies
, timeout
)) {
270 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATUS
);
274 usleep_range(1000, 2000);
275 if ((ret
& GLOBAL_STATUS_PPU_MASK
) !=
276 GLOBAL_STATUS_PPU_POLLING
)
283 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state
*ps
)
286 unsigned long timeout
;
288 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_CONTROL
);
292 err
= mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_CONTROL
,
293 ret
| GLOBAL_CONTROL_PPU_ENABLE
);
297 timeout
= jiffies
+ 1 * HZ
;
298 while (time_before(jiffies
, timeout
)) {
299 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATUS
);
303 usleep_range(1000, 2000);
304 if ((ret
& GLOBAL_STATUS_PPU_MASK
) ==
305 GLOBAL_STATUS_PPU_POLLING
)
312 static void mv88e6xxx_ppu_reenable_work(struct work_struct
*ugly
)
314 struct mv88e6xxx_priv_state
*ps
;
316 ps
= container_of(ugly
, struct mv88e6xxx_priv_state
, ppu_work
);
317 if (mutex_trylock(&ps
->ppu_mutex
)) {
318 if (mv88e6xxx_ppu_enable(ps
) == 0)
319 ps
->ppu_disabled
= 0;
320 mutex_unlock(&ps
->ppu_mutex
);
324 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps
)
326 struct mv88e6xxx_priv_state
*ps
= (void *)_ps
;
328 schedule_work(&ps
->ppu_work
);
331 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state
*ps
)
335 mutex_lock(&ps
->ppu_mutex
);
337 /* If the PHY polling unit is enabled, disable it so that
338 * we can access the PHY registers. If it was already
339 * disabled, cancel the timer that is going to re-enable
342 if (!ps
->ppu_disabled
) {
343 ret
= mv88e6xxx_ppu_disable(ps
);
345 mutex_unlock(&ps
->ppu_mutex
);
348 ps
->ppu_disabled
= 1;
350 del_timer(&ps
->ppu_timer
);
357 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state
*ps
)
359 /* Schedule a timer to re-enable the PHY polling unit. */
360 mod_timer(&ps
->ppu_timer
, jiffies
+ msecs_to_jiffies(10));
361 mutex_unlock(&ps
->ppu_mutex
);
364 void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state
*ps
)
366 mutex_init(&ps
->ppu_mutex
);
367 INIT_WORK(&ps
->ppu_work
, mv88e6xxx_ppu_reenable_work
);
368 init_timer(&ps
->ppu_timer
);
369 ps
->ppu_timer
.data
= (unsigned long)ps
;
370 ps
->ppu_timer
.function
= mv88e6xxx_ppu_reenable_timer
;
373 static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state
*ps
, int addr
,
378 ret
= mv88e6xxx_ppu_access_get(ps
);
380 ret
= _mv88e6xxx_reg_read(ps
, addr
, regnum
);
381 mv88e6xxx_ppu_access_put(ps
);
387 static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state
*ps
, int addr
,
392 ret
= mv88e6xxx_ppu_access_get(ps
);
394 ret
= _mv88e6xxx_reg_write(ps
, addr
, regnum
, val
);
395 mv88e6xxx_ppu_access_put(ps
);
401 static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state
*ps
)
403 return ps
->info
->family
== MV88E6XXX_FAMILY_6065
;
406 static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state
*ps
)
408 return ps
->info
->family
== MV88E6XXX_FAMILY_6095
;
411 static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state
*ps
)
413 return ps
->info
->family
== MV88E6XXX_FAMILY_6097
;
416 static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state
*ps
)
418 return ps
->info
->family
== MV88E6XXX_FAMILY_6165
;
421 static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state
*ps
)
423 return ps
->info
->family
== MV88E6XXX_FAMILY_6185
;
426 static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state
*ps
)
428 return ps
->info
->family
== MV88E6XXX_FAMILY_6320
;
431 static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state
*ps
)
433 return ps
->info
->family
== MV88E6XXX_FAMILY_6351
;
436 static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state
*ps
)
438 return ps
->info
->family
== MV88E6XXX_FAMILY_6352
;
441 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state
*ps
)
443 return ps
->info
->num_databases
;
446 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state
*ps
)
448 /* Does the device have dedicated FID registers for ATU and VTU ops? */
449 if (mv88e6xxx_6097_family(ps
) || mv88e6xxx_6165_family(ps
) ||
450 mv88e6xxx_6351_family(ps
) || mv88e6xxx_6352_family(ps
))
456 static bool mv88e6xxx_has_stu(struct mv88e6xxx_priv_state
*ps
)
458 /* Does the device have STU and dedicated SID registers for VTU ops? */
459 if (mv88e6xxx_6097_family(ps
) || mv88e6xxx_6165_family(ps
) ||
460 mv88e6xxx_6351_family(ps
) || mv88e6xxx_6352_family(ps
))
466 /* We expect the switch to perform auto negotiation if there is a real
467 * phy. However, in the case of a fixed link phy, we force the port
468 * settings from the fixed link settings.
470 void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
471 struct phy_device
*phydev
)
473 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
477 if (!phy_is_pseudo_fixed_link(phydev
))
480 mutex_lock(&ps
->smi_mutex
);
482 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_PCS_CTRL
);
486 reg
= ret
& ~(PORT_PCS_CTRL_LINK_UP
|
487 PORT_PCS_CTRL_FORCE_LINK
|
488 PORT_PCS_CTRL_DUPLEX_FULL
|
489 PORT_PCS_CTRL_FORCE_DUPLEX
|
490 PORT_PCS_CTRL_UNFORCED
);
492 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
494 reg
|= PORT_PCS_CTRL_LINK_UP
;
496 if (mv88e6xxx_6065_family(ps
) && phydev
->speed
> SPEED_100
)
499 switch (phydev
->speed
) {
501 reg
|= PORT_PCS_CTRL_1000
;
504 reg
|= PORT_PCS_CTRL_100
;
507 reg
|= PORT_PCS_CTRL_10
;
510 pr_info("Unknown speed");
514 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
515 if (phydev
->duplex
== DUPLEX_FULL
)
516 reg
|= PORT_PCS_CTRL_DUPLEX_FULL
;
518 if ((mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
)) &&
519 (port
>= ps
->info
->num_ports
- 2)) {
520 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
521 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
522 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
523 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
524 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
525 reg
|= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
526 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
528 _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_PCS_CTRL
, reg
);
531 mutex_unlock(&ps
->smi_mutex
);
534 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state
*ps
)
539 for (i
= 0; i
< 10; i
++) {
540 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
);
541 if ((ret
& GLOBAL_STATS_OP_BUSY
) == 0)
548 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state
*ps
,
553 if (mv88e6xxx_6320_family(ps
) || mv88e6xxx_6352_family(ps
))
554 port
= (port
+ 1) << 5;
556 /* Snapshot the hardware statistics counters for this port. */
557 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
558 GLOBAL_STATS_OP_CAPTURE_PORT
|
559 GLOBAL_STATS_OP_HIST_RX_TX
| port
);
563 /* Wait for the snapshotting to complete. */
564 ret
= _mv88e6xxx_stats_wait(ps
);
571 static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state
*ps
,
579 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
580 GLOBAL_STATS_OP_READ_CAPTURED
|
581 GLOBAL_STATS_OP_HIST_RX_TX
| stat
);
585 ret
= _mv88e6xxx_stats_wait(ps
);
589 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_32
);
595 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_01
);
602 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
603 { "in_good_octets", 8, 0x00, BANK0
, },
604 { "in_bad_octets", 4, 0x02, BANK0
, },
605 { "in_unicast", 4, 0x04, BANK0
, },
606 { "in_broadcasts", 4, 0x06, BANK0
, },
607 { "in_multicasts", 4, 0x07, BANK0
, },
608 { "in_pause", 4, 0x16, BANK0
, },
609 { "in_undersize", 4, 0x18, BANK0
, },
610 { "in_fragments", 4, 0x19, BANK0
, },
611 { "in_oversize", 4, 0x1a, BANK0
, },
612 { "in_jabber", 4, 0x1b, BANK0
, },
613 { "in_rx_error", 4, 0x1c, BANK0
, },
614 { "in_fcs_error", 4, 0x1d, BANK0
, },
615 { "out_octets", 8, 0x0e, BANK0
, },
616 { "out_unicast", 4, 0x10, BANK0
, },
617 { "out_broadcasts", 4, 0x13, BANK0
, },
618 { "out_multicasts", 4, 0x12, BANK0
, },
619 { "out_pause", 4, 0x15, BANK0
, },
620 { "excessive", 4, 0x11, BANK0
, },
621 { "collisions", 4, 0x1e, BANK0
, },
622 { "deferred", 4, 0x05, BANK0
, },
623 { "single", 4, 0x14, BANK0
, },
624 { "multiple", 4, 0x17, BANK0
, },
625 { "out_fcs_error", 4, 0x03, BANK0
, },
626 { "late", 4, 0x1f, BANK0
, },
627 { "hist_64bytes", 4, 0x08, BANK0
, },
628 { "hist_65_127bytes", 4, 0x09, BANK0
, },
629 { "hist_128_255bytes", 4, 0x0a, BANK0
, },
630 { "hist_256_511bytes", 4, 0x0b, BANK0
, },
631 { "hist_512_1023bytes", 4, 0x0c, BANK0
, },
632 { "hist_1024_max_bytes", 4, 0x0d, BANK0
, },
633 { "sw_in_discards", 4, 0x10, PORT
, },
634 { "sw_in_filtered", 2, 0x12, PORT
, },
635 { "sw_out_filtered", 2, 0x13, PORT
, },
636 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
637 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
638 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
639 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
640 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
641 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
642 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
643 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
644 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
645 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
646 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
647 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
648 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
649 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
650 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
651 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
652 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
653 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
654 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
655 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
656 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
657 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
658 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
659 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
660 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
661 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
664 static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state
*ps
,
665 struct mv88e6xxx_hw_stat
*stat
)
667 switch (stat
->type
) {
671 return mv88e6xxx_6320_family(ps
);
673 return mv88e6xxx_6095_family(ps
) ||
674 mv88e6xxx_6185_family(ps
) ||
675 mv88e6xxx_6097_family(ps
) ||
676 mv88e6xxx_6165_family(ps
) ||
677 mv88e6xxx_6351_family(ps
) ||
678 mv88e6xxx_6352_family(ps
);
683 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state
*ps
,
684 struct mv88e6xxx_hw_stat
*s
,
694 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), s
->reg
);
699 if (s
->sizeof_stat
== 4) {
700 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
),
709 _mv88e6xxx_stats_read(ps
, s
->reg
, &low
);
710 if (s
->sizeof_stat
== 8)
711 _mv88e6xxx_stats_read(ps
, s
->reg
+ 1, &high
);
713 value
= (((u64
)high
) << 16) | low
;
717 void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
719 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
720 struct mv88e6xxx_hw_stat
*stat
;
723 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
724 stat
= &mv88e6xxx_hw_stats
[i
];
725 if (mv88e6xxx_has_stat(ps
, stat
)) {
726 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
733 int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
735 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
736 struct mv88e6xxx_hw_stat
*stat
;
739 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
740 stat
= &mv88e6xxx_hw_stats
[i
];
741 if (mv88e6xxx_has_stat(ps
, stat
))
748 mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
,
749 int port
, uint64_t *data
)
751 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
752 struct mv88e6xxx_hw_stat
*stat
;
756 mutex_lock(&ps
->smi_mutex
);
758 ret
= _mv88e6xxx_stats_snapshot(ps
, port
);
760 mutex_unlock(&ps
->smi_mutex
);
763 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
764 stat
= &mv88e6xxx_hw_stats
[i
];
765 if (mv88e6xxx_has_stat(ps
, stat
)) {
766 data
[j
] = _mv88e6xxx_get_ethtool_stat(ps
, stat
, port
);
771 mutex_unlock(&ps
->smi_mutex
);
774 int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
776 return 32 * sizeof(u16
);
779 void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
780 struct ethtool_regs
*regs
, void *_p
)
782 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
788 memset(p
, 0xff, 32 * sizeof(u16
));
790 for (i
= 0; i
< 32; i
++) {
793 ret
= mv88e6xxx_reg_read(ps
, REG_PORT(port
), i
);
799 static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state
*ps
, int reg
, int offset
,
802 unsigned long timeout
= jiffies
+ HZ
/ 10;
804 while (time_before(jiffies
, timeout
)) {
807 ret
= _mv88e6xxx_reg_read(ps
, reg
, offset
);
813 usleep_range(1000, 2000);
818 static int mv88e6xxx_wait(struct mv88e6xxx_priv_state
*ps
, int reg
,
819 int offset
, u16 mask
)
823 mutex_lock(&ps
->smi_mutex
);
824 ret
= _mv88e6xxx_wait(ps
, reg
, offset
, mask
);
825 mutex_unlock(&ps
->smi_mutex
);
830 static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state
*ps
)
832 return _mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
833 GLOBAL2_SMI_OP_BUSY
);
836 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch
*ds
)
838 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
840 return mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
841 GLOBAL2_EEPROM_OP_LOAD
);
844 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch
*ds
)
846 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
848 return mv88e6xxx_wait(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
849 GLOBAL2_EEPROM_OP_BUSY
);
852 static int mv88e6xxx_read_eeprom_word(struct dsa_switch
*ds
, int addr
)
854 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
857 mutex_lock(&ps
->eeprom_mutex
);
859 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
860 GLOBAL2_EEPROM_OP_READ
|
861 (addr
& GLOBAL2_EEPROM_OP_ADDR_MASK
));
865 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
869 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
);
871 mutex_unlock(&ps
->eeprom_mutex
);
875 int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
, struct ethtool_eeprom
*eeprom
,
878 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
883 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
886 offset
= eeprom
->offset
;
890 eeprom
->magic
= 0xc3ec4951;
892 ret
= mv88e6xxx_eeprom_load_wait(ds
);
899 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
903 *data
++ = (word
>> 8) & 0xff;
913 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
917 *data
++ = word
& 0xff;
918 *data
++ = (word
>> 8) & 0xff;
928 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
932 *data
++ = word
& 0xff;
942 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch
*ds
)
944 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
947 ret
= mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
);
951 if (!(ret
& GLOBAL2_EEPROM_OP_WRITE_EN
))
957 static int mv88e6xxx_write_eeprom_word(struct dsa_switch
*ds
, int addr
,
960 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
963 mutex_lock(&ps
->eeprom_mutex
);
965 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
, data
);
969 ret
= mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_EEPROM_OP
,
970 GLOBAL2_EEPROM_OP_WRITE
|
971 (addr
& GLOBAL2_EEPROM_OP_ADDR_MASK
));
975 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
977 mutex_unlock(&ps
->eeprom_mutex
);
981 int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
, struct ethtool_eeprom
*eeprom
,
984 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
989 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
992 if (eeprom
->magic
!= 0xc3ec4951)
995 ret
= mv88e6xxx_eeprom_is_readonly(ds
);
999 offset
= eeprom
->offset
;
1003 ret
= mv88e6xxx_eeprom_load_wait(ds
);
1010 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
1014 word
= (*data
++ << 8) | (word
& 0xff);
1016 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1029 word
|= *data
++ << 8;
1031 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1043 word
= mv88e6xxx_read_eeprom_word(ds
, offset
>> 1);
1047 word
= (word
& 0xff00) | *data
++;
1049 ret
= mv88e6xxx_write_eeprom_word(ds
, offset
>> 1, word
);
1061 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state
*ps
)
1063 return _mv88e6xxx_wait(ps
, REG_GLOBAL
, GLOBAL_ATU_OP
,
1064 GLOBAL_ATU_OP_BUSY
);
1067 static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state
*ps
,
1068 int addr
, int regnum
)
1072 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
1073 GLOBAL2_SMI_OP_22_READ
| (addr
<< 5) |
1078 ret
= _mv88e6xxx_phy_wait(ps
);
1082 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
);
1087 static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state
*ps
,
1088 int addr
, int regnum
, u16 val
)
1092 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
, val
);
1096 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
1097 GLOBAL2_SMI_OP_22_WRITE
| (addr
<< 5) |
1100 return _mv88e6xxx_phy_wait(ps
);
1103 int mv88e6xxx_get_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1105 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1108 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEE
))
1111 mutex_lock(&ps
->smi_mutex
);
1113 reg
= _mv88e6xxx_phy_read_indirect(ps
, port
, 16);
1117 e
->eee_enabled
= !!(reg
& 0x0200);
1118 e
->tx_lpi_enabled
= !!(reg
& 0x0100);
1120 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_STATUS
);
1124 e
->eee_active
= !!(reg
& PORT_STATUS_EEE
);
1128 mutex_unlock(&ps
->smi_mutex
);
1132 int mv88e6xxx_set_eee(struct dsa_switch
*ds
, int port
,
1133 struct phy_device
*phydev
, struct ethtool_eee
*e
)
1135 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1139 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEE
))
1142 mutex_lock(&ps
->smi_mutex
);
1144 ret
= _mv88e6xxx_phy_read_indirect(ps
, port
, 16);
1148 reg
= ret
& ~0x0300;
1151 if (e
->tx_lpi_enabled
)
1154 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 16, reg
);
1156 mutex_unlock(&ps
->smi_mutex
);
1161 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state
*ps
, u16 fid
, u16 cmd
)
1165 if (mv88e6xxx_has_fid_reg(ps
)) {
1166 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_FID
, fid
);
1169 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1170 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1171 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
);
1175 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
1177 ((fid
<< 8) & 0xf000));
1181 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1185 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_OP
, cmd
);
1189 return _mv88e6xxx_atu_wait(ps
);
1192 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state
*ps
,
1193 struct mv88e6xxx_atu_entry
*entry
)
1195 u16 data
= entry
->state
& GLOBAL_ATU_DATA_STATE_MASK
;
1197 if (entry
->state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
1198 unsigned int mask
, shift
;
1201 data
|= GLOBAL_ATU_DATA_TRUNK
;
1202 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
1203 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
1205 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
1206 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
1209 data
|= (entry
->portv_trunkid
<< shift
) & mask
;
1212 return _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_DATA
, data
);
1215 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state
*ps
,
1216 struct mv88e6xxx_atu_entry
*entry
,
1222 err
= _mv88e6xxx_atu_wait(ps
);
1226 err
= _mv88e6xxx_atu_data_write(ps
, entry
);
1231 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB
:
1232 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB
;
1234 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL
:
1235 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC
;
1238 return _mv88e6xxx_atu_cmd(ps
, entry
->fid
, op
);
1241 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state
*ps
,
1242 u16 fid
, bool static_too
)
1244 struct mv88e6xxx_atu_entry entry
= {
1246 .state
= 0, /* EntryState bits must be 0 */
1249 return _mv88e6xxx_atu_flush_move(ps
, &entry
, static_too
);
1252 static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
1253 int from_port
, int to_port
, bool static_too
)
1255 struct mv88e6xxx_atu_entry entry
= {
1260 /* EntryState bits must be 0xF */
1261 entry
.state
= GLOBAL_ATU_DATA_STATE_MASK
;
1263 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1264 entry
.portv_trunkid
= (to_port
& 0x0f) << 4;
1265 entry
.portv_trunkid
|= from_port
& 0x0f;
1267 return _mv88e6xxx_atu_flush_move(ps
, &entry
, static_too
);
1270 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
1271 int port
, bool static_too
)
1273 /* Destination port 0xF means remove the entries */
1274 return _mv88e6xxx_atu_move(ps
, fid
, port
, 0x0f, static_too
);
1277 static const char * const mv88e6xxx_port_state_names
[] = {
1278 [PORT_CONTROL_STATE_DISABLED
] = "Disabled",
1279 [PORT_CONTROL_STATE_BLOCKING
] = "Blocking/Listening",
1280 [PORT_CONTROL_STATE_LEARNING
] = "Learning",
1281 [PORT_CONTROL_STATE_FORWARDING
] = "Forwarding",
1284 static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state
*ps
, int port
,
1287 struct dsa_switch
*ds
= ps
->ds
;
1291 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL
);
1295 oldstate
= reg
& PORT_CONTROL_STATE_MASK
;
1297 if (oldstate
!= state
) {
1298 /* Flush forwarding database if we're moving a port
1299 * from Learning or Forwarding state to Disabled or
1300 * Blocking or Listening state.
1302 if ((oldstate
== PORT_CONTROL_STATE_LEARNING
||
1303 oldstate
== PORT_CONTROL_STATE_FORWARDING
)
1304 && (state
== PORT_CONTROL_STATE_DISABLED
||
1305 state
== PORT_CONTROL_STATE_BLOCKING
)) {
1306 ret
= _mv88e6xxx_atu_remove(ps
, 0, port
, false);
1311 reg
= (reg
& ~PORT_CONTROL_STATE_MASK
) | state
;
1312 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL
,
1317 netdev_dbg(ds
->ports
[port
], "PortState %s (was %s)\n",
1318 mv88e6xxx_port_state_names
[state
],
1319 mv88e6xxx_port_state_names
[oldstate
]);
1325 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state
*ps
,
1328 struct net_device
*bridge
= ps
->ports
[port
].bridge_dev
;
1329 const u16 mask
= (1 << ps
->info
->num_ports
) - 1;
1330 struct dsa_switch
*ds
= ps
->ds
;
1331 u16 output_ports
= 0;
1335 /* allow CPU port or DSA link(s) to send frames to every port */
1336 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
1337 output_ports
= mask
;
1339 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1340 /* allow sending frames to every group member */
1341 if (bridge
&& ps
->ports
[i
].bridge_dev
== bridge
)
1342 output_ports
|= BIT(i
);
1344 /* allow sending frames to CPU port and DSA link(s) */
1345 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1346 output_ports
|= BIT(i
);
1350 /* prevent frames from going back out of the port they came in on */
1351 output_ports
&= ~BIT(port
);
1353 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_BASE_VLAN
);
1358 reg
|= output_ports
& mask
;
1360 return _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_BASE_VLAN
, reg
);
1363 void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1365 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1369 case BR_STATE_DISABLED
:
1370 stp_state
= PORT_CONTROL_STATE_DISABLED
;
1372 case BR_STATE_BLOCKING
:
1373 case BR_STATE_LISTENING
:
1374 stp_state
= PORT_CONTROL_STATE_BLOCKING
;
1376 case BR_STATE_LEARNING
:
1377 stp_state
= PORT_CONTROL_STATE_LEARNING
;
1379 case BR_STATE_FORWARDING
:
1381 stp_state
= PORT_CONTROL_STATE_FORWARDING
;
1385 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
1386 * so we can not update the port state directly but need to schedule it.
1388 ps
->ports
[port
].state
= stp_state
;
1389 set_bit(port
, ps
->port_state_update_mask
);
1390 schedule_work(&ps
->bridge_work
);
1393 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state
*ps
, int port
,
1396 struct dsa_switch
*ds
= ps
->ds
;
1400 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1404 pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1407 ret
&= ~PORT_DEFAULT_VLAN_MASK
;
1408 ret
|= *new & PORT_DEFAULT_VLAN_MASK
;
1410 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
1411 PORT_DEFAULT_VLAN
, ret
);
1415 netdev_dbg(ds
->ports
[port
], "DefaultVID %d (was %d)\n", *new,
1425 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state
*ps
,
1426 int port
, u16
*pvid
)
1428 return _mv88e6xxx_port_pvid(ps
, port
, NULL
, pvid
);
1431 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state
*ps
,
1434 return _mv88e6xxx_port_pvid(ps
, port
, &pvid
, NULL
);
1437 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state
*ps
)
1439 return _mv88e6xxx_wait(ps
, REG_GLOBAL
, GLOBAL_VTU_OP
,
1440 GLOBAL_VTU_OP_BUSY
);
1443 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state
*ps
, u16 op
)
1447 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_OP
, op
);
1451 return _mv88e6xxx_vtu_wait(ps
);
1454 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state
*ps
)
1458 ret
= _mv88e6xxx_vtu_wait(ps
);
1462 return _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_FLUSH_ALL
);
1465 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state
*ps
,
1466 struct mv88e6xxx_vtu_stu_entry
*entry
,
1467 unsigned int nibble_offset
)
1473 for (i
= 0; i
< 3; ++i
) {
1474 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1475 GLOBAL_VTU_DATA_0_3
+ i
);
1482 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1483 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1484 u16 reg
= regs
[i
/ 4];
1486 entry
->data
[i
] = (reg
>> shift
) & GLOBAL_VTU_STU_DATA_MASK
;
1492 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state
*ps
,
1493 struct mv88e6xxx_vtu_stu_entry
*entry
,
1494 unsigned int nibble_offset
)
1496 u16 regs
[3] = { 0 };
1500 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1501 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1502 u8 data
= entry
->data
[i
];
1504 regs
[i
/ 4] |= (data
& GLOBAL_VTU_STU_DATA_MASK
) << shift
;
1507 for (i
= 0; i
< 3; ++i
) {
1508 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
,
1509 GLOBAL_VTU_DATA_0_3
+ i
, regs
[i
]);
1517 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state
*ps
, u16 vid
)
1519 return _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
,
1520 vid
& GLOBAL_VTU_VID_MASK
);
1523 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state
*ps
,
1524 struct mv88e6xxx_vtu_stu_entry
*entry
)
1526 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1529 ret
= _mv88e6xxx_vtu_wait(ps
);
1533 ret
= _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_VTU_GET_NEXT
);
1537 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1541 next
.vid
= ret
& GLOBAL_VTU_VID_MASK
;
1542 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1545 ret
= _mv88e6xxx_vtu_stu_data_read(ps
, &next
, 0);
1549 if (mv88e6xxx_has_fid_reg(ps
)) {
1550 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1555 next
.fid
= ret
& GLOBAL_VTU_FID_MASK
;
1556 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1557 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1558 * VTU DBNum[3:0] are located in VTU Operation 3:0
1560 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1565 next
.fid
= (ret
& 0xf00) >> 4;
1566 next
.fid
|= ret
& 0xf;
1569 if (mv88e6xxx_has_stu(ps
)) {
1570 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
1575 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1583 int mv88e6xxx_port_vlan_dump(struct dsa_switch
*ds
, int port
,
1584 struct switchdev_obj_port_vlan
*vlan
,
1585 int (*cb
)(struct switchdev_obj
*obj
))
1587 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1588 struct mv88e6xxx_vtu_stu_entry next
;
1592 mutex_lock(&ps
->smi_mutex
);
1594 err
= _mv88e6xxx_port_pvid_get(ps
, port
, &pvid
);
1598 err
= _mv88e6xxx_vtu_vid_write(ps
, GLOBAL_VTU_VID_MASK
);
1603 err
= _mv88e6xxx_vtu_getnext(ps
, &next
);
1610 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1613 /* reinit and dump this VLAN obj */
1614 vlan
->vid_begin
= vlan
->vid_end
= next
.vid
;
1617 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1618 vlan
->flags
|= BRIDGE_VLAN_INFO_UNTAGGED
;
1620 if (next
.vid
== pvid
)
1621 vlan
->flags
|= BRIDGE_VLAN_INFO_PVID
;
1623 err
= cb(&vlan
->obj
);
1626 } while (next
.vid
< GLOBAL_VTU_VID_MASK
);
1629 mutex_unlock(&ps
->smi_mutex
);
1634 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state
*ps
,
1635 struct mv88e6xxx_vtu_stu_entry
*entry
)
1637 u16 op
= GLOBAL_VTU_OP_VTU_LOAD_PURGE
;
1641 ret
= _mv88e6xxx_vtu_wait(ps
);
1648 /* Write port member tags */
1649 ret
= _mv88e6xxx_vtu_stu_data_write(ps
, entry
, 0);
1653 if (mv88e6xxx_has_stu(ps
)) {
1654 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1655 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1660 if (mv88e6xxx_has_fid_reg(ps
)) {
1661 reg
= entry
->fid
& GLOBAL_VTU_FID_MASK
;
1662 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_FID
, reg
);
1665 } else if (mv88e6xxx_num_databases(ps
) == 256) {
1666 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1667 * VTU DBNum[3:0] are located in VTU Operation 3:0
1669 op
|= (entry
->fid
& 0xf0) << 8;
1670 op
|= entry
->fid
& 0xf;
1673 reg
= GLOBAL_VTU_VID_VALID
;
1675 reg
|= entry
->vid
& GLOBAL_VTU_VID_MASK
;
1676 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1680 return _mv88e6xxx_vtu_cmd(ps
, op
);
1683 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state
*ps
, u8 sid
,
1684 struct mv88e6xxx_vtu_stu_entry
*entry
)
1686 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1689 ret
= _mv88e6xxx_vtu_wait(ps
);
1693 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1694 sid
& GLOBAL_VTU_SID_MASK
);
1698 ret
= _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_STU_GET_NEXT
);
1702 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
);
1706 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1708 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1712 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1715 ret
= _mv88e6xxx_vtu_stu_data_read(ps
, &next
, 2);
1724 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state
*ps
,
1725 struct mv88e6xxx_vtu_stu_entry
*entry
)
1730 ret
= _mv88e6xxx_vtu_wait(ps
);
1737 /* Write port states */
1738 ret
= _mv88e6xxx_vtu_stu_data_write(ps
, entry
, 2);
1742 reg
= GLOBAL_VTU_VID_VALID
;
1744 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1748 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1749 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1753 return _mv88e6xxx_vtu_cmd(ps
, GLOBAL_VTU_OP_STU_LOAD_PURGE
);
1756 static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state
*ps
, int port
,
1759 struct dsa_switch
*ds
= ps
->ds
;
1764 if (mv88e6xxx_num_databases(ps
) == 4096)
1766 else if (mv88e6xxx_num_databases(ps
) == 256)
1771 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1772 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_BASE_VLAN
);
1776 fid
= (ret
& PORT_BASE_VLAN_FID_3_0_MASK
) >> 12;
1779 ret
&= ~PORT_BASE_VLAN_FID_3_0_MASK
;
1780 ret
|= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK
;
1782 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_BASE_VLAN
,
1788 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1789 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL_1
);
1793 fid
|= (ret
& upper_mask
) << 4;
1797 ret
|= (*new >> 4) & upper_mask
;
1799 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_1
,
1804 netdev_dbg(ds
->ports
[port
], "FID %d (was %d)\n", *new, fid
);
1813 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state
*ps
,
1816 return _mv88e6xxx_port_fid(ps
, port
, NULL
, fid
);
1819 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state
*ps
,
1822 return _mv88e6xxx_port_fid(ps
, port
, &fid
, NULL
);
1825 static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state
*ps
, u16
*fid
)
1827 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1828 struct mv88e6xxx_vtu_stu_entry vlan
;
1831 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1833 /* Set every FID bit used by the (un)bridged ports */
1834 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1835 err
= _mv88e6xxx_port_fid_get(ps
, i
, fid
);
1839 set_bit(*fid
, fid_bitmap
);
1842 /* Set every FID bit used by the VLAN entries */
1843 err
= _mv88e6xxx_vtu_vid_write(ps
, GLOBAL_VTU_VID_MASK
);
1848 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
1855 set_bit(vlan
.fid
, fid_bitmap
);
1856 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
1858 /* The reset value 0x000 is used to indicate that multiple address
1859 * databases are not needed. Return the next positive available.
1861 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1862 if (unlikely(*fid
>= mv88e6xxx_num_databases(ps
)))
1865 /* Clear the database */
1866 return _mv88e6xxx_atu_flush(ps
, *fid
, true);
1869 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state
*ps
, u16 vid
,
1870 struct mv88e6xxx_vtu_stu_entry
*entry
)
1872 struct dsa_switch
*ds
= ps
->ds
;
1873 struct mv88e6xxx_vtu_stu_entry vlan
= {
1879 err
= _mv88e6xxx_fid_new(ps
, &vlan
.fid
);
1883 /* exclude all ports except the CPU and DSA ports */
1884 for (i
= 0; i
< ps
->info
->num_ports
; ++i
)
1885 vlan
.data
[i
] = dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
)
1886 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1887 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1889 if (mv88e6xxx_6097_family(ps
) || mv88e6xxx_6165_family(ps
) ||
1890 mv88e6xxx_6351_family(ps
) || mv88e6xxx_6352_family(ps
)) {
1891 struct mv88e6xxx_vtu_stu_entry vstp
;
1893 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1894 * implemented, only one STU entry is needed to cover all VTU
1895 * entries. Thus, validate the SID 0.
1898 err
= _mv88e6xxx_stu_getnext(ps
, GLOBAL_VTU_SID_MASK
, &vstp
);
1902 if (vstp
.sid
!= vlan
.sid
|| !vstp
.valid
) {
1903 memset(&vstp
, 0, sizeof(vstp
));
1905 vstp
.sid
= vlan
.sid
;
1907 err
= _mv88e6xxx_stu_loadpurge(ps
, &vstp
);
1917 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state
*ps
, u16 vid
,
1918 struct mv88e6xxx_vtu_stu_entry
*entry
, bool creat
)
1925 err
= _mv88e6xxx_vtu_vid_write(ps
, vid
- 1);
1929 err
= _mv88e6xxx_vtu_getnext(ps
, entry
);
1933 if (entry
->vid
!= vid
|| !entry
->valid
) {
1936 /* -ENOENT would've been more appropriate, but switchdev expects
1937 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1940 err
= _mv88e6xxx_vtu_new(ps
, vid
, entry
);
1946 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1947 u16 vid_begin
, u16 vid_end
)
1949 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
1950 struct mv88e6xxx_vtu_stu_entry vlan
;
1956 mutex_lock(&ps
->smi_mutex
);
1958 err
= _mv88e6xxx_vtu_vid_write(ps
, vid_begin
- 1);
1963 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
1970 if (vlan
.vid
> vid_end
)
1973 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
1974 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1978 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1981 if (ps
->ports
[i
].bridge_dev
==
1982 ps
->ports
[port
].bridge_dev
)
1983 break; /* same bridge, check next VLAN */
1985 netdev_warn(ds
->ports
[port
],
1986 "hardware VLAN %d already used by %s\n",
1988 netdev_name(ps
->ports
[i
].bridge_dev
));
1992 } while (vlan
.vid
< vid_end
);
1995 mutex_unlock(&ps
->smi_mutex
);
2000 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
2001 [PORT_CONTROL_2_8021Q_DISABLED
] = "Disabled",
2002 [PORT_CONTROL_2_8021Q_FALLBACK
] = "Fallback",
2003 [PORT_CONTROL_2_8021Q_CHECK
] = "Check",
2004 [PORT_CONTROL_2_8021Q_SECURE
] = "Secure",
2007 int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
2008 bool vlan_filtering
)
2010 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2011 u16 old
, new = vlan_filtering
? PORT_CONTROL_2_8021Q_SECURE
:
2012 PORT_CONTROL_2_8021Q_DISABLED
;
2015 mutex_lock(&ps
->smi_mutex
);
2017 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_CONTROL_2
);
2021 old
= ret
& PORT_CONTROL_2_8021Q_MASK
;
2024 ret
&= ~PORT_CONTROL_2_8021Q_MASK
;
2025 ret
|= new & PORT_CONTROL_2_8021Q_MASK
;
2027 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_2
,
2032 netdev_dbg(ds
->ports
[port
], "802.1Q Mode %s (was %s)\n",
2033 mv88e6xxx_port_8021q_mode_names
[new],
2034 mv88e6xxx_port_8021q_mode_names
[old
]);
2039 mutex_unlock(&ps
->smi_mutex
);
2044 int mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
2045 const struct switchdev_obj_port_vlan
*vlan
,
2046 struct switchdev_trans
*trans
)
2050 /* If the requested port doesn't belong to the same bridge as the VLAN
2051 * members, do not support it (yet) and fallback to software VLAN.
2053 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
2058 /* We don't need any dynamic resource from the kernel (yet),
2059 * so skip the prepare phase.
2064 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state
*ps
, int port
,
2065 u16 vid
, bool untagged
)
2067 struct mv88e6xxx_vtu_stu_entry vlan
;
2070 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, true);
2074 vlan
.data
[port
] = untagged
?
2075 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
:
2076 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
;
2078 return _mv88e6xxx_vtu_loadpurge(ps
, &vlan
);
2081 void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
2082 const struct switchdev_obj_port_vlan
*vlan
,
2083 struct switchdev_trans
*trans
)
2085 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2086 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
2087 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
2090 mutex_lock(&ps
->smi_mutex
);
2092 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
2093 if (_mv88e6xxx_port_vlan_add(ps
, port
, vid
, untagged
))
2094 netdev_err(ds
->ports
[port
], "failed to add VLAN %d%c\n",
2095 vid
, untagged
? 'u' : 't');
2097 if (pvid
&& _mv88e6xxx_port_pvid_set(ps
, port
, vlan
->vid_end
))
2098 netdev_err(ds
->ports
[port
], "failed to set PVID %d\n",
2101 mutex_unlock(&ps
->smi_mutex
);
2104 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state
*ps
,
2107 struct dsa_switch
*ds
= ps
->ds
;
2108 struct mv88e6xxx_vtu_stu_entry vlan
;
2111 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, false);
2115 /* Tell switchdev if this VLAN is handled in software */
2116 if (vlan
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
2119 vlan
.data
[port
] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
2121 /* keep the VLAN unless all ports are excluded */
2123 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
2124 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
2127 if (vlan
.data
[i
] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
2133 err
= _mv88e6xxx_vtu_loadpurge(ps
, &vlan
);
2137 return _mv88e6xxx_atu_remove(ps
, vlan
.fid
, port
, false);
2140 int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
2141 const struct switchdev_obj_port_vlan
*vlan
)
2143 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2147 mutex_lock(&ps
->smi_mutex
);
2149 err
= _mv88e6xxx_port_pvid_get(ps
, port
, &pvid
);
2153 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
2154 err
= _mv88e6xxx_port_vlan_del(ps
, port
, vid
);
2159 err
= _mv88e6xxx_port_pvid_set(ps
, port
, 0);
2166 mutex_unlock(&ps
->smi_mutex
);
2171 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state
*ps
,
2172 const unsigned char *addr
)
2176 for (i
= 0; i
< 3; i
++) {
2177 ret
= _mv88e6xxx_reg_write(
2178 ps
, REG_GLOBAL
, GLOBAL_ATU_MAC_01
+ i
,
2179 (addr
[i
* 2] << 8) | addr
[i
* 2 + 1]);
2187 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state
*ps
,
2188 unsigned char *addr
)
2192 for (i
= 0; i
< 3; i
++) {
2193 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
,
2194 GLOBAL_ATU_MAC_01
+ i
);
2197 addr
[i
* 2] = ret
>> 8;
2198 addr
[i
* 2 + 1] = ret
& 0xff;
2204 static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state
*ps
,
2205 struct mv88e6xxx_atu_entry
*entry
)
2209 ret
= _mv88e6xxx_atu_wait(ps
);
2213 ret
= _mv88e6xxx_atu_mac_write(ps
, entry
->mac
);
2217 ret
= _mv88e6xxx_atu_data_write(ps
, entry
);
2221 return _mv88e6xxx_atu_cmd(ps
, entry
->fid
, GLOBAL_ATU_OP_LOAD_DB
);
2224 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state
*ps
, int port
,
2225 const unsigned char *addr
, u16 vid
,
2228 struct mv88e6xxx_atu_entry entry
= { 0 };
2229 struct mv88e6xxx_vtu_stu_entry vlan
;
2232 /* Null VLAN ID corresponds to the port private database */
2234 err
= _mv88e6xxx_port_fid_get(ps
, port
, &vlan
.fid
);
2236 err
= _mv88e6xxx_vtu_get(ps
, vid
, &vlan
, false);
2240 entry
.fid
= vlan
.fid
;
2241 entry
.state
= state
;
2242 ether_addr_copy(entry
.mac
, addr
);
2243 if (state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2244 entry
.trunk
= false;
2245 entry
.portv_trunkid
= BIT(port
);
2248 return _mv88e6xxx_atu_load(ps
, &entry
);
2251 int mv88e6xxx_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
2252 const struct switchdev_obj_port_fdb
*fdb
,
2253 struct switchdev_trans
*trans
)
2255 /* We don't need any dynamic resource from the kernel (yet),
2256 * so skip the prepare phase.
2261 void mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
2262 const struct switchdev_obj_port_fdb
*fdb
,
2263 struct switchdev_trans
*trans
)
2265 int state
= is_multicast_ether_addr(fdb
->addr
) ?
2266 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2267 GLOBAL_ATU_DATA_STATE_UC_STATIC
;
2268 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2270 mutex_lock(&ps
->smi_mutex
);
2271 if (_mv88e6xxx_port_fdb_load(ps
, port
, fdb
->addr
, fdb
->vid
, state
))
2272 netdev_err(ds
->ports
[port
], "failed to load MAC address\n");
2273 mutex_unlock(&ps
->smi_mutex
);
2276 int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
2277 const struct switchdev_obj_port_fdb
*fdb
)
2279 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2282 mutex_lock(&ps
->smi_mutex
);
2283 ret
= _mv88e6xxx_port_fdb_load(ps
, port
, fdb
->addr
, fdb
->vid
,
2284 GLOBAL_ATU_DATA_STATE_UNUSED
);
2285 mutex_unlock(&ps
->smi_mutex
);
2290 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state
*ps
, u16 fid
,
2291 struct mv88e6xxx_atu_entry
*entry
)
2293 struct mv88e6xxx_atu_entry next
= { 0 };
2298 ret
= _mv88e6xxx_atu_wait(ps
);
2302 ret
= _mv88e6xxx_atu_cmd(ps
, fid
, GLOBAL_ATU_OP_GET_NEXT_DB
);
2306 ret
= _mv88e6xxx_atu_mac_read(ps
, next
.mac
);
2310 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, GLOBAL_ATU_DATA
);
2314 next
.state
= ret
& GLOBAL_ATU_DATA_STATE_MASK
;
2315 if (next
.state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2316 unsigned int mask
, shift
;
2318 if (ret
& GLOBAL_ATU_DATA_TRUNK
) {
2320 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
2321 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
2324 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
2325 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
2328 next
.portv_trunkid
= (ret
& mask
) >> shift
;
2335 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state
*ps
,
2336 u16 fid
, u16 vid
, int port
,
2337 struct switchdev_obj_port_fdb
*fdb
,
2338 int (*cb
)(struct switchdev_obj
*obj
))
2340 struct mv88e6xxx_atu_entry addr
= {
2341 .mac
= { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2345 err
= _mv88e6xxx_atu_mac_write(ps
, addr
.mac
);
2350 err
= _mv88e6xxx_atu_getnext(ps
, fid
, &addr
);
2354 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UNUSED
)
2357 if (!addr
.trunk
&& addr
.portv_trunkid
& BIT(port
)) {
2358 bool is_static
= addr
.state
==
2359 (is_multicast_ether_addr(addr
.mac
) ?
2360 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2361 GLOBAL_ATU_DATA_STATE_UC_STATIC
);
2364 ether_addr_copy(fdb
->addr
, addr
.mac
);
2365 fdb
->ndm_state
= is_static
? NUD_NOARP
: NUD_REACHABLE
;
2367 err
= cb(&fdb
->obj
);
2371 } while (!is_broadcast_ether_addr(addr
.mac
));
2376 int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
2377 struct switchdev_obj_port_fdb
*fdb
,
2378 int (*cb
)(struct switchdev_obj
*obj
))
2380 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2381 struct mv88e6xxx_vtu_stu_entry vlan
= {
2382 .vid
= GLOBAL_VTU_VID_MASK
, /* all ones */
2387 mutex_lock(&ps
->smi_mutex
);
2389 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2390 err
= _mv88e6xxx_port_fid_get(ps
, port
, &fid
);
2394 err
= _mv88e6xxx_port_fdb_dump_one(ps
, fid
, 0, port
, fdb
, cb
);
2398 /* Dump VLANs' Filtering Information Databases */
2399 err
= _mv88e6xxx_vtu_vid_write(ps
, vlan
.vid
);
2404 err
= _mv88e6xxx_vtu_getnext(ps
, &vlan
);
2411 err
= _mv88e6xxx_port_fdb_dump_one(ps
, vlan
.fid
, vlan
.vid
, port
,
2415 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
2418 mutex_unlock(&ps
->smi_mutex
);
2423 int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
2424 struct net_device
*bridge
)
2426 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2429 mutex_lock(&ps
->smi_mutex
);
2431 /* Assign the bridge and remap each port's VLANTable */
2432 ps
->ports
[port
].bridge_dev
= bridge
;
2434 for (i
= 0; i
< ps
->info
->num_ports
; ++i
) {
2435 if (ps
->ports
[i
].bridge_dev
== bridge
) {
2436 err
= _mv88e6xxx_port_based_vlan_map(ps
, i
);
2442 mutex_unlock(&ps
->smi_mutex
);
2447 void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
)
2449 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2450 struct net_device
*bridge
= ps
->ports
[port
].bridge_dev
;
2453 mutex_lock(&ps
->smi_mutex
);
2455 /* Unassign the bridge and remap each port's VLANTable */
2456 ps
->ports
[port
].bridge_dev
= NULL
;
2458 for (i
= 0; i
< ps
->info
->num_ports
; ++i
)
2459 if (i
== port
|| ps
->ports
[i
].bridge_dev
== bridge
)
2460 if (_mv88e6xxx_port_based_vlan_map(ps
, i
))
2461 netdev_warn(ds
->ports
[i
], "failed to remap\n");
2463 mutex_unlock(&ps
->smi_mutex
);
2466 static void mv88e6xxx_bridge_work(struct work_struct
*work
)
2468 struct mv88e6xxx_priv_state
*ps
;
2469 struct dsa_switch
*ds
;
2472 ps
= container_of(work
, struct mv88e6xxx_priv_state
, bridge_work
);
2475 mutex_lock(&ps
->smi_mutex
);
2477 for (port
= 0; port
< ps
->info
->num_ports
; ++port
)
2478 if (test_and_clear_bit(port
, ps
->port_state_update_mask
) &&
2479 _mv88e6xxx_port_state(ps
, port
, ps
->ports
[port
].state
))
2480 netdev_warn(ds
->ports
[port
],
2481 "failed to update state to %s\n",
2482 mv88e6xxx_port_state_names
[ps
->ports
[port
].state
]);
2484 mutex_unlock(&ps
->smi_mutex
);
2487 static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state
*ps
,
2488 int port
, int page
, int reg
, int val
)
2492 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, page
);
2494 goto restore_page_0
;
2496 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, reg
, val
);
2498 _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, 0x0);
2503 static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state
*ps
,
2504 int port
, int page
, int reg
)
2508 ret
= _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, page
);
2510 goto restore_page_0
;
2512 ret
= _mv88e6xxx_phy_read_indirect(ps
, port
, reg
);
2514 _mv88e6xxx_phy_write_indirect(ps
, port
, 0x16, 0x0);
2519 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state
*ps
)
2523 ret
= _mv88e6xxx_phy_page_read(ps
, REG_FIBER_SERDES
, PAGE_FIBER_SERDES
,
2528 if (ret
& BMCR_PDOWN
) {
2530 ret
= _mv88e6xxx_phy_page_write(ps
, REG_FIBER_SERDES
,
2531 PAGE_FIBER_SERDES
, MII_BMCR
,
2538 static int mv88e6xxx_setup_port(struct dsa_switch
*ds
, int port
)
2540 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2544 mutex_lock(&ps
->smi_mutex
);
2546 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2547 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2548 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
2549 mv88e6xxx_6065_family(ps
) || mv88e6xxx_6320_family(ps
)) {
2550 /* MAC Forcing register: don't force link, speed,
2551 * duplex or flow control state to any particular
2552 * values on physical ports, but force the CPU port
2553 * and all DSA ports to their maximum bandwidth and
2556 reg
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_PCS_CTRL
);
2557 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
2558 reg
&= ~PORT_PCS_CTRL_UNFORCED
;
2559 reg
|= PORT_PCS_CTRL_FORCE_LINK
|
2560 PORT_PCS_CTRL_LINK_UP
|
2561 PORT_PCS_CTRL_DUPLEX_FULL
|
2562 PORT_PCS_CTRL_FORCE_DUPLEX
;
2563 if (mv88e6xxx_6065_family(ps
))
2564 reg
|= PORT_PCS_CTRL_100
;
2566 reg
|= PORT_PCS_CTRL_1000
;
2568 reg
|= PORT_PCS_CTRL_UNFORCED
;
2571 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2572 PORT_PCS_CTRL
, reg
);
2577 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2578 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2579 * tunneling, determine priority by looking at 802.1p and IP
2580 * priority fields (IP prio has precedence), and set STP state
2583 * If this is the CPU link, use DSA or EDSA tagging depending
2584 * on which tagging mode was configured.
2586 * If this is a link to another switch, use DSA tagging mode.
2588 * If this is the upstream port for this switch, enable
2589 * forwarding of unknown unicasts and multicasts.
2592 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2593 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2594 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6065_family(ps
) ||
2595 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6320_family(ps
))
2596 reg
= PORT_CONTROL_IGMP_MLD_SNOOP
|
2597 PORT_CONTROL_USE_TAG
| PORT_CONTROL_USE_IP
|
2598 PORT_CONTROL_STATE_FORWARDING
;
2599 if (dsa_is_cpu_port(ds
, port
)) {
2600 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
))
2601 reg
|= PORT_CONTROL_DSA_TAG
;
2602 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2603 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2604 mv88e6xxx_6320_family(ps
)) {
2605 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2606 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
;
2608 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2609 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2610 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2613 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2614 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2615 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6065_family(ps
) ||
2616 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6320_family(ps
)) {
2617 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
2618 reg
|= PORT_CONTROL_EGRESS_ADD_TAG
;
2621 if (dsa_is_dsa_port(ds
, port
)) {
2622 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
))
2623 reg
|= PORT_CONTROL_DSA_TAG
;
2624 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2625 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2626 mv88e6xxx_6320_family(ps
)) {
2627 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2630 if (port
== dsa_upstream_port(ds
))
2631 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2632 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2635 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2641 /* If this port is connected to a SerDes, make sure the SerDes is not
2644 if (mv88e6xxx_6352_family(ps
)) {
2645 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(port
), PORT_STATUS
);
2648 ret
&= PORT_STATUS_CMODE_MASK
;
2649 if ((ret
== PORT_STATUS_CMODE_100BASE_X
) ||
2650 (ret
== PORT_STATUS_CMODE_1000BASE_X
) ||
2651 (ret
== PORT_STATUS_CMODE_SGMII
)) {
2652 ret
= mv88e6xxx_power_on_serdes(ps
);
2658 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2659 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2660 * untagged frames on this port, do a destination address lookup on all
2661 * received packets as usual, disable ARP mirroring and don't send a
2662 * copy of all transmitted/received frames on this port to the CPU.
2665 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2666 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2667 mv88e6xxx_6095_family(ps
) || mv88e6xxx_6320_family(ps
) ||
2668 mv88e6xxx_6185_family(ps
))
2669 reg
= PORT_CONTROL_2_MAP_DA
;
2671 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2672 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6320_family(ps
))
2673 reg
|= PORT_CONTROL_2_JUMBO_10240
;
2675 if (mv88e6xxx_6095_family(ps
) || mv88e6xxx_6185_family(ps
)) {
2676 /* Set the upstream port this port should use */
2677 reg
|= dsa_upstream_port(ds
);
2678 /* enable forwarding of unknown multicast addresses to
2681 if (port
== dsa_upstream_port(ds
))
2682 reg
|= PORT_CONTROL_2_FORWARD_UNKNOWN
;
2685 reg
|= PORT_CONTROL_2_8021Q_DISABLED
;
2688 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2689 PORT_CONTROL_2
, reg
);
2694 /* Port Association Vector: when learning source addresses
2695 * of packets, add the address to the address database using
2696 * a port bitmap that has only the bit for this port set and
2697 * the other bits clear.
2700 /* Disable learning for CPU port */
2701 if (dsa_is_cpu_port(ds
, port
))
2704 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_ASSOC_VECTOR
, reg
);
2708 /* Egress rate control 2: disable egress rate control. */
2709 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_RATE_CONTROL_2
,
2714 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2715 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2716 mv88e6xxx_6320_family(ps
)) {
2717 /* Do not limit the period of time that this port can
2718 * be paused for by the remote end or the period of
2719 * time that this port can pause the remote end.
2721 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2722 PORT_PAUSE_CTRL
, 0x0000);
2726 /* Port ATU control: disable limiting the number of
2727 * address database entries that this port is allowed
2730 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2731 PORT_ATU_CONTROL
, 0x0000);
2732 /* Priority Override: disable DA, SA and VTU priority
2735 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2736 PORT_PRI_OVERRIDE
, 0x0000);
2740 /* Port Ethertype: use the Ethertype DSA Ethertype
2743 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2744 PORT_ETH_TYPE
, ETH_P_EDSA
);
2747 /* Tag Remap: use an identity 802.1p prio -> switch
2750 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2751 PORT_TAG_REGMAP_0123
, 0x3210);
2755 /* Tag Remap 2: use an identity 802.1p prio -> switch
2758 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2759 PORT_TAG_REGMAP_4567
, 0x7654);
2764 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2765 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2766 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
2767 mv88e6xxx_6320_family(ps
)) {
2768 /* Rate Control: disable ingress rate limiting. */
2769 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
),
2770 PORT_RATE_CONTROL
, 0x0001);
2775 /* Port Control 1: disable trunking, disable sending
2776 * learning messages to this port.
2778 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_CONTROL_1
, 0x0000);
2782 /* Port based VLAN map: give each port the same default address
2783 * database, and allow bidirectional communication between the
2784 * CPU and DSA port(s), and the other ports.
2786 ret
= _mv88e6xxx_port_fid_set(ps
, port
, 0);
2790 ret
= _mv88e6xxx_port_based_vlan_map(ps
, port
);
2794 /* Default VLAN ID and priority: don't set a default VLAN
2795 * ID, and set the default packet priority to zero.
2797 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
2800 mutex_unlock(&ps
->smi_mutex
);
2804 int mv88e6xxx_setup_ports(struct dsa_switch
*ds
)
2806 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2810 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
2811 ret
= mv88e6xxx_setup_port(ds
, i
);
2818 int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state
*ps
)
2820 mutex_init(&ps
->smi_mutex
);
2822 INIT_WORK(&ps
->bridge_work
, mv88e6xxx_bridge_work
);
2824 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_EEPROM
))
2825 mutex_init(&ps
->eeprom_mutex
);
2827 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
2828 mv88e6xxx_ppu_state_init(ps
);
2833 int mv88e6xxx_setup_global(struct dsa_switch
*ds
)
2835 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
2839 mutex_lock(&ps
->smi_mutex
);
2840 /* Set the default address aging time to 5 minutes, and
2841 * enable address learn messages to be sent to all message
2844 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
2845 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL
);
2849 /* Configure the IP ToS mapping registers. */
2850 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_0
, 0x0000);
2853 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_1
, 0x0000);
2856 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_2
, 0x5555);
2859 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_3
, 0x5555);
2862 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_4
, 0xaaaa);
2865 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_5
, 0xaaaa);
2868 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_6
, 0xffff);
2871 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IP_PRI_7
, 0xffff);
2875 /* Configure the IEEE 802.1p priority mapping register. */
2876 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_IEEE_PRI
, 0xfa41);
2880 /* Send all frames with destination addresses matching
2881 * 01:80:c2:00:00:0x to the CPU port.
2883 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_MGMT_EN_0X
, 0xffff);
2887 /* Ignore removed tag data on doubly tagged packets, disable
2888 * flow control messages, force flow control priority to the
2889 * highest, and send all special multicast frames to the CPU
2890 * port at the highest priority.
2892 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_SWITCH_MGMT
,
2893 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU
| 0x70 |
2894 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI
);
2898 /* Program the DSA routing table. */
2899 for (i
= 0; i
< 32; i
++) {
2902 if (ds
->pd
->rtable
&&
2903 i
!= ds
->index
&& i
< ds
->dst
->pd
->nr_chips
)
2904 nexthop
= ds
->pd
->rtable
[i
] & 0x1f;
2906 err
= _mv88e6xxx_reg_write(
2908 GLOBAL2_DEVICE_MAPPING
,
2909 GLOBAL2_DEVICE_MAPPING_UPDATE
|
2910 (i
<< GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT
) | nexthop
);
2915 /* Clear all trunk masks. */
2916 for (i
= 0; i
< 8; i
++) {
2917 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
, GLOBAL2_TRUNK_MASK
,
2919 (i
<< GLOBAL2_TRUNK_MASK_NUM_SHIFT
) |
2920 ((1 << ps
->info
->num_ports
) - 1));
2925 /* Clear all trunk mappings. */
2926 for (i
= 0; i
< 16; i
++) {
2927 err
= _mv88e6xxx_reg_write(
2929 GLOBAL2_TRUNK_MAPPING
,
2930 GLOBAL2_TRUNK_MAPPING_UPDATE
|
2931 (i
<< GLOBAL2_TRUNK_MAPPING_ID_SHIFT
));
2936 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2937 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2938 mv88e6xxx_6320_family(ps
)) {
2939 /* Send all frames with destination addresses matching
2940 * 01:80:c2:00:00:2x to the CPU port.
2942 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
2943 GLOBAL2_MGMT_EN_2X
, 0xffff);
2947 /* Initialise cross-chip port VLAN table to reset
2950 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
2951 GLOBAL2_PVT_ADDR
, 0x9000);
2955 /* Clear the priority override table. */
2956 for (i
= 0; i
< 16; i
++) {
2957 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
2958 GLOBAL2_PRIO_OVERRIDE
,
2965 if (mv88e6xxx_6352_family(ps
) || mv88e6xxx_6351_family(ps
) ||
2966 mv88e6xxx_6165_family(ps
) || mv88e6xxx_6097_family(ps
) ||
2967 mv88e6xxx_6185_family(ps
) || mv88e6xxx_6095_family(ps
) ||
2968 mv88e6xxx_6320_family(ps
)) {
2969 /* Disable ingress rate limiting by resetting all
2970 * ingress rate limit registers to their initial
2973 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
2974 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL2
,
2982 /* Clear the statistics counters for all ports */
2983 err
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, GLOBAL_STATS_OP
,
2984 GLOBAL_STATS_OP_FLUSH_ALL
);
2988 /* Wait for the flush to complete. */
2989 err
= _mv88e6xxx_stats_wait(ps
);
2993 /* Clear all ATU entries */
2994 err
= _mv88e6xxx_atu_flush(ps
, 0, true);
2998 /* Clear all the VTU and STU entries */
2999 err
= _mv88e6xxx_vtu_stu_flush(ps
);
3001 mutex_unlock(&ps
->smi_mutex
);
3006 int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state
*ps
, bool ppu_active
)
3008 u16 is_reset
= (ppu_active
? 0x8800 : 0xc800);
3009 struct gpio_desc
*gpiod
= ps
->ds
->pd
->reset
;
3010 unsigned long timeout
;
3014 mutex_lock(&ps
->smi_mutex
);
3016 /* Set all ports to the disabled state. */
3017 for (i
= 0; i
< ps
->info
->num_ports
; i
++) {
3018 ret
= _mv88e6xxx_reg_read(ps
, REG_PORT(i
), PORT_CONTROL
);
3022 ret
= _mv88e6xxx_reg_write(ps
, REG_PORT(i
), PORT_CONTROL
,
3028 /* Wait for transmit queues to drain. */
3029 usleep_range(2000, 4000);
3031 /* If there is a gpio connected to the reset pin, toggle it */
3033 gpiod_set_value_cansleep(gpiod
, 1);
3034 usleep_range(10000, 20000);
3035 gpiod_set_value_cansleep(gpiod
, 0);
3036 usleep_range(10000, 20000);
3039 /* Reset the switch. Keep the PPU active if requested. The PPU
3040 * needs to be active to support indirect phy register access
3041 * through global registers 0x18 and 0x19.
3044 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, 0x04, 0xc000);
3046 ret
= _mv88e6xxx_reg_write(ps
, REG_GLOBAL
, 0x04, 0xc400);
3050 /* Wait up to one second for reset to complete. */
3051 timeout
= jiffies
+ 1 * HZ
;
3052 while (time_before(jiffies
, timeout
)) {
3053 ret
= _mv88e6xxx_reg_read(ps
, REG_GLOBAL
, 0x00);
3057 if ((ret
& is_reset
) == is_reset
)
3059 usleep_range(1000, 2000);
3061 if (time_after(jiffies
, timeout
))
3066 mutex_unlock(&ps
->smi_mutex
);
3071 int mv88e6xxx_phy_page_read(struct dsa_switch
*ds
, int port
, int page
, int reg
)
3073 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3076 mutex_lock(&ps
->smi_mutex
);
3077 ret
= _mv88e6xxx_phy_page_read(ps
, port
, page
, reg
);
3078 mutex_unlock(&ps
->smi_mutex
);
3083 int mv88e6xxx_phy_page_write(struct dsa_switch
*ds
, int port
, int page
,
3086 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3089 mutex_lock(&ps
->smi_mutex
);
3090 ret
= _mv88e6xxx_phy_page_write(ps
, port
, page
, reg
, val
);
3091 mutex_unlock(&ps
->smi_mutex
);
3096 static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state
*ps
,
3099 if (port
>= 0 && port
< ps
->info
->num_ports
)
3105 mv88e6xxx_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
3107 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3108 int addr
= mv88e6xxx_port_to_phy_addr(ps
, port
);
3114 mutex_lock(&ps
->smi_mutex
);
3116 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
3117 ret
= mv88e6xxx_phy_read_ppu(ps
, addr
, regnum
);
3118 else if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SMI_PHY
))
3119 ret
= _mv88e6xxx_phy_read_indirect(ps
, addr
, regnum
);
3121 ret
= _mv88e6xxx_phy_read(ps
, addr
, regnum
);
3123 mutex_unlock(&ps
->smi_mutex
);
3128 mv88e6xxx_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
3130 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3131 int addr
= mv88e6xxx_port_to_phy_addr(ps
, port
);
3137 mutex_lock(&ps
->smi_mutex
);
3139 if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_PPU
))
3140 ret
= mv88e6xxx_phy_write_ppu(ps
, addr
, regnum
, val
);
3141 else if (mv88e6xxx_has(ps
, MV88E6XXX_FLAG_SMI_PHY
))
3142 ret
= _mv88e6xxx_phy_write_indirect(ps
, addr
, regnum
, val
);
3144 ret
= _mv88e6xxx_phy_write(ps
, addr
, regnum
, val
);
3146 mutex_unlock(&ps
->smi_mutex
);
3150 #ifdef CONFIG_NET_DSA_HWMON
3152 static int mv88e61xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3154 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3160 mutex_lock(&ps
->smi_mutex
);
3162 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x16, 0x6);
3166 /* Enable temperature sensor */
3167 ret
= _mv88e6xxx_phy_read(ps
, 0x0, 0x1a);
3171 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x1a, ret
| (1 << 5));
3175 /* Wait for temperature to stabilize */
3176 usleep_range(10000, 12000);
3178 val
= _mv88e6xxx_phy_read(ps
, 0x0, 0x1a);
3184 /* Disable temperature sensor */
3185 ret
= _mv88e6xxx_phy_write(ps
, 0x0, 0x1a, ret
& ~(1 << 5));
3189 *temp
= ((val
& 0x1f) - 5) * 5;
3192 _mv88e6xxx_phy_write(ps
, 0x0, 0x16, 0x0);
3193 mutex_unlock(&ps
->smi_mutex
);
3197 static int mv88e63xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3199 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3200 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3205 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 27);
3209 *temp
= (ret
& 0xff) - 25;
3214 int mv88e6xxx_get_temp(struct dsa_switch
*ds
, int *temp
)
3216 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3218 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP
))
3221 if (mv88e6xxx_6320_family(ps
) || mv88e6xxx_6352_family(ps
))
3222 return mv88e63xx_get_temp(ds
, temp
);
3224 return mv88e61xx_get_temp(ds
, temp
);
3227 int mv88e6xxx_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
3229 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3230 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3233 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3238 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3242 *temp
= (((ret
>> 8) & 0x1f) * 5) - 25;
3247 int mv88e6xxx_set_temp_limit(struct dsa_switch
*ds
, int temp
)
3249 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3250 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3253 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3256 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3259 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
3260 return mv88e6xxx_phy_page_write(ds
, phy
, 6, 26,
3261 (ret
& 0xe0ff) | (temp
<< 8));
3264 int mv88e6xxx_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
3266 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
3267 int phy
= mv88e6xxx_6320_family(ps
) ? 3 : 0;
3270 if (!mv88e6xxx_has(ps
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3275 ret
= mv88e6xxx_phy_page_read(ds
, phy
, 6, 26);
3279 *alarm
= !!(ret
& 0x40);
3283 #endif /* CONFIG_NET_DSA_HWMON */
3285 static const struct mv88e6xxx_info
*
3286 mv88e6xxx_lookup_info(unsigned int prod_num
, const struct mv88e6xxx_info
*table
,
3291 for (i
= 0; i
< num
; ++i
)
3292 if (table
[i
].prod_num
== prod_num
)
3298 const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
, struct device
*host_dev
,
3299 int sw_addr
, void **priv
,
3300 const struct mv88e6xxx_info
*table
,
3303 const struct mv88e6xxx_info
*info
;
3304 struct mv88e6xxx_priv_state
*ps
;
3305 struct mii_bus
*bus
;
3307 int id
, prod_num
, rev
;
3309 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3313 id
= __mv88e6xxx_reg_read(bus
, sw_addr
, REG_PORT(0), PORT_SWITCH_ID
);
3317 prod_num
= (id
& 0xfff0) >> 4;
3320 info
= mv88e6xxx_lookup_info(prod_num
, table
, num
);
3326 ps
= devm_kzalloc(dsa_dev
, sizeof(*ps
), GFP_KERNEL
);
3331 ps
->sw_addr
= sw_addr
;
3336 dev_info(&ps
->bus
->dev
, "switch 0x%x probed: %s, revision %u\n",
3337 prod_num
, name
, rev
);
3342 static int __init
mv88e6xxx_init(void)
3344 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3345 register_switch_driver(&mv88e6131_switch_driver
);
3347 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3348 register_switch_driver(&mv88e6123_switch_driver
);
3350 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3351 register_switch_driver(&mv88e6352_switch_driver
);
3353 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3354 register_switch_driver(&mv88e6171_switch_driver
);
3358 module_init(mv88e6xxx_init
);
3360 static void __exit
mv88e6xxx_cleanup(void)
3362 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3363 unregister_switch_driver(&mv88e6171_switch_driver
);
3365 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3366 unregister_switch_driver(&mv88e6352_switch_driver
);
3368 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3369 unregister_switch_driver(&mv88e6123_switch_driver
);
3371 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3372 unregister_switch_driver(&mv88e6131_switch_driver
);
3375 module_exit(mv88e6xxx_cleanup
);
3377 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3378 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3379 MODULE_LICENSE("GPL");