drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * Copyright (c) 2015 CMC Electronics, Inc.
   6  *      Added support for VLAN Table Unit operations
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/list.h>
  20 #include <linux/module.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/phy.h>
  23 #include <net/dsa.h>
  24 #include <net/switchdev.h>
  25 #include "mv88e6xxx.h"
  26
  27 static void assert_smi_lock(struct dsa_switch *ds)
  28 {
  29         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  30
  31         if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
  32                 dev_err(ds->master_dev, "SMI lock not held!\n");
  33                 dump_stack();
  34         }
  35 }
  36
  37 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  38  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  39  * will be directly accessible on some {device address,register address}
  40  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  41  * will only respond to SMI transactions to that specific address, and
  42  * an indirect addressing mechanism needs to be used to access its
  43  * registers.
  44  */
  45 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  46 {
  47         int ret;
  48         int i;
  49
  50         for (i = 0; i < 16; i++) {
  51                 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
  52                 if (ret < 0)
  53                         return ret;
  54
  55                 if ((ret & SMI_CMD_BUSY) == 0)
  56                         return 0;
  57         }
  58
  59         return -ETIMEDOUT;
  60 }
  61
  62 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
  63                                 int reg)
  64 {
  65         int ret;
  66
  67         if (sw_addr == 0)
  68                 return mdiobus_read_nested(bus, addr, reg);
  69
  70         /* Wait for the bus to become free. */
  71         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  72         if (ret < 0)
  73                 return ret;
  74
  75         /* Transmit the read command. */
  76         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
  77                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         /* Wait for the read command to complete. */
  82         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  83         if (ret < 0)
  84                 return ret;
  85
  86         /* Read the data. */
  87         ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
  88         if (ret < 0)
  89                 return ret;
  90
  91         return ret & 0xffff;
  92 }
  93
  94 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  95 {
  96         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  97         int ret;
  98
  99         assert_smi_lock(ds);
 100
 101         if (bus == NULL)
 102                 return -EINVAL;
 103
 104         ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
 105         if (ret < 0)
 106                 return ret;
 107
 108         dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 109                 addr, reg, ret);
 110
 111         return ret;
 112 }
 113
 114 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
 115 {
 116         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 117         int ret;
 118
 119         mutex_lock(&ps->smi_mutex);
 120         ret = _mv88e6xxx_reg_read(ds, addr, reg);
 121         mutex_unlock(&ps->smi_mutex);
 122
 123         return ret;
 124 }
 125
 126 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 127                                  int reg, u16 val)
 128 {
 129         int ret;
 130
 131         if (sw_addr == 0)
 132                 return mdiobus_write_nested(bus, addr, reg, val);
 133
 134         /* Wait for the bus to become free. */
 135         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 136         if (ret < 0)
 137                 return ret;
 138
 139         /* Transmit the data to write. */
 140         ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
 141         if (ret < 0)
 142                 return ret;
 143
 144         /* Transmit the write command. */
 145         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
 146                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 147         if (ret < 0)
 148                 return ret;
 149
 150         /* Wait for the write command to complete. */
 151         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 152         if (ret < 0)
 153                 return ret;
 154
 155         return 0;
 156 }
 157
 158 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
 159                                 u16 val)
 160 {
 161         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 162
 163         assert_smi_lock(ds);
 164
 165         if (bus == NULL)
 166                 return -EINVAL;
 167
 168         dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 169                 addr, reg, val);
 170
 171         return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
 172 }
 173
 174 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 175 {
 176         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 177         int ret;
 178
 179         mutex_lock(&ps->smi_mutex);
 180         ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
 181         mutex_unlock(&ps->smi_mutex);
 182
 183         return ret;
 184 }
 185
 186 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 187 {
 188         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
 189         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
 190         REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
 191
 192         return 0;
 193 }
 194
 195 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 196 {
 197         int i;
 198         int ret;
 199
 200         for (i = 0; i < 6; i++) {
 201                 int j;
 202
 203                 /* Write the MAC address byte. */
 204                 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
 205                           GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
 206
 207                 /* Wait for the write to complete. */
 208                 for (j = 0; j < 16; j++) {
 209                         ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
 210                         if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
 211                                 break;
 212                 }
 213                 if (j == 16)
 214                         return -ETIMEDOUT;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
 221 {
 222         if (addr >= 0)
 223                 return _mv88e6xxx_reg_read(ds, addr, regnum);
 224         return 0xffff;
 225 }
 226
 227 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
 228                                 u16 val)
 229 {
 230         if (addr >= 0)
 231                 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
 232         return 0;
 233 }
 234
 235 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
 236 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
 237 {
 238         int ret;
 239         unsigned long timeout;
 240
 241         ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
 242         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
 243                   ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 244
 245         timeout = jiffies + 1 * HZ;
 246         while (time_before(jiffies, timeout)) {
 247                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 248                 usleep_range(1000, 2000);
 249                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 250                     GLOBAL_STATUS_PPU_POLLING)
 251                         return 0;
 252         }
 253
 254         return -ETIMEDOUT;
 255 }
 256
 257 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
 258 {
 259         int ret;
 260         unsigned long timeout;
 261
 262         ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
 263         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
 264
 265         timeout = jiffies + 1 * HZ;
 266         while (time_before(jiffies, timeout)) {
 267                 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
 268                 usleep_range(1000, 2000);
 269                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 270                     GLOBAL_STATUS_PPU_POLLING)
 271                         return 0;
 272         }
 273
 274         return -ETIMEDOUT;
 275 }
 276
 277 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 278 {
 279         struct mv88e6xxx_priv_state *ps;
 280
 281         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 282         if (mutex_trylock(&ps->ppu_mutex)) {
 283                 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
 284
 285                 if (mv88e6xxx_ppu_enable(ds) == 0)
 286                         ps->ppu_disabled = 0;
 287                 mutex_unlock(&ps->ppu_mutex);
 288         }
 289 }
 290
 291 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 292 {
 293         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 294
 295         schedule_work(&ps->ppu_work);
 296 }
 297
 298 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
 299 {
 300         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 301         int ret;
 302
 303         mutex_lock(&ps->ppu_mutex);
 304
 305         /* If the PHY polling unit is enabled, disable it so that
 306          * we can access the PHY registers.  If it was already
 307          * disabled, cancel the timer that is going to re-enable
 308          * it.
 309          */
 310         if (!ps->ppu_disabled) {
 311                 ret = mv88e6xxx_ppu_disable(ds);
 312                 if (ret < 0) {
 313                         mutex_unlock(&ps->ppu_mutex);
 314                         return ret;
 315                 }
 316                 ps->ppu_disabled = 1;
 317         } else {
 318                 del_timer(&ps->ppu_timer);
 319                 ret = 0;
 320         }
 321
 322         return ret;
 323 }
 324
 325 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
 326 {
 327         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 328
 329         /* Schedule a timer to re-enable the PHY polling unit. */
 330         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 331         mutex_unlock(&ps->ppu_mutex);
 332 }
 333
 334 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
 335 {
 336         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 337
 338         mutex_init(&ps->ppu_mutex);
 339         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 340         init_timer(&ps->ppu_timer);
 341         ps->ppu_timer.data = (unsigned long)ps;
 342         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 343 }
 344
 345 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
 346 {
 347         int ret;
 348
 349         ret = mv88e6xxx_ppu_access_get(ds);
 350         if (ret >= 0) {
 351                 ret = mv88e6xxx_reg_read(ds, addr, regnum);
 352                 mv88e6xxx_ppu_access_put(ds);
 353         }
 354
 355         return ret;
 356 }
 357
 358 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
 359                             int regnum, u16 val)
 360 {
 361         int ret;
 362
 363         ret = mv88e6xxx_ppu_access_get(ds);
 364         if (ret >= 0) {
 365                 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
 366                 mv88e6xxx_ppu_access_put(ds);
 367         }
 368
 369         return ret;
 370 }
 371 #endif
 372
 373 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
 374 {
 375         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 376
 377         switch (ps->id) {
 378         case PORT_SWITCH_ID_6031:
 379         case PORT_SWITCH_ID_6061:
 380         case PORT_SWITCH_ID_6035:
 381         case PORT_SWITCH_ID_6065:
 382                 return true;
 383         }
 384         return false;
 385 }
 386
 387 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
 388 {
 389         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 390
 391         switch (ps->id) {
 392         case PORT_SWITCH_ID_6092:
 393         case PORT_SWITCH_ID_6095:
 394                 return true;
 395         }
 396         return false;
 397 }
 398
 399 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
 400 {
 401         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 402
 403         switch (ps->id) {
 404         case PORT_SWITCH_ID_6046:
 405         case PORT_SWITCH_ID_6085:
 406         case PORT_SWITCH_ID_6096:
 407         case PORT_SWITCH_ID_6097:
 408                 return true;
 409         }
 410         return false;
 411 }
 412
 413 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
 414 {
 415         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 416
 417         switch (ps->id) {
 418         case PORT_SWITCH_ID_6123:
 419         case PORT_SWITCH_ID_6161:
 420         case PORT_SWITCH_ID_6165:
 421                 return true;
 422         }
 423         return false;
 424 }
 425
 426 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
 427 {
 428         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 429
 430         switch (ps->id) {
 431         case PORT_SWITCH_ID_6121:
 432         case PORT_SWITCH_ID_6122:
 433         case PORT_SWITCH_ID_6152:
 434         case PORT_SWITCH_ID_6155:
 435         case PORT_SWITCH_ID_6182:
 436         case PORT_SWITCH_ID_6185:
 437         case PORT_SWITCH_ID_6108:
 438         case PORT_SWITCH_ID_6131:
 439                 return true;
 440         }
 441         return false;
 442 }
 443
 444 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
 445 {
 446         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 447
 448         switch (ps->id) {
 449         case PORT_SWITCH_ID_6320:
 450         case PORT_SWITCH_ID_6321:
 451                 return true;
 452         }
 453         return false;
 454 }
 455
 456 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
 457 {
 458         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 459
 460         switch (ps->id) {
 461         case PORT_SWITCH_ID_6171:
 462         case PORT_SWITCH_ID_6175:
 463         case PORT_SWITCH_ID_6350:
 464         case PORT_SWITCH_ID_6351:
 465                 return true;
 466         }
 467         return false;
 468 }
 469
 470 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
 471 {
 472         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 473
 474         switch (ps->id) {
 475         case PORT_SWITCH_ID_6172:
 476         case PORT_SWITCH_ID_6176:
 477         case PORT_SWITCH_ID_6240:
 478         case PORT_SWITCH_ID_6352:
 479                 return true;
 480         }
 481         return false;
 482 }
 483
 484 /* We expect the switch to perform auto negotiation if there is a real
 485  * phy. However, in the case of a fixed link phy, we force the port
 486  * settings from the fixed link settings.
 487  */
 488 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 489                            struct phy_device *phydev)
 490 {
 491         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 492         u32 reg;
 493         int ret;
 494
 495         if (!phy_is_pseudo_fixed_link(phydev))
 496                 return;
 497
 498         mutex_lock(&ps->smi_mutex);
 499
 500         ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
 501         if (ret < 0)
 502                 goto out;
 503
 504         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 505                       PORT_PCS_CTRL_FORCE_LINK |
 506                       PORT_PCS_CTRL_DUPLEX_FULL |
 507                       PORT_PCS_CTRL_FORCE_DUPLEX |
 508                       PORT_PCS_CTRL_UNFORCED);
 509
 510         reg |= PORT_PCS_CTRL_FORCE_LINK;
 511         if (phydev->link)
 512                         reg |= PORT_PCS_CTRL_LINK_UP;
 513
 514         if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
 515                 goto out;
 516
 517         switch (phydev->speed) {
 518         case SPEED_1000:
 519                 reg |= PORT_PCS_CTRL_1000;
 520                 break;
 521         case SPEED_100:
 522                 reg |= PORT_PCS_CTRL_100;
 523                 break;
 524         case SPEED_10:
 525                 reg |= PORT_PCS_CTRL_10;
 526                 break;
 527         default:
 528                 pr_info("Unknown speed");
 529                 goto out;
 530         }
 531
 532         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 533         if (phydev->duplex == DUPLEX_FULL)
 534                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 535
 536         if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
 537             (port >= ps->num_ports - 2)) {
 538                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 539                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 540                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 541                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 542                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 543                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 544                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 545         }
 546         _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
 547
 548 out:
 549         mutex_unlock(&ps->smi_mutex);
 550 }
 551
 552 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
 553 {
 554         int ret;
 555         int i;
 556
 557         for (i = 0; i < 10; i++) {
 558                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
 559                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 560                         return 0;
 561         }
 562
 563         return -ETIMEDOUT;
 564 }
 565
 566 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
 567 {
 568         int ret;
 569
 570         if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
 571                 port = (port + 1) << 5;
 572
 573         /* Snapshot the hardware statistics counters for this port. */
 574         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
 575                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 576                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 577         if (ret < 0)
 578                 return ret;
 579
 580         /* Wait for the snapshotting to complete. */
 581         ret = _mv88e6xxx_stats_wait(ds);
 582         if (ret < 0)
 583                 return ret;
 584
 585         return 0;
 586 }
 587
 588 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
 589 {
 590         u32 _val;
 591         int ret;
 592
 593         *val = 0;
 594
 595         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
 596                                    GLOBAL_STATS_OP_READ_CAPTURED |
 597                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 598         if (ret < 0)
 599                 return;
 600
 601         ret = _mv88e6xxx_stats_wait(ds);
 602         if (ret < 0)
 603                 return;
 604
 605         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 606         if (ret < 0)
 607                 return;
 608
 609         _val = ret << 16;
 610
 611         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 612         if (ret < 0)
 613                 return;
 614
 615         *val = _val | ret;
 616 }
 617
 618 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 619         { "in_good_octets", 8, 0x00, },
 620         { "in_bad_octets", 4, 0x02, },
 621         { "in_unicast", 4, 0x04, },
 622         { "in_broadcasts", 4, 0x06, },
 623         { "in_multicasts", 4, 0x07, },
 624         { "in_pause", 4, 0x16, },
 625         { "in_undersize", 4, 0x18, },
 626         { "in_fragments", 4, 0x19, },
 627         { "in_oversize", 4, 0x1a, },
 628         { "in_jabber", 4, 0x1b, },
 629         { "in_rx_error", 4, 0x1c, },
 630         { "in_fcs_error", 4, 0x1d, },
 631         { "out_octets", 8, 0x0e, },
 632         { "out_unicast", 4, 0x10, },
 633         { "out_broadcasts", 4, 0x13, },
 634         { "out_multicasts", 4, 0x12, },
 635         { "out_pause", 4, 0x15, },
 636         { "excessive", 4, 0x11, },
 637         { "collisions", 4, 0x1e, },
 638         { "deferred", 4, 0x05, },
 639         { "single", 4, 0x14, },
 640         { "multiple", 4, 0x17, },
 641         { "out_fcs_error", 4, 0x03, },
 642         { "late", 4, 0x1f, },
 643         { "hist_64bytes", 4, 0x08, },
 644         { "hist_65_127bytes", 4, 0x09, },
 645         { "hist_128_255bytes", 4, 0x0a, },
 646         { "hist_256_511bytes", 4, 0x0b, },
 647         { "hist_512_1023bytes", 4, 0x0c, },
 648         { "hist_1024_max_bytes", 4, 0x0d, },
 649         /* Not all devices have the following counters */
 650         { "sw_in_discards", 4, 0x110, },
 651         { "sw_in_filtered", 2, 0x112, },
 652         { "sw_out_filtered", 2, 0x113, },
 653
 654 };
 655
 656 static bool have_sw_in_discards(struct dsa_switch *ds)
 657 {
 658         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 659
 660         switch (ps->id) {
 661         case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
 662         case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
 663         case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
 664         case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
 665         case PORT_SWITCH_ID_6352:
 666                 return true;
 667         default:
 668                 return false;
 669         }
 670 }
 671
 672 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
 673                                    int nr_stats,
 674                                    struct mv88e6xxx_hw_stat *stats,
 675                                    int port, uint8_t *data)
 676 {
 677         int i;
 678
 679         for (i = 0; i < nr_stats; i++) {
 680                 memcpy(data + i * ETH_GSTRING_LEN,
 681                        stats[i].string, ETH_GSTRING_LEN);
 682         }
 683 }
 684
 685 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
 686                                             int stat,
 687                                             struct mv88e6xxx_hw_stat *stats,
 688                                             int port)
 689 {
 690         struct mv88e6xxx_hw_stat *s = stats + stat;
 691         u32 low;
 692         u32 high = 0;
 693         int ret;
 694         u64 value;
 695
 696         if (s->reg >= 0x100) {
 697                 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
 698                                           s->reg - 0x100);
 699                 if (ret < 0)
 700                         return UINT64_MAX;
 701
 702                 low = ret;
 703                 if (s->sizeof_stat == 4) {
 704                         ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
 705                                                   s->reg - 0x100 + 1);
 706                         if (ret < 0)
 707                                 return UINT64_MAX;
 708                         high = ret;
 709                 }
 710         } else {
 711                 _mv88e6xxx_stats_read(ds, s->reg, &low);
 712                 if (s->sizeof_stat == 8)
 713                         _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
 714         }
 715         value = (((u64)high) << 16) | low;
 716         return value;
 717 }
 718
 719 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 720                                          int nr_stats,
 721                                          struct mv88e6xxx_hw_stat *stats,
 722                                          int port, uint64_t *data)
 723 {
 724         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 725         int ret;
 726         int i;
 727
 728         mutex_lock(&ps->smi_mutex);
 729
 730         ret = _mv88e6xxx_stats_snapshot(ds, port);
 731         if (ret < 0) {
 732                 mutex_unlock(&ps->smi_mutex);
 733                 return;
 734         }
 735
 736         /* Read each of the counters. */
 737         for (i = 0; i < nr_stats; i++)
 738                 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
 739
 740         mutex_unlock(&ps->smi_mutex);
 741 }
 742
 743 /* All the statistics in the table */
 744 void
 745 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 746 {
 747         if (have_sw_in_discards(ds))
 748                 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
 749                                        mv88e6xxx_hw_stats, port, data);
 750         else
 751                 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
 752                                        mv88e6xxx_hw_stats, port, data);
 753 }
 754
 755 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 756 {
 757         if (have_sw_in_discards(ds))
 758                 return ARRAY_SIZE(mv88e6xxx_hw_stats);
 759         return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
 760 }
 761
 762 void
 763 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 764                             int port, uint64_t *data)
 765 {
 766         if (have_sw_in_discards(ds))
 767                 _mv88e6xxx_get_ethtool_stats(
 768                         ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
 769                         mv88e6xxx_hw_stats, port, data);
 770         else
 771                 _mv88e6xxx_get_ethtool_stats(
 772                         ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
 773                         mv88e6xxx_hw_stats, port, data);
 774 }
 775
 776 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 777 {
 778         return 32 * sizeof(u16);
 779 }
 780
 781 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 782                         struct ethtool_regs *regs, void *_p)
 783 {
 784         u16 *p = _p;
 785         int i;
 786
 787         regs->version = 0;
 788
 789         memset(p, 0xff, 32 * sizeof(u16));
 790
 791         for (i = 0; i < 32; i++) {
 792                 int ret;
 793
 794                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
 795                 if (ret >= 0)
 796                         p[i] = ret;
 797         }
 798 }
 799
 800 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
 801                            u16 mask)
 802 {
 803         unsigned long timeout = jiffies + HZ / 10;
 804
 805         while (time_before(jiffies, timeout)) {
 806                 int ret;
 807
 808                 ret = _mv88e6xxx_reg_read(ds, reg, offset);
 809                 if (ret < 0)
 810                         return ret;
 811                 if (!(ret & mask))
 812                         return 0;
 813
 814                 usleep_range(1000, 2000);
 815         }
 816         return -ETIMEDOUT;
 817 }
 818
 819 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 820 {
 821         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 822         int ret;
 823
 824         mutex_lock(&ps->smi_mutex);
 825         ret = _mv88e6xxx_wait(ds, reg, offset, mask);
 826         mutex_unlock(&ps->smi_mutex);
 827
 828         return ret;
 829 }
 830
 831 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
 832 {
 833         return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
 834                                GLOBAL2_SMI_OP_BUSY);
 835 }
 836
 837 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 838 {
 839         return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 840                               GLOBAL2_EEPROM_OP_LOAD);
 841 }
 842
 843 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 844 {
 845         return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 846                               GLOBAL2_EEPROM_OP_BUSY);
 847 }
 848
 849 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
 850 {
 851         return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
 852                                GLOBAL_ATU_OP_BUSY);
 853 }
 854
 855 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
 856                                         int regnum)
 857 {
 858         int ret;
 859
 860         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
 861                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
 862                                    regnum);
 863         if (ret < 0)
 864                 return ret;
 865
 866         ret = _mv88e6xxx_phy_wait(ds);
 867         if (ret < 0)
 868                 return ret;
 869
 870         return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
 871 }
 872
 873 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
 874                                          int regnum, u16 val)
 875 {
 876         int ret;
 877
 878         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
 879         if (ret < 0)
 880                 return ret;
 881
 882         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
 883                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
 884                                    regnum);
 885
 886         return _mv88e6xxx_phy_wait(ds);
 887 }
 888
 889 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
 890 {
 891         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 892         int reg;
 893
 894         mutex_lock(&ps->smi_mutex);
 895
 896         reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
 897         if (reg < 0)
 898                 goto out;
 899
 900         e->eee_enabled = !!(reg & 0x0200);
 901         e->tx_lpi_enabled = !!(reg & 0x0100);
 902
 903         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
 904         if (reg < 0)
 905                 goto out;
 906
 907         e->eee_active = !!(reg & PORT_STATUS_EEE);
 908         reg = 0;
 909
 910 out:
 911         mutex_unlock(&ps->smi_mutex);
 912         return reg;
 913 }
 914
 915 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 916                       struct phy_device *phydev, struct ethtool_eee *e)
 917 {
 918         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 919         int reg;
 920         int ret;
 921
 922         mutex_lock(&ps->smi_mutex);
 923
 924         ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
 925         if (ret < 0)
 926                 goto out;
 927
 928         reg = ret & ~0x0300;
 929         if (e->eee_enabled)
 930                 reg |= 0x0200;
 931         if (e->tx_lpi_enabled)
 932                 reg |= 0x0100;
 933
 934         ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
 935 out:
 936         mutex_unlock(&ps->smi_mutex);
 937
 938         return ret;
 939 }
 940
 941 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
 942 {
 943         int ret;
 944
 945         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
 946         if (ret < 0)
 947                 return ret;
 948
 949         return _mv88e6xxx_atu_wait(ds);
 950 }
 951
 952 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
 953                                      struct mv88e6xxx_atu_entry *entry)
 954 {
 955         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
 956
 957         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
 958                 unsigned int mask, shift;
 959
 960                 if (entry->trunk) {
 961                         data |= GLOBAL_ATU_DATA_TRUNK;
 962                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
 963                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
 964                 } else {
 965                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
 966                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
 967                 }
 968
 969                 data |= (entry->portv_trunkid << shift) & mask;
 970         }
 971
 972         return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
 973 }
 974
 975 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
 976                                      struct mv88e6xxx_atu_entry *entry,
 977                                      bool static_too)
 978 {
 979         int op;
 980         int err;
 981
 982         err = _mv88e6xxx_atu_wait(ds);
 983         if (err)
 984                 return err;
 985
 986         err = _mv88e6xxx_atu_data_write(ds, entry);
 987         if (err)
 988                 return err;
 989
 990         if (entry->fid) {
 991                 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
 992                                            entry->fid);
 993                 if (err)
 994                         return err;
 995
 996                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
 997                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
 998         } else {
 999                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1000                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1001         }
1002
1003         return _mv88e6xxx_atu_cmd(ds, op);
1004 }
1005
1006 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1007 {
1008         struct mv88e6xxx_atu_entry entry = {
1009                 .fid = fid,
1010                 .state = 0, /* EntryState bits must be 0 */
1011         };
1012
1013         return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1014 }
1015
1016 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1017                                int to_port, bool static_too)
1018 {
1019         struct mv88e6xxx_atu_entry entry = {
1020                 .trunk = false,
1021                 .fid = fid,
1022         };
1023
1024         /* EntryState bits must be 0xF */
1025         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1026
1027         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1028         entry.portv_trunkid = (to_port & 0x0f) << 4;
1029         entry.portv_trunkid |= from_port & 0x0f;
1030
1031         return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1032 }
1033
1034 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1035                                  bool static_too)
1036 {
1037         /* Destination port 0xF means remove the entries */
1038         return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1039 }
1040
1041 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1042 {
1043         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1044         int reg, ret = 0;
1045         u8 oldstate;
1046
1047         mutex_lock(&ps->smi_mutex);
1048
1049         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1050         if (reg < 0) {
1051                 ret = reg;
1052                 goto abort;
1053         }
1054
1055         oldstate = reg & PORT_CONTROL_STATE_MASK;
1056         if (oldstate != state) {
1057                 /* Flush forwarding database if we're moving a port
1058                  * from Learning or Forwarding state to Disabled or
1059                  * Blocking or Listening state.
1060                  */
1061                 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1062                     state <= PORT_CONTROL_STATE_BLOCKING) {
1063                         ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1064                         if (ret)
1065                                 goto abort;
1066                 }
1067                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1068                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1069                                            reg);
1070         }
1071
1072 abort:
1073         mutex_unlock(&ps->smi_mutex);
1074         return ret;
1075 }
1076
1077 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1078                                         u16 output_ports)
1079 {
1080         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1081         const u16 mask = (1 << ps->num_ports) - 1;
1082         int reg;
1083
1084         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1085         if (reg < 0)
1086                 return reg;
1087
1088         reg &= ~mask;
1089         reg |= output_ports & mask;
1090
1091         return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1092 }
1093
1094 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1095 {
1096         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1097         int stp_state;
1098
1099         switch (state) {
1100         case BR_STATE_DISABLED:
1101                 stp_state = PORT_CONTROL_STATE_DISABLED;
1102                 break;
1103         case BR_STATE_BLOCKING:
1104         case BR_STATE_LISTENING:
1105                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1106                 break;
1107         case BR_STATE_LEARNING:
1108                 stp_state = PORT_CONTROL_STATE_LEARNING;
1109                 break;
1110         case BR_STATE_FORWARDING:
1111         default:
1112                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1113                 break;
1114         }
1115
1116         netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1117
1118         /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1119          * so we can not update the port state directly but need to schedule it.
1120          */
1121         ps->port_state[port] = stp_state;
1122         set_bit(port, &ps->port_state_update_mask);
1123         schedule_work(&ps->bridge_work);
1124
1125         return 0;
1126 }
1127
1128 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1129 {
1130         int ret;
1131
1132         ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1133         if (ret < 0)
1134                 return ret;
1135
1136         *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1137
1138         return 0;
1139 }
1140
1141 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1142 {
1143         int ret;
1144
1145         ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1146         if (ret < 0)
1147                 return ret;
1148
1149         *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1150
1151         return 0;
1152 }
1153
1154 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1155 {
1156         return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1157                                    pvid & PORT_DEFAULT_VLAN_MASK);
1158 }
1159
1160 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1161 {
1162         return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1163                                GLOBAL_VTU_OP_BUSY);
1164 }
1165
1166 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1167 {
1168         int ret;
1169
1170         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1171         if (ret < 0)
1172                 return ret;
1173
1174         return _mv88e6xxx_vtu_wait(ds);
1175 }
1176
1177 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1178 {
1179         int ret;
1180
1181         ret = _mv88e6xxx_vtu_wait(ds);
1182         if (ret < 0)
1183                 return ret;
1184
1185         return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1186 }
1187
1188 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1189                                         struct mv88e6xxx_vtu_stu_entry *entry,
1190                                         unsigned int nibble_offset)
1191 {
1192         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1193         u16 regs[3];
1194         int i;
1195         int ret;
1196
1197         for (i = 0; i < 3; ++i) {
1198                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1199                                           GLOBAL_VTU_DATA_0_3 + i);
1200                 if (ret < 0)
1201                         return ret;
1202
1203                 regs[i] = ret;
1204         }
1205
1206         for (i = 0; i < ps->num_ports; ++i) {
1207                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1208                 u16 reg = regs[i / 4];
1209
1210                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1217                                          struct mv88e6xxx_vtu_stu_entry *entry,
1218                                          unsigned int nibble_offset)
1219 {
1220         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1221         u16 regs[3] = { 0 };
1222         int i;
1223         int ret;
1224
1225         for (i = 0; i < ps->num_ports; ++i) {
1226                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1227                 u8 data = entry->data[i];
1228
1229                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1230         }
1231
1232         for (i = 0; i < 3; ++i) {
1233                 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1234                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1235                 if (ret < 0)
1236                         return ret;
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1243 {
1244         return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1245                                     vid & GLOBAL_VTU_VID_MASK);
1246 }
1247
1248 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1249                                   struct mv88e6xxx_vtu_stu_entry *entry)
1250 {
1251         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1252         int ret;
1253
1254         ret = _mv88e6xxx_vtu_wait(ds);
1255         if (ret < 0)
1256                 return ret;
1257
1258         ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1259         if (ret < 0)
1260                 return ret;
1261
1262         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1263         if (ret < 0)
1264                 return ret;
1265
1266         next.vid = ret & GLOBAL_VTU_VID_MASK;
1267         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1268
1269         if (next.valid) {
1270                 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1271                 if (ret < 0)
1272                         return ret;
1273
1274                 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1275                     mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1276                         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1277                                                   GLOBAL_VTU_FID);
1278                         if (ret < 0)
1279                                 return ret;
1280
1281                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1282
1283                         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1284                                                   GLOBAL_VTU_SID);
1285                         if (ret < 0)
1286                                 return ret;
1287
1288                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1289                 }
1290         }
1291
1292         *entry = next;
1293         return 0;
1294 }
1295
1296 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1297                                     struct mv88e6xxx_vtu_stu_entry *entry)
1298 {
1299         u16 reg = 0;
1300         int ret;
1301
1302         ret = _mv88e6xxx_vtu_wait(ds);
1303         if (ret < 0)
1304                 return ret;
1305
1306         if (!entry->valid)
1307                 goto loadpurge;
1308
1309         /* Write port member tags */
1310         ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1311         if (ret < 0)
1312                 return ret;
1313
1314         if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1315             mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1316                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1317                 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1318                 if (ret < 0)
1319                         return ret;
1320
1321                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1322                 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1323                 if (ret < 0)
1324                         return ret;
1325         }
1326
1327         reg = GLOBAL_VTU_VID_VALID;
1328 loadpurge:
1329         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1330         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1331         if (ret < 0)
1332                 return ret;
1333
1334         return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1335 }
1336
1337 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1338                                   struct mv88e6xxx_vtu_stu_entry *entry)
1339 {
1340         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1341         int ret;
1342
1343         ret = _mv88e6xxx_vtu_wait(ds);
1344         if (ret < 0)
1345                 return ret;
1346
1347         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1348                                    sid & GLOBAL_VTU_SID_MASK);
1349         if (ret < 0)
1350                 return ret;
1351
1352         ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1353         if (ret < 0)
1354                 return ret;
1355
1356         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1357         if (ret < 0)
1358                 return ret;
1359
1360         next.sid = ret & GLOBAL_VTU_SID_MASK;
1361
1362         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1363         if (ret < 0)
1364                 return ret;
1365
1366         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1367
1368         if (next.valid) {
1369                 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1370                 if (ret < 0)
1371                         return ret;
1372         }
1373
1374         *entry = next;
1375         return 0;
1376 }
1377
1378 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1379                                     struct mv88e6xxx_vtu_stu_entry *entry)
1380 {
1381         u16 reg = 0;
1382         int ret;
1383
1384         ret = _mv88e6xxx_vtu_wait(ds);
1385         if (ret < 0)
1386                 return ret;
1387
1388         if (!entry->valid)
1389                 goto loadpurge;
1390
1391         /* Write port states */
1392         ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1393         if (ret < 0)
1394                 return ret;
1395
1396         reg = GLOBAL_VTU_VID_VALID;
1397 loadpurge:
1398         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1399         if (ret < 0)
1400                 return ret;
1401
1402         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1403         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1404         if (ret < 0)
1405                 return ret;
1406
1407         return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1408 }
1409
1410 static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1411                                 struct mv88e6xxx_vtu_stu_entry *entry)
1412 {
1413         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1414         struct mv88e6xxx_vtu_stu_entry vlan = {
1415                 .valid = true,
1416                 .vid = vid,
1417                 .fid = vid, /* We use one FID per VLAN */
1418         };
1419         int i;
1420
1421         /* exclude all ports except the CPU and DSA ports */
1422         for (i = 0; i < ps->num_ports; ++i)
1423                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1424                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1425                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1426
1427         if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1428             mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1429                 struct mv88e6xxx_vtu_stu_entry vstp;
1430                 int err;
1431
1432                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1433                  * implemented, only one STU entry is needed to cover all VTU
1434                  * entries. Thus, validate the SID 0.
1435                  */
1436                 vlan.sid = 0;
1437                 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1438                 if (err)
1439                         return err;
1440
1441                 if (vstp.sid != vlan.sid || !vstp.valid) {
1442                         memset(&vstp, 0, sizeof(vstp));
1443                         vstp.valid = true;
1444                         vstp.sid = vlan.sid;
1445
1446                         err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1447                         if (err)
1448                                 return err;
1449                 }
1450
1451                 /* Clear all MAC addresses from the new database */
1452                 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
1453                 if (err)
1454                         return err;
1455         }
1456
1457         *entry = vlan;
1458         return 0;
1459 }
1460
1461 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1462                                 const struct switchdev_obj_port_vlan *vlan,
1463                                 struct switchdev_trans *trans)
1464 {
1465         /* We reserve a few VLANs to isolate unbridged ports */
1466         if (vlan->vid_end >= 4000)
1467                 return -EOPNOTSUPP;
1468
1469         /* We don't need any dynamic resource from the kernel (yet),
1470          * so skip the prepare phase.
1471          */
1472         return 0;
1473 }
1474
1475 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1476                                     bool untagged)
1477 {
1478         struct mv88e6xxx_vtu_stu_entry vlan;
1479         int err;
1480
1481         err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1482         if (err)
1483                 return err;
1484
1485         err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1486         if (err)
1487                 return err;
1488
1489         if (vlan.vid != vid || !vlan.valid) {
1490                 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1491                 if (err)
1492                         return err;
1493         }
1494
1495         vlan.data[port] = untagged ?
1496                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1497                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1498
1499         return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1500 }
1501
1502 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1503                             const struct switchdev_obj_port_vlan *vlan,
1504                             struct switchdev_trans *trans)
1505 {
1506         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1507         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1508         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1509         u16 vid;
1510         int err = 0;
1511
1512         mutex_lock(&ps->smi_mutex);
1513
1514         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1515                 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1516                 if (err)
1517                         goto unlock;
1518         }
1519
1520         /* no PVID with ranges, otherwise it's a bug */
1521         if (pvid)
1522                 err = _mv88e6xxx_port_pvid_set(ds, port, vid);
1523 unlock:
1524         mutex_unlock(&ps->smi_mutex);
1525
1526         return err;
1527 }
1528
1529 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1530 {
1531         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1532         struct mv88e6xxx_vtu_stu_entry vlan;
1533         int i, err;
1534
1535         err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1536         if (err)
1537                 return err;
1538
1539         err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1540         if (err)
1541                 return err;
1542
1543         if (vlan.vid != vid || !vlan.valid ||
1544             vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1545                 return -ENOENT;
1546
1547         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1548
1549         /* keep the VLAN unless all ports are excluded */
1550         vlan.valid = false;
1551         for (i = 0; i < ps->num_ports; ++i) {
1552                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1553                         continue;
1554
1555                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1556                         vlan.valid = true;
1557                         break;
1558                 }
1559         }
1560
1561         err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1562         if (err)
1563                 return err;
1564
1565         return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1566 }
1567
1568 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1569                             const struct switchdev_obj_port_vlan *vlan)
1570 {
1571         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1572         u16 pvid, vid;
1573         int err = 0;
1574
1575         mutex_lock(&ps->smi_mutex);
1576
1577         err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1578         if (err)
1579                 goto unlock;
1580
1581         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1582                 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1583                 if (err)
1584                         goto unlock;
1585
1586                 if (vid == pvid) {
1587                         err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1588                         if (err)
1589                                 goto unlock;
1590                 }
1591         }
1592
1593 unlock:
1594         mutex_unlock(&ps->smi_mutex);
1595
1596         return err;
1597 }
1598
1599 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1600                            unsigned long *ports, unsigned long *untagged)
1601 {
1602         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1603         struct mv88e6xxx_vtu_stu_entry next;
1604         int port;
1605         int err;
1606
1607         if (*vid == 4095)
1608                 return -ENOENT;
1609
1610         mutex_lock(&ps->smi_mutex);
1611         err = _mv88e6xxx_vtu_vid_write(ds, *vid);
1612         if (err)
1613                 goto unlock;
1614
1615         err = _mv88e6xxx_vtu_getnext(ds, &next);
1616 unlock:
1617         mutex_unlock(&ps->smi_mutex);
1618
1619         if (err)
1620                 return err;
1621
1622         if (!next.valid)
1623                 return -ENOENT;
1624
1625         *vid = next.vid;
1626
1627         for (port = 0; port < ps->num_ports; ++port) {
1628                 clear_bit(port, ports);
1629                 clear_bit(port, untagged);
1630
1631                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1632                         continue;
1633
1634                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1635                     next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1636                         set_bit(port, ports);
1637
1638                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1639                         set_bit(port, untagged);
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1646                                     const unsigned char *addr)
1647 {
1648         int i, ret;
1649
1650         for (i = 0; i < 3; i++) {
1651                 ret = _mv88e6xxx_reg_write(
1652                         ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1653                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
1654                 if (ret < 0)
1655                         return ret;
1656         }
1657
1658         return 0;
1659 }
1660
1661 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1662 {
1663         int i, ret;
1664
1665         for (i = 0; i < 3; i++) {
1666                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1667                                           GLOBAL_ATU_MAC_01 + i);
1668                 if (ret < 0)
1669                         return ret;
1670                 addr[i * 2] = ret >> 8;
1671                 addr[i * 2 + 1] = ret & 0xff;
1672         }
1673
1674         return 0;
1675 }
1676
1677 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1678                                struct mv88e6xxx_atu_entry *entry)
1679 {
1680         int ret;
1681
1682         ret = _mv88e6xxx_atu_wait(ds);
1683         if (ret < 0)
1684                 return ret;
1685
1686         ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1687         if (ret < 0)
1688                 return ret;
1689
1690         ret = _mv88e6xxx_atu_data_write(ds, entry);
1691         if (ret < 0)
1692                 return ret;
1693
1694         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1695         if (ret < 0)
1696                 return ret;
1697
1698         return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1699 }
1700
1701 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1702                                     const unsigned char *addr, u16 vid,
1703                                     u8 state)
1704 {
1705         struct mv88e6xxx_atu_entry entry = { 0 };
1706
1707         entry.fid = vid; /* We use one FID per VLAN */
1708         entry.state = state;
1709         ether_addr_copy(entry.mac, addr);
1710         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1711                 entry.trunk = false;
1712                 entry.portv_trunkid = BIT(port);
1713         }
1714
1715         return _mv88e6xxx_atu_load(ds, &entry);
1716 }
1717
1718 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1719                                const struct switchdev_obj_port_fdb *fdb,
1720                                struct switchdev_trans *trans)
1721 {
1722         /* We don't use per-port FDB */
1723         if (fdb->vid == 0)
1724                 return -EOPNOTSUPP;
1725
1726         /* We don't need any dynamic resource from the kernel (yet),
1727          * so skip the prepare phase.
1728          */
1729         return 0;
1730 }
1731
1732 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1733                            const struct switchdev_obj_port_fdb *fdb,
1734                            struct switchdev_trans *trans)
1735 {
1736         int state = is_multicast_ether_addr(fdb->addr) ?
1737                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1738                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1739         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1740         int ret;
1741
1742         mutex_lock(&ps->smi_mutex);
1743         ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1744         mutex_unlock(&ps->smi_mutex);
1745
1746         return ret;
1747 }
1748
1749 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1750                            const struct switchdev_obj_port_fdb *fdb)
1751 {
1752         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1753         int ret;
1754
1755         mutex_lock(&ps->smi_mutex);
1756         ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1757                                        GLOBAL_ATU_DATA_STATE_UNUSED);
1758         mutex_unlock(&ps->smi_mutex);
1759
1760         return ret;
1761 }
1762
1763 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1764                                   struct mv88e6xxx_atu_entry *entry)
1765 {
1766         struct mv88e6xxx_atu_entry next = { 0 };
1767         int ret;
1768
1769         next.fid = fid;
1770
1771         ret = _mv88e6xxx_atu_wait(ds);
1772         if (ret < 0)
1773                 return ret;
1774
1775         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1776         if (ret < 0)
1777                 return ret;
1778
1779         ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1780         if (ret < 0)
1781                 return ret;
1782
1783         ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1784         if (ret < 0)
1785                 return ret;
1786
1787         ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1788         if (ret < 0)
1789                 return ret;
1790
1791         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1792         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1793                 unsigned int mask, shift;
1794
1795                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1796                         next.trunk = true;
1797                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1798                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1799                 } else {
1800                         next.trunk = false;
1801                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1802                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1803                 }
1804
1805                 next.portv_trunkid = (ret & mask) >> shift;
1806         }
1807
1808         *entry = next;
1809         return 0;
1810 }
1811
1812 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1813                             struct switchdev_obj_port_fdb *fdb,
1814                             int (*cb)(struct switchdev_obj *obj))
1815 {
1816         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1817         struct mv88e6xxx_vtu_stu_entry vlan = {
1818                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1819         };
1820         int err;
1821
1822         mutex_lock(&ps->smi_mutex);
1823
1824         err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1825         if (err)
1826                 goto unlock;
1827
1828         do {
1829                 struct mv88e6xxx_atu_entry addr = {
1830                         .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1831                 };
1832
1833                 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1834                 if (err)
1835                         goto unlock;
1836
1837                 if (!vlan.valid)
1838                         break;
1839
1840                 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1841                 if (err)
1842                         goto unlock;
1843
1844                 do {
1845                         err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1846                         if (err)
1847                                 goto unlock;
1848
1849                         if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1850                                 break;
1851
1852                         if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1853                                 bool is_static = addr.state ==
1854                                         (is_multicast_ether_addr(addr.mac) ?
1855                                          GLOBAL_ATU_DATA_STATE_MC_STATIC :
1856                                          GLOBAL_ATU_DATA_STATE_UC_STATIC);
1857
1858                                 fdb->vid = vlan.vid;
1859                                 ether_addr_copy(fdb->addr, addr.mac);
1860                                 fdb->ndm_state = is_static ? NUD_NOARP :
1861                                         NUD_REACHABLE;
1862
1863                                 err = cb(&fdb->obj);
1864                                 if (err)
1865                                         goto unlock;
1866                         }
1867                 } while (!is_broadcast_ether_addr(addr.mac));
1868
1869         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1870
1871 unlock:
1872         mutex_unlock(&ps->smi_mutex);
1873
1874         return err;
1875 }
1876
1877 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, u32 members)
1878 {
1879         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1880         const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1881         int err;
1882
1883         /* The port joined a bridge, so leave its reserved VLAN */
1884         mutex_lock(&ps->smi_mutex);
1885         err = _mv88e6xxx_port_vlan_del(ds, port, pvid);
1886         if (!err)
1887                 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1888         mutex_unlock(&ps->smi_mutex);
1889         return err;
1890 }
1891
1892 int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, u32 members)
1893 {
1894         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1895         const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1896         int err;
1897
1898         /* The port left the bridge, so join its reserved VLAN */
1899         mutex_lock(&ps->smi_mutex);
1900         err = _mv88e6xxx_port_vlan_add(ds, port, pvid, true);
1901         if (!err)
1902                 err = _mv88e6xxx_port_pvid_set(ds, port, pvid);
1903         mutex_unlock(&ps->smi_mutex);
1904         return err;
1905 }
1906
1907 static void mv88e6xxx_bridge_work(struct work_struct *work)
1908 {
1909         struct mv88e6xxx_priv_state *ps;
1910         struct dsa_switch *ds;
1911         int port;
1912
1913         ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1914         ds = ((struct dsa_switch *)ps) - 1;
1915
1916         while (ps->port_state_update_mask) {
1917                 port = __ffs(ps->port_state_update_mask);
1918                 clear_bit(port, &ps->port_state_update_mask);
1919                 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1920         }
1921 }
1922
1923 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1924 {
1925         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1926         int ret;
1927         u16 reg;
1928
1929         mutex_lock(&ps->smi_mutex);
1930
1931         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1932             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1933             mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1934             mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1935                 /* MAC Forcing register: don't force link, speed,
1936                  * duplex or flow control state to any particular
1937                  * values on physical ports, but force the CPU port
1938                  * and all DSA ports to their maximum bandwidth and
1939                  * full duplex.
1940                  */
1941                 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1942                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1943                         reg &= ~PORT_PCS_CTRL_UNFORCED;
1944                         reg |= PORT_PCS_CTRL_FORCE_LINK |
1945                                 PORT_PCS_CTRL_LINK_UP |
1946                                 PORT_PCS_CTRL_DUPLEX_FULL |
1947                                 PORT_PCS_CTRL_FORCE_DUPLEX;
1948                         if (mv88e6xxx_6065_family(ds))
1949                                 reg |= PORT_PCS_CTRL_100;
1950                         else
1951                                 reg |= PORT_PCS_CTRL_1000;
1952                 } else {
1953                         reg |= PORT_PCS_CTRL_UNFORCED;
1954                 }
1955
1956                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1957                                            PORT_PCS_CTRL, reg);
1958                 if (ret)
1959                         goto abort;
1960         }
1961
1962         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1963          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1964          * tunneling, determine priority by looking at 802.1p and IP
1965          * priority fields (IP prio has precedence), and set STP state
1966          * to Forwarding.
1967          *
1968          * If this is the CPU link, use DSA or EDSA tagging depending
1969          * on which tagging mode was configured.
1970          *
1971          * If this is a link to another switch, use DSA tagging mode.
1972          *
1973          * If this is the upstream port for this switch, enable
1974          * forwarding of unknown unicasts and multicasts.
1975          */
1976         reg = 0;
1977         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1978             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1979             mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1980             mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1981                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1982                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1983                 PORT_CONTROL_STATE_FORWARDING;
1984         if (dsa_is_cpu_port(ds, port)) {
1985                 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1986                         reg |= PORT_CONTROL_DSA_TAG;
1987                 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1988                     mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1989                     mv88e6xxx_6320_family(ds)) {
1990                         if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1991                                 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1992                         else
1993                                 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1994                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1995                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1996                 }
1997
1998                 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1999                     mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2000                     mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2001                     mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2002                         if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2003                                 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2004                 }
2005         }
2006         if (dsa_is_dsa_port(ds, port)) {
2007                 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2008                         reg |= PORT_CONTROL_DSA_TAG;
2009                 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2010                     mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2011                     mv88e6xxx_6320_family(ds)) {
2012                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2013                 }
2014
2015                 if (port == dsa_upstream_port(ds))
2016                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2017                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2018         }
2019         if (reg) {
2020                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2021                                            PORT_CONTROL, reg);
2022                 if (ret)
2023                         goto abort;
2024         }
2025
2026         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2027          * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2028          * untagged frames on this port, do a destination address lookup on all
2029          * received packets as usual, disable ARP mirroring and don't send a
2030          * copy of all transmitted/received frames on this port to the CPU.
2031          */
2032         reg = 0;
2033         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2034             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2035             mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2036                 reg = PORT_CONTROL_2_MAP_DA;
2037
2038         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2039             mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2040                 reg |= PORT_CONTROL_2_JUMBO_10240;
2041
2042         if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2043                 /* Set the upstream port this port should use */
2044                 reg |= dsa_upstream_port(ds);
2045                 /* enable forwarding of unknown multicast addresses to
2046                  * the upstream port
2047                  */
2048                 if (port == dsa_upstream_port(ds))
2049                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2050         }
2051
2052         reg |= PORT_CONTROL_2_8021Q_SECURE;
2053
2054         if (reg) {
2055                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2056                                            PORT_CONTROL_2, reg);
2057                 if (ret)
2058                         goto abort;
2059         }
2060
2061         /* Port Association Vector: when learning source addresses
2062          * of packets, add the address to the address database using
2063          * a port bitmap that has only the bit for this port set and
2064          * the other bits clear.
2065          */
2066         reg = 1 << port;
2067         /* Disable learning for DSA and CPU ports */
2068         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2069                 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2070
2071         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2072         if (ret)
2073                 goto abort;
2074
2075         /* Egress rate control 2: disable egress rate control. */
2076         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2077                                    0x0000);
2078         if (ret)
2079                 goto abort;
2080
2081         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2082             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2083             mv88e6xxx_6320_family(ds)) {
2084                 /* Do not limit the period of time that this port can
2085                  * be paused for by the remote end or the period of
2086                  * time that this port can pause the remote end.
2087                  */
2088                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2089                                            PORT_PAUSE_CTRL, 0x0000);
2090                 if (ret)
2091                         goto abort;
2092
2093                 /* Port ATU control: disable limiting the number of
2094                  * address database entries that this port is allowed
2095                  * to use.
2096                  */
2097                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2098                                            PORT_ATU_CONTROL, 0x0000);
2099                 /* Priority Override: disable DA, SA and VTU priority
2100                  * override.
2101                  */
2102                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2103                                            PORT_PRI_OVERRIDE, 0x0000);
2104                 if (ret)
2105                         goto abort;
2106
2107                 /* Port Ethertype: use the Ethertype DSA Ethertype
2108                  * value.
2109                  */
2110                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2111                                            PORT_ETH_TYPE, ETH_P_EDSA);
2112                 if (ret)
2113                         goto abort;
2114                 /* Tag Remap: use an identity 802.1p prio -> switch
2115                  * prio mapping.
2116                  */
2117                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2118                                            PORT_TAG_REGMAP_0123, 0x3210);
2119                 if (ret)
2120                         goto abort;
2121
2122                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2123                  * prio mapping.
2124                  */
2125                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2126                                            PORT_TAG_REGMAP_4567, 0x7654);
2127                 if (ret)
2128                         goto abort;
2129         }
2130
2131         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2132             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2133             mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2134             mv88e6xxx_6320_family(ds)) {
2135                 /* Rate Control: disable ingress rate limiting. */
2136                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2137                                            PORT_RATE_CONTROL, 0x0001);
2138                 if (ret)
2139                         goto abort;
2140         }
2141
2142         /* Port Control 1: disable trunking, disable sending
2143          * learning messages to this port.
2144          */
2145         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2146         if (ret)
2147                 goto abort;
2148
2149         /* Port based VLAN map: do not give each port its own address
2150          * database, and allow every port to egress frames on all other ports.
2151          */
2152         reg = BIT(ps->num_ports) - 1; /* all ports */
2153         ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port);
2154         if (ret)
2155                 goto abort;
2156
2157         /* Default VLAN ID and priority: don't set a default VLAN
2158          * ID, and set the default packet priority to zero.
2159          */
2160         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2161                                    0x0000);
2162 abort:
2163         mutex_unlock(&ps->smi_mutex);
2164         return ret;
2165 }
2166
2167 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2168 {
2169         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2170         int ret;
2171         int i;
2172
2173         for (i = 0; i < ps->num_ports; i++) {
2174                 ret = mv88e6xxx_setup_port(ds, i);
2175                 if (ret < 0)
2176                         return ret;
2177
2178                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2179                         continue;
2180
2181                 /* setup the unbridged state */
2182                 ret = mv88e6xxx_port_bridge_leave(ds, i, 0);
2183                 if (ret < 0)
2184                         return ret;
2185         }
2186         return 0;
2187 }
2188
2189 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2190 {
2191         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2192
2193         mutex_init(&ps->smi_mutex);
2194
2195         ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2196
2197         INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2198
2199         return 0;
2200 }
2201
2202 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2203 {
2204         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2205         int ret;
2206         int i;
2207
2208         /* Set the default address aging time to 5 minutes, and
2209          * enable address learn messages to be sent to all message
2210          * ports.
2211          */
2212         REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2213                   0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2214
2215         /* Configure the IP ToS mapping registers. */
2216         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2217         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2218         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2219         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2220         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2221         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2222         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2223         REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2224
2225         /* Configure the IEEE 802.1p priority mapping register. */
2226         REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2227
2228         /* Send all frames with destination addresses matching
2229          * 01:80:c2:00:00:0x to the CPU port.
2230          */
2231         REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2232
2233         /* Ignore removed tag data on doubly tagged packets, disable
2234          * flow control messages, force flow control priority to the
2235          * highest, and send all special multicast frames to the CPU
2236          * port at the highest priority.
2237          */
2238         REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2239                   0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2240                   GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2241
2242         /* Program the DSA routing table. */
2243         for (i = 0; i < 32; i++) {
2244                 int nexthop = 0x1f;
2245
2246                 if (ds->pd->rtable &&
2247                     i != ds->index && i < ds->dst->pd->nr_chips)
2248                         nexthop = ds->pd->rtable[i] & 0x1f;
2249
2250                 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2251                           GLOBAL2_DEVICE_MAPPING_UPDATE |
2252                           (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2253                           nexthop);
2254         }
2255
2256         /* Clear all trunk masks. */
2257         for (i = 0; i < 8; i++)
2258                 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2259                           0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2260                           ((1 << ps->num_ports) - 1));
2261
2262         /* Clear all trunk mappings. */
2263         for (i = 0; i < 16; i++)
2264                 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2265                           GLOBAL2_TRUNK_MAPPING_UPDATE |
2266                           (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2267
2268         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2269             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2270             mv88e6xxx_6320_family(ds)) {
2271                 /* Send all frames with destination addresses matching
2272                  * 01:80:c2:00:00:2x to the CPU port.
2273                  */
2274                 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2275
2276                 /* Initialise cross-chip port VLAN table to reset
2277                  * defaults.
2278                  */
2279                 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2280
2281                 /* Clear the priority override table. */
2282                 for (i = 0; i < 16; i++)
2283                         REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2284                                   0x8000 | (i << 8));
2285         }
2286
2287         if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2288             mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2289             mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2290             mv88e6xxx_6320_family(ds)) {
2291                 /* Disable ingress rate limiting by resetting all
2292                  * ingress rate limit registers to their initial
2293                  * state.
2294                  */
2295                 for (i = 0; i < ps->num_ports; i++)
2296                         REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2297                                   0x9000 | (i << 8));
2298         }
2299
2300         /* Clear the statistics counters for all ports */
2301         REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2302
2303         /* Wait for the flush to complete. */
2304         mutex_lock(&ps->smi_mutex);
2305         ret = _mv88e6xxx_stats_wait(ds);
2306         if (ret < 0)
2307                 goto unlock;
2308
2309         /* Clear all ATU entries */
2310         ret = _mv88e6xxx_atu_flush(ds, 0, true);
2311         if (ret < 0)
2312                 goto unlock;
2313
2314         /* Clear all the VTU and STU entries */
2315         ret = _mv88e6xxx_vtu_stu_flush(ds);
2316 unlock:
2317         mutex_unlock(&ps->smi_mutex);
2318
2319         return ret;
2320 }
2321
2322 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2323 {
2324         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2325         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2326         unsigned long timeout;
2327         int ret;
2328         int i;
2329
2330         /* Set all ports to the disabled state. */
2331         for (i = 0; i < ps->num_ports; i++) {
2332                 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2333                 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2334         }
2335
2336         /* Wait for transmit queues to drain. */
2337         usleep_range(2000, 4000);
2338
2339         /* Reset the switch. Keep the PPU active if requested. The PPU
2340          * needs to be active to support indirect phy register access
2341          * through global registers 0x18 and 0x19.
2342          */
2343         if (ppu_active)
2344                 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2345         else
2346                 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2347
2348         /* Wait up to one second for reset to complete. */
2349         timeout = jiffies + 1 * HZ;
2350         while (time_before(jiffies, timeout)) {
2351                 ret = REG_READ(REG_GLOBAL, 0x00);
2352                 if ((ret & is_reset) == is_reset)
2353                         break;
2354                 usleep_range(1000, 2000);
2355         }
2356         if (time_after(jiffies, timeout))
2357                 return -ETIMEDOUT;
2358
2359         return 0;
2360 }
2361
2362 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2363 {
2364         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2365         int ret;
2366
2367         mutex_lock(&ps->smi_mutex);
2368         ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2369         if (ret < 0)
2370                 goto error;
2371         ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2372 error:
2373         _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2374         mutex_unlock(&ps->smi_mutex);
2375         return ret;
2376 }
2377
2378 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2379                              int reg, int val)
2380 {
2381         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2382         int ret;
2383
2384         mutex_lock(&ps->smi_mutex);
2385         ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2386         if (ret < 0)
2387                 goto error;
2388
2389         ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2390 error:
2391         _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2392         mutex_unlock(&ps->smi_mutex);
2393         return ret;
2394 }
2395
2396 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2397 {
2398         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2399
2400         if (port >= 0 && port < ps->num_ports)
2401                 return port;
2402         return -EINVAL;
2403 }
2404
2405 int
2406 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2407 {
2408         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2409         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2410         int ret;
2411
2412         if (addr < 0)
2413                 return addr;
2414
2415         mutex_lock(&ps->smi_mutex);
2416         ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2417         mutex_unlock(&ps->smi_mutex);
2418         return ret;
2419 }
2420
2421 int
2422 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2423 {
2424         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2425         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2426         int ret;
2427
2428         if (addr < 0)
2429                 return addr;
2430
2431         mutex_lock(&ps->smi_mutex);
2432         ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2433         mutex_unlock(&ps->smi_mutex);
2434         return ret;
2435 }
2436
2437 int
2438 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2439 {
2440         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2441         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2442         int ret;
2443
2444         if (addr < 0)
2445                 return addr;
2446
2447         mutex_lock(&ps->smi_mutex);
2448         ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2449         mutex_unlock(&ps->smi_mutex);
2450         return ret;
2451 }
2452
2453 int
2454 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2455                              u16 val)
2456 {
2457         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2458         int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2459         int ret;
2460
2461         if (addr < 0)
2462                 return addr;
2463
2464         mutex_lock(&ps->smi_mutex);
2465         ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2466         mutex_unlock(&ps->smi_mutex);
2467         return ret;
2468 }
2469
2470 #ifdef CONFIG_NET_DSA_HWMON
2471
2472 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2473 {
2474         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2475         int ret;
2476         int val;
2477
2478         *temp = 0;
2479
2480         mutex_lock(&ps->smi_mutex);
2481
2482         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2483         if (ret < 0)
2484                 goto error;
2485
2486         /* Enable temperature sensor */
2487         ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2488         if (ret < 0)
2489                 goto error;
2490
2491         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2492         if (ret < 0)
2493                 goto error;
2494
2495         /* Wait for temperature to stabilize */
2496         usleep_range(10000, 12000);
2497
2498         val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2499         if (val < 0) {
2500                 ret = val;
2501                 goto error;
2502         }
2503
2504         /* Disable temperature sensor */
2505         ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2506         if (ret < 0)
2507                 goto error;
2508
2509         *temp = ((val & 0x1f) - 5) * 5;
2510
2511 error:
2512         _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2513         mutex_unlock(&ps->smi_mutex);
2514         return ret;
2515 }
2516
2517 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2518 {
2519         int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2520         int ret;
2521
2522         *temp = 0;
2523
2524         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2525         if (ret < 0)
2526                 return ret;
2527
2528         *temp = (ret & 0xff) - 25;
2529
2530         return 0;
2531 }
2532
2533 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2534 {
2535         if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2536                 return mv88e63xx_get_temp(ds, temp);
2537
2538         return mv88e61xx_get_temp(ds, temp);
2539 }
2540
2541 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2542 {
2543         int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2544         int ret;
2545
2546         if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2547                 return -EOPNOTSUPP;
2548
2549         *temp = 0;
2550
2551         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2552         if (ret < 0)
2553                 return ret;
2554
2555         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2556
2557         return 0;
2558 }
2559
2560 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2561 {
2562         int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2563         int ret;
2564
2565         if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2566                 return -EOPNOTSUPP;
2567
2568         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2569         if (ret < 0)
2570                 return ret;
2571         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2572         return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2573                                         (ret & 0xe0ff) | (temp << 8));
2574 }
2575
2576 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2577 {
2578         int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2579         int ret;
2580
2581         if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2582                 return -EOPNOTSUPP;
2583
2584         *alarm = false;
2585
2586         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2587         if (ret < 0)
2588                 return ret;
2589
2590         *alarm = !!(ret & 0x40);
2591
2592         return 0;
2593 }
2594 #endif /* CONFIG_NET_DSA_HWMON */
2595
2596 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2597                             const struct mv88e6xxx_switch_id *table,
2598                             unsigned int num)
2599 {
2600         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2601         int i, ret;
2602
2603         if (!bus)
2604                 return NULL;
2605
2606         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2607         if (ret < 0)
2608                 return NULL;
2609
2610         /* Look up the exact switch ID */
2611         for (i = 0; i < num; ++i)
2612                 if (table[i].id == ret)
2613                         return table[i].name;
2614
2615         /* Look up only the product number */
2616         for (i = 0; i < num; ++i) {
2617                 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2618                         dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2619                                  ret & PORT_SWITCH_ID_REV_MASK,
2620                                  ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2621                         return table[i].name;
2622                 }
2623         }
2624
2625         return NULL;
2626 }
2627
2628 static int __init mv88e6xxx_init(void)
2629 {
2630 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2631         register_switch_driver(&mv88e6131_switch_driver);
2632 #endif
2633 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2634         register_switch_driver(&mv88e6123_61_65_switch_driver);
2635 #endif
2636 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2637         register_switch_driver(&mv88e6352_switch_driver);
2638 #endif
2639 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2640         register_switch_driver(&mv88e6171_switch_driver);
2641 #endif
2642         return 0;
2643 }
2644 module_init(mv88e6xxx_init);
2645
2646 static void __exit mv88e6xxx_cleanup(void)
2647 {
2648 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2649         unregister_switch_driver(&mv88e6171_switch_driver);
2650 #endif
2651 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2652         unregister_switch_driver(&mv88e6352_switch_driver);
2653 #endif
2654 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2655         unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2656 #endif
2657 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2658         unregister_switch_driver(&mv88e6131_switch_driver);
2659 #endif
2660 }
2661 module_exit(mv88e6xxx_cleanup);
2662
2663 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2664 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2665 MODULE_LICENSE("GPL");