drivers/net/dsa/mv88e6xxx.h

   1 /*
   2  * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #ifndef __MV88E6XXX_H
  12 #define __MV88E6XXX_H
  13
  14 #include <linux/if_vlan.h>
  15
  16 #ifndef UINT64_MAX
  17 #define UINT64_MAX              (u64)(~((u64)0))
  18 #endif
  19
  20 #define SMI_CMD                 0x00
  21 #define SMI_CMD_BUSY            BIT(15)
  22 #define SMI_CMD_CLAUSE_22       BIT(12)
  23 #define SMI_CMD_OP_22_WRITE     ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  24 #define SMI_CMD_OP_22_READ      ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  25 #define SMI_CMD_OP_45_WRITE_ADDR        ((0 << 10) | SMI_CMD_BUSY)
  26 #define SMI_CMD_OP_45_WRITE_DATA        ((1 << 10) | SMI_CMD_BUSY)
  27 #define SMI_CMD_OP_45_READ_DATA         ((2 << 10) | SMI_CMD_BUSY)
  28 #define SMI_CMD_OP_45_READ_DATA_INC     ((3 << 10) | SMI_CMD_BUSY)
  29 #define SMI_DATA                0x01
  30
  31 /* Fiber/SERDES Registers are located at SMI address F, page 1 */
  32 #define REG_FIBER_SERDES        0x0f
  33 #define PAGE_FIBER_SERDES       0x01
  34
  35 #define REG_PORT(p)             (0x10 + (p))
  36 #define PORT_STATUS             0x00
  37 #define PORT_STATUS_PAUSE_EN    BIT(15)
  38 #define PORT_STATUS_MY_PAUSE    BIT(14)
  39 #define PORT_STATUS_HD_FLOW     BIT(13)
  40 #define PORT_STATUS_PHY_DETECT  BIT(12)
  41 #define PORT_STATUS_LINK        BIT(11)
  42 #define PORT_STATUS_DUPLEX      BIT(10)
  43 #define PORT_STATUS_SPEED_MASK  0x0300
  44 #define PORT_STATUS_SPEED_10    0x0000
  45 #define PORT_STATUS_SPEED_100   0x0100
  46 #define PORT_STATUS_SPEED_1000  0x0200
  47 #define PORT_STATUS_EEE         BIT(6) /* 6352 */
  48 #define PORT_STATUS_AM_DIS      BIT(6) /* 6165 */
  49 #define PORT_STATUS_MGMII       BIT(6) /* 6185 */
  50 #define PORT_STATUS_TX_PAUSED   BIT(5)
  51 #define PORT_STATUS_FLOW_CTRL   BIT(4)
  52 #define PORT_STATUS_CMODE_MASK  0x0f
  53 #define PORT_STATUS_CMODE_100BASE_X     0x8
  54 #define PORT_STATUS_CMODE_1000BASE_X    0x9
  55 #define PORT_STATUS_CMODE_SGMII         0xa
  56 #define PORT_PCS_CTRL           0x01
  57 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
  58 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
  59 #define PORT_PCS_CTRL_FC                BIT(7)
  60 #define PORT_PCS_CTRL_FORCE_FC          BIT(6)
  61 #define PORT_PCS_CTRL_LINK_UP           BIT(5)
  62 #define PORT_PCS_CTRL_FORCE_LINK        BIT(4)
  63 #define PORT_PCS_CTRL_DUPLEX_FULL       BIT(3)
  64 #define PORT_PCS_CTRL_FORCE_DUPLEX      BIT(2)
  65 #define PORT_PCS_CTRL_10                0x00
  66 #define PORT_PCS_CTRL_100               0x01
  67 #define PORT_PCS_CTRL_1000              0x02
  68 #define PORT_PCS_CTRL_UNFORCED          0x03
  69 #define PORT_PAUSE_CTRL         0x02
  70 #define PORT_SWITCH_ID          0x03
  71 #define PORT_SWITCH_ID_PROD_NUM_6085    0x04a
  72 #define PORT_SWITCH_ID_PROD_NUM_6095    0x095
  73 #define PORT_SWITCH_ID_PROD_NUM_6131    0x106
  74 #define PORT_SWITCH_ID_PROD_NUM_6320    0x115
  75 #define PORT_SWITCH_ID_PROD_NUM_6123    0x121
  76 #define PORT_SWITCH_ID_PROD_NUM_6161    0x161
  77 #define PORT_SWITCH_ID_PROD_NUM_6165    0x165
  78 #define PORT_SWITCH_ID_PROD_NUM_6171    0x171
  79 #define PORT_SWITCH_ID_PROD_NUM_6172    0x172
  80 #define PORT_SWITCH_ID_PROD_NUM_6175    0x175
  81 #define PORT_SWITCH_ID_PROD_NUM_6176    0x176
  82 #define PORT_SWITCH_ID_PROD_NUM_6185    0x1a7
  83 #define PORT_SWITCH_ID_PROD_NUM_6240    0x240
  84 #define PORT_SWITCH_ID_PROD_NUM_6321    0x310
  85 #define PORT_SWITCH_ID_PROD_NUM_6352    0x352
  86 #define PORT_SWITCH_ID_PROD_NUM_6350    0x371
  87 #define PORT_SWITCH_ID_PROD_NUM_6351    0x375
  88 #define PORT_CONTROL            0x04
  89 #define PORT_CONTROL_USE_CORE_TAG       BIT(15)
  90 #define PORT_CONTROL_DROP_ON_LOCK       BIT(14)
  91 #define PORT_CONTROL_EGRESS_UNMODIFIED  (0x0 << 12)
  92 #define PORT_CONTROL_EGRESS_UNTAGGED    (0x1 << 12)
  93 #define PORT_CONTROL_EGRESS_TAGGED      (0x2 << 12)
  94 #define PORT_CONTROL_EGRESS_ADD_TAG     (0x3 << 12)
  95 #define PORT_CONTROL_HEADER             BIT(11)
  96 #define PORT_CONTROL_IGMP_MLD_SNOOP     BIT(10)
  97 #define PORT_CONTROL_DOUBLE_TAG         BIT(9)
  98 #define PORT_CONTROL_FRAME_MODE_NORMAL          (0x0 << 8)
  99 #define PORT_CONTROL_FRAME_MODE_DSA             (0x1 << 8)
 100 #define PORT_CONTROL_FRAME_MODE_PROVIDER        (0x2 << 8)
 101 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA       (0x3 << 8)
 102 #define PORT_CONTROL_DSA_TAG            BIT(8)
 103 #define PORT_CONTROL_VLAN_TUNNEL        BIT(7)
 104 #define PORT_CONTROL_TAG_IF_BOTH        BIT(6)
 105 #define PORT_CONTROL_USE_IP             BIT(5)
 106 #define PORT_CONTROL_USE_TAG            BIT(4)
 107 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
 108 #define PORT_CONTROL_FORWARD_UNKNOWN    BIT(2)
 109 #define PORT_CONTROL_STATE_MASK         0x03
 110 #define PORT_CONTROL_STATE_DISABLED     0x00
 111 #define PORT_CONTROL_STATE_BLOCKING     0x01
 112 #define PORT_CONTROL_STATE_LEARNING     0x02
 113 #define PORT_CONTROL_STATE_FORWARDING   0x03
 114 #define PORT_CONTROL_1          0x05
 115 #define PORT_CONTROL_1_FID_11_4_MASK    (0xff << 0)
 116 #define PORT_BASE_VLAN          0x06
 117 #define PORT_BASE_VLAN_FID_3_0_MASK     (0xf << 12)
 118 #define PORT_DEFAULT_VLAN       0x07
 119 #define PORT_DEFAULT_VLAN_MASK  0xfff
 120 #define PORT_CONTROL_2          0x08
 121 #define PORT_CONTROL_2_IGNORE_FCS       BIT(15)
 122 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
 123 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
 124 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
 125 #define PORT_CONTROL_2_JUMBO_1522       (0x00 << 12)
 126 #define PORT_CONTROL_2_JUMBO_2048       (0x01 << 12)
 127 #define PORT_CONTROL_2_JUMBO_10240      (0x02 << 12)
 128 #define PORT_CONTROL_2_8021Q_MASK       (0x03 << 10)
 129 #define PORT_CONTROL_2_8021Q_DISABLED   (0x00 << 10)
 130 #define PORT_CONTROL_2_8021Q_FALLBACK   (0x01 << 10)
 131 #define PORT_CONTROL_2_8021Q_CHECK      (0x02 << 10)
 132 #define PORT_CONTROL_2_8021Q_SECURE     (0x03 << 10)
 133 #define PORT_CONTROL_2_DISCARD_TAGGED   BIT(9)
 134 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
 135 #define PORT_CONTROL_2_MAP_DA           BIT(7)
 136 #define PORT_CONTROL_2_DEFAULT_FORWARD  BIT(6)
 137 #define PORT_CONTROL_2_FORWARD_UNKNOWN  BIT(6)
 138 #define PORT_CONTROL_2_EGRESS_MONITOR   BIT(5)
 139 #define PORT_CONTROL_2_INGRESS_MONITOR  BIT(4)
 140 #define PORT_RATE_CONTROL       0x09
 141 #define PORT_RATE_CONTROL_2     0x0a
 142 #define PORT_ASSOC_VECTOR       0x0b
 143 #define PORT_ASSOC_VECTOR_HOLD_AT_1             BIT(15)
 144 #define PORT_ASSOC_VECTOR_INT_AGE_OUT           BIT(14)
 145 #define PORT_ASSOC_VECTOR_LOCKED_PORT           BIT(13)
 146 #define PORT_ASSOC_VECTOR_IGNORE_WRONG          BIT(12)
 147 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED        BIT(11)
 148 #define PORT_ATU_CONTROL        0x0c
 149 #define PORT_PRI_OVERRIDE       0x0d
 150 #define PORT_ETH_TYPE           0x0f
 151 #define PORT_IN_DISCARD_LO      0x10
 152 #define PORT_IN_DISCARD_HI      0x11
 153 #define PORT_IN_FILTERED        0x12
 154 #define PORT_OUT_FILTERED       0x13
 155 #define PORT_TAG_REGMAP_0123    0x18
 156 #define PORT_TAG_REGMAP_4567    0x19
 157
 158 #define REG_GLOBAL              0x1b
 159 #define GLOBAL_STATUS           0x00
 160 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
 161 /* Two bits for 6165, 6185 etc */
 162 #define GLOBAL_STATUS_PPU_MASK          (0x3 << 14)
 163 #define GLOBAL_STATUS_PPU_DISABLED_RST  (0x0 << 14)
 164 #define GLOBAL_STATUS_PPU_INITIALIZING  (0x1 << 14)
 165 #define GLOBAL_STATUS_PPU_DISABLED      (0x2 << 14)
 166 #define GLOBAL_STATUS_PPU_POLLING       (0x3 << 14)
 167 #define GLOBAL_MAC_01           0x01
 168 #define GLOBAL_MAC_23           0x02
 169 #define GLOBAL_MAC_45           0x03
 170 #define GLOBAL_ATU_FID          0x01    /* 6097 6165 6351 6352 */
 171 #define GLOBAL_VTU_FID          0x02    /* 6097 6165 6351 6352 */
 172 #define GLOBAL_VTU_FID_MASK     0xfff
 173 #define GLOBAL_VTU_SID          0x03    /* 6097 6165 6351 6352 */
 174 #define GLOBAL_VTU_SID_MASK     0x3f
 175 #define GLOBAL_CONTROL          0x04
 176 #define GLOBAL_CONTROL_SW_RESET         BIT(15)
 177 #define GLOBAL_CONTROL_PPU_ENABLE       BIT(14)
 178 #define GLOBAL_CONTROL_DISCARD_EXCESS   BIT(13) /* 6352 */
 179 #define GLOBAL_CONTROL_SCHED_PRIO       BIT(11) /* 6152 */
 180 #define GLOBAL_CONTROL_MAX_FRAME_1632   BIT(10) /* 6152 */
 181 #define GLOBAL_CONTROL_RELOAD_EEPROM    BIT(9)  /* 6152 */
 182 #define GLOBAL_CONTROL_DEVICE_EN        BIT(7)
 183 #define GLOBAL_CONTROL_STATS_DONE_EN    BIT(6)
 184 #define GLOBAL_CONTROL_VTU_PROBLEM_EN   BIT(5)
 185 #define GLOBAL_CONTROL_VTU_DONE_EN      BIT(4)
 186 #define GLOBAL_CONTROL_ATU_PROBLEM_EN   BIT(3)
 187 #define GLOBAL_CONTROL_ATU_DONE_EN      BIT(2)
 188 #define GLOBAL_CONTROL_TCAM_EN          BIT(1)
 189 #define GLOBAL_CONTROL_EEPROM_DONE_EN   BIT(0)
 190 #define GLOBAL_VTU_OP           0x05
 191 #define GLOBAL_VTU_OP_BUSY      BIT(15)
 192 #define GLOBAL_VTU_OP_FLUSH_ALL         ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
 193 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE    ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
 194 #define GLOBAL_VTU_OP_VTU_GET_NEXT      ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
 195 #define GLOBAL_VTU_OP_STU_LOAD_PURGE    ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
 196 #define GLOBAL_VTU_OP_STU_GET_NEXT      ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
 197 #define GLOBAL_VTU_VID          0x06
 198 #define GLOBAL_VTU_VID_MASK     0xfff
 199 #define GLOBAL_VTU_VID_VALID    BIT(12)
 200 #define GLOBAL_VTU_DATA_0_3     0x07
 201 #define GLOBAL_VTU_DATA_4_7     0x08
 202 #define GLOBAL_VTU_DATA_8_11    0x09
 203 #define GLOBAL_VTU_STU_DATA_MASK                0x03
 204 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED   0x00
 205 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED     0x01
 206 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED       0x02
 207 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER   0x03
 208 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED     0x00
 209 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING     0x01
 210 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING     0x02
 211 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING   0x03
 212 #define GLOBAL_ATU_CONTROL      0x0a
 213 #define GLOBAL_ATU_CONTROL_LEARN2ALL    BIT(3)
 214 #define GLOBAL_ATU_OP           0x0b
 215 #define GLOBAL_ATU_OP_BUSY      BIT(15)
 216 #define GLOBAL_ATU_OP_NOP               (0 << 12)
 217 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL            ((1 << 12) | GLOBAL_ATU_OP_BUSY)
 218 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC     ((2 << 12) | GLOBAL_ATU_OP_BUSY)
 219 #define GLOBAL_ATU_OP_LOAD_DB           ((3 << 12) | GLOBAL_ATU_OP_BUSY)
 220 #define GLOBAL_ATU_OP_GET_NEXT_DB       ((4 << 12) | GLOBAL_ATU_OP_BUSY)
 221 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB         ((5 << 12) | GLOBAL_ATU_OP_BUSY)
 222 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
 223 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION   ((7 << 12) | GLOBAL_ATU_OP_BUSY)
 224 #define GLOBAL_ATU_DATA         0x0c
 225 #define GLOBAL_ATU_DATA_TRUNK                   BIT(15)
 226 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK           0x00f0
 227 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT          4
 228 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK        0x3ff0
 229 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT       4
 230 #define GLOBAL_ATU_DATA_STATE_MASK              0x0f
 231 #define GLOBAL_ATU_DATA_STATE_UNUSED            0x00
 232 #define GLOBAL_ATU_DATA_STATE_UC_MGMT           0x0d
 233 #define GLOBAL_ATU_DATA_STATE_UC_STATIC         0x0e
 234 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER      0x0f
 235 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE      0x05
 236 #define GLOBAL_ATU_DATA_STATE_MC_STATIC         0x07
 237 #define GLOBAL_ATU_DATA_STATE_MC_MGMT           0x0e
 238 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER      0x0f
 239 #define GLOBAL_ATU_MAC_01       0x0d
 240 #define GLOBAL_ATU_MAC_23       0x0e
 241 #define GLOBAL_ATU_MAC_45       0x0f
 242 #define GLOBAL_IP_PRI_0         0x10
 243 #define GLOBAL_IP_PRI_1         0x11
 244 #define GLOBAL_IP_PRI_2         0x12
 245 #define GLOBAL_IP_PRI_3         0x13
 246 #define GLOBAL_IP_PRI_4         0x14
 247 #define GLOBAL_IP_PRI_5         0x15
 248 #define GLOBAL_IP_PRI_6         0x16
 249 #define GLOBAL_IP_PRI_7         0x17
 250 #define GLOBAL_IEEE_PRI         0x18
 251 #define GLOBAL_CORE_TAG_TYPE    0x19
 252 #define GLOBAL_MONITOR_CONTROL  0x1a
 253 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT    12
 254 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT     8
 255 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT        4
 256 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT     0
 257 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED     (0xf0)
 258 #define GLOBAL_CONTROL_2        0x1c
 259 #define GLOBAL_CONTROL_2_NO_CASCADE             0xe000
 260 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE       0xf000
 261
 262 #define GLOBAL_STATS_OP         0x1d
 263 #define GLOBAL_STATS_OP_BUSY    BIT(15)
 264 #define GLOBAL_STATS_OP_NOP             (0 << 12)
 265 #define GLOBAL_STATS_OP_FLUSH_ALL       ((1 << 12) | GLOBAL_STATS_OP_BUSY)
 266 #define GLOBAL_STATS_OP_FLUSH_PORT      ((2 << 12) | GLOBAL_STATS_OP_BUSY)
 267 #define GLOBAL_STATS_OP_READ_CAPTURED   ((4 << 12) | GLOBAL_STATS_OP_BUSY)
 268 #define GLOBAL_STATS_OP_CAPTURE_PORT    ((5 << 12) | GLOBAL_STATS_OP_BUSY)
 269 #define GLOBAL_STATS_OP_HIST_RX         ((1 << 10) | GLOBAL_STATS_OP_BUSY)
 270 #define GLOBAL_STATS_OP_HIST_TX         ((2 << 10) | GLOBAL_STATS_OP_BUSY)
 271 #define GLOBAL_STATS_OP_HIST_RX_TX      ((3 << 10) | GLOBAL_STATS_OP_BUSY)
 272 #define GLOBAL_STATS_OP_BANK_1  BIT(9)
 273 #define GLOBAL_STATS_COUNTER_32 0x1e
 274 #define GLOBAL_STATS_COUNTER_01 0x1f
 275
 276 #define REG_GLOBAL2             0x1c
 277 #define GLOBAL2_INT_SOURCE      0x00
 278 #define GLOBAL2_INT_MASK        0x01
 279 #define GLOBAL2_MGMT_EN_2X      0x02
 280 #define GLOBAL2_MGMT_EN_0X      0x03
 281 #define GLOBAL2_FLOW_CONTROL    0x04
 282 #define GLOBAL2_SWITCH_MGMT     0x05
 283 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
 284 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS       BIT(14)
 285 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG    BIT(13)
 286 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
 287 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU            BIT(3)
 288 #define GLOBAL2_DEVICE_MAPPING  0x06
 289 #define GLOBAL2_DEVICE_MAPPING_UPDATE           BIT(15)
 290 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT     8
 291 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK        0x0f
 292 #define GLOBAL2_TRUNK_MASK      0x07
 293 #define GLOBAL2_TRUNK_MASK_UPDATE               BIT(15)
 294 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT            12
 295 #define GLOBAL2_TRUNK_MAPPING   0x08
 296 #define GLOBAL2_TRUNK_MAPPING_UPDATE            BIT(15)
 297 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT          11
 298 #define GLOBAL2_INGRESS_OP      0x09
 299 #define GLOBAL2_INGRESS_DATA    0x0a
 300 #define GLOBAL2_PVT_ADDR        0x0b
 301 #define GLOBAL2_PVT_DATA        0x0c
 302 #define GLOBAL2_SWITCH_MAC      0x0d
 303 #define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
 304 #define GLOBAL2_ATU_STATS       0x0e
 305 #define GLOBAL2_PRIO_OVERRIDE   0x0f
 306 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP       BIT(7)
 307 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT       4
 308 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP         BIT(3)
 309 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT         0
 310 #define GLOBAL2_EEPROM_OP       0x14
 311 #define GLOBAL2_EEPROM_OP_BUSY          BIT(15)
 312 #define GLOBAL2_EEPROM_OP_WRITE         ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY)
 313 #define GLOBAL2_EEPROM_OP_READ          ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY)
 314 #define GLOBAL2_EEPROM_OP_LOAD          BIT(11)
 315 #define GLOBAL2_EEPROM_OP_WRITE_EN      BIT(10)
 316 #define GLOBAL2_EEPROM_OP_ADDR_MASK     0xff
 317 #define GLOBAL2_EEPROM_DATA     0x15
 318 #define GLOBAL2_PTP_AVB_OP      0x16
 319 #define GLOBAL2_PTP_AVB_DATA    0x17
 320 #define GLOBAL2_SMI_OP          0x18
 321 #define GLOBAL2_SMI_OP_BUSY             BIT(15)
 322 #define GLOBAL2_SMI_OP_CLAUSE_22        BIT(12)
 323 #define GLOBAL2_SMI_OP_22_WRITE         ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
 324                                          GLOBAL2_SMI_OP_CLAUSE_22)
 325 #define GLOBAL2_SMI_OP_22_READ          ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
 326                                          GLOBAL2_SMI_OP_CLAUSE_22)
 327 #define GLOBAL2_SMI_OP_45_WRITE_ADDR    ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
 328 #define GLOBAL2_SMI_OP_45_WRITE_DATA    ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
 329 #define GLOBAL2_SMI_OP_45_READ_DATA     ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
 330 #define GLOBAL2_SMI_DATA        0x19
 331 #define GLOBAL2_SCRATCH_MISC    0x1a
 332 #define GLOBAL2_SCRATCH_BUSY            BIT(15)
 333 #define GLOBAL2_SCRATCH_REGISTER_SHIFT  8
 334 #define GLOBAL2_SCRATCH_VALUE_MASK      0xff
 335 #define GLOBAL2_WDOG_CONTROL    0x1b
 336 #define GLOBAL2_QOS_WEIGHT      0x1c
 337 #define GLOBAL2_MISC            0x1d
 338
 339 #define MV88E6XXX_N_FID         4096
 340
 341 enum mv88e6xxx_family {
 342         MV88E6XXX_FAMILY_NONE,
 343         MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
 344         MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
 345         MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
 346         MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
 347         MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
 348         MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
 349         MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
 350         MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
 351 };
 352
 353 enum mv88e6xxx_cap {
 354         /* EEPROM Command and Data registers.
 355          * See GLOBAL2_EEPROM_OP and GLOBAL2_EEPROM_DATA.
 356          */
 357         MV88E6XXX_CAP_EEPROM,
 358
 359         /* PHY Polling Unit.
 360          * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
 361          */
 362         MV88E6XXX_CAP_PPU,
 363
 364         /* SMI PHY Command and Data registers.
 365          * This requires an indirect access to PHY registers through
 366          * GLOBAL2_SMI_OP, otherwise direct access to PHY registers is done.
 367          */
 368         MV88E6XXX_CAP_SMI_PHY,
 369
 370         /* Internal temperature sensor.
 371          * Available from any enabled port's PHY register 26, page 6.
 372          */
 373         MV88E6XXX_CAP_TEMP,
 374         MV88E6XXX_CAP_TEMP_LIMIT,
 375 };
 376
 377 /* Bitmask of capabilities */
 378 #define MV88E6XXX_FLAG_EEPROM           BIT(MV88E6XXX_CAP_EEPROM)
 379 #define MV88E6XXX_FLAG_PPU              BIT(MV88E6XXX_CAP_PPU)
 380 #define MV88E6XXX_FLAG_SMI_PHY          BIT(MV88E6XXX_CAP_SMI_PHY)
 381 #define MV88E6XXX_FLAG_TEMP             BIT(MV88E6XXX_CAP_TEMP)
 382 #define MV88E6XXX_FLAG_TEMP_LIMIT       BIT(MV88E6XXX_CAP_TEMP_LIMIT)
 383
 384 #define MV88E6XXX_FLAGS_FAMILY_6095     \
 385         MV88E6XXX_FLAG_PPU
 386
 387 #define MV88E6XXX_FLAGS_FAMILY_6097     \
 388         MV88E6XXX_FLAG_PPU
 389
 390 #define MV88E6XXX_FLAGS_FAMILY_6165     \
 391         MV88E6XXX_FLAG_TEMP
 392
 393 #define MV88E6XXX_FLAGS_FAMILY_6185     \
 394         MV88E6XXX_FLAG_PPU
 395
 396 #define MV88E6XXX_FLAGS_FAMILY_6320     \
 397         (MV88E6XXX_FLAG_EEPROM |        \
 398          MV88E6XXX_FLAG_SMI_PHY |       \
 399          MV88E6XXX_FLAG_TEMP |          \
 400          MV88E6XXX_FLAG_TEMP_LIMIT)
 401
 402 #define MV88E6XXX_FLAGS_FAMILY_6351     \
 403         (MV88E6XXX_FLAG_SMI_PHY |       \
 404          MV88E6XXX_FLAG_TEMP)
 405
 406 #define MV88E6XXX_FLAGS_FAMILY_6352     \
 407         (MV88E6XXX_FLAG_EEPROM |        \
 408          MV88E6XXX_FLAG_SMI_PHY |       \
 409          MV88E6XXX_FLAG_TEMP |          \
 410          MV88E6XXX_FLAG_TEMP_LIMIT)
 411
 412 struct mv88e6xxx_info {
 413         enum mv88e6xxx_family family;
 414         u16 prod_num;
 415         const char *name;
 416         unsigned int num_databases;
 417         unsigned int num_ports;
 418         unsigned long flags;
 419 };
 420
 421 struct mv88e6xxx_atu_entry {
 422         u16     fid;
 423         u8      state;
 424         bool    trunk;
 425         u16     portv_trunkid;
 426         u8      mac[ETH_ALEN];
 427 };
 428
 429 struct mv88e6xxx_vtu_stu_entry {
 430         /* VTU only */
 431         u16     vid;
 432         u16     fid;
 433
 434         /* VTU and STU */
 435         u8      sid;
 436         bool    valid;
 437         u8      data[DSA_MAX_PORTS];
 438 };
 439
 440 struct mv88e6xxx_priv_port {
 441         struct net_device *bridge_dev;
 442         u8 state;
 443 };
 444
 445 struct mv88e6xxx_priv_state {
 446         const struct mv88e6xxx_info *info;
 447
 448         /* The dsa_switch this private structure is related to */
 449         struct dsa_switch *ds;
 450
 451         /* The device this structure is associated to */
 452         struct device *dev;
 453
 454         /* When using multi-chip addressing, this mutex protects
 455          * access to the indirect access registers.  (In single-chip
 456          * mode, this mutex is effectively useless.)
 457          */
 458         struct mutex    smi_mutex;
 459
 460         /* The MII bus and the address on the bus that is used to
 461          * communication with the switch
 462          */
 463         struct mii_bus *bus;
 464         int sw_addr;
 465
 466         /* Handles automatic disabling and re-enabling of the PHY
 467          * polling unit.
 468          */
 469         struct mutex            ppu_mutex;
 470         int                     ppu_disabled;
 471         struct work_struct      ppu_work;
 472         struct timer_list       ppu_timer;
 473
 474         /* This mutex serialises access to the statistics unit.
 475          * Hold this mutex over snapshot + dump sequences.
 476          */
 477         struct mutex    stats_mutex;
 478
 479         /* This mutex serializes phy access for chips with
 480          * indirect phy addressing. It is unused for chips
 481          * with direct phy access.
 482          */
 483         struct mutex    phy_mutex;
 484
 485         /* This mutex serializes eeprom access for chips with
 486          * eeprom support.
 487          */
 488         struct mutex eeprom_mutex;
 489
 490         struct mv88e6xxx_priv_port      ports[DSA_MAX_PORTS];
 491
 492         DECLARE_BITMAP(port_state_update_mask, DSA_MAX_PORTS);
 493
 494         struct work_struct bridge_work;
 495 };
 496
 497 enum stat_type {
 498         BANK0,
 499         BANK1,
 500         PORT,
 501 };
 502
 503 struct mv88e6xxx_hw_stat {
 504         char string[ETH_GSTRING_LEN];
 505         int sizeof_stat;
 506         int reg;
 507         enum stat_type type;
 508 };
 509
 510 static inline bool mv88e6xxx_has(struct mv88e6xxx_priv_state *ps,
 511                                  unsigned long flags)
 512 {
 513         return (ps->info->flags & flags) == flags;
 514 }
 515
 516 int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps, bool ppu_active);
 517 const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
 518                                 int sw_addr, void **priv,
 519                                 const struct mv88e6xxx_info *table,
 520                                 unsigned int num);
 521
 522 int mv88e6xxx_setup_ports(struct dsa_switch *ds);
 523 int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps);
 524 int mv88e6xxx_setup_global(struct dsa_switch *ds);
 525 int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg);
 526 int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
 527                         int reg, u16 val);
 528 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
 529 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
 530 int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
 531 int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
 532 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
 533 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 534                                  uint64_t *data);
 535 int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
 536 int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
 537 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 538                            struct phy_device *phydev);
 539 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
 540 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 541                         struct ethtool_regs *regs, void *_p);
 542 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
 543 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp);
 544 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp);
 545 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm);
 546 int mv88e6xxx_get_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
 547                          u8 *data);
 548 int mv88e6xxx_set_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
 549                          u8 *data);
 550 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
 551 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 552                       struct phy_device *phydev, struct ethtool_eee *e);
 553 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
 554                                struct net_device *bridge);
 555 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port);
 556 void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 557 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
 558                                   bool vlan_filtering);
 559 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
 560                                 const struct switchdev_obj_port_vlan *vlan,
 561                                 struct switchdev_trans *trans);
 562 void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
 563                              const struct switchdev_obj_port_vlan *vlan,
 564                              struct switchdev_trans *trans);
 565 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
 566                             const struct switchdev_obj_port_vlan *vlan);
 567 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
 568                              struct switchdev_obj_port_vlan *vlan,
 569                              int (*cb)(struct switchdev_obj *obj));
 570 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
 571                                const struct switchdev_obj_port_fdb *fdb,
 572                                struct switchdev_trans *trans);
 573 void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
 574                             const struct switchdev_obj_port_fdb *fdb,
 575                             struct switchdev_trans *trans);
 576 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
 577                            const struct switchdev_obj_port_fdb *fdb);
 578 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
 579                             struct switchdev_obj_port_fdb *fdb,
 580                             int (*cb)(struct switchdev_obj *obj));
 581 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
 582 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
 583                              int reg, int val);
 584
 585 extern struct dsa_switch_driver mv88e6131_switch_driver;
 586 extern struct dsa_switch_driver mv88e6123_switch_driver;
 587 extern struct dsa_switch_driver mv88e6352_switch_driver;
 588 extern struct dsa_switch_driver mv88e6171_switch_driver;
 589
 590 #endif