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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / dsa / ocelot / felix_vsc9959.c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2017 Microsemi Corporation
3 * Copyright 2018-2019 NXP Semiconductors
4 */
5 #include <linux/fsl/enetc_mdio.h>
6 #include <soc/mscc/ocelot_qsys.h>
7 #include <soc/mscc/ocelot_vcap.h>
8 #include <soc/mscc/ocelot_ptp.h>
9 #include <soc/mscc/ocelot_sys.h>
10 #include <soc/mscc/ocelot.h>
11 #include <net/pkt_sched.h>
12 #include <linux/iopoll.h>
13 #include <linux/pci.h>
14 #include "felix.h"
15
16 #define VSC9959_VCAP_IS2_CNT 1024
17 #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376
18 #define VSC9959_VCAP_PORT_CNT 6
19
20 /* TODO: should find a better place for these */
21 #define USXGMII_BMCR_RESET BIT(15)
22 #define USXGMII_BMCR_AN_EN BIT(12)
23 #define USXGMII_BMCR_RST_AN BIT(9)
24 #define USXGMII_BMSR_LNKS(status) (((status) & GENMASK(2, 2)) >> 2)
25 #define USXGMII_BMSR_AN_CMPL(status) (((status) & GENMASK(5, 5)) >> 5)
26 #define USXGMII_ADVERTISE_LNKS(x) (((x) << 15) & BIT(15))
27 #define USXGMII_ADVERTISE_FDX BIT(12)
28 #define USXGMII_ADVERTISE_SPEED(x) (((x) << 9) & GENMASK(11, 9))
29 #define USXGMII_LPA_LNKS(lpa) ((lpa) >> 15)
30 #define USXGMII_LPA_DUPLEX(lpa) (((lpa) & GENMASK(12, 12)) >> 12)
31 #define USXGMII_LPA_SPEED(lpa) (((lpa) & GENMASK(11, 9)) >> 9)
32
33 #define VSC9959_TAS_GCL_ENTRY_MAX 63
34
35 enum usxgmii_speed {
36 USXGMII_SPEED_10 = 0,
37 USXGMII_SPEED_100 = 1,
38 USXGMII_SPEED_1000 = 2,
39 USXGMII_SPEED_2500 = 4,
40 };
41
42 static const u32 vsc9959_ana_regmap[] = {
43 REG(ANA_ADVLEARN, 0x0089a0),
44 REG(ANA_VLANMASK, 0x0089a4),
45 REG_RESERVED(ANA_PORT_B_DOMAIN),
46 REG(ANA_ANAGEFIL, 0x0089ac),
47 REG(ANA_ANEVENTS, 0x0089b0),
48 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
49 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
50 REG(ANA_ISOLATED_PORTS, 0x0089c8),
51 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
52 REG(ANA_AUTOAGE, 0x0089d0),
53 REG(ANA_MACTOPTIONS, 0x0089d4),
54 REG(ANA_LEARNDISC, 0x0089d8),
55 REG(ANA_AGENCTRL, 0x0089dc),
56 REG(ANA_MIRRORPORTS, 0x0089e0),
57 REG(ANA_EMIRRORPORTS, 0x0089e4),
58 REG(ANA_FLOODING, 0x0089e8),
59 REG(ANA_FLOODING_IPMC, 0x008a08),
60 REG(ANA_SFLOW_CFG, 0x008a0c),
61 REG(ANA_PORT_MODE, 0x008a28),
62 REG(ANA_CUT_THRU_CFG, 0x008a48),
63 REG(ANA_PGID_PGID, 0x008400),
64 REG(ANA_TABLES_ANMOVED, 0x007f1c),
65 REG(ANA_TABLES_MACHDATA, 0x007f20),
66 REG(ANA_TABLES_MACLDATA, 0x007f24),
67 REG(ANA_TABLES_STREAMDATA, 0x007f28),
68 REG(ANA_TABLES_MACACCESS, 0x007f2c),
69 REG(ANA_TABLES_MACTINDX, 0x007f30),
70 REG(ANA_TABLES_VLANACCESS, 0x007f34),
71 REG(ANA_TABLES_VLANTIDX, 0x007f38),
72 REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
73 REG(ANA_TABLES_ISDXTIDX, 0x007f40),
74 REG(ANA_TABLES_ENTRYLIM, 0x007f00),
75 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
76 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
77 REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
78 REG(ANA_TABLES_STREAMTIDX, 0x007f50),
79 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
80 REG(ANA_TABLES_SEQ_MASK, 0x007f58),
81 REG(ANA_TABLES_SFID_MASK, 0x007f5c),
82 REG(ANA_TABLES_SFIDACCESS, 0x007f60),
83 REG(ANA_TABLES_SFIDTIDX, 0x007f64),
84 REG(ANA_MSTI_STATE, 0x008600),
85 REG(ANA_OAM_UPM_LM_CNT, 0x008000),
86 REG(ANA_SG_ACCESS_CTRL, 0x008a64),
87 REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
88 REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
89 REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
90 REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
91 REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
92 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
93 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
94 REG(ANA_SG_STATUS_REG_1, 0x008980),
95 REG(ANA_SG_STATUS_REG_2, 0x008984),
96 REG(ANA_SG_STATUS_REG_3, 0x008988),
97 REG(ANA_PORT_VLAN_CFG, 0x007800),
98 REG(ANA_PORT_DROP_CFG, 0x007804),
99 REG(ANA_PORT_QOS_CFG, 0x007808),
100 REG(ANA_PORT_VCAP_CFG, 0x00780c),
101 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
102 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
103 REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
104 REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
105 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
106 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
107 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
108 REG(ANA_PORT_PORT_CFG, 0x007870),
109 REG(ANA_PORT_POL_CFG, 0x007874),
110 REG(ANA_PORT_PTP_CFG, 0x007878),
111 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
112 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
113 REG(ANA_PORT_SFID_CFG, 0x007884),
114 REG(ANA_PFC_PFC_CFG, 0x008800),
115 REG_RESERVED(ANA_PFC_PFC_TIMER),
116 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
117 REG_RESERVED(ANA_IPT_IPT),
118 REG_RESERVED(ANA_PPT_PPT),
119 REG_RESERVED(ANA_FID_MAP_FID_MAP),
120 REG(ANA_AGGR_CFG, 0x008a68),
121 REG(ANA_CPUQ_CFG, 0x008a6c),
122 REG_RESERVED(ANA_CPUQ_CFG2),
123 REG(ANA_CPUQ_8021_CFG, 0x008a74),
124 REG(ANA_DSCP_CFG, 0x008ab4),
125 REG(ANA_DSCP_REWR_CFG, 0x008bb4),
126 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
127 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
128 REG_RESERVED(ANA_VRAP_CFG),
129 REG_RESERVED(ANA_VRAP_HDR_DATA),
130 REG_RESERVED(ANA_VRAP_HDR_MASK),
131 REG(ANA_DISCARD_CFG, 0x008c40),
132 REG(ANA_FID_CFG, 0x008c44),
133 REG(ANA_POL_PIR_CFG, 0x004000),
134 REG(ANA_POL_CIR_CFG, 0x004004),
135 REG(ANA_POL_MODE_CFG, 0x004008),
136 REG(ANA_POL_PIR_STATE, 0x00400c),
137 REG(ANA_POL_CIR_STATE, 0x004010),
138 REG_RESERVED(ANA_POL_STATE),
139 REG(ANA_POL_FLOWC, 0x008c48),
140 REG(ANA_POL_HYST, 0x008cb4),
141 REG_RESERVED(ANA_POL_MISC_CFG),
142 };
143
144 static const u32 vsc9959_qs_regmap[] = {
145 REG(QS_XTR_GRP_CFG, 0x000000),
146 REG(QS_XTR_RD, 0x000008),
147 REG(QS_XTR_FRM_PRUNING, 0x000010),
148 REG(QS_XTR_FLUSH, 0x000018),
149 REG(QS_XTR_DATA_PRESENT, 0x00001c),
150 REG(QS_XTR_CFG, 0x000020),
151 REG(QS_INJ_GRP_CFG, 0x000024),
152 REG(QS_INJ_WR, 0x00002c),
153 REG(QS_INJ_CTRL, 0x000034),
154 REG(QS_INJ_STATUS, 0x00003c),
155 REG(QS_INJ_ERR, 0x000040),
156 REG_RESERVED(QS_INH_DBG),
157 };
158
159 static const u32 vsc9959_s2_regmap[] = {
160 REG(S2_CORE_UPDATE_CTRL, 0x000000),
161 REG(S2_CORE_MV_CFG, 0x000004),
162 REG(S2_CACHE_ENTRY_DAT, 0x000008),
163 REG(S2_CACHE_MASK_DAT, 0x000108),
164 REG(S2_CACHE_ACTION_DAT, 0x000208),
165 REG(S2_CACHE_CNT_DAT, 0x000308),
166 REG(S2_CACHE_TG_DAT, 0x000388),
167 };
168
169 static const u32 vsc9959_qsys_regmap[] = {
170 REG(QSYS_PORT_MODE, 0x00f460),
171 REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
172 REG(QSYS_STAT_CNT_CFG, 0x00f49c),
173 REG(QSYS_EEE_CFG, 0x00f4a0),
174 REG(QSYS_EEE_THRES, 0x00f4b8),
175 REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
176 REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
177 REG(QSYS_SW_STATUS, 0x00f4c4),
178 REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
179 REG_RESERVED(QSYS_PAD_CFG),
180 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
181 REG_RESERVED(QSYS_QMAP),
182 REG_RESERVED(QSYS_ISDX_SGRP),
183 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
184 REG(QSYS_TFRM_MISC, 0x00f50c),
185 REG(QSYS_TFRM_PORT_DLY, 0x00f510),
186 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
187 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
188 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
189 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
190 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
191 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
192 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
193 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
194 REG(QSYS_RED_PROFILE, 0x00f534),
195 REG(QSYS_RES_QOS_MODE, 0x00f574),
196 REG(QSYS_RES_CFG, 0x00c000),
197 REG(QSYS_RES_STAT, 0x00c004),
198 REG(QSYS_EGR_DROP_MODE, 0x00f578),
199 REG(QSYS_EQ_CTRL, 0x00f57c),
200 REG_RESERVED(QSYS_EVENTS_CORE),
201 REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
202 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
203 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
204 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
205 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
206 REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
207 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
208 REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
209 REG(QSYS_PREEMPTION_CFG, 0x00f664),
210 REG(QSYS_CIR_CFG, 0x000000),
211 REG(QSYS_EIR_CFG, 0x000004),
212 REG(QSYS_SE_CFG, 0x000008),
213 REG(QSYS_SE_DWRR_CFG, 0x00000c),
214 REG_RESERVED(QSYS_SE_CONNECT),
215 REG(QSYS_SE_DLB_SENSE, 0x000040),
216 REG(QSYS_CIR_STATE, 0x000044),
217 REG(QSYS_EIR_STATE, 0x000048),
218 REG_RESERVED(QSYS_SE_STATE),
219 REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
220 REG(QSYS_TAG_CONFIG, 0x00f680),
221 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
222 REG(QSYS_PORT_MAX_SDU, 0x00f69c),
223 REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
224 REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
225 REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
226 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
227 REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
228 REG(QSYS_GCL_CFG_REG_1, 0x00f454),
229 REG(QSYS_GCL_CFG_REG_2, 0x00f458),
230 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
231 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
232 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
233 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
234 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
235 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
236 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
237 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
238 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
239 REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
240 REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
241 };
242
243 static const u32 vsc9959_rew_regmap[] = {
244 REG(REW_PORT_VLAN_CFG, 0x000000),
245 REG(REW_TAG_CFG, 0x000004),
246 REG(REW_PORT_CFG, 0x000008),
247 REG(REW_DSCP_CFG, 0x00000c),
248 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
249 REG(REW_PTP_CFG, 0x000050),
250 REG(REW_PTP_DLY1_CFG, 0x000054),
251 REG(REW_RED_TAG_CFG, 0x000058),
252 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
253 REG(REW_DSCP_REMAP_CFG, 0x000510),
254 REG_RESERVED(REW_STAT_CFG),
255 REG_RESERVED(REW_REW_STICKY),
256 REG_RESERVED(REW_PPT),
257 };
258
259 static const u32 vsc9959_sys_regmap[] = {
260 REG(SYS_COUNT_RX_OCTETS, 0x000000),
261 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
262 REG(SYS_COUNT_RX_SHORTS, 0x000010),
263 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
264 REG(SYS_COUNT_RX_JABBERS, 0x000018),
265 REG(SYS_COUNT_RX_64, 0x000024),
266 REG(SYS_COUNT_RX_65_127, 0x000028),
267 REG(SYS_COUNT_RX_128_255, 0x00002c),
268 REG(SYS_COUNT_RX_256_1023, 0x000030),
269 REG(SYS_COUNT_RX_1024_1526, 0x000034),
270 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
271 REG(SYS_COUNT_RX_LONGS, 0x000044),
272 REG(SYS_COUNT_TX_OCTETS, 0x000200),
273 REG(SYS_COUNT_TX_COLLISION, 0x000210),
274 REG(SYS_COUNT_TX_DROPS, 0x000214),
275 REG(SYS_COUNT_TX_64, 0x00021c),
276 REG(SYS_COUNT_TX_65_127, 0x000220),
277 REG(SYS_COUNT_TX_128_511, 0x000224),
278 REG(SYS_COUNT_TX_512_1023, 0x000228),
279 REG(SYS_COUNT_TX_1024_1526, 0x00022c),
280 REG(SYS_COUNT_TX_1527_MAX, 0x000230),
281 REG(SYS_COUNT_TX_AGING, 0x000278),
282 REG(SYS_RESET_CFG, 0x000e00),
283 REG(SYS_SR_ETYPE_CFG, 0x000e04),
284 REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
285 REG(SYS_PORT_MODE, 0x000e0c),
286 REG(SYS_FRONT_PORT_MODE, 0x000e2c),
287 REG(SYS_FRM_AGING, 0x000e44),
288 REG(SYS_STAT_CFG, 0x000e48),
289 REG(SYS_SW_STATUS, 0x000e4c),
290 REG_RESERVED(SYS_MISC_CFG),
291 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
292 REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
293 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
294 REG(SYS_PAUSE_CFG, 0x000ea0),
295 REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
296 REG(SYS_ATOP, 0x000ec0),
297 REG(SYS_ATOP_TOT_CFG, 0x000edc),
298 REG(SYS_MAC_FC_CFG, 0x000ee0),
299 REG(SYS_MMGT, 0x000ef8),
300 REG_RESERVED(SYS_MMGT_FAST),
301 REG_RESERVED(SYS_EVENTS_DIF),
302 REG_RESERVED(SYS_EVENTS_CORE),
303 REG_RESERVED(SYS_CNT),
304 REG(SYS_PTP_STATUS, 0x000f14),
305 REG(SYS_PTP_TXSTAMP, 0x000f18),
306 REG(SYS_PTP_NXT, 0x000f1c),
307 REG(SYS_PTP_CFG, 0x000f20),
308 REG(SYS_RAM_INIT, 0x000f24),
309 REG_RESERVED(SYS_CM_ADDR),
310 REG_RESERVED(SYS_CM_DATA_WR),
311 REG_RESERVED(SYS_CM_DATA_RD),
312 REG_RESERVED(SYS_CM_OP),
313 REG_RESERVED(SYS_CM_DATA),
314 };
315
316 static const u32 vsc9959_ptp_regmap[] = {
317 REG(PTP_PIN_CFG, 0x000000),
318 REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
319 REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
320 REG(PTP_PIN_TOD_NSEC, 0x00000c),
321 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
322 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
323 REG(PTP_CFG_MISC, 0x0000a0),
324 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
325 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
326 };
327
328 static const u32 vsc9959_gcb_regmap[] = {
329 REG(GCB_SOFT_RST, 0x000004),
330 };
331
332 static const u32 *vsc9959_regmap[] = {
333 [ANA] = vsc9959_ana_regmap,
334 [QS] = vsc9959_qs_regmap,
335 [QSYS] = vsc9959_qsys_regmap,
336 [REW] = vsc9959_rew_regmap,
337 [SYS] = vsc9959_sys_regmap,
338 [S2] = vsc9959_s2_regmap,
339 [PTP] = vsc9959_ptp_regmap,
340 [GCB] = vsc9959_gcb_regmap,
341 };
342
343 /* Addresses are relative to the PCI device's base address */
344 static const struct resource vsc9959_target_io_res[] = {
345 [ANA] = {
346 .start = 0x0280000,
347 .end = 0x028ffff,
348 .name = "ana",
349 },
350 [QS] = {
351 .start = 0x0080000,
352 .end = 0x00800ff,
353 .name = "qs",
354 },
355 [QSYS] = {
356 .start = 0x0200000,
357 .end = 0x021ffff,
358 .name = "qsys",
359 },
360 [REW] = {
361 .start = 0x0030000,
362 .end = 0x003ffff,
363 .name = "rew",
364 },
365 [SYS] = {
366 .start = 0x0010000,
367 .end = 0x001ffff,
368 .name = "sys",
369 },
370 [S2] = {
371 .start = 0x0060000,
372 .end = 0x00603ff,
373 .name = "s2",
374 },
375 [PTP] = {
376 .start = 0x0090000,
377 .end = 0x00900cb,
378 .name = "ptp",
379 },
380 [GCB] = {
381 .start = 0x0070000,
382 .end = 0x00701ff,
383 .name = "devcpu_gcb",
384 },
385 };
386
387 static const struct resource vsc9959_port_io_res[] = {
388 {
389 .start = 0x0100000,
390 .end = 0x010ffff,
391 .name = "port0",
392 },
393 {
394 .start = 0x0110000,
395 .end = 0x011ffff,
396 .name = "port1",
397 },
398 {
399 .start = 0x0120000,
400 .end = 0x012ffff,
401 .name = "port2",
402 },
403 {
404 .start = 0x0130000,
405 .end = 0x013ffff,
406 .name = "port3",
407 },
408 {
409 .start = 0x0140000,
410 .end = 0x014ffff,
411 .name = "port4",
412 },
413 {
414 .start = 0x0150000,
415 .end = 0x015ffff,
416 .name = "port5",
417 },
418 };
419
420 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
421 * SGMII/QSGMII MAC PCS can be found.
422 */
423 static const struct resource vsc9959_imdio_res = {
424 .start = 0x8030,
425 .end = 0x8040,
426 .name = "imdio",
427 };
428
429 static const struct reg_field vsc9959_regfields[] = {
430 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
431 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
432 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
433 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
434 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
435 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
436 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
437 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
438 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
439 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
440 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
441 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
442 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
443 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
444 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
445 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
446 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
447 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
448 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
449 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
450 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
451 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
452 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
453 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
454 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
455 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
456 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
457 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
458 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
459 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
460 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
461 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
462 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
463 };
464
465 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
466 { .offset = 0x00, .name = "rx_octets", },
467 { .offset = 0x01, .name = "rx_unicast", },
468 { .offset = 0x02, .name = "rx_multicast", },
469 { .offset = 0x03, .name = "rx_broadcast", },
470 { .offset = 0x04, .name = "rx_shorts", },
471 { .offset = 0x05, .name = "rx_fragments", },
472 { .offset = 0x06, .name = "rx_jabbers", },
473 { .offset = 0x07, .name = "rx_crc_align_errs", },
474 { .offset = 0x08, .name = "rx_sym_errs", },
475 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
476 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
477 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
478 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
479 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
480 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
481 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
482 { .offset = 0x10, .name = "rx_pause", },
483 { .offset = 0x11, .name = "rx_control", },
484 { .offset = 0x12, .name = "rx_longs", },
485 { .offset = 0x13, .name = "rx_classified_drops", },
486 { .offset = 0x14, .name = "rx_red_prio_0", },
487 { .offset = 0x15, .name = "rx_red_prio_1", },
488 { .offset = 0x16, .name = "rx_red_prio_2", },
489 { .offset = 0x17, .name = "rx_red_prio_3", },
490 { .offset = 0x18, .name = "rx_red_prio_4", },
491 { .offset = 0x19, .name = "rx_red_prio_5", },
492 { .offset = 0x1A, .name = "rx_red_prio_6", },
493 { .offset = 0x1B, .name = "rx_red_prio_7", },
494 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
495 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
496 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
497 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
498 { .offset = 0x20, .name = "rx_yellow_prio_4", },
499 { .offset = 0x21, .name = "rx_yellow_prio_5", },
500 { .offset = 0x22, .name = "rx_yellow_prio_6", },
501 { .offset = 0x23, .name = "rx_yellow_prio_7", },
502 { .offset = 0x24, .name = "rx_green_prio_0", },
503 { .offset = 0x25, .name = "rx_green_prio_1", },
504 { .offset = 0x26, .name = "rx_green_prio_2", },
505 { .offset = 0x27, .name = "rx_green_prio_3", },
506 { .offset = 0x28, .name = "rx_green_prio_4", },
507 { .offset = 0x29, .name = "rx_green_prio_5", },
508 { .offset = 0x2A, .name = "rx_green_prio_6", },
509 { .offset = 0x2B, .name = "rx_green_prio_7", },
510 { .offset = 0x80, .name = "tx_octets", },
511 { .offset = 0x81, .name = "tx_unicast", },
512 { .offset = 0x82, .name = "tx_multicast", },
513 { .offset = 0x83, .name = "tx_broadcast", },
514 { .offset = 0x84, .name = "tx_collision", },
515 { .offset = 0x85, .name = "tx_drops", },
516 { .offset = 0x86, .name = "tx_pause", },
517 { .offset = 0x87, .name = "tx_frames_below_65_octets", },
518 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", },
519 { .offset = 0x89, .name = "tx_frames_128_255_octets", },
520 { .offset = 0x8B, .name = "tx_frames_256_511_octets", },
521 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", },
522 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", },
523 { .offset = 0x8E, .name = "tx_yellow_prio_0", },
524 { .offset = 0x8F, .name = "tx_yellow_prio_1", },
525 { .offset = 0x90, .name = "tx_yellow_prio_2", },
526 { .offset = 0x91, .name = "tx_yellow_prio_3", },
527 { .offset = 0x92, .name = "tx_yellow_prio_4", },
528 { .offset = 0x93, .name = "tx_yellow_prio_5", },
529 { .offset = 0x94, .name = "tx_yellow_prio_6", },
530 { .offset = 0x95, .name = "tx_yellow_prio_7", },
531 { .offset = 0x96, .name = "tx_green_prio_0", },
532 { .offset = 0x97, .name = "tx_green_prio_1", },
533 { .offset = 0x98, .name = "tx_green_prio_2", },
534 { .offset = 0x99, .name = "tx_green_prio_3", },
535 { .offset = 0x9A, .name = "tx_green_prio_4", },
536 { .offset = 0x9B, .name = "tx_green_prio_5", },
537 { .offset = 0x9C, .name = "tx_green_prio_6", },
538 { .offset = 0x9D, .name = "tx_green_prio_7", },
539 { .offset = 0x9E, .name = "tx_aged", },
540 { .offset = 0x100, .name = "drop_local", },
541 { .offset = 0x101, .name = "drop_tail", },
542 { .offset = 0x102, .name = "drop_yellow_prio_0", },
543 { .offset = 0x103, .name = "drop_yellow_prio_1", },
544 { .offset = 0x104, .name = "drop_yellow_prio_2", },
545 { .offset = 0x105, .name = "drop_yellow_prio_3", },
546 { .offset = 0x106, .name = "drop_yellow_prio_4", },
547 { .offset = 0x107, .name = "drop_yellow_prio_5", },
548 { .offset = 0x108, .name = "drop_yellow_prio_6", },
549 { .offset = 0x109, .name = "drop_yellow_prio_7", },
550 { .offset = 0x10A, .name = "drop_green_prio_0", },
551 { .offset = 0x10B, .name = "drop_green_prio_1", },
552 { .offset = 0x10C, .name = "drop_green_prio_2", },
553 { .offset = 0x10D, .name = "drop_green_prio_3", },
554 { .offset = 0x10E, .name = "drop_green_prio_4", },
555 { .offset = 0x10F, .name = "drop_green_prio_5", },
556 { .offset = 0x110, .name = "drop_green_prio_6", },
557 { .offset = 0x111, .name = "drop_green_prio_7", },
558 };
559
560 struct vcap_field vsc9959_vcap_is2_keys[] = {
561 /* Common: 41 bits */
562 [VCAP_IS2_TYPE] = { 0, 4},
563 [VCAP_IS2_HK_FIRST] = { 4, 1},
564 [VCAP_IS2_HK_PAG] = { 5, 8},
565 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7},
566 [VCAP_IS2_HK_RSV2] = { 20, 1},
567 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1},
568 [VCAP_IS2_HK_L2_MC] = { 22, 1},
569 [VCAP_IS2_HK_L2_BC] = { 23, 1},
570 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1},
571 [VCAP_IS2_HK_VID] = { 25, 12},
572 [VCAP_IS2_HK_DEI] = { 37, 1},
573 [VCAP_IS2_HK_PCP] = { 38, 3},
574 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
575 [VCAP_IS2_HK_L2_DMAC] = { 41, 48},
576 [VCAP_IS2_HK_L2_SMAC] = { 89, 48},
577 /* MAC_ETYPE (TYPE=000) */
578 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16},
579 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16},
580 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8},
581 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3},
582 /* MAC_LLC (TYPE=001) */
583 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40},
584 /* MAC_SNAP (TYPE=010) */
585 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40},
586 /* MAC_ARP (TYPE=011) */
587 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48},
588 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1},
589 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1},
590 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1},
591 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1},
592 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1},
593 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1},
594 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2},
595 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32},
596 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32},
597 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1},
598 /* IP4_TCP_UDP / IP4_OTHER common */
599 [VCAP_IS2_HK_IP4] = { 41, 1},
600 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1},
601 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1},
602 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1},
603 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1},
604 [VCAP_IS2_HK_L3_TOS] = { 46, 8},
605 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32},
606 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32},
607 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1},
608 /* IP4_TCP_UDP (TYPE=100) */
609 [VCAP_IS2_HK_TCP] = {119, 1},
610 [VCAP_IS2_HK_L4_SPORT] = {120, 16},
611 [VCAP_IS2_HK_L4_DPORT] = {136, 16},
612 [VCAP_IS2_HK_L4_RNG] = {152, 8},
613 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1},
614 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1},
615 [VCAP_IS2_HK_L4_URG] = {162, 1},
616 [VCAP_IS2_HK_L4_ACK] = {163, 1},
617 [VCAP_IS2_HK_L4_PSH] = {164, 1},
618 [VCAP_IS2_HK_L4_RST] = {165, 1},
619 [VCAP_IS2_HK_L4_SYN] = {166, 1},
620 [VCAP_IS2_HK_L4_FIN] = {167, 1},
621 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8},
622 [VCAP_IS2_HK_L4_1588_VER] = {176, 4},
623 /* IP4_OTHER (TYPE=101) */
624 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8},
625 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56},
626 /* IP6_STD (TYPE=110) */
627 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1},
628 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128},
629 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8},
630 /* OAM (TYPE=111) */
631 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7},
632 [VCAP_IS2_HK_OAM_VER] = {144, 5},
633 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8},
634 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8},
635 [VCAP_IS2_HK_OAM_MEPID] = {165, 16},
636 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1},
637 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1},
638 };
639
640 struct vcap_field vsc9959_vcap_is2_actions[] = {
641 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
642 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
643 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
644 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
645 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
646 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
647 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
648 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9},
649 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1},
650 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11},
651 [VCAP_IS2_ACT_REW_OP] = { 31, 9},
652 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1},
653 [VCAP_IS2_ACT_RSV] = { 41, 2},
654 [VCAP_IS2_ACT_ACL_ID] = { 43, 6},
655 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32},
656 };
657
658 static const struct vcap_props vsc9959_vcap_props[] = {
659 [VCAP_IS2] = {
660 .tg_width = 2,
661 .sw_count = 4,
662 .entry_count = VSC9959_VCAP_IS2_CNT,
663 .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH,
664 .action_count = VSC9959_VCAP_IS2_CNT +
665 VSC9959_VCAP_PORT_CNT + 2,
666 .action_width = 89,
667 .action_type_width = 1,
668 .action_table = {
669 [IS2_ACTION_TYPE_NORMAL] = {
670 .width = 44,
671 .count = 2
672 },
673 [IS2_ACTION_TYPE_SMAC_SIP] = {
674 .width = 6,
675 .count = 4
676 },
677 },
678 .counter_words = 4,
679 .counter_width = 32,
680 },
681 };
682
683 #define VSC9959_INIT_TIMEOUT 50000
684 #define VSC9959_GCB_RST_SLEEP 100
685 #define VSC9959_SYS_RAMINIT_SLEEP 80
686
687 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
688 {
689 int val;
690
691 regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val);
692
693 return val;
694 }
695
696 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
697 {
698 return ocelot_read(ocelot, SYS_RAM_INIT);
699 }
700
701 static int vsc9959_reset(struct ocelot *ocelot)
702 {
703 int val, err;
704
705 /* soft-reset the switch core */
706 regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1);
707
708 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
709 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
710 if (err) {
711 dev_err(ocelot->dev, "timeout: switch core reset\n");
712 return err;
713 }
714
715 /* initialize switch mem ~40us */
716 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
717 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
718 VSC9959_SYS_RAMINIT_SLEEP,
719 VSC9959_INIT_TIMEOUT);
720 if (err) {
721 dev_err(ocelot->dev, "timeout: switch sram init\n");
722 return err;
723 }
724
725 /* enable switch core */
726 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
727
728 return 0;
729 }
730
731 static void vsc9959_pcs_an_restart_sgmii(struct phy_device *pcs)
732 {
733 phy_set_bits(pcs, MII_BMCR, BMCR_ANRESTART);
734 }
735
736 static void vsc9959_pcs_an_restart_usxgmii(struct phy_device *pcs)
737 {
738 phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_BMCR,
739 USXGMII_BMCR_RESET |
740 USXGMII_BMCR_AN_EN |
741 USXGMII_BMCR_RST_AN);
742 }
743
744 static void vsc9959_pcs_an_restart(struct ocelot *ocelot, int port)
745 {
746 struct felix *felix = ocelot_to_felix(ocelot);
747 struct phy_device *pcs = felix->pcs[port];
748
749 if (!pcs)
750 return;
751
752 switch (pcs->interface) {
753 case PHY_INTERFACE_MODE_SGMII:
754 case PHY_INTERFACE_MODE_QSGMII:
755 vsc9959_pcs_an_restart_sgmii(pcs);
756 break;
757 case PHY_INTERFACE_MODE_USXGMII:
758 vsc9959_pcs_an_restart_usxgmii(pcs);
759 break;
760 default:
761 dev_err(ocelot->dev, "Invalid PCS interface type %s\n",
762 phy_modes(pcs->interface));
763 break;
764 }
765 }
766
767 /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the
768 * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed
769 * into the PCS, which is retrieved out-of-band over MDIO. This also has the
770 * benefit of working with SGMII fixed-links, like downstream switches, where
771 * both link partners attempt to operate as AN slaves and therefore AN never
772 * completes. But it also has the disadvantage that some PHY chips don't pass
773 * traffic if SGMII AN is enabled but not completed (acknowledged by us), so
774 * setting MLO_AN_INBAND is actually required for those.
775 */
776 static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
777 unsigned int link_an_mode,
778 const struct phylink_link_state *state)
779 {
780 if (link_an_mode == MLO_AN_INBAND) {
781 int bmsr, bmcr;
782
783 /* Some PHYs like VSC8234 don't like it when AN restarts on
784 * their system side and they restart line side AN too, going
785 * into an endless link up/down loop. Don't restart PCS AN if
786 * link is up already.
787 * We do check that AN is enabled just in case this is the 1st
788 * call, PCS detects a carrier but AN is disabled from power on
789 * or by boot loader.
790 */
791 bmcr = phy_read(pcs, MII_BMCR);
792 if (bmcr < 0)
793 return;
794
795 bmsr = phy_read(pcs, MII_BMSR);
796 if (bmsr < 0)
797 return;
798
799 if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS))
800 return;
801
802 /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001
803 * for the MAC PCS in order to acknowledge the AN.
804 */
805 phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII |
806 ADVERTISE_LPACK);
807
808 phy_write(pcs, ENETC_PCS_IF_MODE,
809 ENETC_PCS_IF_MODE_SGMII_EN |
810 ENETC_PCS_IF_MODE_USE_SGMII_AN);
811
812 /* Adjust link timer for SGMII */
813 phy_write(pcs, ENETC_PCS_LINK_TIMER1,
814 ENETC_PCS_LINK_TIMER1_VAL);
815 phy_write(pcs, ENETC_PCS_LINK_TIMER2,
816 ENETC_PCS_LINK_TIMER2_VAL);
817
818 phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE);
819 } else {
820 int speed;
821
822 if (state->duplex == DUPLEX_HALF) {
823 phydev_err(pcs, "Half duplex not supported\n");
824 return;
825 }
826 switch (state->speed) {
827 case SPEED_1000:
828 speed = ENETC_PCS_SPEED_1000;
829 break;
830 case SPEED_100:
831 speed = ENETC_PCS_SPEED_100;
832 break;
833 case SPEED_10:
834 speed = ENETC_PCS_SPEED_10;
835 break;
836 case SPEED_UNKNOWN:
837 /* Silently don't do anything */
838 return;
839 default:
840 phydev_err(pcs, "Invalid PCS speed %d\n", state->speed);
841 return;
842 }
843
844 phy_write(pcs, ENETC_PCS_IF_MODE,
845 ENETC_PCS_IF_MODE_SGMII_EN |
846 ENETC_PCS_IF_MODE_SGMII_SPEED(speed));
847
848 /* Yes, not a mistake: speed is given by IF_MODE. */
849 phy_write(pcs, MII_BMCR, BMCR_RESET |
850 BMCR_SPEED1000 |
851 BMCR_FULLDPLX);
852 }
853 }
854
855 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
856 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
857 * auto-negotiation of any link parameters. Electrically it is compatible with
858 * a single lane of XAUI.
859 * The hardware reference manual wants to call this mode SGMII, but it isn't
860 * really, since the fundamental features of SGMII:
861 * - Downgrading the link speed by duplicating symbols
862 * - Auto-negotiation
863 * are not there.
864 * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers
865 * because the clock frequency is actually given by a PLL configured in the
866 * Reset Configuration Word (RCW).
867 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
868 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
869 * lower link speed on line side, the system-side interface remains fixed at
870 * 2500 Mbps and we do rate adaptation through pause frames.
871 */
872 static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
873 unsigned int link_an_mode,
874 const struct phylink_link_state *state)
875 {
876 if (link_an_mode == MLO_AN_INBAND) {
877 phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
878 return;
879 }
880
881 phy_write(pcs, ENETC_PCS_IF_MODE,
882 ENETC_PCS_IF_MODE_SGMII_EN |
883 ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500));
884
885 phy_write(pcs, MII_BMCR, BMCR_SPEED1000 |
886 BMCR_FULLDPLX |
887 BMCR_RESET);
888 }
889
890 static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs,
891 unsigned int link_an_mode,
892 const struct phylink_link_state *state)
893 {
894 if (link_an_mode != MLO_AN_INBAND) {
895 phydev_err(pcs, "USXGMII only supports in-band AN for now\n");
896 return;
897 }
898
899 /* Configure device ability for the USXGMII Replicator */
900 phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE,
901 USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) |
902 USXGMII_ADVERTISE_LNKS(1) |
903 ADVERTISE_SGMII |
904 ADVERTISE_LPACK |
905 USXGMII_ADVERTISE_FDX);
906 }
907
908 static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
909 unsigned int link_an_mode,
910 const struct phylink_link_state *state)
911 {
912 struct felix *felix = ocelot_to_felix(ocelot);
913 struct phy_device *pcs = felix->pcs[port];
914
915 if (!pcs)
916 return;
917
918 /* The PCS does not implement the BMSR register fully, so capability
919 * detection via genphy_read_abilities does not work. Since we can get
920 * the PHY config word from the LPA register though, there is still
921 * value in using the generic phy_resolve_aneg_linkmode function. So
922 * populate the supported and advertising link modes manually here.
923 */
924 linkmode_set_bit_array(phy_basic_ports_array,
925 ARRAY_SIZE(phy_basic_ports_array),
926 pcs->supported);
927 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported);
928 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported);
929 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported);
930 if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX ||
931 pcs->interface == PHY_INTERFACE_MODE_USXGMII)
932 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
933 pcs->supported);
934 if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX)
935 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
936 pcs->supported);
937 phy_advertise_supported(pcs);
938
939 switch (pcs->interface) {
940 case PHY_INTERFACE_MODE_SGMII:
941 case PHY_INTERFACE_MODE_QSGMII:
942 vsc9959_pcs_init_sgmii(pcs, link_an_mode, state);
943 break;
944 case PHY_INTERFACE_MODE_2500BASEX:
945 vsc9959_pcs_init_2500basex(pcs, link_an_mode, state);
946 break;
947 case PHY_INTERFACE_MODE_USXGMII:
948 vsc9959_pcs_init_usxgmii(pcs, link_an_mode, state);
949 break;
950 default:
951 dev_err(ocelot->dev, "Unsupported link mode %s\n",
952 phy_modes(pcs->interface));
953 }
954 }
955
956 static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs,
957 struct phylink_link_state *state)
958 {
959 state->an_complete = pcs->autoneg_complete;
960 state->an_enabled = pcs->autoneg;
961 state->link = pcs->link;
962 state->duplex = pcs->duplex;
963 state->speed = pcs->speed;
964 /* SGMII AN does not negotiate flow control, but that's ok,
965 * since phylink already knows that, and does:
966 * link_state.pause |= pl->phy_state.pause;
967 */
968 state->pause = MLO_PAUSE_NONE;
969
970 phydev_dbg(pcs,
971 "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n",
972 phy_modes(pcs->interface),
973 phy_speed_to_str(pcs->speed),
974 phy_duplex_to_str(pcs->duplex),
975 __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising,
976 __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising,
977 pcs->link, pcs->autoneg, pcs->autoneg_complete);
978 }
979
980 static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs,
981 struct phylink_link_state *state)
982 {
983 int err;
984
985 err = genphy_update_link(pcs);
986 if (err < 0)
987 return;
988
989 if (pcs->autoneg_complete) {
990 u16 lpa = phy_read(pcs, MII_LPA);
991
992 mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa);
993
994 phy_resolve_aneg_linkmode(pcs);
995 }
996 }
997
998 static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs,
999 struct phylink_link_state *state)
1000 {
1001 int err;
1002
1003 err = genphy_update_link(pcs);
1004 if (err < 0)
1005 return;
1006
1007 pcs->speed = SPEED_2500;
1008 pcs->asym_pause = true;
1009 pcs->pause = true;
1010 }
1011
1012 static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs,
1013 struct phylink_link_state *state)
1014 {
1015 int status, lpa;
1016
1017 status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR);
1018 if (status < 0)
1019 return;
1020
1021 pcs->autoneg = true;
1022 pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status);
1023 pcs->link = USXGMII_BMSR_LNKS(status);
1024
1025 if (!pcs->link || !pcs->autoneg_complete)
1026 return;
1027
1028 lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA);
1029 if (lpa < 0)
1030 return;
1031
1032 switch (USXGMII_LPA_SPEED(lpa)) {
1033 case USXGMII_SPEED_10:
1034 pcs->speed = SPEED_10;
1035 break;
1036 case USXGMII_SPEED_100:
1037 pcs->speed = SPEED_100;
1038 break;
1039 case USXGMII_SPEED_1000:
1040 pcs->speed = SPEED_1000;
1041 break;
1042 case USXGMII_SPEED_2500:
1043 pcs->speed = SPEED_2500;
1044 break;
1045 default:
1046 break;
1047 }
1048
1049 if (USXGMII_LPA_DUPLEX(lpa))
1050 pcs->duplex = DUPLEX_FULL;
1051 else
1052 pcs->duplex = DUPLEX_HALF;
1053 }
1054
1055 static void vsc9959_pcs_link_state(struct ocelot *ocelot, int port,
1056 struct phylink_link_state *state)
1057 {
1058 struct felix *felix = ocelot_to_felix(ocelot);
1059 struct phy_device *pcs = felix->pcs[port];
1060
1061 if (!pcs)
1062 return;
1063
1064 pcs->speed = SPEED_UNKNOWN;
1065 pcs->duplex = DUPLEX_UNKNOWN;
1066 pcs->pause = 0;
1067 pcs->asym_pause = 0;
1068
1069 switch (pcs->interface) {
1070 case PHY_INTERFACE_MODE_SGMII:
1071 case PHY_INTERFACE_MODE_QSGMII:
1072 vsc9959_pcs_link_state_sgmii(pcs, state);
1073 break;
1074 case PHY_INTERFACE_MODE_2500BASEX:
1075 vsc9959_pcs_link_state_2500basex(pcs, state);
1076 break;
1077 case PHY_INTERFACE_MODE_USXGMII:
1078 vsc9959_pcs_link_state_usxgmii(pcs, state);
1079 break;
1080 default:
1081 return;
1082 }
1083
1084 vsc9959_pcs_link_state_resolve(pcs, state);
1085 }
1086
1087 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
1088 phy_interface_t phy_mode)
1089 {
1090 switch (phy_mode) {
1091 case PHY_INTERFACE_MODE_INTERNAL:
1092 if (port != 4 && port != 5)
1093 return -ENOTSUPP;
1094 return 0;
1095 case PHY_INTERFACE_MODE_SGMII:
1096 case PHY_INTERFACE_MODE_QSGMII:
1097 case PHY_INTERFACE_MODE_USXGMII:
1098 case PHY_INTERFACE_MODE_2500BASEX:
1099 /* Not supported on internal to-CPU ports */
1100 if (port == 4 || port == 5)
1101 return -ENOTSUPP;
1102 return 0;
1103 default:
1104 return -ENOTSUPP;
1105 }
1106 }
1107
1108 static const struct ocelot_ops vsc9959_ops = {
1109 .reset = vsc9959_reset,
1110 };
1111
1112 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1113 {
1114 struct felix *felix = ocelot_to_felix(ocelot);
1115 struct enetc_mdio_priv *mdio_priv;
1116 struct device *dev = ocelot->dev;
1117 resource_size_t imdio_base;
1118 void __iomem *imdio_regs;
1119 struct resource res;
1120 struct enetc_hw *hw;
1121 struct mii_bus *bus;
1122 int port;
1123 int rc;
1124
1125 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1126 sizeof(struct phy_device *),
1127 GFP_KERNEL);
1128 if (!felix->pcs) {
1129 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1130 return -ENOMEM;
1131 }
1132
1133 imdio_base = pci_resource_start(felix->pdev,
1134 felix->info->imdio_pci_bar);
1135
1136 memcpy(&res, felix->info->imdio_res, sizeof(res));
1137 res.flags = IORESOURCE_MEM;
1138 res.start += imdio_base;
1139 res.end += imdio_base;
1140
1141 imdio_regs = devm_ioremap_resource(dev, &res);
1142 if (IS_ERR(imdio_regs)) {
1143 dev_err(dev, "failed to map internal MDIO registers\n");
1144 return PTR_ERR(imdio_regs);
1145 }
1146
1147 hw = enetc_hw_alloc(dev, imdio_regs);
1148 if (IS_ERR(hw)) {
1149 dev_err(dev, "failed to allocate ENETC HW structure\n");
1150 return PTR_ERR(hw);
1151 }
1152
1153 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
1154 if (!bus)
1155 return -ENOMEM;
1156
1157 bus->name = "VSC9959 internal MDIO bus";
1158 bus->read = enetc_mdio_read;
1159 bus->write = enetc_mdio_write;
1160 bus->parent = dev;
1161 mdio_priv = bus->priv;
1162 mdio_priv->hw = hw;
1163 /* This gets added to imdio_regs, which already maps addresses
1164 * starting with the proper offset.
1165 */
1166 mdio_priv->mdio_base = 0;
1167 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1168
1169 /* Needed in order to initialize the bus mutex lock */
1170 rc = mdiobus_register(bus);
1171 if (rc < 0) {
1172 dev_err(dev, "failed to register MDIO bus\n");
1173 return rc;
1174 }
1175
1176 felix->imdio = bus;
1177
1178 for (port = 0; port < felix->info->num_ports; port++) {
1179 struct ocelot_port *ocelot_port = ocelot->ports[port];
1180 struct phy_device *pcs;
1181 bool is_c45 = false;
1182
1183 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII)
1184 is_c45 = true;
1185
1186 pcs = get_phy_device(felix->imdio, port, is_c45);
1187 if (IS_ERR(pcs))
1188 continue;
1189
1190 pcs->interface = ocelot_port->phy_mode;
1191 felix->pcs[port] = pcs;
1192
1193 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1194 }
1195
1196 return 0;
1197 }
1198
1199 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1200 {
1201 struct felix *felix = ocelot_to_felix(ocelot);
1202 int port;
1203
1204 for (port = 0; port < ocelot->num_phys_ports; port++) {
1205 struct phy_device *pcs = felix->pcs[port];
1206
1207 if (!pcs)
1208 continue;
1209
1210 put_device(&pcs->mdio.dev);
1211 }
1212 mdiobus_unregister(felix->imdio);
1213 }
1214
1215 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1216 u32 speed)
1217 {
1218 ocelot_rmw_rix(ocelot,
1219 QSYS_TAG_CONFIG_LINK_SPEED(speed),
1220 QSYS_TAG_CONFIG_LINK_SPEED_M,
1221 QSYS_TAG_CONFIG, port);
1222 }
1223
1224 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1225 u64 cycle_time,
1226 struct timespec64 *new_base_ts)
1227 {
1228 struct timespec64 ts;
1229 ktime_t new_base_time;
1230 ktime_t current_time;
1231
1232 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1233 current_time = timespec64_to_ktime(ts);
1234 new_base_time = base_time;
1235
1236 if (base_time < current_time) {
1237 u64 nr_of_cycles = current_time - base_time;
1238
1239 do_div(nr_of_cycles, cycle_time);
1240 new_base_time += cycle_time * (nr_of_cycles + 1);
1241 }
1242
1243 *new_base_ts = ktime_to_timespec64(new_base_time);
1244 }
1245
1246 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1247 {
1248 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1249 }
1250
1251 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1252 struct tc_taprio_sched_entry *entry)
1253 {
1254 ocelot_write(ocelot,
1255 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1256 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1257 QSYS_GCL_CFG_REG_1);
1258 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1259 }
1260
1261 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1262 struct tc_taprio_qopt_offload *taprio)
1263 {
1264 struct timespec64 base_ts;
1265 int ret, i;
1266 u32 val;
1267
1268 if (!taprio->enable) {
1269 ocelot_rmw_rix(ocelot,
1270 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1271 QSYS_TAG_CONFIG_ENABLE |
1272 QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1273 QSYS_TAG_CONFIG, port);
1274
1275 return 0;
1276 }
1277
1278 if (taprio->cycle_time > NSEC_PER_SEC ||
1279 taprio->cycle_time_extension >= NSEC_PER_SEC)
1280 return -EINVAL;
1281
1282 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1283 return -ERANGE;
1284
1285 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1286 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1287 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1288 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1289 QSYS_TAS_PARAM_CFG_CTRL);
1290
1291 /* Hardware errata - Admin config could not be overwritten if
1292 * config is pending, need reset the TAS module
1293 */
1294 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1295 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1296 return -EBUSY;
1297
1298 ocelot_rmw_rix(ocelot,
1299 QSYS_TAG_CONFIG_ENABLE |
1300 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1301 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1302 QSYS_TAG_CONFIG_ENABLE |
1303 QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1304 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1305 QSYS_TAG_CONFIG, port);
1306
1307 vsc9959_new_base_time(ocelot, taprio->base_time,
1308 taprio->cycle_time, &base_ts);
1309 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1310 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1311 val = upper_32_bits(base_ts.tv_sec);
1312 ocelot_write(ocelot,
1313 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1314 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1315 QSYS_PARAM_CFG_REG_3);
1316 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1317 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1318
1319 for (i = 0; i < taprio->num_entries; i++)
1320 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1321
1322 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1323 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1324 QSYS_TAS_PARAM_CFG_CTRL);
1325
1326 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1327 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1328 10, 100000);
1329
1330 return ret;
1331 }
1332
1333 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1334 struct tc_cbs_qopt_offload *cbs_qopt)
1335 {
1336 struct ocelot *ocelot = ds->priv;
1337 int port_ix = port * 8 + cbs_qopt->queue;
1338 u32 rate, burst;
1339
1340 if (cbs_qopt->queue >= ds->num_tx_queues)
1341 return -EINVAL;
1342
1343 if (!cbs_qopt->enable) {
1344 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1345 QSYS_CIR_CFG_CIR_BURST(0),
1346 QSYS_CIR_CFG, port_ix);
1347
1348 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1349 QSYS_SE_CFG, port_ix);
1350
1351 return 0;
1352 }
1353
1354 /* Rate unit is 100 kbps */
1355 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1356 /* Avoid using zero rate */
1357 rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1358 /* Burst unit is 4kB */
1359 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1360 /* Avoid using zero burst size */
1361 burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1362 ocelot_write_gix(ocelot,
1363 QSYS_CIR_CFG_CIR_RATE(rate) |
1364 QSYS_CIR_CFG_CIR_BURST(burst),
1365 QSYS_CIR_CFG,
1366 port_ix);
1367
1368 ocelot_rmw_gix(ocelot,
1369 QSYS_SE_CFG_SE_FRM_MODE(0) |
1370 QSYS_SE_CFG_SE_AVB_ENA,
1371 QSYS_SE_CFG_SE_AVB_ENA |
1372 QSYS_SE_CFG_SE_FRM_MODE_M,
1373 QSYS_SE_CFG,
1374 port_ix);
1375
1376 return 0;
1377 }
1378
1379 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1380 enum tc_setup_type type,
1381 void *type_data)
1382 {
1383 struct ocelot *ocelot = ds->priv;
1384
1385 switch (type) {
1386 case TC_SETUP_QDISC_TAPRIO:
1387 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1388 case TC_SETUP_QDISC_CBS:
1389 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1390 default:
1391 return -EOPNOTSUPP;
1392 }
1393 }
1394
1395 struct felix_info felix_info_vsc9959 = {
1396 .target_io_res = vsc9959_target_io_res,
1397 .port_io_res = vsc9959_port_io_res,
1398 .imdio_res = &vsc9959_imdio_res,
1399 .regfields = vsc9959_regfields,
1400 .map = vsc9959_regmap,
1401 .ops = &vsc9959_ops,
1402 .stats_layout = vsc9959_stats_layout,
1403 .num_stats = ARRAY_SIZE(vsc9959_stats_layout),
1404 .vcap_is2_keys = vsc9959_vcap_is2_keys,
1405 .vcap_is2_actions = vsc9959_vcap_is2_actions,
1406 .vcap = vsc9959_vcap_props,
1407 .shared_queue_sz = 128 * 1024,
1408 .num_mact_rows = 2048,
1409 .num_ports = 6,
1410 .num_tx_queues = FELIX_NUM_TC,
1411 .switch_pci_bar = 4,
1412 .imdio_pci_bar = 0,
1413 .mdio_bus_alloc = vsc9959_mdio_bus_alloc,
1414 .mdio_bus_free = vsc9959_mdio_bus_free,
1415 .pcs_init = vsc9959_pcs_init,
1416 .pcs_an_restart = vsc9959_pcs_an_restart,
1417 .pcs_link_state = vsc9959_pcs_link_state,
1418 .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode,
1419 .port_setup_tc = vsc9959_port_setup_tc,
1420 .port_sched_speed_set = vsc9959_sched_speed_set,
1421 };
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