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net: dsa: ocelot: document why reset procedure is different for felix/seville
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / dsa / ocelot / seville_vsc9953.c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Distributed Switch Architecture VSC9953 driver
3 * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru>
4 */
5 #include <linux/types.h>
6 #include <soc/mscc/ocelot_vcap.h>
7 #include <soc/mscc/ocelot_sys.h>
8 #include <soc/mscc/ocelot.h>
9 #include <linux/of_platform.h>
10 #include <linux/pcs-lynx.h>
11 #include <linux/packing.h>
12 #include <linux/iopoll.h>
13 #include "felix.h"
14
15 #define VSC9953_VCAP_IS2_CNT 1024
16 #define VSC9953_VCAP_IS2_ENTRY_WIDTH 376
17 #define VSC9953_VCAP_PORT_CNT 10
18
19 #define MSCC_MIIM_REG_STATUS 0x0
20 #define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
21 #define MSCC_MIIM_REG_CMD 0x8
22 #define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
23 #define MSCC_MIIM_CMD_OPR_READ BIT(2)
24 #define MSCC_MIIM_CMD_WRDATA_SHIFT 4
25 #define MSCC_MIIM_CMD_REGAD_SHIFT 20
26 #define MSCC_MIIM_CMD_PHYAD_SHIFT 25
27 #define MSCC_MIIM_CMD_VLD BIT(31)
28 #define MSCC_MIIM_REG_DATA 0xC
29 #define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
30
31 #define MSCC_PHY_REG_PHY_CFG 0x0
32 #define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
33 #define PHY_CFG_PHY_COMMON_RESET BIT(4)
34 #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
35 #define MSCC_PHY_REG_PHY_STATUS 0x4
36
37 static const u32 vsc9953_ana_regmap[] = {
38 REG(ANA_ADVLEARN, 0x00b500),
39 REG(ANA_VLANMASK, 0x00b504),
40 REG_RESERVED(ANA_PORT_B_DOMAIN),
41 REG(ANA_ANAGEFIL, 0x00b50c),
42 REG(ANA_ANEVENTS, 0x00b510),
43 REG(ANA_STORMLIMIT_BURST, 0x00b514),
44 REG(ANA_STORMLIMIT_CFG, 0x00b518),
45 REG(ANA_ISOLATED_PORTS, 0x00b528),
46 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
47 REG(ANA_AUTOAGE, 0x00b530),
48 REG(ANA_MACTOPTIONS, 0x00b534),
49 REG(ANA_LEARNDISC, 0x00b538),
50 REG(ANA_AGENCTRL, 0x00b53c),
51 REG(ANA_MIRRORPORTS, 0x00b540),
52 REG(ANA_EMIRRORPORTS, 0x00b544),
53 REG(ANA_FLOODING, 0x00b548),
54 REG(ANA_FLOODING_IPMC, 0x00b54c),
55 REG(ANA_SFLOW_CFG, 0x00b550),
56 REG(ANA_PORT_MODE, 0x00b57c),
57 REG_RESERVED(ANA_CUT_THRU_CFG),
58 REG(ANA_PGID_PGID, 0x00b600),
59 REG(ANA_TABLES_ANMOVED, 0x00b4ac),
60 REG(ANA_TABLES_MACHDATA, 0x00b4b0),
61 REG(ANA_TABLES_MACLDATA, 0x00b4b4),
62 REG_RESERVED(ANA_TABLES_STREAMDATA),
63 REG(ANA_TABLES_MACACCESS, 0x00b4b8),
64 REG(ANA_TABLES_MACTINDX, 0x00b4bc),
65 REG(ANA_TABLES_VLANACCESS, 0x00b4c0),
66 REG(ANA_TABLES_VLANTIDX, 0x00b4c4),
67 REG_RESERVED(ANA_TABLES_ISDXACCESS),
68 REG_RESERVED(ANA_TABLES_ISDXTIDX),
69 REG(ANA_TABLES_ENTRYLIM, 0x00b480),
70 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH),
71 REG_RESERVED(ANA_TABLES_PTP_ID_LOW),
72 REG_RESERVED(ANA_TABLES_STREAMACCESS),
73 REG_RESERVED(ANA_TABLES_STREAMTIDX),
74 REG_RESERVED(ANA_TABLES_SEQ_HISTORY),
75 REG_RESERVED(ANA_TABLES_SEQ_MASK),
76 REG_RESERVED(ANA_TABLES_SFID_MASK),
77 REG_RESERVED(ANA_TABLES_SFIDACCESS),
78 REG_RESERVED(ANA_TABLES_SFIDTIDX),
79 REG_RESERVED(ANA_MSTI_STATE),
80 REG_RESERVED(ANA_OAM_UPM_LM_CNT),
81 REG_RESERVED(ANA_SG_ACCESS_CTRL),
82 REG_RESERVED(ANA_SG_CONFIG_REG_1),
83 REG_RESERVED(ANA_SG_CONFIG_REG_2),
84 REG_RESERVED(ANA_SG_CONFIG_REG_3),
85 REG_RESERVED(ANA_SG_CONFIG_REG_4),
86 REG_RESERVED(ANA_SG_CONFIG_REG_5),
87 REG_RESERVED(ANA_SG_GCL_GS_CONFIG),
88 REG_RESERVED(ANA_SG_GCL_TI_CONFIG),
89 REG_RESERVED(ANA_SG_STATUS_REG_1),
90 REG_RESERVED(ANA_SG_STATUS_REG_2),
91 REG_RESERVED(ANA_SG_STATUS_REG_3),
92 REG(ANA_PORT_VLAN_CFG, 0x000000),
93 REG(ANA_PORT_DROP_CFG, 0x000004),
94 REG(ANA_PORT_QOS_CFG, 0x000008),
95 REG(ANA_PORT_VCAP_CFG, 0x00000c),
96 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010),
97 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c),
98 REG(ANA_PORT_PCP_DEI_MAP, 0x000020),
99 REG(ANA_PORT_CPU_FWD_CFG, 0x000060),
100 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064),
101 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068),
102 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c),
103 REG(ANA_PORT_PORT_CFG, 0x000070),
104 REG(ANA_PORT_POL_CFG, 0x000074),
105 REG_RESERVED(ANA_PORT_PTP_CFG),
106 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG),
107 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG),
108 REG_RESERVED(ANA_PORT_SFID_CFG),
109 REG(ANA_PFC_PFC_CFG, 0x00c000),
110 REG_RESERVED(ANA_PFC_PFC_TIMER),
111 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
112 REG_RESERVED(ANA_IPT_IPT),
113 REG_RESERVED(ANA_PPT_PPT),
114 REG_RESERVED(ANA_FID_MAP_FID_MAP),
115 REG(ANA_AGGR_CFG, 0x00c600),
116 REG(ANA_CPUQ_CFG, 0x00c604),
117 REG_RESERVED(ANA_CPUQ_CFG2),
118 REG(ANA_CPUQ_8021_CFG, 0x00c60c),
119 REG(ANA_DSCP_CFG, 0x00c64c),
120 REG(ANA_DSCP_REWR_CFG, 0x00c74c),
121 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c),
122 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac),
123 REG_RESERVED(ANA_VRAP_CFG),
124 REG_RESERVED(ANA_VRAP_HDR_DATA),
125 REG_RESERVED(ANA_VRAP_HDR_MASK),
126 REG(ANA_DISCARD_CFG, 0x00c7d8),
127 REG(ANA_FID_CFG, 0x00c7dc),
128 REG(ANA_POL_PIR_CFG, 0x00a000),
129 REG(ANA_POL_CIR_CFG, 0x00a004),
130 REG(ANA_POL_MODE_CFG, 0x00a008),
131 REG(ANA_POL_PIR_STATE, 0x00a00c),
132 REG(ANA_POL_CIR_STATE, 0x00a010),
133 REG_RESERVED(ANA_POL_STATE),
134 REG(ANA_POL_FLOWC, 0x00c280),
135 REG(ANA_POL_HYST, 0x00c2ec),
136 REG_RESERVED(ANA_POL_MISC_CFG),
137 };
138
139 static const u32 vsc9953_qs_regmap[] = {
140 REG(QS_XTR_GRP_CFG, 0x000000),
141 REG(QS_XTR_RD, 0x000008),
142 REG(QS_XTR_FRM_PRUNING, 0x000010),
143 REG(QS_XTR_FLUSH, 0x000018),
144 REG(QS_XTR_DATA_PRESENT, 0x00001c),
145 REG(QS_XTR_CFG, 0x000020),
146 REG(QS_INJ_GRP_CFG, 0x000024),
147 REG(QS_INJ_WR, 0x00002c),
148 REG(QS_INJ_CTRL, 0x000034),
149 REG(QS_INJ_STATUS, 0x00003c),
150 REG(QS_INJ_ERR, 0x000040),
151 REG_RESERVED(QS_INH_DBG),
152 };
153
154 static const u32 vsc9953_s2_regmap[] = {
155 REG(S2_CORE_UPDATE_CTRL, 0x000000),
156 REG(S2_CORE_MV_CFG, 0x000004),
157 REG(S2_CACHE_ENTRY_DAT, 0x000008),
158 REG(S2_CACHE_MASK_DAT, 0x000108),
159 REG(S2_CACHE_ACTION_DAT, 0x000208),
160 REG(S2_CACHE_CNT_DAT, 0x000308),
161 REG(S2_CACHE_TG_DAT, 0x000388),
162 };
163
164 static const u32 vsc9953_qsys_regmap[] = {
165 REG(QSYS_PORT_MODE, 0x003600),
166 REG(QSYS_SWITCH_PORT_MODE, 0x003630),
167 REG(QSYS_STAT_CNT_CFG, 0x00365c),
168 REG(QSYS_EEE_CFG, 0x003660),
169 REG(QSYS_EEE_THRES, 0x003688),
170 REG(QSYS_IGR_NO_SHARING, 0x00368c),
171 REG(QSYS_EGR_NO_SHARING, 0x003690),
172 REG(QSYS_SW_STATUS, 0x003694),
173 REG(QSYS_EXT_CPU_CFG, 0x0036c0),
174 REG_RESERVED(QSYS_PAD_CFG),
175 REG(QSYS_CPU_GROUP_MAP, 0x0036c8),
176 REG_RESERVED(QSYS_QMAP),
177 REG_RESERVED(QSYS_ISDX_SGRP),
178 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
179 REG_RESERVED(QSYS_TFRM_MISC),
180 REG_RESERVED(QSYS_TFRM_PORT_DLY),
181 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1),
182 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2),
183 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3),
184 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4),
185 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5),
186 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6),
187 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7),
188 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8),
189 REG(QSYS_RED_PROFILE, 0x003724),
190 REG(QSYS_RES_QOS_MODE, 0x003764),
191 REG(QSYS_RES_CFG, 0x004000),
192 REG(QSYS_RES_STAT, 0x004004),
193 REG(QSYS_EGR_DROP_MODE, 0x003768),
194 REG(QSYS_EQ_CTRL, 0x00376c),
195 REG_RESERVED(QSYS_EVENTS_CORE),
196 REG_RESERVED(QSYS_QMAXSDU_CFG_0),
197 REG_RESERVED(QSYS_QMAXSDU_CFG_1),
198 REG_RESERVED(QSYS_QMAXSDU_CFG_2),
199 REG_RESERVED(QSYS_QMAXSDU_CFG_3),
200 REG_RESERVED(QSYS_QMAXSDU_CFG_4),
201 REG_RESERVED(QSYS_QMAXSDU_CFG_5),
202 REG_RESERVED(QSYS_QMAXSDU_CFG_6),
203 REG_RESERVED(QSYS_QMAXSDU_CFG_7),
204 REG_RESERVED(QSYS_PREEMPTION_CFG),
205 REG(QSYS_CIR_CFG, 0x000000),
206 REG_RESERVED(QSYS_EIR_CFG),
207 REG(QSYS_SE_CFG, 0x000008),
208 REG(QSYS_SE_DWRR_CFG, 0x00000c),
209 REG_RESERVED(QSYS_SE_CONNECT),
210 REG_RESERVED(QSYS_SE_DLB_SENSE),
211 REG(QSYS_CIR_STATE, 0x000044),
212 REG_RESERVED(QSYS_EIR_STATE),
213 REG_RESERVED(QSYS_SE_STATE),
214 REG(QSYS_HSCH_MISC_CFG, 0x003774),
215 REG_RESERVED(QSYS_TAG_CONFIG),
216 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL),
217 REG_RESERVED(QSYS_PORT_MAX_SDU),
218 REG_RESERVED(QSYS_PARAM_CFG_REG_1),
219 REG_RESERVED(QSYS_PARAM_CFG_REG_2),
220 REG_RESERVED(QSYS_PARAM_CFG_REG_3),
221 REG_RESERVED(QSYS_PARAM_CFG_REG_4),
222 REG_RESERVED(QSYS_PARAM_CFG_REG_5),
223 REG_RESERVED(QSYS_GCL_CFG_REG_1),
224 REG_RESERVED(QSYS_GCL_CFG_REG_2),
225 REG_RESERVED(QSYS_PARAM_STATUS_REG_1),
226 REG_RESERVED(QSYS_PARAM_STATUS_REG_2),
227 REG_RESERVED(QSYS_PARAM_STATUS_REG_3),
228 REG_RESERVED(QSYS_PARAM_STATUS_REG_4),
229 REG_RESERVED(QSYS_PARAM_STATUS_REG_5),
230 REG_RESERVED(QSYS_PARAM_STATUS_REG_6),
231 REG_RESERVED(QSYS_PARAM_STATUS_REG_7),
232 REG_RESERVED(QSYS_PARAM_STATUS_REG_8),
233 REG_RESERVED(QSYS_PARAM_STATUS_REG_9),
234 REG_RESERVED(QSYS_GCL_STATUS_REG_1),
235 REG_RESERVED(QSYS_GCL_STATUS_REG_2),
236 };
237
238 static const u32 vsc9953_rew_regmap[] = {
239 REG(REW_PORT_VLAN_CFG, 0x000000),
240 REG(REW_TAG_CFG, 0x000004),
241 REG(REW_PORT_CFG, 0x000008),
242 REG(REW_DSCP_CFG, 0x00000c),
243 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
244 REG_RESERVED(REW_PTP_CFG),
245 REG_RESERVED(REW_PTP_DLY1_CFG),
246 REG_RESERVED(REW_RED_TAG_CFG),
247 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610),
248 REG(REW_DSCP_REMAP_CFG, 0x000710),
249 REG_RESERVED(REW_STAT_CFG),
250 REG_RESERVED(REW_REW_STICKY),
251 REG_RESERVED(REW_PPT),
252 };
253
254 static const u32 vsc9953_sys_regmap[] = {
255 REG(SYS_COUNT_RX_OCTETS, 0x000000),
256 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
257 REG(SYS_COUNT_RX_SHORTS, 0x000010),
258 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
259 REG(SYS_COUNT_RX_JABBERS, 0x000018),
260 REG(SYS_COUNT_RX_64, 0x000024),
261 REG(SYS_COUNT_RX_65_127, 0x000028),
262 REG(SYS_COUNT_RX_128_255, 0x00002c),
263 REG(SYS_COUNT_RX_256_1023, 0x000030),
264 REG(SYS_COUNT_RX_1024_1526, 0x000034),
265 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
266 REG(SYS_COUNT_RX_LONGS, 0x000048),
267 REG(SYS_COUNT_TX_OCTETS, 0x000100),
268 REG(SYS_COUNT_TX_COLLISION, 0x000110),
269 REG(SYS_COUNT_TX_DROPS, 0x000114),
270 REG(SYS_COUNT_TX_64, 0x00011c),
271 REG(SYS_COUNT_TX_65_127, 0x000120),
272 REG(SYS_COUNT_TX_128_511, 0x000124),
273 REG(SYS_COUNT_TX_512_1023, 0x000128),
274 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
275 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
276 REG(SYS_COUNT_TX_AGING, 0x000178),
277 REG(SYS_RESET_CFG, 0x000318),
278 REG_RESERVED(SYS_SR_ETYPE_CFG),
279 REG(SYS_VLAN_ETYPE_CFG, 0x000320),
280 REG(SYS_PORT_MODE, 0x000324),
281 REG(SYS_FRONT_PORT_MODE, 0x000354),
282 REG(SYS_FRM_AGING, 0x00037c),
283 REG(SYS_STAT_CFG, 0x000380),
284 REG_RESERVED(SYS_SW_STATUS),
285 REG_RESERVED(SYS_MISC_CFG),
286 REG_RESERVED(SYS_REW_MAC_HIGH_CFG),
287 REG_RESERVED(SYS_REW_MAC_LOW_CFG),
288 REG_RESERVED(SYS_TIMESTAMP_OFFSET),
289 REG(SYS_PAUSE_CFG, 0x00044c),
290 REG(SYS_PAUSE_TOT_CFG, 0x000478),
291 REG(SYS_ATOP, 0x00047c),
292 REG(SYS_ATOP_TOT_CFG, 0x0004a8),
293 REG(SYS_MAC_FC_CFG, 0x0004ac),
294 REG(SYS_MMGT, 0x0004d4),
295 REG_RESERVED(SYS_MMGT_FAST),
296 REG_RESERVED(SYS_EVENTS_DIF),
297 REG_RESERVED(SYS_EVENTS_CORE),
298 REG_RESERVED(SYS_CNT),
299 REG_RESERVED(SYS_PTP_STATUS),
300 REG_RESERVED(SYS_PTP_TXSTAMP),
301 REG_RESERVED(SYS_PTP_NXT),
302 REG_RESERVED(SYS_PTP_CFG),
303 REG_RESERVED(SYS_RAM_INIT),
304 REG_RESERVED(SYS_CM_ADDR),
305 REG_RESERVED(SYS_CM_DATA_WR),
306 REG_RESERVED(SYS_CM_DATA_RD),
307 REG_RESERVED(SYS_CM_OP),
308 REG_RESERVED(SYS_CM_DATA),
309 };
310
311 static const u32 vsc9953_gcb_regmap[] = {
312 REG(GCB_SOFT_RST, 0x000008),
313 REG(GCB_MIIM_MII_STATUS, 0x0000ac),
314 REG(GCB_MIIM_MII_CMD, 0x0000b4),
315 REG(GCB_MIIM_MII_DATA, 0x0000b8),
316 };
317
318 static const u32 vsc9953_dev_gmii_regmap[] = {
319 REG(DEV_CLOCK_CFG, 0x0),
320 REG(DEV_PORT_MISC, 0x4),
321 REG_RESERVED(DEV_EVENTS),
322 REG(DEV_EEE_CFG, 0xc),
323 REG_RESERVED(DEV_RX_PATH_DELAY),
324 REG_RESERVED(DEV_TX_PATH_DELAY),
325 REG_RESERVED(DEV_PTP_PREDICT_CFG),
326 REG(DEV_MAC_ENA_CFG, 0x10),
327 REG(DEV_MAC_MODE_CFG, 0x14),
328 REG(DEV_MAC_MAXLEN_CFG, 0x18),
329 REG(DEV_MAC_TAGS_CFG, 0x1c),
330 REG(DEV_MAC_ADV_CHK_CFG, 0x20),
331 REG(DEV_MAC_IFG_CFG, 0x24),
332 REG(DEV_MAC_HDX_CFG, 0x28),
333 REG_RESERVED(DEV_MAC_DBG_CFG),
334 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30),
335 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34),
336 REG(DEV_MAC_STICKY, 0x38),
337 REG_RESERVED(PCS1G_CFG),
338 REG_RESERVED(PCS1G_MODE_CFG),
339 REG_RESERVED(PCS1G_SD_CFG),
340 REG_RESERVED(PCS1G_ANEG_CFG),
341 REG_RESERVED(PCS1G_ANEG_NP_CFG),
342 REG_RESERVED(PCS1G_LB_CFG),
343 REG_RESERVED(PCS1G_DBG_CFG),
344 REG_RESERVED(PCS1G_CDET_CFG),
345 REG_RESERVED(PCS1G_ANEG_STATUS),
346 REG_RESERVED(PCS1G_ANEG_NP_STATUS),
347 REG_RESERVED(PCS1G_LINK_STATUS),
348 REG_RESERVED(PCS1G_LINK_DOWN_CNT),
349 REG_RESERVED(PCS1G_STICKY),
350 REG_RESERVED(PCS1G_DEBUG_STATUS),
351 REG_RESERVED(PCS1G_LPI_CFG),
352 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
353 REG_RESERVED(PCS1G_LPI_STATUS),
354 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
355 REG_RESERVED(PCS1G_TSTPAT_STATUS),
356 REG_RESERVED(DEV_PCS_FX100_CFG),
357 REG_RESERVED(DEV_PCS_FX100_STATUS),
358 };
359
360 static const u32 *vsc9953_regmap[TARGET_MAX] = {
361 [ANA] = vsc9953_ana_regmap,
362 [QS] = vsc9953_qs_regmap,
363 [QSYS] = vsc9953_qsys_regmap,
364 [REW] = vsc9953_rew_regmap,
365 [SYS] = vsc9953_sys_regmap,
366 [S2] = vsc9953_s2_regmap,
367 [GCB] = vsc9953_gcb_regmap,
368 [DEV_GMII] = vsc9953_dev_gmii_regmap,
369 };
370
371 /* Addresses are relative to the device's base address */
372 static const struct resource vsc9953_target_io_res[TARGET_MAX] = {
373 [ANA] = {
374 .start = 0x0280000,
375 .end = 0x028ffff,
376 .name = "ana",
377 },
378 [QS] = {
379 .start = 0x0080000,
380 .end = 0x00800ff,
381 .name = "qs",
382 },
383 [QSYS] = {
384 .start = 0x0200000,
385 .end = 0x021ffff,
386 .name = "qsys",
387 },
388 [REW] = {
389 .start = 0x0030000,
390 .end = 0x003ffff,
391 .name = "rew",
392 },
393 [SYS] = {
394 .start = 0x0010000,
395 .end = 0x001ffff,
396 .name = "sys",
397 },
398 [S2] = {
399 .start = 0x0060000,
400 .end = 0x00603ff,
401 .name = "s2",
402 },
403 [PTP] = {
404 .start = 0x0090000,
405 .end = 0x00900cb,
406 .name = "ptp",
407 },
408 [GCB] = {
409 .start = 0x0070000,
410 .end = 0x00701ff,
411 .name = "devcpu_gcb",
412 },
413 };
414
415 static const struct resource vsc9953_port_io_res[] = {
416 {
417 .start = 0x0100000,
418 .end = 0x010ffff,
419 .name = "port0",
420 },
421 {
422 .start = 0x0110000,
423 .end = 0x011ffff,
424 .name = "port1",
425 },
426 {
427 .start = 0x0120000,
428 .end = 0x012ffff,
429 .name = "port2",
430 },
431 {
432 .start = 0x0130000,
433 .end = 0x013ffff,
434 .name = "port3",
435 },
436 {
437 .start = 0x0140000,
438 .end = 0x014ffff,
439 .name = "port4",
440 },
441 {
442 .start = 0x0150000,
443 .end = 0x015ffff,
444 .name = "port5",
445 },
446 {
447 .start = 0x0160000,
448 .end = 0x016ffff,
449 .name = "port6",
450 },
451 {
452 .start = 0x0170000,
453 .end = 0x017ffff,
454 .name = "port7",
455 },
456 {
457 .start = 0x0180000,
458 .end = 0x018ffff,
459 .name = "port8",
460 },
461 {
462 .start = 0x0190000,
463 .end = 0x019ffff,
464 .name = "port9",
465 },
466 };
467
468 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {
469 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10),
470 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9),
471 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
472 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
473 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
474 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
475 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
476 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
477 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
478 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
479 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
480 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
481 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
482 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
483 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
484 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
485 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
486 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
487 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
488 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
489 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
490 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
491 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
492 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
493 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
494 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
495 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
496 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
497 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7),
498 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6),
499 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5),
500 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
501 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2),
502 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3),
503 /* Replicated per number of ports (11), register size 4 per port */
504 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4),
505 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4),
506 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4),
507 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4),
508 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4),
509 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4),
510 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4),
511 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4),
512 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4),
513 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4),
514 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4),
515 };
516
517 static const struct ocelot_stat_layout vsc9953_stats_layout[] = {
518 { .offset = 0x00, .name = "rx_octets", },
519 { .offset = 0x01, .name = "rx_unicast", },
520 { .offset = 0x02, .name = "rx_multicast", },
521 { .offset = 0x03, .name = "rx_broadcast", },
522 { .offset = 0x04, .name = "rx_shorts", },
523 { .offset = 0x05, .name = "rx_fragments", },
524 { .offset = 0x06, .name = "rx_jabbers", },
525 { .offset = 0x07, .name = "rx_crc_align_errs", },
526 { .offset = 0x08, .name = "rx_sym_errs", },
527 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
528 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
529 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
530 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
531 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
532 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
533 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
534 { .offset = 0x10, .name = "rx_pause", },
535 { .offset = 0x11, .name = "rx_control", },
536 { .offset = 0x12, .name = "rx_longs", },
537 { .offset = 0x13, .name = "rx_classified_drops", },
538 { .offset = 0x14, .name = "rx_red_prio_0", },
539 { .offset = 0x15, .name = "rx_red_prio_1", },
540 { .offset = 0x16, .name = "rx_red_prio_2", },
541 { .offset = 0x17, .name = "rx_red_prio_3", },
542 { .offset = 0x18, .name = "rx_red_prio_4", },
543 { .offset = 0x19, .name = "rx_red_prio_5", },
544 { .offset = 0x1A, .name = "rx_red_prio_6", },
545 { .offset = 0x1B, .name = "rx_red_prio_7", },
546 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
547 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
548 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
549 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
550 { .offset = 0x20, .name = "rx_yellow_prio_4", },
551 { .offset = 0x21, .name = "rx_yellow_prio_5", },
552 { .offset = 0x22, .name = "rx_yellow_prio_6", },
553 { .offset = 0x23, .name = "rx_yellow_prio_7", },
554 { .offset = 0x24, .name = "rx_green_prio_0", },
555 { .offset = 0x25, .name = "rx_green_prio_1", },
556 { .offset = 0x26, .name = "rx_green_prio_2", },
557 { .offset = 0x27, .name = "rx_green_prio_3", },
558 { .offset = 0x28, .name = "rx_green_prio_4", },
559 { .offset = 0x29, .name = "rx_green_prio_5", },
560 { .offset = 0x2A, .name = "rx_green_prio_6", },
561 { .offset = 0x2B, .name = "rx_green_prio_7", },
562 { .offset = 0x40, .name = "tx_octets", },
563 { .offset = 0x41, .name = "tx_unicast", },
564 { .offset = 0x42, .name = "tx_multicast", },
565 { .offset = 0x43, .name = "tx_broadcast", },
566 { .offset = 0x44, .name = "tx_collision", },
567 { .offset = 0x45, .name = "tx_drops", },
568 { .offset = 0x46, .name = "tx_pause", },
569 { .offset = 0x47, .name = "tx_frames_below_65_octets", },
570 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", },
571 { .offset = 0x49, .name = "tx_frames_128_255_octets", },
572 { .offset = 0x4A, .name = "tx_frames_256_511_octets", },
573 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", },
574 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", },
575 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", },
576 { .offset = 0x4E, .name = "tx_yellow_prio_0", },
577 { .offset = 0x4F, .name = "tx_yellow_prio_1", },
578 { .offset = 0x50, .name = "tx_yellow_prio_2", },
579 { .offset = 0x51, .name = "tx_yellow_prio_3", },
580 { .offset = 0x52, .name = "tx_yellow_prio_4", },
581 { .offset = 0x53, .name = "tx_yellow_prio_5", },
582 { .offset = 0x54, .name = "tx_yellow_prio_6", },
583 { .offset = 0x55, .name = "tx_yellow_prio_7", },
584 { .offset = 0x56, .name = "tx_green_prio_0", },
585 { .offset = 0x57, .name = "tx_green_prio_1", },
586 { .offset = 0x58, .name = "tx_green_prio_2", },
587 { .offset = 0x59, .name = "tx_green_prio_3", },
588 { .offset = 0x5A, .name = "tx_green_prio_4", },
589 { .offset = 0x5B, .name = "tx_green_prio_5", },
590 { .offset = 0x5C, .name = "tx_green_prio_6", },
591 { .offset = 0x5D, .name = "tx_green_prio_7", },
592 { .offset = 0x5E, .name = "tx_aged", },
593 { .offset = 0x80, .name = "drop_local", },
594 { .offset = 0x81, .name = "drop_tail", },
595 { .offset = 0x82, .name = "drop_yellow_prio_0", },
596 { .offset = 0x83, .name = "drop_yellow_prio_1", },
597 { .offset = 0x84, .name = "drop_yellow_prio_2", },
598 { .offset = 0x85, .name = "drop_yellow_prio_3", },
599 { .offset = 0x86, .name = "drop_yellow_prio_4", },
600 { .offset = 0x87, .name = "drop_yellow_prio_5", },
601 { .offset = 0x88, .name = "drop_yellow_prio_6", },
602 { .offset = 0x89, .name = "drop_yellow_prio_7", },
603 { .offset = 0x8A, .name = "drop_green_prio_0", },
604 { .offset = 0x8B, .name = "drop_green_prio_1", },
605 { .offset = 0x8C, .name = "drop_green_prio_2", },
606 { .offset = 0x8D, .name = "drop_green_prio_3", },
607 { .offset = 0x8E, .name = "drop_green_prio_4", },
608 { .offset = 0x8F, .name = "drop_green_prio_5", },
609 { .offset = 0x90, .name = "drop_green_prio_6", },
610 { .offset = 0x91, .name = "drop_green_prio_7", },
611 };
612
613 static struct vcap_field vsc9953_vcap_is2_keys[] = {
614 /* Common: 41 bits */
615 [VCAP_IS2_TYPE] = { 0, 4},
616 [VCAP_IS2_HK_FIRST] = { 4, 1},
617 [VCAP_IS2_HK_PAG] = { 5, 8},
618 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11},
619 [VCAP_IS2_HK_RSV2] = { 24, 1},
620 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1},
621 [VCAP_IS2_HK_L2_MC] = { 26, 1},
622 [VCAP_IS2_HK_L2_BC] = { 27, 1},
623 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1},
624 [VCAP_IS2_HK_VID] = { 29, 12},
625 [VCAP_IS2_HK_DEI] = { 41, 1},
626 [VCAP_IS2_HK_PCP] = { 42, 3},
627 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
628 [VCAP_IS2_HK_L2_DMAC] = { 45, 48},
629 [VCAP_IS2_HK_L2_SMAC] = { 93, 48},
630 /* MAC_ETYPE (TYPE=000) */
631 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16},
632 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16},
633 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8},
634 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3},
635 /* MAC_LLC (TYPE=001) */
636 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40},
637 /* MAC_SNAP (TYPE=010) */
638 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40},
639 /* MAC_ARP (TYPE=011) */
640 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48},
641 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1},
642 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1},
643 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1},
644 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1},
645 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1},
646 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1},
647 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2},
648 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32},
649 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32},
650 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1},
651 /* IP4_TCP_UDP / IP4_OTHER common */
652 [VCAP_IS2_HK_IP4] = { 45, 1},
653 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1},
654 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1},
655 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1},
656 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1},
657 [VCAP_IS2_HK_L3_TOS] = { 50, 8},
658 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32},
659 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32},
660 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1},
661 /* IP4_TCP_UDP (TYPE=100) */
662 [VCAP_IS2_HK_TCP] = {123, 1},
663 [VCAP_IS2_HK_L4_SPORT] = {124, 16},
664 [VCAP_IS2_HK_L4_DPORT] = {140, 16},
665 [VCAP_IS2_HK_L4_RNG] = {156, 8},
666 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1},
667 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1},
668 [VCAP_IS2_HK_L4_URG] = {166, 1},
669 [VCAP_IS2_HK_L4_ACK] = {167, 1},
670 [VCAP_IS2_HK_L4_PSH] = {168, 1},
671 [VCAP_IS2_HK_L4_RST] = {169, 1},
672 [VCAP_IS2_HK_L4_SYN] = {170, 1},
673 [VCAP_IS2_HK_L4_FIN] = {171, 1},
674 /* IP4_OTHER (TYPE=101) */
675 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8},
676 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56},
677 /* IP6_STD (TYPE=110) */
678 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1},
679 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128},
680 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8},
681 };
682
683 static struct vcap_field vsc9953_vcap_is2_actions[] = {
684 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
685 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
686 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
687 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
688 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
689 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
690 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
691 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8},
692 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1},
693 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10},
694 [VCAP_IS2_ACT_ACL_ID] = { 44, 6},
695 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32},
696 };
697
698 static const struct vcap_props vsc9953_vcap_props[] = {
699 [VCAP_IS2] = {
700 .tg_width = 2,
701 .sw_count = 4,
702 .entry_count = VSC9953_VCAP_IS2_CNT,
703 .entry_width = VSC9953_VCAP_IS2_ENTRY_WIDTH,
704 .action_count = VSC9953_VCAP_IS2_CNT +
705 VSC9953_VCAP_PORT_CNT + 2,
706 .action_width = 101,
707 .action_type_width = 1,
708 .action_table = {
709 [IS2_ACTION_TYPE_NORMAL] = {
710 .width = 44,
711 .count = 2
712 },
713 [IS2_ACTION_TYPE_SMAC_SIP] = {
714 .width = 6,
715 .count = 4
716 },
717 },
718 .counter_words = 4,
719 .counter_width = 32,
720 },
721 };
722
723 #define VSC9953_INIT_TIMEOUT 50000
724 #define VSC9953_GCB_RST_SLEEP 100
725 #define VSC9953_SYS_RAMINIT_SLEEP 80
726 #define VCS9953_MII_TIMEOUT 10000
727
728 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
729 {
730 int val;
731
732 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
733
734 return val;
735 }
736
737 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
738 {
739 int val;
740
741 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val);
742
743 return val;
744 }
745
746 static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot)
747 {
748 int val;
749
750 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val);
751
752 return val;
753 }
754
755 static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot)
756 {
757 int val;
758
759 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val);
760
761 return val;
762 }
763
764 static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
765 u16 value)
766 {
767 struct ocelot *ocelot = bus->priv;
768 int err, cmd, val;
769
770 /* Wait while MIIM controller becomes idle */
771 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
772 val, !val, 10, VCS9953_MII_TIMEOUT);
773 if (err) {
774 dev_err(ocelot->dev, "MDIO write: pending timeout\n");
775 goto out;
776 }
777
778 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
779 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
780 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
781 MSCC_MIIM_CMD_OPR_WRITE;
782
783 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
784
785 out:
786 return err;
787 }
788
789 static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
790 {
791 struct ocelot *ocelot = bus->priv;
792 int err, cmd, val;
793
794 /* Wait until MIIM controller becomes idle */
795 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
796 val, !val, 10, VCS9953_MII_TIMEOUT);
797 if (err) {
798 dev_err(ocelot->dev, "MDIO read: pending timeout\n");
799 goto out;
800 }
801
802 /* Write the MIIM COMMAND register */
803 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
804 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ;
805
806 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
807
808 /* Wait while read operation via the MIIM controller is in progress */
809 err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot,
810 val, !val, 10, VCS9953_MII_TIMEOUT);
811 if (err) {
812 dev_err(ocelot->dev, "MDIO read: busy timeout\n");
813 goto out;
814 }
815
816 val = ocelot_read(ocelot, GCB_MIIM_MII_DATA);
817
818 err = val & 0xFFFF;
819 out:
820 return err;
821 }
822
823 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
824 * MEM_INIT is in SYS:SYSTEM:RESET_CFG
825 * MEM_ENA is in SYS:SYSTEM:RESET_CFG
826 */
827 static int vsc9953_reset(struct ocelot *ocelot)
828 {
829 int val, err;
830
831 /* soft-reset the switch core */
832 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
833
834 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val,
835 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT);
836 if (err) {
837 dev_err(ocelot->dev, "timeout: switch core reset\n");
838 return err;
839 }
840
841 /* initialize switch mem ~40us */
842 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
843 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1);
844
845 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val,
846 VSC9953_SYS_RAMINIT_SLEEP,
847 VSC9953_INIT_TIMEOUT);
848 if (err) {
849 dev_err(ocelot->dev, "timeout: switch sram init\n");
850 return err;
851 }
852
853 /* enable switch core */
854 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
855
856 return 0;
857 }
858
859 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port,
860 unsigned long *supported,
861 struct phylink_link_state *state)
862 {
863 struct ocelot_port *ocelot_port = ocelot->ports[port];
864 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
865
866 if (state->interface != PHY_INTERFACE_MODE_NA &&
867 state->interface != ocelot_port->phy_mode) {
868 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
869 return;
870 }
871
872 phylink_set_port_modes(mask);
873 phylink_set(mask, Autoneg);
874 phylink_set(mask, Pause);
875 phylink_set(mask, Asym_Pause);
876 phylink_set(mask, 10baseT_Full);
877 phylink_set(mask, 10baseT_Half);
878 phylink_set(mask, 100baseT_Full);
879 phylink_set(mask, 100baseT_Half);
880 phylink_set(mask, 1000baseT_Full);
881
882 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
883 phylink_set(mask, 2500baseT_Full);
884 phylink_set(mask, 2500baseX_Full);
885 }
886
887 bitmap_and(supported, supported, mask,
888 __ETHTOOL_LINK_MODE_MASK_NBITS);
889 bitmap_and(state->advertising, state->advertising, mask,
890 __ETHTOOL_LINK_MODE_MASK_NBITS);
891 }
892
893 static int vsc9953_prevalidate_phy_mode(struct ocelot *ocelot, int port,
894 phy_interface_t phy_mode)
895 {
896 switch (phy_mode) {
897 case PHY_INTERFACE_MODE_INTERNAL:
898 if (port != 8 && port != 9)
899 return -ENOTSUPP;
900 return 0;
901 case PHY_INTERFACE_MODE_SGMII:
902 case PHY_INTERFACE_MODE_QSGMII:
903 /* Not supported on internal to-CPU ports */
904 if (port == 8 || port == 9)
905 return -ENOTSUPP;
906 return 0;
907 default:
908 return -ENOTSUPP;
909 }
910 }
911
912 /* Watermark encode
913 * Bit 9: Unit; 0:1, 1:16
914 * Bit 8-0: Value to be multiplied with unit
915 */
916 static u16 vsc9953_wm_enc(u16 value)
917 {
918 if (value >= BIT(9))
919 return BIT(9) | (value / 16);
920
921 return value;
922 }
923
924 static const struct ocelot_ops vsc9953_ops = {
925 .reset = vsc9953_reset,
926 .wm_enc = vsc9953_wm_enc,
927 };
928
929 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
930 {
931 struct felix *felix = ocelot_to_felix(ocelot);
932 struct device *dev = ocelot->dev;
933 struct mii_bus *bus;
934 int port;
935 int rc;
936
937 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
938 sizeof(struct phy_device *),
939 GFP_KERNEL);
940 if (!felix->pcs) {
941 dev_err(dev, "failed to allocate array for PCS PHYs\n");
942 return -ENOMEM;
943 }
944
945 bus = devm_mdiobus_alloc(dev);
946 if (!bus)
947 return -ENOMEM;
948
949 bus->name = "VSC9953 internal MDIO bus";
950 bus->read = vsc9953_mdio_read;
951 bus->write = vsc9953_mdio_write;
952 bus->parent = dev;
953 bus->priv = ocelot;
954 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
955
956 /* Needed in order to initialize the bus mutex lock */
957 rc = mdiobus_register(bus);
958 if (rc < 0) {
959 dev_err(dev, "failed to register MDIO bus\n");
960 return rc;
961 }
962
963 felix->imdio = bus;
964
965 for (port = 0; port < felix->info->num_ports; port++) {
966 struct ocelot_port *ocelot_port = ocelot->ports[port];
967 int addr = port + 4;
968 struct mdio_device *pcs;
969 struct lynx_pcs *lynx;
970
971 if (dsa_is_unused_port(felix->ds, port))
972 continue;
973
974 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
975 continue;
976
977 pcs = mdio_device_create(felix->imdio, addr);
978 if (IS_ERR(pcs))
979 continue;
980
981 lynx = lynx_pcs_create(pcs);
982 if (!lynx) {
983 mdio_device_free(pcs);
984 continue;
985 }
986
987 felix->pcs[port] = lynx;
988
989 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr);
990 }
991
992 return 0;
993 }
994
995 static void vsc9953_xmit_template_populate(struct ocelot *ocelot, int port)
996 {
997 struct ocelot_port *ocelot_port = ocelot->ports[port];
998 u8 *template = ocelot_port->xmit_template;
999 u64 bypass, dest, src;
1000
1001 /* Set the source port as the CPU port module and not the
1002 * NPI port
1003 */
1004 src = ocelot->num_phys_ports;
1005 dest = BIT(port);
1006 bypass = true;
1007
1008 packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
1009 packing(template, &dest, 67, 57, OCELOT_TAG_LEN, PACK, 0);
1010 packing(template, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0);
1011 }
1012
1013 static const struct felix_info seville_info_vsc9953 = {
1014 .target_io_res = vsc9953_target_io_res,
1015 .port_io_res = vsc9953_port_io_res,
1016 .regfields = vsc9953_regfields,
1017 .map = vsc9953_regmap,
1018 .ops = &vsc9953_ops,
1019 .stats_layout = vsc9953_stats_layout,
1020 .num_stats = ARRAY_SIZE(vsc9953_stats_layout),
1021 .vcap_is2_keys = vsc9953_vcap_is2_keys,
1022 .vcap_is2_actions = vsc9953_vcap_is2_actions,
1023 .vcap = vsc9953_vcap_props,
1024 .shared_queue_sz = 128 * 1024,
1025 .num_mact_rows = 2048,
1026 .num_ports = 10,
1027 .mdio_bus_alloc = vsc9953_mdio_bus_alloc,
1028 .mdio_bus_free = vsc9959_mdio_bus_free,
1029 .phylink_validate = vsc9953_phylink_validate,
1030 .prevalidate_phy_mode = vsc9953_prevalidate_phy_mode,
1031 .xmit_template_populate = vsc9953_xmit_template_populate,
1032 };
1033
1034 static int seville_probe(struct platform_device *pdev)
1035 {
1036 struct dsa_switch *ds;
1037 struct ocelot *ocelot;
1038 struct resource *res;
1039 struct felix *felix;
1040 int err;
1041
1042 felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1043 if (!felix) {
1044 err = -ENOMEM;
1045 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1046 goto err_alloc_felix;
1047 }
1048
1049 platform_set_drvdata(pdev, felix);
1050
1051 ocelot = &felix->ocelot;
1052 ocelot->dev = &pdev->dev;
1053 felix->info = &seville_info_vsc9953;
1054
1055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 felix->switch_base = res->start;
1057
1058 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1059 if (!ds) {
1060 err = -ENOMEM;
1061 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1062 goto err_alloc_ds;
1063 }
1064
1065 ds->dev = &pdev->dev;
1066 ds->num_ports = felix->info->num_ports;
1067 ds->ops = &felix_switch_ops;
1068 ds->priv = ocelot;
1069 felix->ds = ds;
1070
1071 err = dsa_register_switch(ds);
1072 if (err) {
1073 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1074 goto err_register_ds;
1075 }
1076
1077 return 0;
1078
1079 err_register_ds:
1080 kfree(ds);
1081 err_alloc_ds:
1082 err_alloc_felix:
1083 kfree(felix);
1084 return err;
1085 }
1086
1087 static int seville_remove(struct platform_device *pdev)
1088 {
1089 struct felix *felix;
1090
1091 felix = platform_get_drvdata(pdev);
1092
1093 dsa_unregister_switch(felix->ds);
1094
1095 kfree(felix->ds);
1096 kfree(felix);
1097
1098 return 0;
1099 }
1100
1101 static const struct of_device_id seville_of_match[] = {
1102 { .compatible = "mscc,vsc9953-switch" },
1103 { },
1104 };
1105 MODULE_DEVICE_TABLE(of, seville_of_match);
1106
1107 struct platform_driver seville_vsc9953_driver = {
1108 .probe = seville_probe,
1109 .remove = seville_remove,
1110 .driver = {
1111 .name = "mscc_seville",
1112 .of_match_table = of_match_ptr(seville_of_match),
1113 },
1114 };
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