2 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
3 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/netdevice.h>
21 #include <linux/of_net.h>
22 #include <linux/of_platform.h>
23 #include <linux/if_bridge.h>
24 #include <linux/mdio.h>
25 #include <linux/etherdevice.h>
29 #define MIB_DESC(_s, _o, _n) \
36 static const struct qca8k_mib_desc ar8327_mib
[] = {
37 MIB_DESC(1, 0x00, "RxBroad"),
38 MIB_DESC(1, 0x04, "RxPause"),
39 MIB_DESC(1, 0x08, "RxMulti"),
40 MIB_DESC(1, 0x0c, "RxFcsErr"),
41 MIB_DESC(1, 0x10, "RxAlignErr"),
42 MIB_DESC(1, 0x14, "RxRunt"),
43 MIB_DESC(1, 0x18, "RxFragment"),
44 MIB_DESC(1, 0x1c, "Rx64Byte"),
45 MIB_DESC(1, 0x20, "Rx128Byte"),
46 MIB_DESC(1, 0x24, "Rx256Byte"),
47 MIB_DESC(1, 0x28, "Rx512Byte"),
48 MIB_DESC(1, 0x2c, "Rx1024Byte"),
49 MIB_DESC(1, 0x30, "Rx1518Byte"),
50 MIB_DESC(1, 0x34, "RxMaxByte"),
51 MIB_DESC(1, 0x38, "RxTooLong"),
52 MIB_DESC(2, 0x3c, "RxGoodByte"),
53 MIB_DESC(2, 0x44, "RxBadByte"),
54 MIB_DESC(1, 0x4c, "RxOverFlow"),
55 MIB_DESC(1, 0x50, "Filtered"),
56 MIB_DESC(1, 0x54, "TxBroad"),
57 MIB_DESC(1, 0x58, "TxPause"),
58 MIB_DESC(1, 0x5c, "TxMulti"),
59 MIB_DESC(1, 0x60, "TxUnderRun"),
60 MIB_DESC(1, 0x64, "Tx64Byte"),
61 MIB_DESC(1, 0x68, "Tx128Byte"),
62 MIB_DESC(1, 0x6c, "Tx256Byte"),
63 MIB_DESC(1, 0x70, "Tx512Byte"),
64 MIB_DESC(1, 0x74, "Tx1024Byte"),
65 MIB_DESC(1, 0x78, "Tx1518Byte"),
66 MIB_DESC(1, 0x7c, "TxMaxByte"),
67 MIB_DESC(1, 0x80, "TxOverSize"),
68 MIB_DESC(2, 0x84, "TxByte"),
69 MIB_DESC(1, 0x8c, "TxCollision"),
70 MIB_DESC(1, 0x90, "TxAbortCol"),
71 MIB_DESC(1, 0x94, "TxMultiCol"),
72 MIB_DESC(1, 0x98, "TxSingleCol"),
73 MIB_DESC(1, 0x9c, "TxExcDefer"),
74 MIB_DESC(1, 0xa0, "TxDefer"),
75 MIB_DESC(1, 0xa4, "TxLateCol"),
78 /* The 32bit switch registers are accessed indirectly. To achieve this we need
79 * to set the page of the register. Track the last page that was set to reduce
82 static u16 qca8k_current_page
= 0xffff;
85 qca8k_split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
94 *page
= regaddr
& 0x3ff;
98 qca8k_mii_read32(struct mii_bus
*bus
, int phy_id
, u32 regnum
)
103 ret
= bus
->read(bus
, phy_id
, regnum
);
106 ret
= bus
->read(bus
, phy_id
, regnum
+ 1);
111 dev_err_ratelimited(&bus
->dev
,
112 "failed to read qca8k 32bit register\n");
120 qca8k_mii_write32(struct mii_bus
*bus
, int phy_id
, u32 regnum
, u32 val
)
126 hi
= (u16
)(val
>> 16);
128 ret
= bus
->write(bus
, phy_id
, regnum
, lo
);
130 ret
= bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
132 dev_err_ratelimited(&bus
->dev
,
133 "failed to write qca8k 32bit register\n");
137 qca8k_set_page(struct mii_bus
*bus
, u16 page
)
139 if (page
== qca8k_current_page
)
142 if (bus
->write(bus
, 0x18, 0, page
) < 0)
143 dev_err_ratelimited(&bus
->dev
,
144 "failed to set qca8k page\n");
145 qca8k_current_page
= page
;
149 qca8k_read(struct qca8k_priv
*priv
, u32 reg
)
154 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
156 mutex_lock_nested(&priv
->bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
158 qca8k_set_page(priv
->bus
, page
);
159 val
= qca8k_mii_read32(priv
->bus
, 0x10 | r2
, r1
);
161 mutex_unlock(&priv
->bus
->mdio_lock
);
167 qca8k_write(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
171 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
173 mutex_lock_nested(&priv
->bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
175 qca8k_set_page(priv
->bus
, page
);
176 qca8k_mii_write32(priv
->bus
, 0x10 | r2
, r1
, val
);
178 mutex_unlock(&priv
->bus
->mdio_lock
);
182 qca8k_rmw(struct qca8k_priv
*priv
, u32 reg
, u32 mask
, u32 val
)
187 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
189 mutex_lock_nested(&priv
->bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
191 qca8k_set_page(priv
->bus
, page
);
192 ret
= qca8k_mii_read32(priv
->bus
, 0x10 | r2
, r1
);
195 qca8k_mii_write32(priv
->bus
, 0x10 | r2
, r1
, ret
);
197 mutex_unlock(&priv
->bus
->mdio_lock
);
203 qca8k_reg_set(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
205 qca8k_rmw(priv
, reg
, 0, val
);
209 qca8k_reg_clear(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
211 qca8k_rmw(priv
, reg
, val
, 0);
215 qca8k_regmap_read(void *ctx
, uint32_t reg
, uint32_t *val
)
217 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ctx
;
219 *val
= qca8k_read(priv
, reg
);
225 qca8k_regmap_write(void *ctx
, uint32_t reg
, uint32_t val
)
227 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ctx
;
229 qca8k_write(priv
, reg
, val
);
234 static const struct regmap_range qca8k_readable_ranges
[] = {
235 regmap_reg_range(0x0000, 0x00e4), /* Global control */
236 regmap_reg_range(0x0100, 0x0168), /* EEE control */
237 regmap_reg_range(0x0200, 0x0270), /* Parser control */
238 regmap_reg_range(0x0400, 0x0454), /* ACL */
239 regmap_reg_range(0x0600, 0x0718), /* Lookup */
240 regmap_reg_range(0x0800, 0x0b70), /* QM */
241 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
242 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
243 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
244 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
245 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
246 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
247 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
248 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
249 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
253 static const struct regmap_access_table qca8k_readable_table
= {
254 .yes_ranges
= qca8k_readable_ranges
,
255 .n_yes_ranges
= ARRAY_SIZE(qca8k_readable_ranges
),
258 static struct regmap_config qca8k_regmap_config
= {
262 .max_register
= 0x16ac, /* end MIB - Port6 range */
263 .reg_read
= qca8k_regmap_read
,
264 .reg_write
= qca8k_regmap_write
,
265 .rd_table
= &qca8k_readable_table
,
269 qca8k_busy_wait(struct qca8k_priv
*priv
, u32 reg
, u32 mask
)
271 unsigned long timeout
;
273 timeout
= jiffies
+ msecs_to_jiffies(20);
275 /* loop until the busy flag has cleared */
277 u32 val
= qca8k_read(priv
, reg
);
278 int busy
= val
& mask
;
283 } while (!time_after_eq(jiffies
, timeout
));
285 return time_after_eq(jiffies
, timeout
);
289 qca8k_fdb_read(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
)
294 /* load the ARL table into an array */
295 for (i
= 0; i
< 4; i
++)
296 reg
[i
] = qca8k_read(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4));
299 fdb
->vid
= (reg
[2] >> QCA8K_ATU_VID_S
) & QCA8K_ATU_VID_M
;
301 fdb
->aging
= reg
[2] & QCA8K_ATU_STATUS_M
;
302 /* portmask - 54:48 */
303 fdb
->port_mask
= (reg
[1] >> QCA8K_ATU_PORT_S
) & QCA8K_ATU_PORT_M
;
305 fdb
->mac
[0] = (reg
[1] >> QCA8K_ATU_ADDR0_S
) & 0xff;
306 fdb
->mac
[1] = reg
[1] & 0xff;
307 fdb
->mac
[2] = (reg
[0] >> QCA8K_ATU_ADDR2_S
) & 0xff;
308 fdb
->mac
[3] = (reg
[0] >> QCA8K_ATU_ADDR3_S
) & 0xff;
309 fdb
->mac
[4] = (reg
[0] >> QCA8K_ATU_ADDR4_S
) & 0xff;
310 fdb
->mac
[5] = reg
[0] & 0xff;
314 qca8k_fdb_write(struct qca8k_priv
*priv
, u16 vid
, u8 port_mask
, const u8
*mac
,
321 reg
[2] = (vid
& QCA8K_ATU_VID_M
) << QCA8K_ATU_VID_S
;
323 reg
[2] |= aging
& QCA8K_ATU_STATUS_M
;
324 /* portmask - 54:48 */
325 reg
[1] = (port_mask
& QCA8K_ATU_PORT_M
) << QCA8K_ATU_PORT_S
;
327 reg
[1] |= mac
[0] << QCA8K_ATU_ADDR0_S
;
329 reg
[0] |= mac
[2] << QCA8K_ATU_ADDR2_S
;
330 reg
[0] |= mac
[3] << QCA8K_ATU_ADDR3_S
;
331 reg
[0] |= mac
[4] << QCA8K_ATU_ADDR4_S
;
334 /* load the array into the ARL table */
335 for (i
= 0; i
< 3; i
++)
336 qca8k_write(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), reg
[i
]);
340 qca8k_fdb_access(struct qca8k_priv
*priv
, enum qca8k_fdb_cmd cmd
, int port
)
344 /* Set the command and FDB index */
345 reg
= QCA8K_ATU_FUNC_BUSY
;
348 reg
|= QCA8K_ATU_FUNC_PORT_EN
;
349 reg
|= (port
& QCA8K_ATU_FUNC_PORT_M
) << QCA8K_ATU_FUNC_PORT_S
;
352 /* Write the function register triggering the table access */
353 qca8k_write(priv
, QCA8K_REG_ATU_FUNC
, reg
);
355 /* wait for completion */
356 if (qca8k_busy_wait(priv
, QCA8K_REG_ATU_FUNC
, QCA8K_ATU_FUNC_BUSY
))
359 /* Check for table full violation when adding an entry */
360 if (cmd
== QCA8K_FDB_LOAD
) {
361 reg
= qca8k_read(priv
, QCA8K_REG_ATU_FUNC
);
362 if (reg
& QCA8K_ATU_FUNC_FULL
)
370 qca8k_fdb_next(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
, int port
)
374 qca8k_fdb_write(priv
, fdb
->vid
, fdb
->port_mask
, fdb
->mac
, fdb
->aging
);
375 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_NEXT
, port
);
377 qca8k_fdb_read(priv
, fdb
);
383 qca8k_fdb_add(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
,
388 mutex_lock(&priv
->reg_mutex
);
389 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, aging
);
390 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_LOAD
, -1);
391 mutex_unlock(&priv
->reg_mutex
);
397 qca8k_fdb_del(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
, u16 vid
)
401 mutex_lock(&priv
->reg_mutex
);
402 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, 0);
403 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_PURGE
, -1);
404 mutex_unlock(&priv
->reg_mutex
);
410 qca8k_fdb_flush(struct qca8k_priv
*priv
)
412 mutex_lock(&priv
->reg_mutex
);
413 qca8k_fdb_access(priv
, QCA8K_FDB_FLUSH
, -1);
414 mutex_unlock(&priv
->reg_mutex
);
418 qca8k_mib_init(struct qca8k_priv
*priv
)
420 mutex_lock(&priv
->reg_mutex
);
421 qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_FLUSH
| QCA8K_MIB_BUSY
);
422 qca8k_busy_wait(priv
, QCA8K_REG_MIB
, QCA8K_MIB_BUSY
);
423 qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_CPU_KEEP
);
424 qca8k_write(priv
, QCA8K_REG_MODULE_EN
, QCA8K_MODULE_EN_MIB
);
425 mutex_unlock(&priv
->reg_mutex
);
429 qca8k_set_pad_ctrl(struct qca8k_priv
*priv
, int port
, int mode
)
435 reg
= QCA8K_REG_PORT0_PAD_CTRL
;
438 reg
= QCA8K_REG_PORT6_PAD_CTRL
;
441 pr_err("Can't set PAD_CTRL on port %d\n", port
);
445 /* Configure a port to be directly connected to an external
449 case PHY_INTERFACE_MODE_RGMII
:
450 qca8k_write(priv
, reg
,
451 QCA8K_PORT_PAD_RGMII_EN
|
452 QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
453 QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
455 /* According to the datasheet, RGMII delay is enabled through
456 * PORT5_PAD_CTRL for all ports, rather than individual port
459 qca8k_write(priv
, QCA8K_REG_PORT5_PAD_CTRL
,
460 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN
);
462 case PHY_INTERFACE_MODE_SGMII
:
463 qca8k_write(priv
, reg
, QCA8K_PORT_PAD_SGMII_EN
);
466 pr_err("xMII mode %d not supported\n", mode
);
474 qca8k_port_set_status(struct qca8k_priv
*priv
, int port
, int enable
)
476 u32 mask
= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
478 /* Port 0 and 6 have no internal PHY */
479 if ((port
> 0) && (port
< 6))
480 mask
|= QCA8K_PORT_STATUS_LINK_AUTO
;
483 qca8k_reg_set(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
485 qca8k_reg_clear(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
489 qca8k_setup(struct dsa_switch
*ds
)
491 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
492 int ret
, i
, phy_mode
= -1;
495 /* Make sure that port 0 is the cpu port */
496 if (!dsa_is_cpu_port(ds
, 0)) {
497 pr_err("port 0 is not the CPU port\n");
501 mutex_init(&priv
->reg_mutex
);
503 /* Start by setting up the register mapping */
504 priv
->regmap
= devm_regmap_init(ds
->dev
, NULL
, priv
,
505 &qca8k_regmap_config
);
506 if (IS_ERR(priv
->regmap
))
507 pr_warn("regmap initialization failed");
509 /* Initialize CPU port pad mode (xMII type, delays...) */
510 phy_mode
= of_get_phy_mode(ds
->ports
[QCA8K_CPU_PORT
].dn
);
512 pr_err("Can't find phy-mode for master device\n");
515 ret
= qca8k_set_pad_ctrl(priv
, QCA8K_CPU_PORT
, phy_mode
);
519 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
520 mask
= QCA8K_PORT_STATUS_SPEED_1000
| QCA8K_PORT_STATUS_TXFLOW
|
521 QCA8K_PORT_STATUS_RXFLOW
| QCA8K_PORT_STATUS_DUPLEX
;
522 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT
), mask
);
523 qca8k_reg_set(priv
, QCA8K_REG_GLOBAL_FW_CTRL0
,
524 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN
);
525 qca8k_port_set_status(priv
, QCA8K_CPU_PORT
, 1);
526 priv
->port_sts
[QCA8K_CPU_PORT
].enabled
= 1;
528 /* Enable MIB counters */
529 qca8k_mib_init(priv
);
531 /* Enable QCA header mode on the cpu port */
532 qca8k_write(priv
, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT
),
533 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_TX_S
|
534 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_RX_S
);
536 /* Disable forwarding by default on all ports */
537 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
538 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
539 QCA8K_PORT_LOOKUP_MEMBER
, 0);
541 /* Disable MAC by default on all user ports */
542 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++)
543 if (dsa_is_user_port(ds
, i
))
544 qca8k_port_set_status(priv
, i
, 0);
546 /* Forward all unknown frames to CPU port for Linux processing */
547 qca8k_write(priv
, QCA8K_REG_GLOBAL_FW_CTRL1
,
548 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S
|
549 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S
|
550 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S
|
551 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S
);
553 /* Setup connection between CPU port & user ports */
554 for (i
= 0; i
< DSA_MAX_PORTS
; i
++) {
555 /* CPU port gets connected to all user ports of the switch */
556 if (dsa_is_cpu_port(ds
, i
)) {
557 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
558 QCA8K_PORT_LOOKUP_MEMBER
, dsa_user_ports(ds
));
561 /* Invividual user ports get connected to CPU port only */
562 if (dsa_is_user_port(ds
, i
)) {
563 int shift
= 16 * (i
% 2);
565 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
566 QCA8K_PORT_LOOKUP_MEMBER
,
567 BIT(QCA8K_CPU_PORT
));
569 /* Enable ARP Auto-learning by default */
570 qca8k_reg_set(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
571 QCA8K_PORT_LOOKUP_LEARN
);
573 /* For port based vlans to work we need to set the
576 qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(i
),
577 0xffff << shift
, 1 << shift
);
578 qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(i
),
579 QCA8K_PORT_VLAN_CVID(1) |
580 QCA8K_PORT_VLAN_SVID(1));
584 /* Flush the FDB table */
585 qca8k_fdb_flush(priv
);
591 qca8k_phy_read(struct dsa_switch
*ds
, int phy
, int regnum
)
593 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
595 return mdiobus_read(priv
->bus
, phy
, regnum
);
599 qca8k_phy_write(struct dsa_switch
*ds
, int phy
, int regnum
, u16 val
)
601 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
603 return mdiobus_write(priv
->bus
, phy
, regnum
, val
);
607 qca8k_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
611 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++)
612 strncpy(data
+ i
* ETH_GSTRING_LEN
, ar8327_mib
[i
].name
,
617 qca8k_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
620 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
621 const struct qca8k_mib_desc
*mib
;
625 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++) {
626 mib
= &ar8327_mib
[i
];
627 reg
= QCA8K_PORT_MIB_COUNTER(port
) + mib
->offset
;
629 data
[i
] = qca8k_read(priv
, reg
);
630 if (mib
->size
== 2) {
631 hi
= qca8k_read(priv
, reg
+ 4);
638 qca8k_get_sset_count(struct dsa_switch
*ds
)
640 return ARRAY_SIZE(ar8327_mib
);
644 qca8k_set_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*eee
)
646 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
647 u32 lpi_en
= QCA8K_REG_EEE_CTRL_LPI_EN(port
);
650 mutex_lock(&priv
->reg_mutex
);
651 reg
= qca8k_read(priv
, QCA8K_REG_EEE_CTRL
);
652 if (eee
->eee_enabled
)
656 qca8k_write(priv
, QCA8K_REG_EEE_CTRL
, reg
);
657 mutex_unlock(&priv
->reg_mutex
);
663 qca8k_get_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
665 /* Nothing to do on the port's MAC */
670 qca8k_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
672 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
676 case BR_STATE_DISABLED
:
677 stp_state
= QCA8K_PORT_LOOKUP_STATE_DISABLED
;
679 case BR_STATE_BLOCKING
:
680 stp_state
= QCA8K_PORT_LOOKUP_STATE_BLOCKING
;
682 case BR_STATE_LISTENING
:
683 stp_state
= QCA8K_PORT_LOOKUP_STATE_LISTENING
;
685 case BR_STATE_LEARNING
:
686 stp_state
= QCA8K_PORT_LOOKUP_STATE_LEARNING
;
688 case BR_STATE_FORWARDING
:
690 stp_state
= QCA8K_PORT_LOOKUP_STATE_FORWARD
;
694 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
695 QCA8K_PORT_LOOKUP_STATE_MASK
, stp_state
);
699 qca8k_port_bridge_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
701 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
702 int port_mask
= BIT(QCA8K_CPU_PORT
);
705 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++) {
706 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
708 /* Add this port to the portvlan mask of the other ports
712 QCA8K_PORT_LOOKUP_CTRL(i
),
717 /* Add all other ports to this ports portvlan mask */
718 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
719 QCA8K_PORT_LOOKUP_MEMBER
, port_mask
);
725 qca8k_port_bridge_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
727 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
730 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++) {
731 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
733 /* Remove this port to the portvlan mask of the other ports
736 qca8k_reg_clear(priv
,
737 QCA8K_PORT_LOOKUP_CTRL(i
),
741 /* Set the cpu port to be the only one in the portvlan mask of
744 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
745 QCA8K_PORT_LOOKUP_MEMBER
, BIT(QCA8K_CPU_PORT
));
749 qca8k_port_enable(struct dsa_switch
*ds
, int port
,
750 struct phy_device
*phy
)
752 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
754 qca8k_port_set_status(priv
, port
, 1);
755 priv
->port_sts
[port
].enabled
= 1;
761 qca8k_port_disable(struct dsa_switch
*ds
, int port
,
762 struct phy_device
*phy
)
764 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
766 qca8k_port_set_status(priv
, port
, 0);
767 priv
->port_sts
[port
].enabled
= 0;
771 qca8k_port_fdb_insert(struct qca8k_priv
*priv
, const u8
*addr
,
772 u16 port_mask
, u16 vid
)
774 /* Set the vid to the port vlan id if no vid is set */
778 return qca8k_fdb_add(priv
, addr
, port_mask
, vid
,
779 QCA8K_ATU_STATUS_STATIC
);
783 qca8k_port_fdb_add(struct dsa_switch
*ds
, int port
,
784 const unsigned char *addr
, u16 vid
)
786 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
787 u16 port_mask
= BIT(port
);
789 return qca8k_port_fdb_insert(priv
, addr
, port_mask
, vid
);
793 qca8k_port_fdb_del(struct dsa_switch
*ds
, int port
,
794 const unsigned char *addr
, u16 vid
)
796 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
797 u16 port_mask
= BIT(port
);
802 return qca8k_fdb_del(priv
, addr
, port_mask
, vid
);
806 qca8k_port_fdb_dump(struct dsa_switch
*ds
, int port
,
807 dsa_fdb_dump_cb_t
*cb
, void *data
)
809 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
810 struct qca8k_fdb _fdb
= { 0 };
811 int cnt
= QCA8K_NUM_FDB_RECORDS
;
815 mutex_lock(&priv
->reg_mutex
);
816 while (cnt
-- && !qca8k_fdb_next(priv
, &_fdb
, port
)) {
819 is_static
= (_fdb
.aging
== QCA8K_ATU_STATUS_STATIC
);
820 ret
= cb(_fdb
.mac
, _fdb
.vid
, is_static
, data
);
824 mutex_unlock(&priv
->reg_mutex
);
829 static enum dsa_tag_protocol
830 qca8k_get_tag_protocol(struct dsa_switch
*ds
, int port
)
832 return DSA_TAG_PROTO_QCA
;
835 static const struct dsa_switch_ops qca8k_switch_ops
= {
836 .get_tag_protocol
= qca8k_get_tag_protocol
,
837 .setup
= qca8k_setup
,
838 .get_strings
= qca8k_get_strings
,
839 .phy_read
= qca8k_phy_read
,
840 .phy_write
= qca8k_phy_write
,
841 .get_ethtool_stats
= qca8k_get_ethtool_stats
,
842 .get_sset_count
= qca8k_get_sset_count
,
843 .get_mac_eee
= qca8k_get_mac_eee
,
844 .set_mac_eee
= qca8k_set_mac_eee
,
845 .port_enable
= qca8k_port_enable
,
846 .port_disable
= qca8k_port_disable
,
847 .port_stp_state_set
= qca8k_port_stp_state_set
,
848 .port_bridge_join
= qca8k_port_bridge_join
,
849 .port_bridge_leave
= qca8k_port_bridge_leave
,
850 .port_fdb_add
= qca8k_port_fdb_add
,
851 .port_fdb_del
= qca8k_port_fdb_del
,
852 .port_fdb_dump
= qca8k_port_fdb_dump
,
856 qca8k_sw_probe(struct mdio_device
*mdiodev
)
858 struct qca8k_priv
*priv
;
861 /* allocate the private data struct so that we can probe the switches
864 priv
= devm_kzalloc(&mdiodev
->dev
, sizeof(*priv
), GFP_KERNEL
);
868 priv
->bus
= mdiodev
->bus
;
870 /* read the switches ID register */
871 id
= qca8k_read(priv
, QCA8K_REG_MASK_CTRL
);
872 id
>>= QCA8K_MASK_CTRL_ID_S
;
873 id
&= QCA8K_MASK_CTRL_ID_M
;
874 if (id
!= QCA8K_ID_QCA8337
)
877 priv
->ds
= dsa_switch_alloc(&mdiodev
->dev
, DSA_MAX_PORTS
);
881 priv
->ds
->priv
= priv
;
882 priv
->ds
->ops
= &qca8k_switch_ops
;
883 mutex_init(&priv
->reg_mutex
);
884 dev_set_drvdata(&mdiodev
->dev
, priv
);
886 return dsa_register_switch(priv
->ds
);
890 qca8k_sw_remove(struct mdio_device
*mdiodev
)
892 struct qca8k_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
895 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
896 qca8k_port_set_status(priv
, i
, 0);
898 dsa_unregister_switch(priv
->ds
);
901 #ifdef CONFIG_PM_SLEEP
903 qca8k_set_pm(struct qca8k_priv
*priv
, int enable
)
907 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
908 if (!priv
->port_sts
[i
].enabled
)
911 qca8k_port_set_status(priv
, i
, enable
);
915 static int qca8k_suspend(struct device
*dev
)
917 struct platform_device
*pdev
= to_platform_device(dev
);
918 struct qca8k_priv
*priv
= platform_get_drvdata(pdev
);
920 qca8k_set_pm(priv
, 0);
922 return dsa_switch_suspend(priv
->ds
);
925 static int qca8k_resume(struct device
*dev
)
927 struct platform_device
*pdev
= to_platform_device(dev
);
928 struct qca8k_priv
*priv
= platform_get_drvdata(pdev
);
930 qca8k_set_pm(priv
, 1);
932 return dsa_switch_resume(priv
->ds
);
934 #endif /* CONFIG_PM_SLEEP */
936 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops
,
937 qca8k_suspend
, qca8k_resume
);
939 static const struct of_device_id qca8k_of_match
[] = {
940 { .compatible
= "qca,qca8334" },
941 { .compatible
= "qca,qca8337" },
945 static struct mdio_driver qca8kmdio_driver
= {
946 .probe
= qca8k_sw_probe
,
947 .remove
= qca8k_sw_remove
,
950 .of_match_table
= qca8k_of_match
,
955 mdio_module_driver(qca8kmdio_driver
);
957 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
958 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
959 MODULE_LICENSE("GPL v2");
960 MODULE_ALIAS("platform:qca8k");