1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
13 #include <linux/of_net.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_platform.h>
16 #include <linux/if_bridge.h>
17 #include <linux/mdio.h>
18 #include <linux/phylink.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/etherdevice.h>
24 #define MIB_DESC(_s, _o, _n) \
31 static const struct qca8k_mib_desc ar8327_mib
[] = {
32 MIB_DESC(1, 0x00, "RxBroad"),
33 MIB_DESC(1, 0x04, "RxPause"),
34 MIB_DESC(1, 0x08, "RxMulti"),
35 MIB_DESC(1, 0x0c, "RxFcsErr"),
36 MIB_DESC(1, 0x10, "RxAlignErr"),
37 MIB_DESC(1, 0x14, "RxRunt"),
38 MIB_DESC(1, 0x18, "RxFragment"),
39 MIB_DESC(1, 0x1c, "Rx64Byte"),
40 MIB_DESC(1, 0x20, "Rx128Byte"),
41 MIB_DESC(1, 0x24, "Rx256Byte"),
42 MIB_DESC(1, 0x28, "Rx512Byte"),
43 MIB_DESC(1, 0x2c, "Rx1024Byte"),
44 MIB_DESC(1, 0x30, "Rx1518Byte"),
45 MIB_DESC(1, 0x34, "RxMaxByte"),
46 MIB_DESC(1, 0x38, "RxTooLong"),
47 MIB_DESC(2, 0x3c, "RxGoodByte"),
48 MIB_DESC(2, 0x44, "RxBadByte"),
49 MIB_DESC(1, 0x4c, "RxOverFlow"),
50 MIB_DESC(1, 0x50, "Filtered"),
51 MIB_DESC(1, 0x54, "TxBroad"),
52 MIB_DESC(1, 0x58, "TxPause"),
53 MIB_DESC(1, 0x5c, "TxMulti"),
54 MIB_DESC(1, 0x60, "TxUnderRun"),
55 MIB_DESC(1, 0x64, "Tx64Byte"),
56 MIB_DESC(1, 0x68, "Tx128Byte"),
57 MIB_DESC(1, 0x6c, "Tx256Byte"),
58 MIB_DESC(1, 0x70, "Tx512Byte"),
59 MIB_DESC(1, 0x74, "Tx1024Byte"),
60 MIB_DESC(1, 0x78, "Tx1518Byte"),
61 MIB_DESC(1, 0x7c, "TxMaxByte"),
62 MIB_DESC(1, 0x80, "TxOverSize"),
63 MIB_DESC(2, 0x84, "TxByte"),
64 MIB_DESC(1, 0x8c, "TxCollision"),
65 MIB_DESC(1, 0x90, "TxAbortCol"),
66 MIB_DESC(1, 0x94, "TxMultiCol"),
67 MIB_DESC(1, 0x98, "TxSingleCol"),
68 MIB_DESC(1, 0x9c, "TxExcDefer"),
69 MIB_DESC(1, 0xa0, "TxDefer"),
70 MIB_DESC(1, 0xa4, "TxLateCol"),
73 /* The 32bit switch registers are accessed indirectly. To achieve this we need
74 * to set the page of the register. Track the last page that was set to reduce
77 static u16 qca8k_current_page
= 0xffff;
80 qca8k_split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
89 *page
= regaddr
& 0x3ff;
93 qca8k_mii_read32(struct mii_bus
*bus
, int phy_id
, u32 regnum
, u32
*val
)
97 ret
= bus
->read(bus
, phy_id
, regnum
);
100 ret
= bus
->read(bus
, phy_id
, regnum
+ 1);
105 dev_err_ratelimited(&bus
->dev
,
106 "failed to read qca8k 32bit register\n");
115 qca8k_mii_write32(struct mii_bus
*bus
, int phy_id
, u32 regnum
, u32 val
)
121 hi
= (u16
)(val
>> 16);
123 ret
= bus
->write(bus
, phy_id
, regnum
, lo
);
125 ret
= bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
127 dev_err_ratelimited(&bus
->dev
,
128 "failed to write qca8k 32bit register\n");
132 qca8k_set_page(struct mii_bus
*bus
, u16 page
)
136 if (page
== qca8k_current_page
)
139 ret
= bus
->write(bus
, 0x18, 0, page
);
141 dev_err_ratelimited(&bus
->dev
,
142 "failed to set qca8k page\n");
146 qca8k_current_page
= page
;
147 usleep_range(1000, 2000);
152 qca8k_read(struct qca8k_priv
*priv
, u32 reg
, u32
*val
)
154 struct mii_bus
*bus
= priv
->bus
;
158 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
160 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
162 ret
= qca8k_set_page(bus
, page
);
166 ret
= qca8k_mii_read32(bus
, 0x10 | r2
, r1
, val
);
169 mutex_unlock(&bus
->mdio_lock
);
174 qca8k_write(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
176 struct mii_bus
*bus
= priv
->bus
;
180 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
182 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
184 ret
= qca8k_set_page(bus
, page
);
188 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, val
);
191 mutex_unlock(&bus
->mdio_lock
);
196 qca8k_rmw(struct qca8k_priv
*priv
, u32 reg
, u32 mask
, u32 write_val
)
198 struct mii_bus
*bus
= priv
->bus
;
203 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
205 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
207 ret
= qca8k_set_page(bus
, page
);
211 ret
= qca8k_mii_read32(bus
, 0x10 | r2
, r1
, &val
);
217 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, val
);
220 mutex_unlock(&bus
->mdio_lock
);
226 qca8k_reg_set(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
228 return qca8k_rmw(priv
, reg
, 0, val
);
232 qca8k_reg_clear(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
234 return qca8k_rmw(priv
, reg
, val
, 0);
238 qca8k_regmap_read(void *ctx
, uint32_t reg
, uint32_t *val
)
240 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ctx
;
242 return qca8k_read(priv
, reg
, val
);
246 qca8k_regmap_write(void *ctx
, uint32_t reg
, uint32_t val
)
248 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ctx
;
250 return qca8k_write(priv
, reg
, val
);
253 static const struct regmap_range qca8k_readable_ranges
[] = {
254 regmap_reg_range(0x0000, 0x00e4), /* Global control */
255 regmap_reg_range(0x0100, 0x0168), /* EEE control */
256 regmap_reg_range(0x0200, 0x0270), /* Parser control */
257 regmap_reg_range(0x0400, 0x0454), /* ACL */
258 regmap_reg_range(0x0600, 0x0718), /* Lookup */
259 regmap_reg_range(0x0800, 0x0b70), /* QM */
260 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
261 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
262 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
263 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
264 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
265 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
266 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
267 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
268 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
272 static const struct regmap_access_table qca8k_readable_table
= {
273 .yes_ranges
= qca8k_readable_ranges
,
274 .n_yes_ranges
= ARRAY_SIZE(qca8k_readable_ranges
),
277 static struct regmap_config qca8k_regmap_config
= {
281 .max_register
= 0x16ac, /* end MIB - Port6 range */
282 .reg_read
= qca8k_regmap_read
,
283 .reg_write
= qca8k_regmap_write
,
284 .rd_table
= &qca8k_readable_table
,
288 qca8k_busy_wait(struct qca8k_priv
*priv
, u32 reg
, u32 mask
)
293 ret
= read_poll_timeout(qca8k_read
, ret1
, !(val
& mask
),
294 0, QCA8K_BUSY_WAIT_TIMEOUT
* USEC_PER_MSEC
, false,
297 /* Check if qca8k_read has failed for a different reason
298 * before returning -ETIMEDOUT
300 if (ret
< 0 && ret1
< 0)
307 qca8k_fdb_read(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
)
312 /* load the ARL table into an array */
313 for (i
= 0; i
< 4; i
++) {
314 ret
= qca8k_read(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), &val
);
322 fdb
->vid
= (reg
[2] >> QCA8K_ATU_VID_S
) & QCA8K_ATU_VID_M
;
324 fdb
->aging
= reg
[2] & QCA8K_ATU_STATUS_M
;
325 /* portmask - 54:48 */
326 fdb
->port_mask
= (reg
[1] >> QCA8K_ATU_PORT_S
) & QCA8K_ATU_PORT_M
;
328 fdb
->mac
[0] = (reg
[1] >> QCA8K_ATU_ADDR0_S
) & 0xff;
329 fdb
->mac
[1] = reg
[1] & 0xff;
330 fdb
->mac
[2] = (reg
[0] >> QCA8K_ATU_ADDR2_S
) & 0xff;
331 fdb
->mac
[3] = (reg
[0] >> QCA8K_ATU_ADDR3_S
) & 0xff;
332 fdb
->mac
[4] = (reg
[0] >> QCA8K_ATU_ADDR4_S
) & 0xff;
333 fdb
->mac
[5] = reg
[0] & 0xff;
339 qca8k_fdb_write(struct qca8k_priv
*priv
, u16 vid
, u8 port_mask
, const u8
*mac
,
346 reg
[2] = (vid
& QCA8K_ATU_VID_M
) << QCA8K_ATU_VID_S
;
348 reg
[2] |= aging
& QCA8K_ATU_STATUS_M
;
349 /* portmask - 54:48 */
350 reg
[1] = (port_mask
& QCA8K_ATU_PORT_M
) << QCA8K_ATU_PORT_S
;
352 reg
[1] |= mac
[0] << QCA8K_ATU_ADDR0_S
;
354 reg
[0] |= mac
[2] << QCA8K_ATU_ADDR2_S
;
355 reg
[0] |= mac
[3] << QCA8K_ATU_ADDR3_S
;
356 reg
[0] |= mac
[4] << QCA8K_ATU_ADDR4_S
;
359 /* load the array into the ARL table */
360 for (i
= 0; i
< 3; i
++)
361 qca8k_write(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), reg
[i
]);
365 qca8k_fdb_access(struct qca8k_priv
*priv
, enum qca8k_fdb_cmd cmd
, int port
)
370 /* Set the command and FDB index */
371 reg
= QCA8K_ATU_FUNC_BUSY
;
374 reg
|= QCA8K_ATU_FUNC_PORT_EN
;
375 reg
|= (port
& QCA8K_ATU_FUNC_PORT_M
) << QCA8K_ATU_FUNC_PORT_S
;
378 /* Write the function register triggering the table access */
379 ret
= qca8k_write(priv
, QCA8K_REG_ATU_FUNC
, reg
);
383 /* wait for completion */
384 ret
= qca8k_busy_wait(priv
, QCA8K_REG_ATU_FUNC
, QCA8K_ATU_FUNC_BUSY
);
388 /* Check for table full violation when adding an entry */
389 if (cmd
== QCA8K_FDB_LOAD
) {
390 ret
= qca8k_read(priv
, QCA8K_REG_ATU_FUNC
, ®
);
393 if (reg
& QCA8K_ATU_FUNC_FULL
)
401 qca8k_fdb_next(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
, int port
)
405 qca8k_fdb_write(priv
, fdb
->vid
, fdb
->port_mask
, fdb
->mac
, fdb
->aging
);
406 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_NEXT
, port
);
410 return qca8k_fdb_read(priv
, fdb
);
414 qca8k_fdb_add(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
,
419 mutex_lock(&priv
->reg_mutex
);
420 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, aging
);
421 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_LOAD
, -1);
422 mutex_unlock(&priv
->reg_mutex
);
428 qca8k_fdb_del(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
, u16 vid
)
432 mutex_lock(&priv
->reg_mutex
);
433 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, 0);
434 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_PURGE
, -1);
435 mutex_unlock(&priv
->reg_mutex
);
441 qca8k_fdb_flush(struct qca8k_priv
*priv
)
443 mutex_lock(&priv
->reg_mutex
);
444 qca8k_fdb_access(priv
, QCA8K_FDB_FLUSH
, -1);
445 mutex_unlock(&priv
->reg_mutex
);
449 qca8k_vlan_access(struct qca8k_priv
*priv
, enum qca8k_vlan_cmd cmd
, u16 vid
)
454 /* Set the command and VLAN index */
455 reg
= QCA8K_VTU_FUNC1_BUSY
;
457 reg
|= vid
<< QCA8K_VTU_FUNC1_VID_S
;
459 /* Write the function register triggering the table access */
460 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC1
, reg
);
464 /* wait for completion */
465 ret
= qca8k_busy_wait(priv
, QCA8K_REG_VTU_FUNC1
, QCA8K_VTU_FUNC1_BUSY
);
469 /* Check for table full violation when adding an entry */
470 if (cmd
== QCA8K_VLAN_LOAD
) {
471 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC1
, ®
);
474 if (reg
& QCA8K_VTU_FUNC1_FULL
)
482 qca8k_vlan_add(struct qca8k_priv
*priv
, u8 port
, u16 vid
, bool untagged
)
488 We do the right thing with VLAN 0 and treat it as untagged while
489 preserving the tag on egress.
494 mutex_lock(&priv
->reg_mutex
);
495 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
499 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
502 reg
|= QCA8K_VTU_FUNC0_VALID
| QCA8K_VTU_FUNC0_IVL_EN
;
503 reg
&= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK
<< QCA8K_VTU_FUNC0_EG_MODE_S(port
));
505 reg
|= QCA8K_VTU_FUNC0_EG_MODE_UNTAG
<<
506 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
508 reg
|= QCA8K_VTU_FUNC0_EG_MODE_TAG
<<
509 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
511 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
514 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
517 mutex_unlock(&priv
->reg_mutex
);
523 qca8k_vlan_del(struct qca8k_priv
*priv
, u8 port
, u16 vid
)
529 mutex_lock(&priv
->reg_mutex
);
530 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
534 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
537 reg
&= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port
));
538 reg
|= QCA8K_VTU_FUNC0_EG_MODE_NOT
<<
539 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
541 /* Check if we're the last member to be removed */
543 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
544 mask
= QCA8K_VTU_FUNC0_EG_MODE_NOT
;
545 mask
<<= QCA8K_VTU_FUNC0_EG_MODE_S(i
);
547 if ((reg
& mask
) != mask
) {
554 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_PURGE
, vid
);
556 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
559 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
563 mutex_unlock(&priv
->reg_mutex
);
569 qca8k_mib_init(struct qca8k_priv
*priv
)
573 mutex_lock(&priv
->reg_mutex
);
574 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_FLUSH
| QCA8K_MIB_BUSY
);
578 ret
= qca8k_busy_wait(priv
, QCA8K_REG_MIB
, QCA8K_MIB_BUSY
);
582 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_CPU_KEEP
);
586 ret
= qca8k_write(priv
, QCA8K_REG_MODULE_EN
, QCA8K_MODULE_EN_MIB
);
589 mutex_unlock(&priv
->reg_mutex
);
594 qca8k_port_set_status(struct qca8k_priv
*priv
, int port
, int enable
)
596 u32 mask
= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
598 /* Port 0 and 6 have no internal PHY */
599 if (port
> 0 && port
< 6)
600 mask
|= QCA8K_PORT_STATUS_LINK_AUTO
;
603 qca8k_reg_set(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
605 qca8k_reg_clear(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
609 qca8k_port_to_phy(int port
)
612 * Port 0 has no internal phy.
613 * Port 1 has an internal PHY at MDIO address 0.
614 * Port 2 has an internal PHY at MDIO address 1.
616 * Port 5 has an internal PHY at MDIO address 4.
617 * Port 6 has no internal PHY.
624 qca8k_mdio_busy_wait(struct mii_bus
*bus
, u32 reg
, u32 mask
)
630 qca8k_split_addr(reg
, &r1
, &r2
, &page
);
632 ret
= read_poll_timeout(qca8k_mii_read32
, ret1
, !(val
& mask
), 0,
633 QCA8K_BUSY_WAIT_TIMEOUT
* USEC_PER_MSEC
, false,
634 bus
, 0x10 | r2
, r1
, &val
);
636 /* Check if qca8k_read has failed for a different reason
637 * before returnting -ETIMEDOUT
639 if (ret
< 0 && ret1
< 0)
646 qca8k_mdio_write(struct mii_bus
*bus
, int phy
, int regnum
, u16 data
)
652 if (regnum
>= QCA8K_MDIO_MASTER_MAX_REG
)
655 val
= QCA8K_MDIO_MASTER_BUSY
| QCA8K_MDIO_MASTER_EN
|
656 QCA8K_MDIO_MASTER_WRITE
| QCA8K_MDIO_MASTER_PHY_ADDR(phy
) |
657 QCA8K_MDIO_MASTER_REG_ADDR(regnum
) |
658 QCA8K_MDIO_MASTER_DATA(data
);
660 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL
, &r1
, &r2
, &page
);
662 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
664 ret
= qca8k_set_page(bus
, page
);
668 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, val
);
670 ret
= qca8k_mdio_busy_wait(bus
, QCA8K_MDIO_MASTER_CTRL
,
671 QCA8K_MDIO_MASTER_BUSY
);
674 /* even if the busy_wait timeouts try to clear the MASTER_EN */
675 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, 0);
677 mutex_unlock(&bus
->mdio_lock
);
683 qca8k_mdio_read(struct mii_bus
*bus
, int phy
, int regnum
)
689 if (regnum
>= QCA8K_MDIO_MASTER_MAX_REG
)
692 val
= QCA8K_MDIO_MASTER_BUSY
| QCA8K_MDIO_MASTER_EN
|
693 QCA8K_MDIO_MASTER_READ
| QCA8K_MDIO_MASTER_PHY_ADDR(phy
) |
694 QCA8K_MDIO_MASTER_REG_ADDR(regnum
);
696 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL
, &r1
, &r2
, &page
);
698 mutex_lock_nested(&bus
->mdio_lock
, MDIO_MUTEX_NESTED
);
700 ret
= qca8k_set_page(bus
, page
);
704 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, val
);
706 ret
= qca8k_mdio_busy_wait(bus
, QCA8K_MDIO_MASTER_CTRL
,
707 QCA8K_MDIO_MASTER_BUSY
);
711 ret
= qca8k_mii_read32(bus
, 0x10 | r2
, r1
, &val
);
714 /* even if the busy_wait timeouts try to clear the MASTER_EN */
715 qca8k_mii_write32(bus
, 0x10 | r2
, r1
, 0);
717 mutex_unlock(&bus
->mdio_lock
);
720 ret
= val
& QCA8K_MDIO_MASTER_DATA_MASK
;
726 qca8k_internal_mdio_write(struct mii_bus
*slave_bus
, int phy
, int regnum
, u16 data
)
728 struct qca8k_priv
*priv
= slave_bus
->priv
;
729 struct mii_bus
*bus
= priv
->bus
;
731 return qca8k_mdio_write(bus
, phy
, regnum
, data
);
735 qca8k_internal_mdio_read(struct mii_bus
*slave_bus
, int phy
, int regnum
)
737 struct qca8k_priv
*priv
= slave_bus
->priv
;
738 struct mii_bus
*bus
= priv
->bus
;
740 return qca8k_mdio_read(bus
, phy
, regnum
);
744 qca8k_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 data
)
746 struct qca8k_priv
*priv
= ds
->priv
;
748 /* Check if the legacy mapping should be used and the
749 * port is not correctly mapped to the right PHY in the
752 if (priv
->legacy_phy_port_mapping
)
753 port
= qca8k_port_to_phy(port
) % PHY_MAX_ADDR
;
755 return qca8k_mdio_write(priv
->bus
, port
, regnum
, data
);
759 qca8k_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
761 struct qca8k_priv
*priv
= ds
->priv
;
764 /* Check if the legacy mapping should be used and the
765 * port is not correctly mapped to the right PHY in the
768 if (priv
->legacy_phy_port_mapping
)
769 port
= qca8k_port_to_phy(port
) % PHY_MAX_ADDR
;
771 ret
= qca8k_mdio_read(priv
->bus
, port
, regnum
);
780 qca8k_mdio_register(struct qca8k_priv
*priv
, struct device_node
*mdio
)
782 struct dsa_switch
*ds
= priv
->ds
;
785 bus
= devm_mdiobus_alloc(ds
->dev
);
790 bus
->priv
= (void *)priv
;
791 bus
->name
= "qca8k slave mii";
792 bus
->read
= qca8k_internal_mdio_read
;
793 bus
->write
= qca8k_internal_mdio_write
;
794 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "qca8k-%d",
797 bus
->parent
= ds
->dev
;
798 bus
->phy_mask
= ~ds
->phys_mii_mask
;
800 ds
->slave_mii_bus
= bus
;
802 return devm_of_mdiobus_register(priv
->dev
, bus
, mdio
);
806 qca8k_setup_mdio_bus(struct qca8k_priv
*priv
)
808 u32 internal_mdio_mask
= 0, external_mdio_mask
= 0, reg
;
809 struct device_node
*ports
, *port
, *mdio
;
810 phy_interface_t mode
;
813 ports
= of_get_child_by_name(priv
->dev
->of_node
, "ports");
815 ports
= of_get_child_by_name(priv
->dev
->of_node
, "ethernet-ports");
820 for_each_available_child_of_node(ports
, port
) {
821 err
= of_property_read_u32(port
, "reg", ®
);
828 if (!dsa_is_user_port(priv
->ds
, reg
))
831 of_get_phy_mode(port
, &mode
);
833 if (of_property_read_bool(port
, "phy-handle") &&
834 mode
!= PHY_INTERFACE_MODE_INTERNAL
)
835 external_mdio_mask
|= BIT(reg
);
837 internal_mdio_mask
|= BIT(reg
);
841 if (!external_mdio_mask
&& !internal_mdio_mask
) {
842 dev_err(priv
->dev
, "no PHYs are defined.\n");
846 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
847 * the MDIO_MASTER register also _disconnects_ the external MDC
848 * passthrough to the internal PHYs. It's not possible to use both
849 * configurations at the same time!
851 * Because this came up during the review process:
852 * If the external mdio-bus driver is capable magically disabling
853 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
854 * accessors for the time being, it would be possible to pull this
857 if (!!external_mdio_mask
&& !!internal_mdio_mask
) {
858 dev_err(priv
->dev
, "either internal or external mdio bus configuration is supported.\n");
862 if (external_mdio_mask
) {
863 /* Make sure to disable the internal mdio bus in cases
864 * a dt-overlay and driver reload changed the configuration
867 return qca8k_reg_clear(priv
, QCA8K_MDIO_MASTER_CTRL
,
868 QCA8K_MDIO_MASTER_EN
);
871 /* Check if the devicetree declare the port:phy mapping */
872 mdio
= of_get_child_by_name(priv
->dev
->of_node
, "mdio");
873 if (of_device_is_available(mdio
)) {
874 err
= qca8k_mdio_register(priv
, mdio
);
881 /* If a mapping can't be found the legacy mapping is used,
882 * using the qca8k_port_to_phy function
884 priv
->legacy_phy_port_mapping
= true;
885 priv
->ops
.phy_read
= qca8k_phy_read
;
886 priv
->ops
.phy_write
= qca8k_phy_write
;
892 qca8k_setup_of_rgmii_delay(struct qca8k_priv
*priv
)
894 struct device_node
*port_dn
;
895 phy_interface_t mode
;
899 /* CPU port is already checked */
900 dp
= dsa_to_port(priv
->ds
, 0);
904 /* Check if port 0 is set to the correct type */
905 of_get_phy_mode(port_dn
, &mode
);
906 if (mode
!= PHY_INTERFACE_MODE_RGMII_ID
&&
907 mode
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
908 mode
!= PHY_INTERFACE_MODE_RGMII_TXID
) {
913 case PHY_INTERFACE_MODE_RGMII_ID
:
914 case PHY_INTERFACE_MODE_RGMII_RXID
:
915 if (of_property_read_u32(port_dn
, "rx-internal-delay-ps", &val
))
918 /* Switch regs accept value in ns, convert ps to ns */
921 if (val
> QCA8K_MAX_DELAY
) {
922 dev_err(priv
->dev
, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
926 priv
->rgmii_rx_delay
= val
;
927 /* Stop here if we need to check only for rx delay */
928 if (mode
!= PHY_INTERFACE_MODE_RGMII_ID
)
932 case PHY_INTERFACE_MODE_RGMII_TXID
:
933 if (of_property_read_u32(port_dn
, "tx-internal-delay-ps", &val
))
936 /* Switch regs accept value in ns, convert ps to ns */
939 if (val
> QCA8K_MAX_DELAY
) {
940 dev_err(priv
->dev
, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
944 priv
->rgmii_tx_delay
= val
;
954 qca8k_setup(struct dsa_switch
*ds
)
956 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
960 /* Make sure that port 0 is the cpu port */
961 if (!dsa_is_cpu_port(ds
, 0)) {
962 dev_err(priv
->dev
, "port 0 is not the CPU port");
966 mutex_init(&priv
->reg_mutex
);
968 /* Start by setting up the register mapping */
969 priv
->regmap
= devm_regmap_init(ds
->dev
, NULL
, priv
,
970 &qca8k_regmap_config
);
971 if (IS_ERR(priv
->regmap
))
972 dev_warn(priv
->dev
, "regmap initialization failed");
974 ret
= qca8k_setup_mdio_bus(priv
);
978 ret
= qca8k_setup_of_rgmii_delay(priv
);
982 /* Enable CPU Port */
983 ret
= qca8k_reg_set(priv
, QCA8K_REG_GLOBAL_FW_CTRL0
,
984 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN
);
986 dev_err(priv
->dev
, "failed enabling CPU port");
990 /* Enable MIB counters */
991 ret
= qca8k_mib_init(priv
);
993 dev_warn(priv
->dev
, "mib init failed");
995 /* Enable QCA header mode on the cpu port */
996 ret
= qca8k_write(priv
, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT
),
997 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_TX_S
|
998 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_RX_S
);
1000 dev_err(priv
->dev
, "failed enabling QCA header mode");
1004 /* Disable forwarding by default on all ports */
1005 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1006 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
1007 QCA8K_PORT_LOOKUP_MEMBER
, 0);
1012 /* Disable MAC by default on all ports */
1013 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++)
1014 qca8k_port_set_status(priv
, i
, 0);
1016 /* Forward all unknown frames to CPU port for Linux processing */
1017 ret
= qca8k_write(priv
, QCA8K_REG_GLOBAL_FW_CTRL1
,
1018 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S
|
1019 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S
|
1020 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S
|
1021 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S
);
1025 /* Setup connection between CPU port & user ports */
1026 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1027 /* CPU port gets connected to all user ports of the switch */
1028 if (dsa_is_cpu_port(ds
, i
)) {
1029 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
1030 QCA8K_PORT_LOOKUP_MEMBER
, dsa_user_ports(ds
));
1035 /* Individual user ports get connected to CPU port only */
1036 if (dsa_is_user_port(ds
, i
)) {
1037 int shift
= 16 * (i
% 2);
1039 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
1040 QCA8K_PORT_LOOKUP_MEMBER
,
1041 BIT(QCA8K_CPU_PORT
));
1045 /* Enable ARP Auto-learning by default */
1046 ret
= qca8k_reg_set(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
1047 QCA8K_PORT_LOOKUP_LEARN
);
1051 /* For port based vlans to work we need to set the
1052 * default egress vid
1054 ret
= qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(i
),
1056 QCA8K_PORT_VID_DEF
<< shift
);
1060 ret
= qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(i
),
1061 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF
) |
1062 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF
));
1068 /* The port 5 of the qca8337 have some problem in flood condition. The
1069 * original legacy driver had some specific buffer and priority settings
1070 * for the different port suggested by the QCA switch team. Add this
1071 * missing settings to improve switch stability under load condition.
1072 * This problem is limited to qca8337 and other qca8k switch are not affected.
1074 if (priv
->switch_id
== QCA8K_ID_QCA8337
) {
1075 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1077 /* The 2 CPU port and port 5 requires some different
1078 * priority than any other ports.
1083 mask
= QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1084 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1085 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1086 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1087 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1088 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1089 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1092 mask
= QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1093 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1094 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1095 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1096 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1098 qca8k_write(priv
, QCA8K_REG_PORT_HOL_CTRL0(i
), mask
);
1100 mask
= QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1101 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN
|
1102 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN
|
1103 QCA8K_PORT_HOL_CTRL1_WRED_EN
;
1104 qca8k_rmw(priv
, QCA8K_REG_PORT_HOL_CTRL1(i
),
1105 QCA8K_PORT_HOL_CTRL1_ING_BUF
|
1106 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN
|
1107 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN
|
1108 QCA8K_PORT_HOL_CTRL1_WRED_EN
,
1113 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1114 if (priv
->switch_id
== QCA8K_ID_QCA8327
) {
1115 mask
= QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1116 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1117 qca8k_rmw(priv
, QCA8K_REG_GLOBAL_FC_THRESH
,
1118 QCA8K_GLOBAL_FC_GOL_XON_THRES_S
|
1119 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S
,
1123 /* Setup our port MTUs to match power on defaults */
1124 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1125 priv
->port_mtu
[i
] = ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1126 ret
= qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, ETH_FRAME_LEN
+ ETH_FCS_LEN
);
1128 dev_warn(priv
->dev
, "failed setting MTU settings");
1130 /* Flush the FDB table */
1131 qca8k_fdb_flush(priv
);
1133 /* We don't have interrupts for link changes, so we need to poll */
1134 ds
->pcs_poll
= true;
1140 qca8k_phylink_mac_config(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1141 const struct phylink_link_state
*state
)
1143 struct qca8k_priv
*priv
= ds
->priv
;
1148 case 0: /* 1st CPU port */
1149 if (state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1150 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1151 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
&&
1152 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1153 state
->interface
!= PHY_INTERFACE_MODE_SGMII
)
1156 reg
= QCA8K_REG_PORT0_PAD_CTRL
;
1163 /* Internal PHY, nothing to do */
1165 case 6: /* 2nd CPU port / external PHY */
1166 if (state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1167 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1168 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
&&
1169 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1170 state
->interface
!= PHY_INTERFACE_MODE_SGMII
&&
1171 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
)
1174 reg
= QCA8K_REG_PORT6_PAD_CTRL
;
1177 dev_err(ds
->dev
, "%s: unsupported port: %i\n", __func__
, port
);
1181 if (port
!= 6 && phylink_autoneg_inband(mode
)) {
1182 dev_err(ds
->dev
, "%s: in-band negotiation unsupported\n",
1187 switch (state
->interface
) {
1188 case PHY_INTERFACE_MODE_RGMII
:
1189 /* RGMII mode means no delay so don't enable the delay */
1190 qca8k_write(priv
, reg
, QCA8K_PORT_PAD_RGMII_EN
);
1192 case PHY_INTERFACE_MODE_RGMII_ID
:
1193 case PHY_INTERFACE_MODE_RGMII_TXID
:
1194 case PHY_INTERFACE_MODE_RGMII_RXID
:
1195 /* RGMII_ID needs internal delay. This is enabled through
1196 * PORT5_PAD_CTRL for all ports, rather than individual port
1199 qca8k_write(priv
, reg
,
1200 QCA8K_PORT_PAD_RGMII_EN
|
1201 QCA8K_PORT_PAD_RGMII_TX_DELAY(priv
->rgmii_tx_delay
) |
1202 QCA8K_PORT_PAD_RGMII_RX_DELAY(priv
->rgmii_rx_delay
) |
1203 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN
|
1204 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN
);
1205 /* QCA8337 requires to set rgmii rx delay */
1206 if (priv
->switch_id
== QCA8K_ID_QCA8337
)
1207 qca8k_write(priv
, QCA8K_REG_PORT5_PAD_CTRL
,
1208 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN
);
1210 case PHY_INTERFACE_MODE_SGMII
:
1211 case PHY_INTERFACE_MODE_1000BASEX
:
1212 /* Enable SGMII on the port */
1213 qca8k_write(priv
, reg
, QCA8K_PORT_PAD_SGMII_EN
);
1215 /* Enable/disable SerDes auto-negotiation as necessary */
1216 ret
= qca8k_read(priv
, QCA8K_REG_PWS
, &val
);
1219 if (phylink_autoneg_inband(mode
))
1220 val
&= ~QCA8K_PWS_SERDES_AEN_DIS
;
1222 val
|= QCA8K_PWS_SERDES_AEN_DIS
;
1223 qca8k_write(priv
, QCA8K_REG_PWS
, val
);
1225 /* Configure the SGMII parameters */
1226 ret
= qca8k_read(priv
, QCA8K_REG_SGMII_CTRL
, &val
);
1230 val
|= QCA8K_SGMII_EN_PLL
| QCA8K_SGMII_EN_RX
|
1231 QCA8K_SGMII_EN_TX
| QCA8K_SGMII_EN_SD
;
1233 if (dsa_is_cpu_port(ds
, port
)) {
1234 /* CPU port, we're talking to the CPU MAC, be a PHY */
1235 val
&= ~QCA8K_SGMII_MODE_CTRL_MASK
;
1236 val
|= QCA8K_SGMII_MODE_CTRL_PHY
;
1237 } else if (state
->interface
== PHY_INTERFACE_MODE_SGMII
) {
1238 val
&= ~QCA8K_SGMII_MODE_CTRL_MASK
;
1239 val
|= QCA8K_SGMII_MODE_CTRL_MAC
;
1240 } else if (state
->interface
== PHY_INTERFACE_MODE_1000BASEX
) {
1241 val
&= ~QCA8K_SGMII_MODE_CTRL_MASK
;
1242 val
|= QCA8K_SGMII_MODE_CTRL_BASEX
;
1245 qca8k_write(priv
, QCA8K_REG_SGMII_CTRL
, val
);
1248 dev_err(ds
->dev
, "xMII mode %s not supported for port %d\n",
1249 phy_modes(state
->interface
), port
);
1255 qca8k_phylink_validate(struct dsa_switch
*ds
, int port
,
1256 unsigned long *supported
,
1257 struct phylink_link_state
*state
)
1259 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1262 case 0: /* 1st CPU port */
1263 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1264 state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1265 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1266 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
&&
1267 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1268 state
->interface
!= PHY_INTERFACE_MODE_SGMII
)
1277 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1278 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
1279 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1282 case 6: /* 2nd CPU port / external PHY */
1283 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1284 state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1285 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1286 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
&&
1287 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1288 state
->interface
!= PHY_INTERFACE_MODE_SGMII
&&
1289 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
)
1294 linkmode_zero(supported
);
1298 phylink_set_port_modes(mask
);
1299 phylink_set(mask
, Autoneg
);
1301 phylink_set(mask
, 1000baseT_Full
);
1302 phylink_set(mask
, 10baseT_Half
);
1303 phylink_set(mask
, 10baseT_Full
);
1304 phylink_set(mask
, 100baseT_Half
);
1305 phylink_set(mask
, 100baseT_Full
);
1307 if (state
->interface
== PHY_INTERFACE_MODE_1000BASEX
)
1308 phylink_set(mask
, 1000baseX_Full
);
1310 phylink_set(mask
, Pause
);
1311 phylink_set(mask
, Asym_Pause
);
1313 linkmode_and(supported
, supported
, mask
);
1314 linkmode_and(state
->advertising
, state
->advertising
, mask
);
1318 qca8k_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
1319 struct phylink_link_state
*state
)
1321 struct qca8k_priv
*priv
= ds
->priv
;
1325 ret
= qca8k_read(priv
, QCA8K_REG_PORT_STATUS(port
), ®
);
1329 state
->link
= !!(reg
& QCA8K_PORT_STATUS_LINK_UP
);
1330 state
->an_complete
= state
->link
;
1331 state
->an_enabled
= !!(reg
& QCA8K_PORT_STATUS_LINK_AUTO
);
1332 state
->duplex
= (reg
& QCA8K_PORT_STATUS_DUPLEX
) ? DUPLEX_FULL
:
1335 switch (reg
& QCA8K_PORT_STATUS_SPEED
) {
1336 case QCA8K_PORT_STATUS_SPEED_10
:
1337 state
->speed
= SPEED_10
;
1339 case QCA8K_PORT_STATUS_SPEED_100
:
1340 state
->speed
= SPEED_100
;
1342 case QCA8K_PORT_STATUS_SPEED_1000
:
1343 state
->speed
= SPEED_1000
;
1346 state
->speed
= SPEED_UNKNOWN
;
1350 state
->pause
= MLO_PAUSE_NONE
;
1351 if (reg
& QCA8K_PORT_STATUS_RXFLOW
)
1352 state
->pause
|= MLO_PAUSE_RX
;
1353 if (reg
& QCA8K_PORT_STATUS_TXFLOW
)
1354 state
->pause
|= MLO_PAUSE_TX
;
1360 qca8k_phylink_mac_link_down(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1361 phy_interface_t interface
)
1363 struct qca8k_priv
*priv
= ds
->priv
;
1365 qca8k_port_set_status(priv
, port
, 0);
1369 qca8k_phylink_mac_link_up(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1370 phy_interface_t interface
, struct phy_device
*phydev
,
1371 int speed
, int duplex
, bool tx_pause
, bool rx_pause
)
1373 struct qca8k_priv
*priv
= ds
->priv
;
1376 if (phylink_autoneg_inband(mode
)) {
1377 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1381 reg
= QCA8K_PORT_STATUS_SPEED_10
;
1384 reg
= QCA8K_PORT_STATUS_SPEED_100
;
1387 reg
= QCA8K_PORT_STATUS_SPEED_1000
;
1390 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1394 if (duplex
== DUPLEX_FULL
)
1395 reg
|= QCA8K_PORT_STATUS_DUPLEX
;
1397 if (rx_pause
|| dsa_is_cpu_port(ds
, port
))
1398 reg
|= QCA8K_PORT_STATUS_RXFLOW
;
1400 if (tx_pause
|| dsa_is_cpu_port(ds
, port
))
1401 reg
|= QCA8K_PORT_STATUS_TXFLOW
;
1404 reg
|= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
1406 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(port
), reg
);
1410 qca8k_get_strings(struct dsa_switch
*ds
, int port
, u32 stringset
, uint8_t *data
)
1414 if (stringset
!= ETH_SS_STATS
)
1417 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++)
1418 strncpy(data
+ i
* ETH_GSTRING_LEN
, ar8327_mib
[i
].name
,
1423 qca8k_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
1426 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1427 const struct qca8k_mib_desc
*mib
;
1432 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++) {
1433 mib
= &ar8327_mib
[i
];
1434 reg
= QCA8K_PORT_MIB_COUNTER(port
) + mib
->offset
;
1436 ret
= qca8k_read(priv
, reg
, &val
);
1440 if (mib
->size
== 2) {
1441 ret
= qca8k_read(priv
, reg
+ 4, &hi
);
1448 data
[i
] |= (u64
)hi
<< 32;
1453 qca8k_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
1455 if (sset
!= ETH_SS_STATS
)
1458 return ARRAY_SIZE(ar8327_mib
);
1462 qca8k_set_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*eee
)
1464 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1465 u32 lpi_en
= QCA8K_REG_EEE_CTRL_LPI_EN(port
);
1469 mutex_lock(&priv
->reg_mutex
);
1470 ret
= qca8k_read(priv
, QCA8K_REG_EEE_CTRL
, ®
);
1474 if (eee
->eee_enabled
)
1478 ret
= qca8k_write(priv
, QCA8K_REG_EEE_CTRL
, reg
);
1481 mutex_unlock(&priv
->reg_mutex
);
1486 qca8k_get_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1488 /* Nothing to do on the port's MAC */
1493 qca8k_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1495 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1499 case BR_STATE_DISABLED
:
1500 stp_state
= QCA8K_PORT_LOOKUP_STATE_DISABLED
;
1502 case BR_STATE_BLOCKING
:
1503 stp_state
= QCA8K_PORT_LOOKUP_STATE_BLOCKING
;
1505 case BR_STATE_LISTENING
:
1506 stp_state
= QCA8K_PORT_LOOKUP_STATE_LISTENING
;
1508 case BR_STATE_LEARNING
:
1509 stp_state
= QCA8K_PORT_LOOKUP_STATE_LEARNING
;
1511 case BR_STATE_FORWARDING
:
1513 stp_state
= QCA8K_PORT_LOOKUP_STATE_FORWARD
;
1517 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1518 QCA8K_PORT_LOOKUP_STATE_MASK
, stp_state
);
1522 qca8k_port_bridge_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1524 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1525 int port_mask
= BIT(QCA8K_CPU_PORT
);
1528 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++) {
1529 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1531 /* Add this port to the portvlan mask of the other ports
1534 ret
= qca8k_reg_set(priv
,
1535 QCA8K_PORT_LOOKUP_CTRL(i
),
1540 port_mask
|= BIT(i
);
1543 /* Add all other ports to this ports portvlan mask */
1544 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1545 QCA8K_PORT_LOOKUP_MEMBER
, port_mask
);
1551 qca8k_port_bridge_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1553 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1556 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++) {
1557 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1559 /* Remove this port to the portvlan mask of the other ports
1562 qca8k_reg_clear(priv
,
1563 QCA8K_PORT_LOOKUP_CTRL(i
),
1567 /* Set the cpu port to be the only one in the portvlan mask of
1570 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1571 QCA8K_PORT_LOOKUP_MEMBER
, BIT(QCA8K_CPU_PORT
));
1575 qca8k_port_enable(struct dsa_switch
*ds
, int port
,
1576 struct phy_device
*phy
)
1578 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1580 qca8k_port_set_status(priv
, port
, 1);
1581 priv
->port_sts
[port
].enabled
= 1;
1583 if (dsa_is_user_port(ds
, port
))
1584 phy_support_asym_pause(phy
);
1590 qca8k_port_disable(struct dsa_switch
*ds
, int port
)
1592 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1594 qca8k_port_set_status(priv
, port
, 0);
1595 priv
->port_sts
[port
].enabled
= 0;
1599 qca8k_port_change_mtu(struct dsa_switch
*ds
, int port
, int new_mtu
)
1601 struct qca8k_priv
*priv
= ds
->priv
;
1604 priv
->port_mtu
[port
] = new_mtu
;
1606 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1607 if (priv
->port_mtu
[i
] > mtu
)
1608 mtu
= priv
->port_mtu
[i
];
1610 /* Include L2 header / FCS length */
1611 return qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, mtu
+ ETH_HLEN
+ ETH_FCS_LEN
);
1615 qca8k_port_max_mtu(struct dsa_switch
*ds
, int port
)
1617 return QCA8K_MAX_MTU
;
1621 qca8k_port_fdb_insert(struct qca8k_priv
*priv
, const u8
*addr
,
1622 u16 port_mask
, u16 vid
)
1624 /* Set the vid to the port vlan id if no vid is set */
1626 vid
= QCA8K_PORT_VID_DEF
;
1628 return qca8k_fdb_add(priv
, addr
, port_mask
, vid
,
1629 QCA8K_ATU_STATUS_STATIC
);
1633 qca8k_port_fdb_add(struct dsa_switch
*ds
, int port
,
1634 const unsigned char *addr
, u16 vid
)
1636 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1637 u16 port_mask
= BIT(port
);
1639 return qca8k_port_fdb_insert(priv
, addr
, port_mask
, vid
);
1643 qca8k_port_fdb_del(struct dsa_switch
*ds
, int port
,
1644 const unsigned char *addr
, u16 vid
)
1646 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1647 u16 port_mask
= BIT(port
);
1650 vid
= QCA8K_PORT_VID_DEF
;
1652 return qca8k_fdb_del(priv
, addr
, port_mask
, vid
);
1656 qca8k_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1657 dsa_fdb_dump_cb_t
*cb
, void *data
)
1659 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1660 struct qca8k_fdb _fdb
= { 0 };
1661 int cnt
= QCA8K_NUM_FDB_RECORDS
;
1665 mutex_lock(&priv
->reg_mutex
);
1666 while (cnt
-- && !qca8k_fdb_next(priv
, &_fdb
, port
)) {
1669 is_static
= (_fdb
.aging
== QCA8K_ATU_STATUS_STATIC
);
1670 ret
= cb(_fdb
.mac
, _fdb
.vid
, is_static
, data
);
1674 mutex_unlock(&priv
->reg_mutex
);
1680 qca8k_port_vlan_filtering(struct dsa_switch
*ds
, int port
, bool vlan_filtering
,
1681 struct netlink_ext_ack
*extack
)
1683 struct qca8k_priv
*priv
= ds
->priv
;
1686 if (vlan_filtering
) {
1687 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1688 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1689 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE
);
1691 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1692 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1693 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE
);
1700 qca8k_port_vlan_add(struct dsa_switch
*ds
, int port
,
1701 const struct switchdev_obj_port_vlan
*vlan
,
1702 struct netlink_ext_ack
*extack
)
1704 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1705 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1706 struct qca8k_priv
*priv
= ds
->priv
;
1709 ret
= qca8k_vlan_add(priv
, port
, vlan
->vid
, untagged
);
1711 dev_err(priv
->dev
, "Failed to add VLAN to port %d (%d)", port
, ret
);
1716 int shift
= 16 * (port
% 2);
1718 ret
= qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(port
),
1719 0xfff << shift
, vlan
->vid
<< shift
);
1723 ret
= qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(port
),
1724 QCA8K_PORT_VLAN_CVID(vlan
->vid
) |
1725 QCA8K_PORT_VLAN_SVID(vlan
->vid
));
1732 qca8k_port_vlan_del(struct dsa_switch
*ds
, int port
,
1733 const struct switchdev_obj_port_vlan
*vlan
)
1735 struct qca8k_priv
*priv
= ds
->priv
;
1738 ret
= qca8k_vlan_del(priv
, port
, vlan
->vid
);
1740 dev_err(priv
->dev
, "Failed to delete VLAN from port %d (%d)", port
, ret
);
1745 static u32
qca8k_get_phy_flags(struct dsa_switch
*ds
, int port
)
1747 struct qca8k_priv
*priv
= ds
->priv
;
1749 /* Communicate to the phy internal driver the switch revision.
1750 * Based on the switch revision different values needs to be
1751 * set to the dbg and mmd reg on the phy.
1752 * The first 2 bit are used to communicate the switch revision
1753 * to the phy driver.
1755 if (port
> 0 && port
< 6)
1756 return priv
->switch_revision
;
1761 static enum dsa_tag_protocol
1762 qca8k_get_tag_protocol(struct dsa_switch
*ds
, int port
,
1763 enum dsa_tag_protocol mp
)
1765 return DSA_TAG_PROTO_QCA
;
1768 static const struct dsa_switch_ops qca8k_switch_ops
= {
1769 .get_tag_protocol
= qca8k_get_tag_protocol
,
1770 .setup
= qca8k_setup
,
1771 .get_strings
= qca8k_get_strings
,
1772 .get_ethtool_stats
= qca8k_get_ethtool_stats
,
1773 .get_sset_count
= qca8k_get_sset_count
,
1774 .get_mac_eee
= qca8k_get_mac_eee
,
1775 .set_mac_eee
= qca8k_set_mac_eee
,
1776 .port_enable
= qca8k_port_enable
,
1777 .port_disable
= qca8k_port_disable
,
1778 .port_change_mtu
= qca8k_port_change_mtu
,
1779 .port_max_mtu
= qca8k_port_max_mtu
,
1780 .port_stp_state_set
= qca8k_port_stp_state_set
,
1781 .port_bridge_join
= qca8k_port_bridge_join
,
1782 .port_bridge_leave
= qca8k_port_bridge_leave
,
1783 .port_fdb_add
= qca8k_port_fdb_add
,
1784 .port_fdb_del
= qca8k_port_fdb_del
,
1785 .port_fdb_dump
= qca8k_port_fdb_dump
,
1786 .port_vlan_filtering
= qca8k_port_vlan_filtering
,
1787 .port_vlan_add
= qca8k_port_vlan_add
,
1788 .port_vlan_del
= qca8k_port_vlan_del
,
1789 .phylink_validate
= qca8k_phylink_validate
,
1790 .phylink_mac_link_state
= qca8k_phylink_mac_link_state
,
1791 .phylink_mac_config
= qca8k_phylink_mac_config
,
1792 .phylink_mac_link_down
= qca8k_phylink_mac_link_down
,
1793 .phylink_mac_link_up
= qca8k_phylink_mac_link_up
,
1794 .get_phy_flags
= qca8k_get_phy_flags
,
1797 static int qca8k_read_switch_id(struct qca8k_priv
*priv
)
1799 const struct qca8k_match_data
*data
;
1804 /* get the switches ID from the compatible */
1805 data
= of_device_get_match_data(priv
->dev
);
1809 ret
= qca8k_read(priv
, QCA8K_REG_MASK_CTRL
, &val
);
1813 id
= QCA8K_MASK_CTRL_DEVICE_ID(val
& QCA8K_MASK_CTRL_DEVICE_ID_MASK
);
1814 if (id
!= data
->id
) {
1815 dev_err(priv
->dev
, "Switch id detected %x but expected %x", id
, data
->id
);
1819 priv
->switch_id
= id
;
1821 /* Save revision to communicate to the internal PHY driver */
1822 priv
->switch_revision
= (val
& QCA8K_MASK_CTRL_REV_ID_MASK
);
1828 qca8k_sw_probe(struct mdio_device
*mdiodev
)
1830 struct qca8k_priv
*priv
;
1833 /* allocate the private data struct so that we can probe the switches
1836 priv
= devm_kzalloc(&mdiodev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1840 priv
->bus
= mdiodev
->bus
;
1841 priv
->dev
= &mdiodev
->dev
;
1843 priv
->reset_gpio
= devm_gpiod_get_optional(priv
->dev
, "reset",
1845 if (IS_ERR(priv
->reset_gpio
))
1846 return PTR_ERR(priv
->reset_gpio
);
1848 if (priv
->reset_gpio
) {
1849 gpiod_set_value_cansleep(priv
->reset_gpio
, 1);
1850 /* The active low duration must be greater than 10 ms
1851 * and checkpatch.pl wants 20 ms.
1854 gpiod_set_value_cansleep(priv
->reset_gpio
, 0);
1857 /* Check the detected switch id */
1858 ret
= qca8k_read_switch_id(priv
);
1862 priv
->ds
= devm_kzalloc(&mdiodev
->dev
, sizeof(*priv
->ds
), GFP_KERNEL
);
1866 priv
->ds
->dev
= &mdiodev
->dev
;
1867 priv
->ds
->num_ports
= QCA8K_NUM_PORTS
;
1868 priv
->ds
->priv
= priv
;
1869 priv
->ops
= qca8k_switch_ops
;
1870 priv
->ds
->ops
= &priv
->ops
;
1871 mutex_init(&priv
->reg_mutex
);
1872 dev_set_drvdata(&mdiodev
->dev
, priv
);
1874 return dsa_register_switch(priv
->ds
);
1878 qca8k_sw_remove(struct mdio_device
*mdiodev
)
1880 struct qca8k_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
1886 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1887 qca8k_port_set_status(priv
, i
, 0);
1889 dsa_unregister_switch(priv
->ds
);
1891 dev_set_drvdata(&mdiodev
->dev
, NULL
);
1894 static void qca8k_sw_shutdown(struct mdio_device
*mdiodev
)
1896 struct qca8k_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
1901 dsa_switch_shutdown(priv
->ds
);
1903 dev_set_drvdata(&mdiodev
->dev
, NULL
);
1906 #ifdef CONFIG_PM_SLEEP
1908 qca8k_set_pm(struct qca8k_priv
*priv
, int enable
)
1912 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1913 if (!priv
->port_sts
[i
].enabled
)
1916 qca8k_port_set_status(priv
, i
, enable
);
1920 static int qca8k_suspend(struct device
*dev
)
1922 struct qca8k_priv
*priv
= dev_get_drvdata(dev
);
1924 qca8k_set_pm(priv
, 0);
1926 return dsa_switch_suspend(priv
->ds
);
1929 static int qca8k_resume(struct device
*dev
)
1931 struct qca8k_priv
*priv
= dev_get_drvdata(dev
);
1933 qca8k_set_pm(priv
, 1);
1935 return dsa_switch_resume(priv
->ds
);
1937 #endif /* CONFIG_PM_SLEEP */
1939 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops
,
1940 qca8k_suspend
, qca8k_resume
);
1942 static const struct qca8k_match_data qca832x
= {
1943 .id
= QCA8K_ID_QCA8327
,
1946 static const struct qca8k_match_data qca833x
= {
1947 .id
= QCA8K_ID_QCA8337
,
1950 static const struct of_device_id qca8k_of_match
[] = {
1951 { .compatible
= "qca,qca8327", .data
= &qca832x
},
1952 { .compatible
= "qca,qca8334", .data
= &qca833x
},
1953 { .compatible
= "qca,qca8337", .data
= &qca833x
},
1957 static struct mdio_driver qca8kmdio_driver
= {
1958 .probe
= qca8k_sw_probe
,
1959 .remove
= qca8k_sw_remove
,
1960 .shutdown
= qca8k_sw_shutdown
,
1963 .of_match_table
= qca8k_of_match
,
1964 .pm
= &qca8k_pm_ops
,
1968 mdio_module_driver(qca8kmdio_driver
);
1970 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1971 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1972 MODULE_LICENSE("GPL v2");
1973 MODULE_ALIAS("platform:qca8k");