drivers/net/dsa/sja1105/sja1105.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #ifndef _SJA1105_H
   6 #define _SJA1105_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/timecounter.h>
  10 #include <linux/dsa/sja1105.h>
  11 #include <linux/dsa/8021q.h>
  12 #include <net/dsa.h>
  13 #include <linux/mutex.h>
  14 #include "sja1105_static_config.h"
  15
  16 #define SJA1105ET_FDB_BIN_SIZE          4
  17 /* The hardware value is in multiples of 10 ms.
  18  * The passed parameter is in multiples of 1 ms.
  19  */
  20 #define SJA1105_AGEING_TIME_MS(ms)      ((ms) / 10)
  21 #define SJA1105_NUM_L2_POLICERS         SJA1110_MAX_L2_POLICING_COUNT
  22
  23 typedef enum {
  24         SPI_READ = 0,
  25         SPI_WRITE = 1,
  26 } sja1105_spi_rw_mode_t;
  27
  28 #include "sja1105_tas.h"
  29 #include "sja1105_ptp.h"
  30
  31 enum sja1105_stats_area {
  32         MAC,
  33         HL1,
  34         HL2,
  35         ETHER,
  36         __MAX_SJA1105_STATS_AREA,
  37 };
  38
  39 /* Keeps the different addresses between E/T and P/Q/R/S */
  40 struct sja1105_regs {
  41         u64 device_id;
  42         u64 prod_id;
  43         u64 status;
  44         u64 port_control;
  45         u64 rgu;
  46         u64 vl_status;
  47         u64 config;
  48         u64 rmii_pll1;
  49         u64 ptppinst;
  50         u64 ptppindur;
  51         u64 ptp_control;
  52         u64 ptpclkval;
  53         u64 ptpclkrate;
  54         u64 ptpclkcorp;
  55         u64 ptpsyncts;
  56         u64 ptpschtm;
  57         u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
  58         u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
  59         u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
  60         u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
  61         u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
  62         u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
  63         u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
  64         u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  65         u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
  66         u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
  67         u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
  68         u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  69         u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
  70         u64 mdio_100base_tx;
  71         u64 mdio_100base_t1;
  72         u64 pcs_base[SJA1105_MAX_NUM_PORTS];
  73 };
  74
  75 struct sja1105_mdio_private {
  76         struct sja1105_private *priv;
  77 };
  78
  79 enum {
  80         SJA1105_SPEED_AUTO,
  81         SJA1105_SPEED_10MBPS,
  82         SJA1105_SPEED_100MBPS,
  83         SJA1105_SPEED_1000MBPS,
  84         SJA1105_SPEED_2500MBPS,
  85         SJA1105_SPEED_MAX,
  86 };
  87
  88 enum sja1105_internal_phy_t {
  89         SJA1105_NO_PHY          = 0,
  90         SJA1105_PHY_BASE_TX,
  91         SJA1105_PHY_BASE_T1,
  92 };
  93
  94 struct sja1105_info {
  95         u64 device_id;
  96         /* Needed for distinction between P and R, and between Q and S
  97          * (since the parts with/without SGMII share the same
  98          * switch core and device_id)
  99          */
 100         u64 part_no;
 101         /* E/T and P/Q/R/S have partial timestamps of different sizes.
 102          * They must be reconstructed on both families anyway to get the full
 103          * 64-bit values back.
 104          */
 105         int ptp_ts_bits;
 106         /* Also SPI commands are of different sizes to retrieve
 107          * the egress timestamps.
 108          */
 109         int ptpegr_ts_bytes;
 110         int num_cbs_shapers;
 111         int max_frame_mem;
 112         int num_ports;
 113         bool multiple_cascade_ports;
 114         enum dsa_tag_protocol tag_proto;
 115         const struct sja1105_dynamic_table_ops *dyn_ops;
 116         const struct sja1105_table_ops *static_ops;
 117         const struct sja1105_regs *regs;
 118         /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag
 119          * from double-tagged frames. E/T will pop it only when it's equal to
 120          * TPID from the General Parameters Table, while P/Q/R/S will only
 121          * pop it when it's equal to TPID2.
 122          */
 123         u16 qinq_tpid;
 124         bool can_limit_mcast_flood;
 125         int (*reset_cmd)(struct dsa_switch *ds);
 126         int (*setup_rgmii_delay)(const void *ctx, int port);
 127         /* Prototypes from include/net/dsa.h */
 128         int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
 129                            const unsigned char *addr, u16 vid);
 130         int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
 131                            const unsigned char *addr, u16 vid);
 132         void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
 133                                 enum packing_op op);
 134         bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 135         void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 136         int (*clocking_setup)(struct sja1105_private *priv);
 137         int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);
 138         int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);
 139         int (*disable_microcontroller)(struct sja1105_private *priv);
 140         const char *name;
 141         bool supports_mii[SJA1105_MAX_NUM_PORTS];
 142         bool supports_rmii[SJA1105_MAX_NUM_PORTS];
 143         bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
 144         bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
 145         bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
 146         enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
 147         const u64 port_speed[SJA1105_SPEED_MAX];
 148 };
 149
 150 enum sja1105_key_type {
 151         SJA1105_KEY_BCAST,
 152         SJA1105_KEY_TC,
 153         SJA1105_KEY_VLAN_UNAWARE_VL,
 154         SJA1105_KEY_VLAN_AWARE_VL,
 155 };
 156
 157 struct sja1105_key {
 158         enum sja1105_key_type type;
 159
 160         union {
 161                 /* SJA1105_KEY_TC */
 162                 struct {
 163                         int pcp;
 164                 } tc;
 165
 166                 /* SJA1105_KEY_VLAN_UNAWARE_VL */
 167                 /* SJA1105_KEY_VLAN_AWARE_VL */
 168                 struct {
 169                         u64 dmac;
 170                         u16 vid;
 171                         u16 pcp;
 172                 } vl;
 173         };
 174 };
 175
 176 enum sja1105_rule_type {
 177         SJA1105_RULE_BCAST_POLICER,
 178         SJA1105_RULE_TC_POLICER,
 179         SJA1105_RULE_VL,
 180 };
 181
 182 enum sja1105_vl_type {
 183         SJA1105_VL_NONCRITICAL,
 184         SJA1105_VL_RATE_CONSTRAINED,
 185         SJA1105_VL_TIME_TRIGGERED,
 186 };
 187
 188 struct sja1105_rule {
 189         struct list_head list;
 190         unsigned long cookie;
 191         unsigned long port_mask;
 192         struct sja1105_key key;
 193         enum sja1105_rule_type type;
 194
 195         /* Action */
 196         union {
 197                 /* SJA1105_RULE_BCAST_POLICER */
 198                 struct {
 199                         int sharindx;
 200                 } bcast_pol;
 201
 202                 /* SJA1105_RULE_TC_POLICER */
 203                 struct {
 204                         int sharindx;
 205                 } tc_pol;
 206
 207                 /* SJA1105_RULE_VL */
 208                 struct {
 209                         enum sja1105_vl_type type;
 210                         unsigned long destports;
 211                         int sharindx;
 212                         int maxlen;
 213                         int ipv;
 214                         u64 base_time;
 215                         u64 cycle_time;
 216                         int num_entries;
 217                         struct action_gate_entry *entries;
 218                         struct flow_stats stats;
 219                 } vl;
 220         };
 221 };
 222
 223 struct sja1105_flow_block {
 224         struct list_head rules;
 225         bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
 226         int num_virtual_links;
 227 };
 228
 229 struct sja1105_private {
 230         struct sja1105_static_config static_config;
 231         bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
 232         bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
 233         phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
 234         bool fixed_link[SJA1105_MAX_NUM_PORTS];
 235         bool vlan_aware;
 236         unsigned long ucast_egress_floods;
 237         unsigned long bcast_egress_floods;
 238         const struct sja1105_info *info;
 239         size_t max_xfer_len;
 240         struct gpio_desc *reset_gpio;
 241         struct spi_device *spidev;
 242         struct dsa_switch *ds;
 243         u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
 244         u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
 245         struct sja1105_flow_block flow_block;
 246         struct sja1105_port ports[SJA1105_MAX_NUM_PORTS];
 247         /* Serializes transmission of management frames so that
 248          * the switch doesn't confuse them with one another.
 249          */
 250         struct mutex mgmt_lock;
 251         struct devlink_region **regions;
 252         struct sja1105_cbs_entry *cbs;
 253         struct mii_bus *mdio_base_t1;
 254         struct mii_bus *mdio_base_tx;
 255         struct mii_bus *mdio_pcs;
 256         struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
 257         struct sja1105_tagger_data tagger_data;
 258         struct sja1105_ptp_data ptp_data;
 259         struct sja1105_tas_data tas_data;
 260 };
 261
 262 #include "sja1105_dynamic_config.h"
 263
 264 struct sja1105_spi_message {
 265         u64 access;
 266         u64 read_count;
 267         u64 address;
 268 };
 269
 270 /* From sja1105_main.c */
 271 enum sja1105_reset_reason {
 272         SJA1105_VLAN_FILTERING = 0,
 273         SJA1105_RX_HWTSTAMPING,
 274         SJA1105_AGEING_TIME,
 275         SJA1105_SCHEDULING,
 276         SJA1105_BEST_EFFORT_POLICING,
 277         SJA1105_VIRTUAL_LINKS,
 278 };
 279
 280 int sja1105_static_config_reload(struct sja1105_private *priv,
 281                                  enum sja1105_reset_reason reason);
 282 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
 283                            struct netlink_ext_ack *extack);
 284 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
 285
 286 /* From sja1105_mdio.c */
 287 int sja1105_mdiobus_register(struct dsa_switch *ds);
 288 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
 289 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
 290 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
 291 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
 292 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
 293
 294 /* From sja1105_devlink.c */
 295 int sja1105_devlink_setup(struct dsa_switch *ds);
 296 void sja1105_devlink_teardown(struct dsa_switch *ds);
 297 int sja1105_devlink_info_get(struct dsa_switch *ds,
 298                              struct devlink_info_req *req,
 299                              struct netlink_ext_ack *extack);
 300
 301 /* From sja1105_spi.c */
 302 int sja1105_xfer_buf(const struct sja1105_private *priv,
 303                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 304                      u8 *buf, size_t len);
 305 int sja1105_xfer_u32(const struct sja1105_private *priv,
 306                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 307                      struct ptp_system_timestamp *ptp_sts);
 308 int sja1105_xfer_u64(const struct sja1105_private *priv,
 309                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 310                      struct ptp_system_timestamp *ptp_sts);
 311 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 312                                          void *config_buf, int buf_len);
 313 int sja1105_static_config_upload(struct sja1105_private *priv);
 314 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 315                        unsigned long port_bitmap, bool tx_inhibited);
 316
 317 extern const struct sja1105_info sja1105e_info;
 318 extern const struct sja1105_info sja1105t_info;
 319 extern const struct sja1105_info sja1105p_info;
 320 extern const struct sja1105_info sja1105q_info;
 321 extern const struct sja1105_info sja1105r_info;
 322 extern const struct sja1105_info sja1105s_info;
 323 extern const struct sja1105_info sja1110a_info;
 324 extern const struct sja1105_info sja1110b_info;
 325 extern const struct sja1105_info sja1110c_info;
 326 extern const struct sja1105_info sja1110d_info;
 327
 328 /* From sja1105_clocking.c */
 329
 330 typedef enum {
 331         XMII_MAC = 0,
 332         XMII_PHY = 1,
 333 } sja1105_mii_role_t;
 334
 335 typedef enum {
 336         XMII_MODE_MII           = 0,
 337         XMII_MODE_RMII          = 1,
 338         XMII_MODE_RGMII         = 2,
 339         XMII_MODE_SGMII         = 3,
 340 } sja1105_phy_interface_t;
 341
 342 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
 343 int sja1110_setup_rgmii_delay(const void *ctx, int port);
 344 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
 345 int sja1105_clocking_setup(struct sja1105_private *priv);
 346 int sja1110_disable_microcontroller(struct sja1105_private *priv);
 347
 348 /* From sja1105_ethtool.c */
 349 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
 350 void sja1105_get_strings(struct dsa_switch *ds, int port,
 351                          u32 stringset, u8 *data);
 352 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
 353
 354 /* From sja1105_dynamic_config.c */
 355 int sja1105_dynamic_config_read(struct sja1105_private *priv,
 356                                 enum sja1105_blk_idx blk_idx,
 357                                 int index, void *entry);
 358 int sja1105_dynamic_config_write(struct sja1105_private *priv,
 359                                  enum sja1105_blk_idx blk_idx,
 360                                  int index, void *entry, bool keep);
 361
 362 enum sja1105_iotag {
 363         SJA1105_C_TAG = 0, /* Inner VLAN header */
 364         SJA1105_S_TAG = 1, /* Outer VLAN header */
 365 };
 366
 367 enum sja1110_vlan_type {
 368         SJA1110_VLAN_INVALID = 0,
 369         SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
 370         SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
 371         SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
 372 };
 373
 374 enum sja1110_shaper_type {
 375         SJA1110_LEAKY_BUCKET_SHAPER = 0,
 376         SJA1110_CBS_SHAPER = 1,
 377 };
 378
 379 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
 380 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
 381                       const unsigned char *addr, u16 vid);
 382 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
 383                       const unsigned char *addr, u16 vid);
 384 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
 385                         const unsigned char *addr, u16 vid);
 386 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
 387                         const unsigned char *addr, u16 vid);
 388
 389 /* From sja1105_flower.c */
 390 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
 391                            struct flow_cls_offload *cls, bool ingress);
 392 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
 393                            struct flow_cls_offload *cls, bool ingress);
 394 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
 395                              struct flow_cls_offload *cls, bool ingress);
 396 void sja1105_flower_setup(struct dsa_switch *ds);
 397 void sja1105_flower_teardown(struct dsa_switch *ds);
 398 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
 399                                        unsigned long cookie);
 400
 401 #endif