1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/printk.h>
11 #include <linux/spi/spi.h>
12 #include <linux/errno.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/phylink.h>
16 #include <linux/of_net.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_device.h>
19 #include <linux/pcs/pcs-xpcs.h>
20 #include <linux/netdev_features.h>
21 #include <linux/netdevice.h>
22 #include <linux/if_bridge.h>
23 #include <linux/if_ether.h>
24 #include <linux/dsa/8021q.h>
26 #include "sja1105_tas.h"
28 #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
29 #define SJA1105_DEFAULT_VLAN (VLAN_N_VID - 1)
31 static const struct dsa_switch_ops sja1105_switch_ops
;
33 static void sja1105_hw_reset(struct gpio_desc
*gpio
, unsigned int pulse_len
,
34 unsigned int startup_delay
)
36 gpiod_set_value_cansleep(gpio
, 1);
37 /* Wait for minimum reset pulse length */
39 gpiod_set_value_cansleep(gpio
, 0);
40 /* Wait until chip is ready after reset */
41 msleep(startup_delay
);
45 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry
*l2_fwd
,
46 int from
, int to
, bool allow
)
49 l2_fwd
[from
].reach_port
|= BIT(to
);
51 l2_fwd
[from
].reach_port
&= ~BIT(to
);
54 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry
*l2_fwd
,
57 return !!(l2_fwd
[from
].reach_port
& BIT(to
));
60 static int sja1105_is_vlan_configured(struct sja1105_private
*priv
, u16 vid
)
62 struct sja1105_vlan_lookup_entry
*vlan
;
65 vlan
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entries
;
66 count
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entry_count
;
68 for (i
= 0; i
< count
; i
++)
69 if (vlan
[i
].vlanid
== vid
)
72 /* Return an invalid entry index if not found */
76 static int sja1105_drop_untagged(struct dsa_switch
*ds
, int port
, bool drop
)
78 struct sja1105_private
*priv
= ds
->priv
;
79 struct sja1105_mac_config_entry
*mac
;
81 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
83 if (mac
[port
].drpuntag
== drop
)
86 mac
[port
].drpuntag
= drop
;
88 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
92 static int sja1105_pvid_apply(struct sja1105_private
*priv
, int port
, u16 pvid
)
94 struct sja1105_mac_config_entry
*mac
;
96 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
98 if (mac
[port
].vlanid
== pvid
)
101 mac
[port
].vlanid
= pvid
;
103 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
107 static int sja1105_commit_pvid(struct dsa_switch
*ds
, int port
)
109 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
110 struct sja1105_private
*priv
= ds
->priv
;
111 struct sja1105_vlan_lookup_entry
*vlan
;
112 bool drop_untagged
= false;
116 if (dp
->bridge_dev
&& br_vlan_enabled(dp
->bridge_dev
))
117 pvid
= priv
->bridge_pvid
[port
];
119 pvid
= priv
->tag_8021q_pvid
[port
];
121 rc
= sja1105_pvid_apply(priv
, port
, pvid
);
125 vlan
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entries
;
127 match
= sja1105_is_vlan_configured(priv
, pvid
);
129 if (match
< 0 || !(vlan
[match
].vmemb_port
& BIT(port
)))
130 drop_untagged
= true;
132 return sja1105_drop_untagged(ds
, port
, drop_untagged
);
135 static int sja1105_init_mac_settings(struct sja1105_private
*priv
)
137 struct sja1105_mac_config_entry default_mac
= {
138 /* Enable all 8 priority queues on egress.
139 * Every queue i holds top[i] - base[i] frames.
140 * Sum of top[i] - base[i] is 511 (max hardware limit).
142 .top
= {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
143 .base
= {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
144 .enabled
= {true, true, true, true, true, true, true, true},
145 /* Keep standard IFG of 12 bytes on egress. */
147 /* Always put the MAC speed in automatic mode, where it can be
148 * adjusted at runtime by PHYLINK.
150 .speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
],
151 /* No static correction for 1-step 1588 events */
154 /* Disable aging for critical TTEthernet traffic */
156 /* Internal VLAN (pvid) to apply to untagged ingress */
161 /* Don't drop traffic with other EtherType than ETH_P_IP */
163 /* Don't drop double-tagged traffic */
165 /* Don't drop untagged traffic */
167 /* Don't retag 802.1p (VID 0) traffic with the pvid */
169 /* Disable learning and I/O on user ports by default -
170 * STP will enable it.
176 struct sja1105_mac_config_entry
*mac
;
177 struct dsa_switch
*ds
= priv
->ds
;
178 struct sja1105_table
*table
;
181 table
= &priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
];
183 /* Discard previous MAC Configuration Table */
184 if (table
->entry_count
) {
185 kfree(table
->entries
);
186 table
->entry_count
= 0;
189 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
190 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
194 table
->entry_count
= table
->ops
->max_entry_count
;
196 mac
= table
->entries
;
198 list_for_each_entry(dp
, &ds
->dst
->ports
, list
) {
202 mac
[dp
->index
] = default_mac
;
204 /* Let sja1105_bridge_stp_state_set() keep address learning
205 * enabled for the DSA ports. CPU ports use software-assisted
206 * learning to ensure that only FDB entries belonging to the
207 * bridge are learned, and that they are learned towards all
208 * CPU ports in a cross-chip topology if multiple CPU ports
211 if (dsa_port_is_dsa(dp
))
218 static int sja1105_init_mii_settings(struct sja1105_private
*priv
)
220 struct device
*dev
= &priv
->spidev
->dev
;
221 struct sja1105_xmii_params_entry
*mii
;
222 struct dsa_switch
*ds
= priv
->ds
;
223 struct sja1105_table
*table
;
226 table
= &priv
->static_config
.tables
[BLK_IDX_XMII_PARAMS
];
228 /* Discard previous xMII Mode Parameters Table */
229 if (table
->entry_count
) {
230 kfree(table
->entries
);
231 table
->entry_count
= 0;
234 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
235 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
239 /* Override table based on PHYLINK DT bindings */
240 table
->entry_count
= table
->ops
->max_entry_count
;
242 mii
= table
->entries
;
244 for (i
= 0; i
< ds
->num_ports
; i
++) {
245 sja1105_mii_role_t role
= XMII_MAC
;
247 if (dsa_is_unused_port(priv
->ds
, i
))
250 switch (priv
->phy_mode
[i
]) {
251 case PHY_INTERFACE_MODE_INTERNAL
:
252 if (priv
->info
->internal_phy
[i
] == SJA1105_NO_PHY
)
255 mii
->xmii_mode
[i
] = XMII_MODE_MII
;
256 if (priv
->info
->internal_phy
[i
] == SJA1105_PHY_BASE_TX
)
257 mii
->special
[i
] = true;
260 case PHY_INTERFACE_MODE_REVMII
:
263 case PHY_INTERFACE_MODE_MII
:
264 if (!priv
->info
->supports_mii
[i
])
267 mii
->xmii_mode
[i
] = XMII_MODE_MII
;
269 case PHY_INTERFACE_MODE_REVRMII
:
272 case PHY_INTERFACE_MODE_RMII
:
273 if (!priv
->info
->supports_rmii
[i
])
276 mii
->xmii_mode
[i
] = XMII_MODE_RMII
;
278 case PHY_INTERFACE_MODE_RGMII
:
279 case PHY_INTERFACE_MODE_RGMII_ID
:
280 case PHY_INTERFACE_MODE_RGMII_RXID
:
281 case PHY_INTERFACE_MODE_RGMII_TXID
:
282 if (!priv
->info
->supports_rgmii
[i
])
285 mii
->xmii_mode
[i
] = XMII_MODE_RGMII
;
287 case PHY_INTERFACE_MODE_SGMII
:
288 if (!priv
->info
->supports_sgmii
[i
])
291 mii
->xmii_mode
[i
] = XMII_MODE_SGMII
;
292 mii
->special
[i
] = true;
294 case PHY_INTERFACE_MODE_2500BASEX
:
295 if (!priv
->info
->supports_2500basex
[i
])
298 mii
->xmii_mode
[i
] = XMII_MODE_SGMII
;
299 mii
->special
[i
] = true;
303 dev_err(dev
, "Unsupported PHY mode %s on port %d!\n",
304 phy_modes(priv
->phy_mode
[i
]), i
);
308 mii
->phy_mac
[i
] = role
;
313 static int sja1105_init_static_fdb(struct sja1105_private
*priv
)
315 struct sja1105_l2_lookup_entry
*l2_lookup
;
316 struct sja1105_table
*table
;
319 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
321 /* We only populate the FDB table through dynamic L2 Address Lookup
322 * entries, except for a special entry at the end which is a catch-all
323 * for unknown multicast and will be used to control flooding domain.
325 if (table
->entry_count
) {
326 kfree(table
->entries
);
327 table
->entry_count
= 0;
330 if (!priv
->info
->can_limit_mcast_flood
)
333 table
->entries
= kcalloc(1, table
->ops
->unpacked_entry_size
,
338 table
->entry_count
= 1;
339 l2_lookup
= table
->entries
;
341 /* All L2 multicast addresses have an odd first octet */
342 l2_lookup
[0].macaddr
= SJA1105_UNKNOWN_MULTICAST
;
343 l2_lookup
[0].mask_macaddr
= SJA1105_UNKNOWN_MULTICAST
;
344 l2_lookup
[0].lockeds
= true;
345 l2_lookup
[0].index
= SJA1105_MAX_L2_LOOKUP_COUNT
- 1;
347 /* Flood multicast to every port by default */
348 for (port
= 0; port
< priv
->ds
->num_ports
; port
++)
349 if (!dsa_is_unused_port(priv
->ds
, port
))
350 l2_lookup
[0].destports
|= BIT(port
);
355 static int sja1105_init_l2_lookup_params(struct sja1105_private
*priv
)
357 struct sja1105_l2_lookup_params_entry default_l2_lookup_params
= {
358 /* Learned FDB entries are forgotten after 300 seconds */
359 .maxage
= SJA1105_AGEING_TIME_MS(300000),
360 /* All entries within a FDB bin are available for learning */
361 .dyn_tbsz
= SJA1105ET_FDB_BIN_SIZE
,
362 /* And the P/Q/R/S equivalent setting: */
364 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
366 /* This selects between Independent VLAN Learning (IVL) and
367 * Shared VLAN Learning (SVL)
369 .shared_learn
= true,
370 /* Don't discard management traffic based on ENFPORT -
371 * we don't perform SMAC port enforcement anyway, so
372 * what we are setting here doesn't matter.
374 .no_enf_hostprt
= false,
375 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
376 * Maybe correlate with no_linklocal_learn from bridge driver?
378 .no_mgmt_learn
= true,
381 /* Dynamically learned FDB entries can overwrite other (older)
382 * dynamic FDB entries
387 struct dsa_switch
*ds
= priv
->ds
;
388 int port
, num_used_ports
= 0;
389 struct sja1105_table
*table
;
392 for (port
= 0; port
< ds
->num_ports
; port
++)
393 if (!dsa_is_unused_port(ds
, port
))
396 max_fdb_entries
= SJA1105_MAX_L2_LOOKUP_COUNT
/ num_used_ports
;
398 for (port
= 0; port
< ds
->num_ports
; port
++) {
399 if (dsa_is_unused_port(ds
, port
))
402 default_l2_lookup_params
.maxaddrp
[port
] = max_fdb_entries
;
405 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
407 if (table
->entry_count
) {
408 kfree(table
->entries
);
409 table
->entry_count
= 0;
412 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
413 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
417 table
->entry_count
= table
->ops
->max_entry_count
;
419 /* This table only has a single entry */
420 ((struct sja1105_l2_lookup_params_entry
*)table
->entries
)[0] =
421 default_l2_lookup_params
;
426 /* Set up a default VLAN for untagged traffic injected from the CPU
427 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
428 * All DT-defined ports are members of this VLAN, and there are no
429 * restrictions on forwarding (since the CPU selects the destination).
430 * Frames from this VLAN will always be transmitted as untagged, and
431 * neither the bridge nor the 8021q module cannot create this VLAN ID.
433 static int sja1105_init_static_vlan(struct sja1105_private
*priv
)
435 struct sja1105_table
*table
;
436 struct sja1105_vlan_lookup_entry pvid
= {
437 .type_entry
= SJA1110_VLAN_D_TAG
,
443 .vlanid
= SJA1105_DEFAULT_VLAN
,
445 struct dsa_switch
*ds
= priv
->ds
;
448 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
450 if (table
->entry_count
) {
451 kfree(table
->entries
);
452 table
->entry_count
= 0;
455 table
->entries
= kzalloc(table
->ops
->unpacked_entry_size
,
460 table
->entry_count
= 1;
462 for (port
= 0; port
< ds
->num_ports
; port
++) {
463 if (dsa_is_unused_port(ds
, port
))
466 pvid
.vmemb_port
|= BIT(port
);
467 pvid
.vlan_bc
|= BIT(port
);
468 pvid
.tag_port
&= ~BIT(port
);
470 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
471 priv
->tag_8021q_pvid
[port
] = SJA1105_DEFAULT_VLAN
;
472 priv
->bridge_pvid
[port
] = SJA1105_DEFAULT_VLAN
;
476 ((struct sja1105_vlan_lookup_entry
*)table
->entries
)[0] = pvid
;
480 static int sja1105_init_l2_forwarding(struct sja1105_private
*priv
)
482 struct sja1105_l2_forwarding_entry
*l2fwd
;
483 struct dsa_switch
*ds
= priv
->ds
;
484 struct dsa_switch_tree
*dst
;
485 struct sja1105_table
*table
;
490 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
];
492 if (table
->entry_count
) {
493 kfree(table
->entries
);
494 table
->entry_count
= 0;
497 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
498 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
502 table
->entry_count
= table
->ops
->max_entry_count
;
504 l2fwd
= table
->entries
;
506 /* First 5 entries in the L2 Forwarding Table define the forwarding
507 * rules and the VLAN PCP to ingress queue mapping.
508 * Set up the ingress queue mapping first.
510 for (port
= 0; port
< ds
->num_ports
; port
++) {
511 if (dsa_is_unused_port(ds
, port
))
514 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
515 l2fwd
[port
].vlan_pmap
[tc
] = tc
;
518 /* Then manage the forwarding domain for user ports. These can forward
519 * only to the always-on domain (CPU port and DSA links)
521 for (from
= 0; from
< ds
->num_ports
; from
++) {
522 if (!dsa_is_user_port(ds
, from
))
525 for (to
= 0; to
< ds
->num_ports
; to
++) {
526 if (!dsa_is_cpu_port(ds
, to
) &&
527 !dsa_is_dsa_port(ds
, to
))
530 l2fwd
[from
].bc_domain
|= BIT(to
);
531 l2fwd
[from
].fl_domain
|= BIT(to
);
533 sja1105_port_allow_traffic(l2fwd
, from
, to
, true);
537 /* Then manage the forwarding domain for DSA links and CPU ports (the
538 * always-on domain). These can send packets to any enabled port except
541 for (from
= 0; from
< ds
->num_ports
; from
++) {
542 if (!dsa_is_cpu_port(ds
, from
) && !dsa_is_dsa_port(ds
, from
))
545 for (to
= 0; to
< ds
->num_ports
; to
++) {
546 if (dsa_is_unused_port(ds
, to
))
552 l2fwd
[from
].bc_domain
|= BIT(to
);
553 l2fwd
[from
].fl_domain
|= BIT(to
);
555 sja1105_port_allow_traffic(l2fwd
, from
, to
, true);
559 /* In odd topologies ("H" connections where there is a DSA link to
560 * another switch which also has its own CPU port), TX packets can loop
561 * back into the system (they are flooded from CPU port 1 to the DSA
562 * link, and from there to CPU port 2). Prevent this from happening by
563 * cutting RX from DSA links towards our CPU port, if the remote switch
564 * has its own CPU port and therefore doesn't need ours for network
569 list_for_each_entry(dl
, &dst
->rtable
, list
) {
570 if (dl
->dp
->ds
!= ds
|| dl
->link_dp
->cpu_dp
== dl
->dp
->cpu_dp
)
573 from
= dl
->dp
->index
;
574 to
= dsa_upstream_port(ds
, from
);
577 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
580 sja1105_port_allow_traffic(l2fwd
, from
, to
, false);
582 l2fwd
[from
].bc_domain
&= ~BIT(to
);
583 l2fwd
[from
].fl_domain
&= ~BIT(to
);
586 /* Finally, manage the egress flooding domain. All ports start up with
587 * flooding enabled, including the CPU port and DSA links.
589 for (port
= 0; port
< ds
->num_ports
; port
++) {
590 if (dsa_is_unused_port(ds
, port
))
593 priv
->ucast_egress_floods
|= BIT(port
);
594 priv
->bcast_egress_floods
|= BIT(port
);
597 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
598 * Create a one-to-one mapping.
600 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++) {
601 for (port
= 0; port
< ds
->num_ports
; port
++) {
602 if (dsa_is_unused_port(ds
, port
))
605 l2fwd
[ds
->num_ports
+ tc
].vlan_pmap
[port
] = tc
;
608 l2fwd
[ds
->num_ports
+ tc
].type_egrpcp2outputq
= true;
614 static int sja1110_init_pcp_remapping(struct sja1105_private
*priv
)
616 struct sja1110_pcp_remapping_entry
*pcp_remap
;
617 struct dsa_switch
*ds
= priv
->ds
;
618 struct sja1105_table
*table
;
621 table
= &priv
->static_config
.tables
[BLK_IDX_PCP_REMAPPING
];
623 /* Nothing to do for SJA1105 */
624 if (!table
->ops
->max_entry_count
)
627 if (table
->entry_count
) {
628 kfree(table
->entries
);
629 table
->entry_count
= 0;
632 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
633 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
637 table
->entry_count
= table
->ops
->max_entry_count
;
639 pcp_remap
= table
->entries
;
641 /* Repeat the configuration done for vlan_pmap */
642 for (port
= 0; port
< ds
->num_ports
; port
++) {
643 if (dsa_is_unused_port(ds
, port
))
646 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
647 pcp_remap
[port
].egrpcp
[tc
] = tc
;
653 static int sja1105_init_l2_forwarding_params(struct sja1105_private
*priv
)
655 struct sja1105_l2_forwarding_params_entry
*l2fwd_params
;
656 struct sja1105_table
*table
;
658 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING_PARAMS
];
660 if (table
->entry_count
) {
661 kfree(table
->entries
);
662 table
->entry_count
= 0;
665 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
666 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
670 table
->entry_count
= table
->ops
->max_entry_count
;
672 /* This table only has a single entry */
673 l2fwd_params
= table
->entries
;
675 /* Disallow dynamic reconfiguration of vlan_pmap */
676 l2fwd_params
->max_dynp
= 0;
677 /* Use a single memory partition for all ingress queues */
678 l2fwd_params
->part_spc
[0] = priv
->info
->max_frame_mem
;
683 void sja1105_frame_memory_partitioning(struct sja1105_private
*priv
)
685 struct sja1105_l2_forwarding_params_entry
*l2_fwd_params
;
686 struct sja1105_vl_forwarding_params_entry
*vl_fwd_params
;
687 struct sja1105_table
*table
;
689 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING_PARAMS
];
690 l2_fwd_params
= table
->entries
;
691 l2_fwd_params
->part_spc
[0] = SJA1105_MAX_FRAME_MEMORY
;
693 /* If we have any critical-traffic virtual links, we need to reserve
694 * some frame buffer memory for them. At the moment, hardcode the value
695 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
696 * remaining for best-effort traffic. TODO: figure out a more flexible
697 * way to perform the frame buffer partitioning.
699 if (!priv
->static_config
.tables
[BLK_IDX_VL_FORWARDING
].entry_count
)
702 table
= &priv
->static_config
.tables
[BLK_IDX_VL_FORWARDING_PARAMS
];
703 vl_fwd_params
= table
->entries
;
705 l2_fwd_params
->part_spc
[0] -= SJA1105_VL_FRAME_MEMORY
;
706 vl_fwd_params
->partspc
[0] = SJA1105_VL_FRAME_MEMORY
;
709 /* SJA1110 TDMACONFIGIDX values:
711 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
712 * -----+----------------+---------------+---------------+---------------
713 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
714 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
715 * 2 | 0, [5:10] | [1:3], retag | 4 | -
716 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
717 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
718 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
719 * 14 | 0, [5:10] | [1:4], retag | - | -
720 * 15 | [5:10] | [0:4], retag | - | -
722 static void sja1110_select_tdmaconfigidx(struct sja1105_private
*priv
)
724 struct sja1105_general_params_entry
*general_params
;
725 struct sja1105_table
*table
;
726 bool port_1_is_base_tx
;
731 if (priv
->info
->device_id
!= SJA1110_DEVICE_ID
)
734 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
735 general_params
= table
->entries
;
737 /* All the settings below are "as opposed to SGMII", which is the
738 * other pinmuxing option.
740 port_1_is_base_tx
= priv
->phy_mode
[1] == PHY_INTERFACE_MODE_INTERNAL
;
741 port_3_is_2500
= priv
->phy_mode
[3] == PHY_INTERFACE_MODE_2500BASEX
;
742 port_4_is_2500
= priv
->phy_mode
[4] == PHY_INTERFACE_MODE_2500BASEX
;
744 if (port_1_is_base_tx
)
745 /* Retagging port will operate at 1 Gbps */
747 else if (port_3_is_2500
&& port_4_is_2500
)
748 /* Retagging port will operate at 100 Mbps */
750 else if (port_3_is_2500
)
751 /* Retagging port will operate at 1 Gbps */
753 else if (port_4_is_2500
)
754 /* Retagging port will operate at 1 Gbps */
757 /* Retagging port will operate at 1 Gbps */
760 general_params
->tdmaconfigidx
= tdmaconfigidx
;
763 static int sja1105_init_topology(struct sja1105_private
*priv
,
764 struct sja1105_general_params_entry
*general_params
)
766 struct dsa_switch
*ds
= priv
->ds
;
769 /* The host port is the destination for traffic matching mac_fltres1
770 * and mac_fltres0 on all ports except itself. Default to an invalid
773 general_params
->host_port
= ds
->num_ports
;
775 /* Link-local traffic received on casc_port will be forwarded
776 * to host_port without embedding the source port and device ID
777 * info in the destination MAC address, and no RX timestamps will be
778 * taken either (presumably because it is a cascaded port and a
779 * downstream SJA switch already did that).
780 * To disable the feature, we need to do different things depending on
781 * switch generation. On SJA1105 we need to set an invalid port, while
782 * on SJA1110 which support multiple cascaded ports, this field is a
783 * bitmask so it must be left zero.
785 if (!priv
->info
->multiple_cascade_ports
)
786 general_params
->casc_port
= ds
->num_ports
;
788 for (port
= 0; port
< ds
->num_ports
; port
++) {
789 bool is_upstream
= dsa_is_upstream_port(ds
, port
);
790 bool is_dsa_link
= dsa_is_dsa_port(ds
, port
);
792 /* Upstream ports can be dedicated CPU ports or
793 * upstream-facing DSA links
796 if (general_params
->host_port
== ds
->num_ports
) {
797 general_params
->host_port
= port
;
800 "Port %llu is already a host port, configuring %d as one too is not supported\n",
801 general_params
->host_port
, port
);
806 /* Cascade ports are downstream-facing DSA links */
807 if (is_dsa_link
&& !is_upstream
) {
808 if (priv
->info
->multiple_cascade_ports
) {
809 general_params
->casc_port
|= BIT(port
);
810 } else if (general_params
->casc_port
== ds
->num_ports
) {
811 general_params
->casc_port
= port
;
814 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
815 general_params
->casc_port
, port
);
821 if (general_params
->host_port
== ds
->num_ports
) {
822 dev_err(ds
->dev
, "No host port configured\n");
829 static int sja1105_init_general_params(struct sja1105_private
*priv
)
831 struct sja1105_general_params_entry default_general_params
= {
832 /* Allow dynamic changing of the mirror port */
834 .switchid
= priv
->ds
->index
,
835 /* Priority queue for link-local management frames
836 * (both ingress to and egress from CPU - PTP, STP etc)
839 .mac_fltres1
= SJA1105_LINKLOCAL_FILTER_A
,
840 .mac_flt1
= SJA1105_LINKLOCAL_FILTER_A_MASK
,
841 .incl_srcpt1
= false,
843 .mac_fltres0
= SJA1105_LINKLOCAL_FILTER_B
,
844 .mac_flt0
= SJA1105_LINKLOCAL_FILTER_B_MASK
,
845 .incl_srcpt0
= false,
847 /* Default to an invalid value */
848 .mirr_port
= priv
->ds
->num_ports
,
850 .vllupformat
= SJA1105_VL_FORMAT_PSFP
,
853 /* Only update correctionField for 1-step PTP (L2 transport) */
855 /* Forcefully disable VLAN filtering by telling
856 * the switch that VLAN has a different EtherType.
858 .tpid
= ETH_P_SJA1105
,
859 .tpid2
= ETH_P_SJA1105
,
860 /* Enable the TTEthernet engine on SJA1110 */
862 /* Set up the EtherType for control packets on SJA1110 */
863 .header_type
= ETH_P_SJA1110
,
865 struct sja1105_general_params_entry
*general_params
;
866 struct sja1105_table
*table
;
869 rc
= sja1105_init_topology(priv
, &default_general_params
);
873 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
875 if (table
->entry_count
) {
876 kfree(table
->entries
);
877 table
->entry_count
= 0;
880 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
881 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
885 table
->entry_count
= table
->ops
->max_entry_count
;
887 general_params
= table
->entries
;
889 /* This table only has a single entry */
890 general_params
[0] = default_general_params
;
892 sja1110_select_tdmaconfigidx(priv
);
897 static int sja1105_init_avb_params(struct sja1105_private
*priv
)
899 struct sja1105_avb_params_entry
*avb
;
900 struct sja1105_table
*table
;
902 table
= &priv
->static_config
.tables
[BLK_IDX_AVB_PARAMS
];
904 /* Discard previous AVB Parameters Table */
905 if (table
->entry_count
) {
906 kfree(table
->entries
);
907 table
->entry_count
= 0;
910 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
911 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
915 table
->entry_count
= table
->ops
->max_entry_count
;
917 avb
= table
->entries
;
919 /* Configure the MAC addresses for meta frames */
920 avb
->destmeta
= SJA1105_META_DMAC
;
921 avb
->srcmeta
= SJA1105_META_SMAC
;
922 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
923 * default. This is because there might be boards with a hardware
924 * layout where enabling the pin as output might cause an electrical
925 * clash. On E/T the pin is always an output, which the board designers
926 * probably already knew, so even if there are going to be electrical
927 * issues, there's nothing we can do.
929 avb
->cas_master
= false;
934 /* The L2 policing table is 2-stage. The table is looked up for each frame
935 * according to the ingress port, whether it was broadcast or not, and the
936 * classified traffic class (given by VLAN PCP). This portion of the lookup is
937 * fixed, and gives access to the SHARINDX, an indirection register pointing
938 * within the policing table itself, which is used to resolve the policer that
939 * will be used for this frame.
942 * +------------+--------+ +---------------------------------+
943 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
944 * +------------+--------+ +---------------------------------+
945 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
946 * +------------+--------+ +---------------------------------+
947 * ... | Policer 2: Rate, Burst, MTU |
948 * +------------+--------+ +---------------------------------+
949 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
950 * +------------+--------+ +---------------------------------+
951 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
952 * +------------+--------+ +---------------------------------+
953 * ... | Policer 5: Rate, Burst, MTU |
954 * +------------+--------+ +---------------------------------+
955 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
956 * +------------+--------+ +---------------------------------+
957 * ... | Policer 7: Rate, Burst, MTU |
958 * +------------+--------+ +---------------------------------+
959 * |Port 4 TC 7 |SHARINDX| ...
960 * +------------+--------+
961 * |Port 0 BCAST|SHARINDX| ...
962 * +------------+--------+
963 * |Port 1 BCAST|SHARINDX| ...
964 * +------------+--------+
966 * +------------+--------+ +---------------------------------+
967 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
968 * +------------+--------+ +---------------------------------+
970 * In this driver, we shall use policers 0-4 as statically alocated port
971 * (matchall) policers. So we need to make the SHARINDX for all lookups
972 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
974 * The remaining policers (40) shall be dynamically allocated for flower
975 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
977 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
979 static int sja1105_init_l2_policing(struct sja1105_private
*priv
)
981 struct sja1105_l2_policing_entry
*policing
;
982 struct dsa_switch
*ds
= priv
->ds
;
983 struct sja1105_table
*table
;
986 table
= &priv
->static_config
.tables
[BLK_IDX_L2_POLICING
];
988 /* Discard previous L2 Policing Table */
989 if (table
->entry_count
) {
990 kfree(table
->entries
);
991 table
->entry_count
= 0;
994 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
995 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
999 table
->entry_count
= table
->ops
->max_entry_count
;
1001 policing
= table
->entries
;
1003 /* Setup shared indices for the matchall policers */
1004 for (port
= 0; port
< ds
->num_ports
; port
++) {
1005 int mcast
= (ds
->num_ports
* (SJA1105_NUM_TC
+ 1)) + port
;
1006 int bcast
= (ds
->num_ports
* SJA1105_NUM_TC
) + port
;
1008 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
1009 policing
[port
* SJA1105_NUM_TC
+ tc
].sharindx
= port
;
1011 policing
[bcast
].sharindx
= port
;
1012 /* Only SJA1110 has multicast policers */
1013 if (mcast
<= table
->ops
->max_entry_count
)
1014 policing
[mcast
].sharindx
= port
;
1017 /* Setup the matchall policer parameters */
1018 for (port
= 0; port
< ds
->num_ports
; port
++) {
1019 int mtu
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1021 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1024 policing
[port
].smax
= 65535; /* Burst size in bytes */
1025 policing
[port
].rate
= SJA1105_RATE_MBPS(1000);
1026 policing
[port
].maxlen
= mtu
;
1027 policing
[port
].partition
= 0;
1033 static int sja1105_static_config_load(struct sja1105_private
*priv
)
1037 sja1105_static_config_free(&priv
->static_config
);
1038 rc
= sja1105_static_config_init(&priv
->static_config
,
1039 priv
->info
->static_ops
,
1040 priv
->info
->device_id
);
1044 /* Build static configuration */
1045 rc
= sja1105_init_mac_settings(priv
);
1048 rc
= sja1105_init_mii_settings(priv
);
1051 rc
= sja1105_init_static_fdb(priv
);
1054 rc
= sja1105_init_static_vlan(priv
);
1057 rc
= sja1105_init_l2_lookup_params(priv
);
1060 rc
= sja1105_init_l2_forwarding(priv
);
1063 rc
= sja1105_init_l2_forwarding_params(priv
);
1066 rc
= sja1105_init_l2_policing(priv
);
1069 rc
= sja1105_init_general_params(priv
);
1072 rc
= sja1105_init_avb_params(priv
);
1075 rc
= sja1110_init_pcp_remapping(priv
);
1079 /* Send initial configuration to hardware via SPI */
1080 return sja1105_static_config_upload(priv
);
1083 static int sja1105_parse_rgmii_delays(struct sja1105_private
*priv
)
1085 struct dsa_switch
*ds
= priv
->ds
;
1088 for (port
= 0; port
< ds
->num_ports
; port
++) {
1089 if (!priv
->fixed_link
[port
])
1092 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_RXID
||
1093 priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_ID
)
1094 priv
->rgmii_rx_delay
[port
] = true;
1096 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_TXID
||
1097 priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_ID
)
1098 priv
->rgmii_tx_delay
[port
] = true;
1100 if ((priv
->rgmii_rx_delay
[port
] || priv
->rgmii_tx_delay
[port
]) &&
1101 !priv
->info
->setup_rgmii_delay
)
1107 static int sja1105_parse_ports_node(struct sja1105_private
*priv
,
1108 struct device_node
*ports_node
)
1110 struct device
*dev
= &priv
->spidev
->dev
;
1111 struct device_node
*child
;
1113 for_each_available_child_of_node(ports_node
, child
) {
1114 struct device_node
*phy_node
;
1115 phy_interface_t phy_mode
;
1119 /* Get switch port number from DT */
1120 if (of_property_read_u32(child
, "reg", &index
) < 0) {
1121 dev_err(dev
, "Port number not defined in device tree "
1122 "(property \"reg\")\n");
1127 /* Get PHY mode from DT */
1128 err
= of_get_phy_mode(child
, &phy_mode
);
1130 dev_err(dev
, "Failed to read phy-mode or "
1131 "phy-interface-type property for port %d\n",
1137 phy_node
= of_parse_phandle(child
, "phy-handle", 0);
1139 if (!of_phy_is_fixed_link(child
)) {
1140 dev_err(dev
, "phy-handle or fixed-link "
1141 "properties missing!\n");
1145 /* phy-handle is missing, but fixed-link isn't.
1146 * So it's a fixed link. Default to PHY role.
1148 priv
->fixed_link
[index
] = true;
1150 of_node_put(phy_node
);
1153 priv
->phy_mode
[index
] = phy_mode
;
1159 static int sja1105_parse_dt(struct sja1105_private
*priv
)
1161 struct device
*dev
= &priv
->spidev
->dev
;
1162 struct device_node
*switch_node
= dev
->of_node
;
1163 struct device_node
*ports_node
;
1166 ports_node
= of_get_child_by_name(switch_node
, "ports");
1168 ports_node
= of_get_child_by_name(switch_node
, "ethernet-ports");
1170 dev_err(dev
, "Incorrect bindings: absent \"ports\" node\n");
1174 rc
= sja1105_parse_ports_node(priv
, ports_node
);
1175 of_node_put(ports_node
);
1180 /* Convert link speed from SJA1105 to ethtool encoding */
1181 static int sja1105_port_speed_to_ethtool(struct sja1105_private
*priv
,
1184 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_10MBPS
])
1186 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_100MBPS
])
1188 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
])
1190 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
])
1192 return SPEED_UNKNOWN
;
1195 /* Set link speed in the MAC configuration for a specific port. */
1196 static int sja1105_adjust_port_config(struct sja1105_private
*priv
, int port
,
1199 struct sja1105_mac_config_entry
*mac
;
1200 struct device
*dev
= priv
->ds
->dev
;
1204 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1205 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1206 * We have to *know* what the MAC looks like. For the sake of keeping
1207 * the code common, we'll use the static configuration tables as a
1208 * reasonable approximation for both E/T and P/Q/R/S.
1210 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
1212 switch (speed_mbps
) {
1214 /* PHYLINK called sja1105_mac_config() to inform us about
1215 * the state->interface, but AN has not completed and the
1216 * speed is not yet valid. UM10944.pdf says that setting
1217 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1218 * ok for power consumption in case AN will never complete -
1219 * otherwise PHYLINK should come back with a new update.
1221 speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
];
1224 speed
= priv
->info
->port_speed
[SJA1105_SPEED_10MBPS
];
1227 speed
= priv
->info
->port_speed
[SJA1105_SPEED_100MBPS
];
1230 speed
= priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
];
1233 speed
= priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
];
1236 dev_err(dev
, "Invalid speed %iMbps\n", speed_mbps
);
1240 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1241 * table, since this will be used for the clocking setup, and we no
1242 * longer need to store it in the static config (already told hardware
1243 * we want auto during upload phase).
1244 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1245 * we need to configure the PCS only (if even that).
1247 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_SGMII
)
1248 mac
[port
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
];
1249 else if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_2500BASEX
)
1250 mac
[port
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
];
1252 mac
[port
].speed
= speed
;
1254 /* Write to the dynamic reconfiguration tables */
1255 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
1258 dev_err(dev
, "Failed to write MAC config: %d\n", rc
);
1262 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1263 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1264 * RMII no change of the clock setup is required. Actually, changing
1265 * the clock setup does interrupt the clock signal for a certain time
1266 * which causes trouble for all PHYs relying on this signal.
1268 if (!phy_interface_mode_is_rgmii(priv
->phy_mode
[port
]))
1271 return sja1105_clocking_setup_port(priv
, port
);
1274 /* The SJA1105 MAC programming model is through the static config (the xMII
1275 * Mode table cannot be dynamically reconfigured), and we have to program
1276 * that early (earlier than PHYLINK calls us, anyway).
1277 * So just error out in case the connected PHY attempts to change the initial
1278 * system interface MII protocol from what is defined in the DT, at least for
1281 static bool sja1105_phy_mode_mismatch(struct sja1105_private
*priv
, int port
,
1282 phy_interface_t interface
)
1284 return priv
->phy_mode
[port
] != interface
;
1287 static void sja1105_mac_config(struct dsa_switch
*ds
, int port
,
1289 const struct phylink_link_state
*state
)
1291 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
1292 struct sja1105_private
*priv
= ds
->priv
;
1293 struct dw_xpcs
*xpcs
;
1295 if (sja1105_phy_mode_mismatch(priv
, port
, state
->interface
)) {
1296 dev_err(ds
->dev
, "Changing PHY mode to %s not supported!\n",
1297 phy_modes(state
->interface
));
1301 xpcs
= priv
->xpcs
[port
];
1304 phylink_set_pcs(dp
->pl
, &xpcs
->pcs
);
1307 static void sja1105_mac_link_down(struct dsa_switch
*ds
, int port
,
1309 phy_interface_t interface
)
1311 sja1105_inhibit_tx(ds
->priv
, BIT(port
), true);
1314 static void sja1105_mac_link_up(struct dsa_switch
*ds
, int port
,
1316 phy_interface_t interface
,
1317 struct phy_device
*phydev
,
1318 int speed
, int duplex
,
1319 bool tx_pause
, bool rx_pause
)
1321 struct sja1105_private
*priv
= ds
->priv
;
1323 sja1105_adjust_port_config(priv
, port
, speed
);
1325 sja1105_inhibit_tx(priv
, BIT(port
), false);
1328 static void sja1105_phylink_validate(struct dsa_switch
*ds
, int port
,
1329 unsigned long *supported
,
1330 struct phylink_link_state
*state
)
1332 /* Construct a new mask which exhaustively contains all link features
1333 * supported by the MAC, and then apply that (logical AND) to what will
1334 * be sent to the PHY for "marketing".
1336 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1337 struct sja1105_private
*priv
= ds
->priv
;
1338 struct sja1105_xmii_params_entry
*mii
;
1340 mii
= priv
->static_config
.tables
[BLK_IDX_XMII_PARAMS
].entries
;
1342 /* include/linux/phylink.h says:
1343 * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1344 * expects the MAC driver to return all supported link modes.
1346 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1347 sja1105_phy_mode_mismatch(priv
, port
, state
->interface
)) {
1348 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1352 /* The MAC does not support pause frames, and also doesn't
1353 * support half-duplex traffic modes.
1355 phylink_set(mask
, Autoneg
);
1356 phylink_set(mask
, MII
);
1357 phylink_set(mask
, 10baseT_Full
);
1358 phylink_set(mask
, 100baseT_Full
);
1359 phylink_set(mask
, 100baseT1_Full
);
1360 if (mii
->xmii_mode
[port
] == XMII_MODE_RGMII
||
1361 mii
->xmii_mode
[port
] == XMII_MODE_SGMII
)
1362 phylink_set(mask
, 1000baseT_Full
);
1363 if (priv
->info
->supports_2500basex
[port
]) {
1364 phylink_set(mask
, 2500baseT_Full
);
1365 phylink_set(mask
, 2500baseX_Full
);
1368 bitmap_and(supported
, supported
, mask
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1369 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1370 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1374 sja1105_find_static_fdb_entry(struct sja1105_private
*priv
, int port
,
1375 const struct sja1105_l2_lookup_entry
*requested
)
1377 struct sja1105_l2_lookup_entry
*l2_lookup
;
1378 struct sja1105_table
*table
;
1381 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
1382 l2_lookup
= table
->entries
;
1384 for (i
= 0; i
< table
->entry_count
; i
++)
1385 if (l2_lookup
[i
].macaddr
== requested
->macaddr
&&
1386 l2_lookup
[i
].vlanid
== requested
->vlanid
&&
1387 l2_lookup
[i
].destports
& BIT(port
))
1393 /* We want FDB entries added statically through the bridge command to persist
1394 * across switch resets, which are a common thing during normal SJA1105
1395 * operation. So we have to back them up in the static configuration tables
1396 * and hence apply them on next static config upload... yay!
1399 sja1105_static_fdb_change(struct sja1105_private
*priv
, int port
,
1400 const struct sja1105_l2_lookup_entry
*requested
,
1403 struct sja1105_l2_lookup_entry
*l2_lookup
;
1404 struct sja1105_table
*table
;
1407 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
1409 match
= sja1105_find_static_fdb_entry(priv
, port
, requested
);
1411 /* Can't delete a missing entry. */
1415 /* No match => new entry */
1416 rc
= sja1105_table_resize(table
, table
->entry_count
+ 1);
1420 match
= table
->entry_count
- 1;
1423 /* Assign pointer after the resize (it may be new memory) */
1424 l2_lookup
= table
->entries
;
1427 * If the job was to add this FDB entry, it's already done (mostly
1428 * anyway, since the port forwarding mask may have changed, case in
1429 * which we update it).
1430 * Otherwise we have to delete it.
1433 l2_lookup
[match
] = *requested
;
1437 /* To remove, the strategy is to overwrite the element with
1438 * the last one, and then reduce the array size by 1
1440 l2_lookup
[match
] = l2_lookup
[table
->entry_count
- 1];
1441 return sja1105_table_resize(table
, table
->entry_count
- 1);
1444 /* First-generation switches have a 4-way set associative TCAM that
1445 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1446 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1447 * For the placement of a newly learnt FDB entry, the switch selects the bin
1448 * based on a hash function, and the way within that bin incrementally.
1450 static int sja1105et_fdb_index(int bin
, int way
)
1452 return bin
* SJA1105ET_FDB_BIN_SIZE
+ way
;
1455 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private
*priv
, int bin
,
1456 const u8
*addr
, u16 vid
,
1457 struct sja1105_l2_lookup_entry
*match
,
1462 for (way
= 0; way
< SJA1105ET_FDB_BIN_SIZE
; way
++) {
1463 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1464 int index
= sja1105et_fdb_index(bin
, way
);
1466 /* Skip unused entries, optionally marking them
1467 * into the return value
1469 if (sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1470 index
, &l2_lookup
)) {
1476 if (l2_lookup
.macaddr
== ether_addr_to_u64(addr
) &&
1477 l2_lookup
.vlanid
== vid
) {
1483 /* Return an invalid entry index if not found */
1487 int sja1105et_fdb_add(struct dsa_switch
*ds
, int port
,
1488 const unsigned char *addr
, u16 vid
)
1490 struct sja1105_l2_lookup_entry l2_lookup
= {0}, tmp
;
1491 struct sja1105_private
*priv
= ds
->priv
;
1492 struct device
*dev
= ds
->dev
;
1493 int last_unused
= -1;
1497 bin
= sja1105et_fdb_hash(priv
, addr
, vid
);
1499 way
= sja1105et_is_fdb_entry_in_bin(priv
, bin
, addr
, vid
,
1500 &l2_lookup
, &last_unused
);
1502 /* We have an FDB entry. Is our port in the destination
1503 * mask? If yes, we need to do nothing. If not, we need
1504 * to rewrite the entry by adding this port to it.
1506 if ((l2_lookup
.destports
& BIT(port
)) && l2_lookup
.lockeds
)
1508 l2_lookup
.destports
|= BIT(port
);
1510 int index
= sja1105et_fdb_index(bin
, way
);
1512 /* We don't have an FDB entry. We construct a new one and
1513 * try to find a place for it within the FDB table.
1515 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1516 l2_lookup
.destports
= BIT(port
);
1517 l2_lookup
.vlanid
= vid
;
1519 if (last_unused
>= 0) {
1522 /* Bin is full, need to evict somebody.
1523 * Choose victim at random. If you get these messages
1524 * often, you may need to consider changing the
1525 * distribution function:
1526 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1528 get_random_bytes(&way
, sizeof(u8
));
1529 way
%= SJA1105ET_FDB_BIN_SIZE
;
1530 dev_warn(dev
, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1533 sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1534 index
, NULL
, false);
1537 l2_lookup
.lockeds
= true;
1538 l2_lookup
.index
= sja1105et_fdb_index(bin
, way
);
1540 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1541 l2_lookup
.index
, &l2_lookup
,
1546 /* Invalidate a dynamically learned entry if that exists */
1547 start
= sja1105et_fdb_index(bin
, 0);
1548 end
= sja1105et_fdb_index(bin
, way
);
1550 for (i
= start
; i
< end
; i
++) {
1551 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1558 if (tmp
.macaddr
!= ether_addr_to_u64(addr
) || tmp
.vlanid
!= vid
)
1561 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1569 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, true);
1572 int sja1105et_fdb_del(struct dsa_switch
*ds
, int port
,
1573 const unsigned char *addr
, u16 vid
)
1575 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1576 struct sja1105_private
*priv
= ds
->priv
;
1577 int index
, bin
, way
, rc
;
1580 bin
= sja1105et_fdb_hash(priv
, addr
, vid
);
1581 way
= sja1105et_is_fdb_entry_in_bin(priv
, bin
, addr
, vid
,
1585 index
= sja1105et_fdb_index(bin
, way
);
1587 /* We have an FDB entry. Is our port in the destination mask? If yes,
1588 * we need to remove it. If the resulting port mask becomes empty, we
1589 * need to completely evict the FDB entry.
1590 * Otherwise we just write it back.
1592 l2_lookup
.destports
&= ~BIT(port
);
1594 if (l2_lookup
.destports
)
1599 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1600 index
, &l2_lookup
, keep
);
1604 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, keep
);
1607 int sja1105pqrs_fdb_add(struct dsa_switch
*ds
, int port
,
1608 const unsigned char *addr
, u16 vid
)
1610 struct sja1105_l2_lookup_entry l2_lookup
= {0}, tmp
;
1611 struct sja1105_private
*priv
= ds
->priv
;
1614 /* Search for an existing entry in the FDB table */
1615 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1616 l2_lookup
.vlanid
= vid
;
1617 l2_lookup
.mask_macaddr
= GENMASK_ULL(ETH_ALEN
* 8 - 1, 0);
1618 l2_lookup
.mask_vlanid
= VLAN_VID_MASK
;
1619 l2_lookup
.destports
= BIT(port
);
1623 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1624 SJA1105_SEARCH
, &tmp
);
1625 if (rc
== 0 && tmp
.index
!= SJA1105_MAX_L2_LOOKUP_COUNT
- 1) {
1626 /* Found a static entry and this port is already in the entry's
1627 * port mask => job done
1629 if ((tmp
.destports
& BIT(port
)) && tmp
.lockeds
)
1634 /* l2_lookup.index is populated by the switch in case it
1637 l2_lookup
.destports
|= BIT(port
);
1638 goto skip_finding_an_index
;
1641 /* Not found, so try to find an unused spot in the FDB.
1642 * This is slightly inefficient because the strategy is knock-knock at
1643 * every possible position from 0 to 1023.
1645 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1646 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1651 if (i
== SJA1105_MAX_L2_LOOKUP_COUNT
) {
1652 dev_err(ds
->dev
, "FDB is full, cannot add entry.\n");
1655 l2_lookup
.index
= i
;
1657 skip_finding_an_index
:
1658 l2_lookup
.lockeds
= true;
1660 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1661 l2_lookup
.index
, &l2_lookup
,
1666 /* The switch learns dynamic entries and looks up the FDB left to
1667 * right. It is possible that our addition was concurrent with the
1668 * dynamic learning of the same address, so now that the static entry
1669 * has been installed, we are certain that address learning for this
1670 * particular address has been turned off, so the dynamic entry either
1671 * is in the FDB at an index smaller than the static one, or isn't (it
1672 * can also be at a larger index, but in that case it is inactive
1673 * because the static FDB entry will match first, and the dynamic one
1674 * will eventually age out). Search for a dynamically learned address
1675 * prior to our static one and invalidate it.
1679 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1680 SJA1105_SEARCH
, &tmp
);
1683 "port %d failed to read back entry for %pM vid %d: %pe\n",
1684 port
, addr
, vid
, ERR_PTR(rc
));
1688 if (tmp
.index
< l2_lookup
.index
) {
1689 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1690 tmp
.index
, NULL
, false);
1695 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, true);
1698 int sja1105pqrs_fdb_del(struct dsa_switch
*ds
, int port
,
1699 const unsigned char *addr
, u16 vid
)
1701 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1702 struct sja1105_private
*priv
= ds
->priv
;
1706 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1707 l2_lookup
.vlanid
= vid
;
1708 l2_lookup
.mask_macaddr
= GENMASK_ULL(ETH_ALEN
* 8 - 1, 0);
1709 l2_lookup
.mask_vlanid
= VLAN_VID_MASK
;
1710 l2_lookup
.destports
= BIT(port
);
1712 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1713 SJA1105_SEARCH
, &l2_lookup
);
1717 l2_lookup
.destports
&= ~BIT(port
);
1719 /* Decide whether we remove just this port from the FDB entry,
1720 * or if we remove it completely.
1722 if (l2_lookup
.destports
)
1727 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1728 l2_lookup
.index
, &l2_lookup
, keep
);
1732 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, keep
);
1735 static int sja1105_fdb_add(struct dsa_switch
*ds
, int port
,
1736 const unsigned char *addr
, u16 vid
)
1738 struct sja1105_private
*priv
= ds
->priv
;
1740 return priv
->info
->fdb_add_cmd(ds
, port
, addr
, vid
);
1743 static int sja1105_fdb_del(struct dsa_switch
*ds
, int port
,
1744 const unsigned char *addr
, u16 vid
)
1746 struct sja1105_private
*priv
= ds
->priv
;
1748 return priv
->info
->fdb_del_cmd(ds
, port
, addr
, vid
);
1751 static int sja1105_fdb_dump(struct dsa_switch
*ds
, int port
,
1752 dsa_fdb_dump_cb_t
*cb
, void *data
)
1754 struct sja1105_private
*priv
= ds
->priv
;
1755 struct device
*dev
= ds
->dev
;
1758 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1759 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1760 u8 macaddr
[ETH_ALEN
];
1763 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1765 /* No fdb entry at i, not an issue */
1769 dev_err(dev
, "Failed to dump FDB: %d\n", rc
);
1773 /* FDB dump callback is per port. This means we have to
1774 * disregard a valid entry if it's not for this port, even if
1775 * only to revisit it later. This is inefficient because the
1776 * 1024-sized FDB table needs to be traversed 4 times through
1777 * SPI during a 'bridge fdb show' command.
1779 if (!(l2_lookup
.destports
& BIT(port
)))
1782 /* We need to hide the FDB entry for unknown multicast */
1783 if (l2_lookup
.macaddr
== SJA1105_UNKNOWN_MULTICAST
&&
1784 l2_lookup
.mask_macaddr
== SJA1105_UNKNOWN_MULTICAST
)
1787 u64_to_ether_addr(l2_lookup
.macaddr
, macaddr
);
1789 /* We need to hide the dsa_8021q VLANs from the user. */
1790 if (!priv
->vlan_aware
)
1791 l2_lookup
.vlanid
= 0;
1792 cb(macaddr
, l2_lookup
.vlanid
, l2_lookup
.lockeds
, data
);
1797 static void sja1105_fast_age(struct dsa_switch
*ds
, int port
)
1799 struct sja1105_private
*priv
= ds
->priv
;
1802 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1803 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1804 u8 macaddr
[ETH_ALEN
];
1807 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1809 /* No fdb entry at i, not an issue */
1813 dev_err(ds
->dev
, "Failed to read FDB: %pe\n",
1818 if (!(l2_lookup
.destports
& BIT(port
)))
1821 /* Don't delete static FDB entries */
1822 if (l2_lookup
.lockeds
)
1825 u64_to_ether_addr(l2_lookup
.macaddr
, macaddr
);
1827 rc
= sja1105_fdb_del(ds
, port
, macaddr
, l2_lookup
.vlanid
);
1830 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1831 macaddr
, l2_lookup
.vlanid
, ERR_PTR(rc
));
1837 static int sja1105_mdb_add(struct dsa_switch
*ds
, int port
,
1838 const struct switchdev_obj_port_mdb
*mdb
)
1840 return sja1105_fdb_add(ds
, port
, mdb
->addr
, mdb
->vid
);
1843 static int sja1105_mdb_del(struct dsa_switch
*ds
, int port
,
1844 const struct switchdev_obj_port_mdb
*mdb
)
1846 return sja1105_fdb_del(ds
, port
, mdb
->addr
, mdb
->vid
);
1849 /* Common function for unicast and broadcast flood configuration.
1850 * Flooding is configured between each {ingress, egress} port pair, and since
1851 * the bridge's semantics are those of "egress flooding", it means we must
1852 * enable flooding towards this port from all ingress ports that are in the
1853 * same forwarding domain.
1855 static int sja1105_manage_flood_domains(struct sja1105_private
*priv
)
1857 struct sja1105_l2_forwarding_entry
*l2_fwd
;
1858 struct dsa_switch
*ds
= priv
->ds
;
1861 l2_fwd
= priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
].entries
;
1863 for (from
= 0; from
< ds
->num_ports
; from
++) {
1864 u64 fl_domain
= 0, bc_domain
= 0;
1866 for (to
= 0; to
< priv
->ds
->num_ports
; to
++) {
1867 if (!sja1105_can_forward(l2_fwd
, from
, to
))
1870 if (priv
->ucast_egress_floods
& BIT(to
))
1871 fl_domain
|= BIT(to
);
1872 if (priv
->bcast_egress_floods
& BIT(to
))
1873 bc_domain
|= BIT(to
);
1876 /* Nothing changed, nothing to do */
1877 if (l2_fwd
[from
].fl_domain
== fl_domain
&&
1878 l2_fwd
[from
].bc_domain
== bc_domain
)
1881 l2_fwd
[from
].fl_domain
= fl_domain
;
1882 l2_fwd
[from
].bc_domain
= bc_domain
;
1884 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1885 from
, &l2_fwd
[from
], true);
1893 static int sja1105_bridge_member(struct dsa_switch
*ds
, int port
,
1894 struct net_device
*br
, bool member
)
1896 struct sja1105_l2_forwarding_entry
*l2_fwd
;
1897 struct sja1105_private
*priv
= ds
->priv
;
1900 l2_fwd
= priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
].entries
;
1902 for (i
= 0; i
< ds
->num_ports
; i
++) {
1903 /* Add this port to the forwarding matrix of the
1904 * other ports in the same bridge, and viceversa.
1906 if (!dsa_is_user_port(ds
, i
))
1908 /* For the ports already under the bridge, only one thing needs
1909 * to be done, and that is to add this port to their
1910 * reachability domain. So we can perform the SPI write for
1911 * them immediately. However, for this port itself (the one
1912 * that is new to the bridge), we need to add all other ports
1913 * to its reachability domain. So we do that incrementally in
1914 * this loop, and perform the SPI write only at the end, once
1915 * the domain contains all other bridge ports.
1919 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1921 sja1105_port_allow_traffic(l2_fwd
, i
, port
, member
);
1922 sja1105_port_allow_traffic(l2_fwd
, port
, i
, member
);
1924 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1925 i
, &l2_fwd
[i
], true);
1930 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1931 port
, &l2_fwd
[port
], true);
1935 rc
= sja1105_commit_pvid(ds
, port
);
1939 return sja1105_manage_flood_domains(priv
);
1942 static void sja1105_bridge_stp_state_set(struct dsa_switch
*ds
, int port
,
1945 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
1946 struct sja1105_private
*priv
= ds
->priv
;
1947 struct sja1105_mac_config_entry
*mac
;
1949 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
1952 case BR_STATE_DISABLED
:
1953 case BR_STATE_BLOCKING
:
1954 /* From UM10944 description of DRPDTAG (why put this there?):
1955 * "Management traffic flows to the port regardless of the state
1956 * of the INGRESS flag". So BPDUs are still be allowed to pass.
1957 * At the moment no difference between DISABLED and BLOCKING.
1959 mac
[port
].ingress
= false;
1960 mac
[port
].egress
= false;
1961 mac
[port
].dyn_learn
= false;
1963 case BR_STATE_LISTENING
:
1964 mac
[port
].ingress
= true;
1965 mac
[port
].egress
= false;
1966 mac
[port
].dyn_learn
= false;
1968 case BR_STATE_LEARNING
:
1969 mac
[port
].ingress
= true;
1970 mac
[port
].egress
= false;
1971 mac
[port
].dyn_learn
= dp
->learning
;
1973 case BR_STATE_FORWARDING
:
1974 mac
[port
].ingress
= true;
1975 mac
[port
].egress
= true;
1976 mac
[port
].dyn_learn
= dp
->learning
;
1979 dev_err(ds
->dev
, "invalid STP state: %d\n", state
);
1983 sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
1987 static int sja1105_bridge_join(struct dsa_switch
*ds
, int port
,
1988 struct net_device
*br
)
1990 return sja1105_bridge_member(ds
, port
, br
, true);
1993 static void sja1105_bridge_leave(struct dsa_switch
*ds
, int port
,
1994 struct net_device
*br
)
1996 sja1105_bridge_member(ds
, port
, br
, false);
1999 #define BYTES_PER_KBIT (1000LL / 8)
2001 static int sja1105_find_unused_cbs_shaper(struct sja1105_private
*priv
)
2005 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++)
2006 if (!priv
->cbs
[i
].idle_slope
&& !priv
->cbs
[i
].send_slope
)
2012 static int sja1105_delete_cbs_shaper(struct sja1105_private
*priv
, int port
,
2017 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++) {
2018 struct sja1105_cbs_entry
*cbs
= &priv
->cbs
[i
];
2020 if (cbs
->port
== port
&& cbs
->prio
== prio
) {
2021 memset(cbs
, 0, sizeof(*cbs
));
2022 return sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
,
2030 static int sja1105_setup_tc_cbs(struct dsa_switch
*ds
, int port
,
2031 struct tc_cbs_qopt_offload
*offload
)
2033 struct sja1105_private
*priv
= ds
->priv
;
2034 struct sja1105_cbs_entry
*cbs
;
2037 if (!offload
->enable
)
2038 return sja1105_delete_cbs_shaper(priv
, port
, offload
->queue
);
2040 index
= sja1105_find_unused_cbs_shaper(priv
);
2044 cbs
= &priv
->cbs
[index
];
2046 cbs
->prio
= offload
->queue
;
2047 /* locredit and sendslope are negative by definition. In hardware,
2048 * positive values must be provided, and the negative sign is implicit.
2050 cbs
->credit_hi
= offload
->hicredit
;
2051 cbs
->credit_lo
= abs(offload
->locredit
);
2052 /* User space is in kbits/sec, hardware in bytes/sec */
2053 cbs
->idle_slope
= offload
->idleslope
* BYTES_PER_KBIT
;
2054 cbs
->send_slope
= abs(offload
->sendslope
* BYTES_PER_KBIT
);
2055 /* Convert the negative values from 64-bit 2's complement
2056 * to 32-bit 2's complement (for the case of 0x80000000 whose
2057 * negative is still negative).
2059 cbs
->credit_lo
&= GENMASK_ULL(31, 0);
2060 cbs
->send_slope
&= GENMASK_ULL(31, 0);
2062 return sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
, index
, cbs
,
2066 static int sja1105_reload_cbs(struct sja1105_private
*priv
)
2070 /* The credit based shapers are only allocated if
2071 * CONFIG_NET_SCH_CBS is enabled.
2076 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++) {
2077 struct sja1105_cbs_entry
*cbs
= &priv
->cbs
[i
];
2079 if (!cbs
->idle_slope
&& !cbs
->send_slope
)
2082 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
, i
, cbs
,
2091 static const char * const sja1105_reset_reasons
[] = {
2092 [SJA1105_VLAN_FILTERING
] = "VLAN filtering",
2093 [SJA1105_RX_HWTSTAMPING
] = "RX timestamping",
2094 [SJA1105_AGEING_TIME
] = "Ageing time",
2095 [SJA1105_SCHEDULING
] = "Time-aware scheduling",
2096 [SJA1105_BEST_EFFORT_POLICING
] = "Best-effort policing",
2097 [SJA1105_VIRTUAL_LINKS
] = "Virtual links",
2100 /* For situations where we need to change a setting at runtime that is only
2101 * available through the static configuration, resetting the switch in order
2102 * to upload the new static config is unavoidable. Back up the settings we
2103 * modify at runtime (currently only MAC) and restore them after uploading,
2104 * such that this operation is relatively seamless.
2106 int sja1105_static_config_reload(struct sja1105_private
*priv
,
2107 enum sja1105_reset_reason reason
)
2109 struct ptp_system_timestamp ptp_sts_before
;
2110 struct ptp_system_timestamp ptp_sts_after
;
2111 int speed_mbps
[SJA1105_MAX_NUM_PORTS
];
2112 u16 bmcr
[SJA1105_MAX_NUM_PORTS
] = {0};
2113 struct sja1105_mac_config_entry
*mac
;
2114 struct dsa_switch
*ds
= priv
->ds
;
2120 mutex_lock(&priv
->mgmt_lock
);
2122 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2124 /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2125 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2126 * switch wants to see in the static config in order to allow us to
2127 * change it through the dynamic interface later.
2129 for (i
= 0; i
< ds
->num_ports
; i
++) {
2130 u32 reg_addr
= mdiobus_c45_addr(MDIO_MMD_VEND2
, MDIO_CTRL1
);
2132 speed_mbps
[i
] = sja1105_port_speed_to_ethtool(priv
,
2134 mac
[i
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
];
2137 bmcr
[i
] = mdiobus_read(priv
->mdio_pcs
, i
, reg_addr
);
2140 /* No PTP operations can run right now */
2141 mutex_lock(&priv
->ptp_data
.lock
);
2143 rc
= __sja1105_ptp_gettimex(ds
, &now
, &ptp_sts_before
);
2145 mutex_unlock(&priv
->ptp_data
.lock
);
2149 /* Reset switch and send updated static configuration */
2150 rc
= sja1105_static_config_upload(priv
);
2152 mutex_unlock(&priv
->ptp_data
.lock
);
2156 rc
= __sja1105_ptp_settime(ds
, 0, &ptp_sts_after
);
2158 mutex_unlock(&priv
->ptp_data
.lock
);
2162 t1
= timespec64_to_ns(&ptp_sts_before
.pre_ts
);
2163 t2
= timespec64_to_ns(&ptp_sts_before
.post_ts
);
2164 t3
= timespec64_to_ns(&ptp_sts_after
.pre_ts
);
2165 t4
= timespec64_to_ns(&ptp_sts_after
.post_ts
);
2166 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2167 t12
= t1
+ (t2
- t1
) / 2;
2168 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2169 t34
= t3
+ (t4
- t3
) / 2;
2170 /* Advance PTPCLKVAL by the time it took since its readout */
2173 __sja1105_ptp_adjtime(ds
, now
);
2175 mutex_unlock(&priv
->ptp_data
.lock
);
2177 dev_info(priv
->ds
->dev
,
2178 "Reset switch and programmed static config. Reason: %s\n",
2179 sja1105_reset_reasons
[reason
]);
2181 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2182 * For these interfaces there is no dynamic configuration
2183 * needed, since PLLs have same settings at all speeds.
2185 if (priv
->info
->clocking_setup
) {
2186 rc
= priv
->info
->clocking_setup(priv
);
2191 for (i
= 0; i
< ds
->num_ports
; i
++) {
2192 struct dw_xpcs
*xpcs
= priv
->xpcs
[i
];
2195 rc
= sja1105_adjust_port_config(priv
, i
, speed_mbps
[i
]);
2202 if (bmcr
[i
] & BMCR_ANENABLE
)
2203 mode
= MLO_AN_INBAND
;
2204 else if (priv
->fixed_link
[i
])
2205 mode
= MLO_AN_FIXED
;
2209 rc
= xpcs_do_config(xpcs
, priv
->phy_mode
[i
], mode
);
2213 if (!phylink_autoneg_inband(mode
)) {
2214 int speed
= SPEED_UNKNOWN
;
2216 if (priv
->phy_mode
[i
] == PHY_INTERFACE_MODE_2500BASEX
)
2218 else if (bmcr
[i
] & BMCR_SPEED1000
)
2220 else if (bmcr
[i
] & BMCR_SPEED100
)
2225 xpcs_link_up(&xpcs
->pcs
, mode
, priv
->phy_mode
[i
],
2226 speed
, DUPLEX_FULL
);
2230 rc
= sja1105_reload_cbs(priv
);
2234 mutex_unlock(&priv
->mgmt_lock
);
2239 static enum dsa_tag_protocol
2240 sja1105_get_tag_protocol(struct dsa_switch
*ds
, int port
,
2241 enum dsa_tag_protocol mp
)
2243 struct sja1105_private
*priv
= ds
->priv
;
2245 return priv
->info
->tag_proto
;
2248 /* The TPID setting belongs to the General Parameters table,
2249 * which can only be partially reconfigured at runtime (and not the TPID).
2250 * So a switch reset is required.
2252 int sja1105_vlan_filtering(struct dsa_switch
*ds
, int port
, bool enabled
,
2253 struct netlink_ext_ack
*extack
)
2255 struct sja1105_l2_lookup_params_entry
*l2_lookup_params
;
2256 struct sja1105_general_params_entry
*general_params
;
2257 struct sja1105_private
*priv
= ds
->priv
;
2258 struct sja1105_table
*table
;
2259 struct sja1105_rule
*rule
;
2263 list_for_each_entry(rule
, &priv
->flow_block
.rules
, list
) {
2264 if (rule
->type
== SJA1105_RULE_VL
) {
2265 NL_SET_ERR_MSG_MOD(extack
,
2266 "Cannot change VLAN filtering with active VL rules");
2272 /* Enable VLAN filtering. */
2274 tpid2
= ETH_P_8021AD
;
2276 /* Disable VLAN filtering. */
2277 tpid
= ETH_P_SJA1105
;
2278 tpid2
= ETH_P_SJA1105
;
2281 for (port
= 0; port
< ds
->num_ports
; port
++) {
2282 struct sja1105_port
*sp
= &priv
->ports
[port
];
2285 sp
->xmit_tpid
= priv
->info
->qinq_tpid
;
2287 sp
->xmit_tpid
= ETH_P_SJA1105
;
2290 if (priv
->vlan_aware
== enabled
)
2293 priv
->vlan_aware
= enabled
;
2295 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
2296 general_params
= table
->entries
;
2297 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2298 general_params
->tpid
= tpid
;
2299 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2300 general_params
->tpid2
= tpid2
;
2301 /* When VLAN filtering is on, we need to at least be able to
2302 * decode management traffic through the "backup plan".
2304 general_params
->incl_srcpt1
= enabled
;
2305 general_params
->incl_srcpt0
= enabled
;
2307 /* VLAN filtering => independent VLAN learning.
2308 * No VLAN filtering (or best effort) => shared VLAN learning.
2310 * In shared VLAN learning mode, untagged traffic still gets
2311 * pvid-tagged, and the FDB table gets populated with entries
2312 * containing the "real" (pvid or from VLAN tag) VLAN ID.
2313 * However the switch performs a masked L2 lookup in the FDB,
2314 * effectively only looking up a frame's DMAC (and not VID) for the
2315 * forwarding decision.
2317 * This is extremely convenient for us, because in modes with
2318 * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2319 * each front panel port. This is good for identification but breaks
2320 * learning badly - the VID of the learnt FDB entry is unique, aka
2321 * no frames coming from any other port are going to have it. So
2322 * for forwarding purposes, this is as though learning was broken
2323 * (all frames get flooded).
2325 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
2326 l2_lookup_params
= table
->entries
;
2327 l2_lookup_params
->shared_learn
= !priv
->vlan_aware
;
2329 for (port
= 0; port
< ds
->num_ports
; port
++) {
2330 if (dsa_is_unused_port(ds
, port
))
2333 rc
= sja1105_commit_pvid(ds
, port
);
2338 rc
= sja1105_static_config_reload(priv
, SJA1105_VLAN_FILTERING
);
2340 NL_SET_ERR_MSG_MOD(extack
, "Failed to change VLAN Ethertype");
2345 static int sja1105_vlan_add(struct sja1105_private
*priv
, int port
, u16 vid
,
2348 struct sja1105_vlan_lookup_entry
*vlan
;
2349 struct sja1105_table
*table
;
2352 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
2354 match
= sja1105_is_vlan_configured(priv
, vid
);
2356 rc
= sja1105_table_resize(table
, table
->entry_count
+ 1);
2359 match
= table
->entry_count
- 1;
2362 /* Assign pointer after the resize (it's new memory) */
2363 vlan
= table
->entries
;
2365 vlan
[match
].type_entry
= SJA1110_VLAN_D_TAG
;
2366 vlan
[match
].vlanid
= vid
;
2367 vlan
[match
].vlan_bc
|= BIT(port
);
2368 vlan
[match
].vmemb_port
|= BIT(port
);
2369 if (flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
2370 vlan
[match
].tag_port
&= ~BIT(port
);
2372 vlan
[match
].tag_port
|= BIT(port
);
2374 return sja1105_dynamic_config_write(priv
, BLK_IDX_VLAN_LOOKUP
, vid
,
2375 &vlan
[match
], true);
2378 static int sja1105_vlan_del(struct sja1105_private
*priv
, int port
, u16 vid
)
2380 struct sja1105_vlan_lookup_entry
*vlan
;
2381 struct sja1105_table
*table
;
2385 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
2387 match
= sja1105_is_vlan_configured(priv
, vid
);
2388 /* Can't delete a missing entry. */
2392 /* Assign pointer after the resize (it's new memory) */
2393 vlan
= table
->entries
;
2395 vlan
[match
].vlanid
= vid
;
2396 vlan
[match
].vlan_bc
&= ~BIT(port
);
2397 vlan
[match
].vmemb_port
&= ~BIT(port
);
2398 /* Also unset tag_port, just so we don't have a confusing bitmap
2399 * (no practical purpose).
2401 vlan
[match
].tag_port
&= ~BIT(port
);
2403 /* If there's no port left as member of this VLAN,
2404 * it's time for it to go.
2406 if (!vlan
[match
].vmemb_port
)
2409 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_VLAN_LOOKUP
, vid
,
2410 &vlan
[match
], keep
);
2415 return sja1105_table_delete_entry(table
, match
);
2420 static int sja1105_bridge_vlan_add(struct dsa_switch
*ds
, int port
,
2421 const struct switchdev_obj_port_vlan
*vlan
,
2422 struct netlink_ext_ack
*extack
)
2424 struct sja1105_private
*priv
= ds
->priv
;
2425 u16 flags
= vlan
->flags
;
2428 /* Be sure to deny alterations to the configuration done by tag_8021q.
2430 if (vid_is_dsa_8021q(vlan
->vid
)) {
2431 NL_SET_ERR_MSG_MOD(extack
,
2432 "Range 1024-3071 reserved for dsa_8021q operation");
2436 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2437 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
2440 rc
= sja1105_vlan_add(priv
, port
, vlan
->vid
, flags
);
2444 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
)
2445 priv
->bridge_pvid
[port
] = vlan
->vid
;
2447 return sja1105_commit_pvid(ds
, port
);
2450 static int sja1105_bridge_vlan_del(struct dsa_switch
*ds
, int port
,
2451 const struct switchdev_obj_port_vlan
*vlan
)
2453 struct sja1105_private
*priv
= ds
->priv
;
2456 rc
= sja1105_vlan_del(priv
, port
, vlan
->vid
);
2460 /* In case the pvid was deleted, make sure that untagged packets will
2463 return sja1105_commit_pvid(ds
, port
);
2466 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch
*ds
, int port
, u16 vid
,
2469 struct sja1105_private
*priv
= ds
->priv
;
2472 rc
= sja1105_vlan_add(priv
, port
, vid
, flags
);
2476 if (flags
& BRIDGE_VLAN_INFO_PVID
)
2477 priv
->tag_8021q_pvid
[port
] = vid
;
2479 return sja1105_commit_pvid(ds
, port
);
2482 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch
*ds
, int port
, u16 vid
)
2484 struct sja1105_private
*priv
= ds
->priv
;
2486 return sja1105_vlan_del(priv
, port
, vid
);
2489 static int sja1105_prechangeupper(struct dsa_switch
*ds
, int port
,
2490 struct netdev_notifier_changeupper_info
*info
)
2492 struct netlink_ext_ack
*extack
= info
->info
.extack
;
2493 struct net_device
*upper
= info
->upper_dev
;
2494 struct dsa_switch_tree
*dst
= ds
->dst
;
2495 struct dsa_port
*dp
;
2497 if (is_vlan_dev(upper
)) {
2498 NL_SET_ERR_MSG_MOD(extack
, "8021q uppers are not supported");
2502 if (netif_is_bridge_master(upper
)) {
2503 list_for_each_entry(dp
, &dst
->ports
, list
) {
2504 if (dp
->bridge_dev
&& dp
->bridge_dev
!= upper
&&
2505 br_vlan_enabled(dp
->bridge_dev
)) {
2506 NL_SET_ERR_MSG_MOD(extack
,
2507 "Only one VLAN-aware bridge is supported");
2516 /* The programming model for the SJA1105 switch is "all-at-once" via static
2517 * configuration tables. Some of these can be dynamically modified at runtime,
2518 * but not the xMII mode parameters table.
2519 * Furthermode, some PHYs may not have crystals for generating their clocks
2520 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
2521 * ref_clk pin. So port clocking needs to be initialized early, before
2522 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
2523 * Setting correct PHY link speed does not matter now.
2524 * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
2525 * bindings are not yet parsed by DSA core. We need to parse early so that we
2526 * can populate the xMII mode parameters table.
2528 static int sja1105_setup(struct dsa_switch
*ds
)
2530 struct sja1105_private
*priv
= ds
->priv
;
2533 rc
= sja1105_parse_dt(priv
);
2535 dev_err(ds
->dev
, "Failed to parse DT: %d\n", rc
);
2539 /* Error out early if internal delays are required through DT
2540 * and we can't apply them.
2542 rc
= sja1105_parse_rgmii_delays(priv
);
2544 dev_err(ds
->dev
, "RGMII delay not supported\n");
2548 rc
= sja1105_ptp_clock_register(ds
);
2550 dev_err(ds
->dev
, "Failed to register PTP clock: %d\n", rc
);
2554 rc
= sja1105_mdiobus_register(ds
);
2556 dev_err(ds
->dev
, "Failed to register MDIO bus: %pe\n",
2558 goto out_ptp_clock_unregister
;
2561 if (priv
->info
->disable_microcontroller
) {
2562 rc
= priv
->info
->disable_microcontroller(priv
);
2565 "Failed to disable microcontroller: %pe\n",
2567 goto out_mdiobus_unregister
;
2571 /* Create and send configuration down to device */
2572 rc
= sja1105_static_config_load(priv
);
2574 dev_err(ds
->dev
, "Failed to load static config: %d\n", rc
);
2575 goto out_mdiobus_unregister
;
2578 /* Configure the CGU (PHY link modes and speeds) */
2579 if (priv
->info
->clocking_setup
) {
2580 rc
= priv
->info
->clocking_setup(priv
);
2583 "Failed to configure MII clocking: %pe\n",
2585 goto out_static_config_free
;
2589 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
2590 * The only thing we can do to disable it is lie about what the 802.1Q
2592 * So it will still try to apply VLAN filtering, but all ingress
2593 * traffic (except frames received with EtherType of ETH_P_SJA1105)
2594 * will be internally tagged with a distorted VLAN header where the
2595 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
2597 ds
->vlan_filtering_is_global
= true;
2598 ds
->untag_bridge_pvid
= true;
2599 /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
2600 ds
->num_fwd_offloading_bridges
= 7;
2602 /* Advertise the 8 egress queues */
2603 ds
->num_tx_queues
= SJA1105_NUM_TC
;
2605 ds
->mtu_enforcement_ingress
= true;
2606 ds
->assisted_learning_on_cpu_port
= true;
2608 rc
= sja1105_devlink_setup(ds
);
2610 goto out_static_config_free
;
2613 rc
= dsa_tag_8021q_register(ds
, htons(ETH_P_8021Q
));
2616 goto out_devlink_teardown
;
2620 out_devlink_teardown
:
2621 sja1105_devlink_teardown(ds
);
2622 out_mdiobus_unregister
:
2623 sja1105_mdiobus_unregister(ds
);
2624 out_ptp_clock_unregister
:
2625 sja1105_ptp_clock_unregister(ds
);
2626 out_static_config_free
:
2627 sja1105_static_config_free(&priv
->static_config
);
2632 static void sja1105_teardown(struct dsa_switch
*ds
)
2634 struct sja1105_private
*priv
= ds
->priv
;
2638 dsa_tag_8021q_unregister(ds
);
2641 for (port
= 0; port
< ds
->num_ports
; port
++) {
2642 struct sja1105_port
*sp
= &priv
->ports
[port
];
2644 if (!dsa_is_user_port(ds
, port
))
2647 if (sp
->xmit_worker
)
2648 kthread_destroy_worker(sp
->xmit_worker
);
2651 sja1105_devlink_teardown(ds
);
2652 sja1105_flower_teardown(ds
);
2653 sja1105_tas_teardown(ds
);
2654 sja1105_ptp_clock_unregister(ds
);
2655 sja1105_static_config_free(&priv
->static_config
);
2658 static void sja1105_port_disable(struct dsa_switch
*ds
, int port
)
2660 struct sja1105_private
*priv
= ds
->priv
;
2661 struct sja1105_port
*sp
= &priv
->ports
[port
];
2663 if (!dsa_is_user_port(ds
, port
))
2666 kthread_cancel_work_sync(&sp
->xmit_work
);
2667 skb_queue_purge(&sp
->xmit_queue
);
2670 static int sja1105_mgmt_xmit(struct dsa_switch
*ds
, int port
, int slot
,
2671 struct sk_buff
*skb
, bool takets
)
2673 struct sja1105_mgmt_entry mgmt_route
= {0};
2674 struct sja1105_private
*priv
= ds
->priv
;
2681 mgmt_route
.macaddr
= ether_addr_to_u64(hdr
->h_dest
);
2682 mgmt_route
.destports
= BIT(port
);
2683 mgmt_route
.enfport
= 1;
2684 mgmt_route
.tsreg
= 0;
2685 mgmt_route
.takets
= takets
;
2687 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_MGMT_ROUTE
,
2688 slot
, &mgmt_route
, true);
2694 /* Transfer skb to the host port. */
2695 dsa_enqueue_skb(skb
, dsa_to_port(ds
, port
)->slave
);
2697 /* Wait until the switch has processed the frame */
2699 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_MGMT_ROUTE
,
2702 dev_err_ratelimited(priv
->ds
->dev
,
2703 "failed to poll for mgmt route\n");
2707 /* UM10944: The ENFPORT flag of the respective entry is
2708 * cleared when a match is found. The host can use this
2709 * flag as an acknowledgment.
2712 } while (mgmt_route
.enfport
&& --timeout
);
2715 /* Clean up the management route so that a follow-up
2716 * frame may not match on it by mistake.
2717 * This is only hardware supported on P/Q/R/S - on E/T it is
2718 * a no-op and we are silently discarding the -EOPNOTSUPP.
2720 sja1105_dynamic_config_write(priv
, BLK_IDX_MGMT_ROUTE
,
2721 slot
, &mgmt_route
, false);
2722 dev_err_ratelimited(priv
->ds
->dev
, "xmit timed out\n");
2725 return NETDEV_TX_OK
;
2728 #define work_to_port(work) \
2729 container_of((work), struct sja1105_port, xmit_work)
2730 #define tagger_to_sja1105(t) \
2731 container_of((t), struct sja1105_private, tagger_data)
2733 /* Deferred work is unfortunately necessary because setting up the management
2734 * route cannot be done from atomit context (SPI transfer takes a sleepable
2737 static void sja1105_port_deferred_xmit(struct kthread_work
*work
)
2739 struct sja1105_port
*sp
= work_to_port(work
);
2740 struct sja1105_tagger_data
*tagger_data
= sp
->data
;
2741 struct sja1105_private
*priv
= tagger_to_sja1105(tagger_data
);
2742 int port
= sp
- priv
->ports
;
2743 struct sk_buff
*skb
;
2745 while ((skb
= skb_dequeue(&sp
->xmit_queue
)) != NULL
) {
2746 struct sk_buff
*clone
= SJA1105_SKB_CB(skb
)->clone
;
2748 mutex_lock(&priv
->mgmt_lock
);
2750 sja1105_mgmt_xmit(priv
->ds
, port
, 0, skb
, !!clone
);
2752 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2754 sja1105_ptp_txtstamp_skb(priv
->ds
, port
, clone
);
2756 mutex_unlock(&priv
->mgmt_lock
);
2760 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2761 * which cannot be reconfigured at runtime. So a switch reset is required.
2763 static int sja1105_set_ageing_time(struct dsa_switch
*ds
,
2764 unsigned int ageing_time
)
2766 struct sja1105_l2_lookup_params_entry
*l2_lookup_params
;
2767 struct sja1105_private
*priv
= ds
->priv
;
2768 struct sja1105_table
*table
;
2769 unsigned int maxage
;
2771 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
2772 l2_lookup_params
= table
->entries
;
2774 maxage
= SJA1105_AGEING_TIME_MS(ageing_time
);
2776 if (l2_lookup_params
->maxage
== maxage
)
2779 l2_lookup_params
->maxage
= maxage
;
2781 return sja1105_static_config_reload(priv
, SJA1105_AGEING_TIME
);
2784 static int sja1105_change_mtu(struct dsa_switch
*ds
, int port
, int new_mtu
)
2786 struct sja1105_l2_policing_entry
*policing
;
2787 struct sja1105_private
*priv
= ds
->priv
;
2789 new_mtu
+= VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
2791 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
2792 new_mtu
+= VLAN_HLEN
;
2794 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2796 if (policing
[port
].maxlen
== new_mtu
)
2799 policing
[port
].maxlen
= new_mtu
;
2801 return sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2804 static int sja1105_get_max_mtu(struct dsa_switch
*ds
, int port
)
2806 return 2043 - VLAN_ETH_HLEN
- ETH_FCS_LEN
;
2809 static int sja1105_port_setup_tc(struct dsa_switch
*ds
, int port
,
2810 enum tc_setup_type type
,
2814 case TC_SETUP_QDISC_TAPRIO
:
2815 return sja1105_setup_tc_taprio(ds
, port
, type_data
);
2816 case TC_SETUP_QDISC_CBS
:
2817 return sja1105_setup_tc_cbs(ds
, port
, type_data
);
2823 /* We have a single mirror (@to) port, but can configure ingress and egress
2824 * mirroring on all other (@from) ports.
2825 * We need to allow mirroring rules only as long as the @to port is always the
2826 * same, and we need to unset the @to port from mirr_port only when there is no
2827 * mirroring rule that references it.
2829 static int sja1105_mirror_apply(struct sja1105_private
*priv
, int from
, int to
,
2830 bool ingress
, bool enabled
)
2832 struct sja1105_general_params_entry
*general_params
;
2833 struct sja1105_mac_config_entry
*mac
;
2834 struct dsa_switch
*ds
= priv
->ds
;
2835 struct sja1105_table
*table
;
2836 bool already_enabled
;
2840 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
2841 general_params
= table
->entries
;
2843 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2845 already_enabled
= (general_params
->mirr_port
!= ds
->num_ports
);
2846 if (already_enabled
&& enabled
&& general_params
->mirr_port
!= to
) {
2847 dev_err(priv
->ds
->dev
,
2848 "Delete mirroring rules towards port %llu first\n",
2849 general_params
->mirr_port
);
2858 /* Anybody still referencing mirr_port? */
2859 for (port
= 0; port
< ds
->num_ports
; port
++) {
2860 if (mac
[port
].ing_mirr
|| mac
[port
].egr_mirr
) {
2865 /* Unset already_enabled for next time */
2867 new_mirr_port
= ds
->num_ports
;
2869 if (new_mirr_port
!= general_params
->mirr_port
) {
2870 general_params
->mirr_port
= new_mirr_port
;
2872 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_GENERAL_PARAMS
,
2873 0, general_params
, true);
2879 mac
[from
].ing_mirr
= enabled
;
2881 mac
[from
].egr_mirr
= enabled
;
2883 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, from
,
2887 static int sja1105_mirror_add(struct dsa_switch
*ds
, int port
,
2888 struct dsa_mall_mirror_tc_entry
*mirror
,
2891 return sja1105_mirror_apply(ds
->priv
, port
, mirror
->to_local_port
,
2895 static void sja1105_mirror_del(struct dsa_switch
*ds
, int port
,
2896 struct dsa_mall_mirror_tc_entry
*mirror
)
2898 sja1105_mirror_apply(ds
->priv
, port
, mirror
->to_local_port
,
2899 mirror
->ingress
, false);
2902 static int sja1105_port_policer_add(struct dsa_switch
*ds
, int port
,
2903 struct dsa_mall_policer_tc_entry
*policer
)
2905 struct sja1105_l2_policing_entry
*policing
;
2906 struct sja1105_private
*priv
= ds
->priv
;
2908 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2910 /* In hardware, every 8 microseconds the credit level is incremented by
2911 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2914 policing
[port
].rate
= div_u64(512 * policer
->rate_bytes_per_sec
,
2916 policing
[port
].smax
= policer
->burst
;
2918 return sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2921 static void sja1105_port_policer_del(struct dsa_switch
*ds
, int port
)
2923 struct sja1105_l2_policing_entry
*policing
;
2924 struct sja1105_private
*priv
= ds
->priv
;
2926 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2928 policing
[port
].rate
= SJA1105_RATE_MBPS(1000);
2929 policing
[port
].smax
= 65535;
2931 sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2934 static int sja1105_port_set_learning(struct sja1105_private
*priv
, int port
,
2937 struct sja1105_mac_config_entry
*mac
;
2939 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2941 mac
[port
].dyn_learn
= enabled
;
2943 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
2947 static int sja1105_port_ucast_bcast_flood(struct sja1105_private
*priv
, int to
,
2948 struct switchdev_brport_flags flags
)
2950 if (flags
.mask
& BR_FLOOD
) {
2951 if (flags
.val
& BR_FLOOD
)
2952 priv
->ucast_egress_floods
|= BIT(to
);
2954 priv
->ucast_egress_floods
&= ~BIT(to
);
2957 if (flags
.mask
& BR_BCAST_FLOOD
) {
2958 if (flags
.val
& BR_BCAST_FLOOD
)
2959 priv
->bcast_egress_floods
|= BIT(to
);
2961 priv
->bcast_egress_floods
&= ~BIT(to
);
2964 return sja1105_manage_flood_domains(priv
);
2967 static int sja1105_port_mcast_flood(struct sja1105_private
*priv
, int to
,
2968 struct switchdev_brport_flags flags
,
2969 struct netlink_ext_ack
*extack
)
2971 struct sja1105_l2_lookup_entry
*l2_lookup
;
2972 struct sja1105_table
*table
;
2975 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
2976 l2_lookup
= table
->entries
;
2978 for (match
= 0; match
< table
->entry_count
; match
++)
2979 if (l2_lookup
[match
].macaddr
== SJA1105_UNKNOWN_MULTICAST
&&
2980 l2_lookup
[match
].mask_macaddr
== SJA1105_UNKNOWN_MULTICAST
)
2983 if (match
== table
->entry_count
) {
2984 NL_SET_ERR_MSG_MOD(extack
,
2985 "Could not find FDB entry for unknown multicast");
2989 if (flags
.val
& BR_MCAST_FLOOD
)
2990 l2_lookup
[match
].destports
|= BIT(to
);
2992 l2_lookup
[match
].destports
&= ~BIT(to
);
2994 return sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
2995 l2_lookup
[match
].index
,
3000 static int sja1105_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
,
3001 struct switchdev_brport_flags flags
,
3002 struct netlink_ext_ack
*extack
)
3004 struct sja1105_private
*priv
= ds
->priv
;
3006 if (flags
.mask
& ~(BR_LEARNING
| BR_FLOOD
| BR_MCAST_FLOOD
|
3010 if (flags
.mask
& (BR_FLOOD
| BR_MCAST_FLOOD
) &&
3011 !priv
->info
->can_limit_mcast_flood
) {
3012 bool multicast
= !!(flags
.val
& BR_MCAST_FLOOD
);
3013 bool unicast
= !!(flags
.val
& BR_FLOOD
);
3015 if (unicast
!= multicast
) {
3016 NL_SET_ERR_MSG_MOD(extack
,
3017 "This chip cannot configure multicast flooding independently of unicast");
3025 static int sja1105_port_bridge_flags(struct dsa_switch
*ds
, int port
,
3026 struct switchdev_brport_flags flags
,
3027 struct netlink_ext_ack
*extack
)
3029 struct sja1105_private
*priv
= ds
->priv
;
3032 if (flags
.mask
& BR_LEARNING
) {
3033 bool learn_ena
= !!(flags
.val
& BR_LEARNING
);
3035 rc
= sja1105_port_set_learning(priv
, port
, learn_ena
);
3040 if (flags
.mask
& (BR_FLOOD
| BR_BCAST_FLOOD
)) {
3041 rc
= sja1105_port_ucast_bcast_flood(priv
, port
, flags
);
3046 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3047 * is nothing to do here, we ensured the configuration is in sync by
3048 * offloading BR_FLOOD.
3050 if (flags
.mask
& BR_MCAST_FLOOD
&& priv
->info
->can_limit_mcast_flood
) {
3051 rc
= sja1105_port_mcast_flood(priv
, port
, flags
,
3060 static const struct dsa_switch_ops sja1105_switch_ops
= {
3061 .get_tag_protocol
= sja1105_get_tag_protocol
,
3062 .setup
= sja1105_setup
,
3063 .teardown
= sja1105_teardown
,
3064 .set_ageing_time
= sja1105_set_ageing_time
,
3065 .port_change_mtu
= sja1105_change_mtu
,
3066 .port_max_mtu
= sja1105_get_max_mtu
,
3067 .phylink_validate
= sja1105_phylink_validate
,
3068 .phylink_mac_config
= sja1105_mac_config
,
3069 .phylink_mac_link_up
= sja1105_mac_link_up
,
3070 .phylink_mac_link_down
= sja1105_mac_link_down
,
3071 .get_strings
= sja1105_get_strings
,
3072 .get_ethtool_stats
= sja1105_get_ethtool_stats
,
3073 .get_sset_count
= sja1105_get_sset_count
,
3074 .get_ts_info
= sja1105_get_ts_info
,
3075 .port_disable
= sja1105_port_disable
,
3076 .port_fdb_dump
= sja1105_fdb_dump
,
3077 .port_fdb_add
= sja1105_fdb_add
,
3078 .port_fdb_del
= sja1105_fdb_del
,
3079 .port_fast_age
= sja1105_fast_age
,
3080 .port_bridge_join
= sja1105_bridge_join
,
3081 .port_bridge_leave
= sja1105_bridge_leave
,
3082 .port_pre_bridge_flags
= sja1105_port_pre_bridge_flags
,
3083 .port_bridge_flags
= sja1105_port_bridge_flags
,
3084 .port_stp_state_set
= sja1105_bridge_stp_state_set
,
3085 .port_vlan_filtering
= sja1105_vlan_filtering
,
3086 .port_vlan_add
= sja1105_bridge_vlan_add
,
3087 .port_vlan_del
= sja1105_bridge_vlan_del
,
3088 .port_mdb_add
= sja1105_mdb_add
,
3089 .port_mdb_del
= sja1105_mdb_del
,
3090 .port_hwtstamp_get
= sja1105_hwtstamp_get
,
3091 .port_hwtstamp_set
= sja1105_hwtstamp_set
,
3092 .port_rxtstamp
= sja1105_port_rxtstamp
,
3093 .port_txtstamp
= sja1105_port_txtstamp
,
3094 .port_setup_tc
= sja1105_port_setup_tc
,
3095 .port_mirror_add
= sja1105_mirror_add
,
3096 .port_mirror_del
= sja1105_mirror_del
,
3097 .port_policer_add
= sja1105_port_policer_add
,
3098 .port_policer_del
= sja1105_port_policer_del
,
3099 .cls_flower_add
= sja1105_cls_flower_add
,
3100 .cls_flower_del
= sja1105_cls_flower_del
,
3101 .cls_flower_stats
= sja1105_cls_flower_stats
,
3102 .devlink_info_get
= sja1105_devlink_info_get
,
3103 .tag_8021q_vlan_add
= sja1105_dsa_8021q_vlan_add
,
3104 .tag_8021q_vlan_del
= sja1105_dsa_8021q_vlan_del
,
3105 .port_prechangeupper
= sja1105_prechangeupper
,
3106 .port_bridge_tx_fwd_offload
= dsa_tag_8021q_bridge_tx_fwd_offload
,
3107 .port_bridge_tx_fwd_unoffload
= dsa_tag_8021q_bridge_tx_fwd_unoffload
,
3110 static const struct of_device_id sja1105_dt_ids
[];
3112 static int sja1105_check_device_id(struct sja1105_private
*priv
)
3114 const struct sja1105_regs
*regs
= priv
->info
->regs
;
3115 u8 prod_id
[SJA1105_SIZE_DEVICE_ID
] = {0};
3116 struct device
*dev
= &priv
->spidev
->dev
;
3117 const struct of_device_id
*match
;
3122 rc
= sja1105_xfer_u32(priv
, SPI_READ
, regs
->device_id
, &device_id
,
3127 rc
= sja1105_xfer_buf(priv
, SPI_READ
, regs
->prod_id
, prod_id
,
3128 SJA1105_SIZE_DEVICE_ID
);
3132 sja1105_unpack(prod_id
, &part_no
, 19, 4, SJA1105_SIZE_DEVICE_ID
);
3134 for (match
= sja1105_dt_ids
; match
->compatible
[0]; match
++) {
3135 const struct sja1105_info
*info
= match
->data
;
3137 /* Is what's been probed in our match table at all? */
3138 if (info
->device_id
!= device_id
|| info
->part_no
!= part_no
)
3141 /* But is it what's in the device tree? */
3142 if (priv
->info
->device_id
!= device_id
||
3143 priv
->info
->part_no
!= part_no
) {
3144 dev_warn(dev
, "Device tree specifies chip %s but found %s, please fix it!\n",
3145 priv
->info
->name
, info
->name
);
3146 /* It isn't. No problem, pick that up. */
3153 dev_err(dev
, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3154 device_id
, part_no
);
3159 static int sja1105_probe(struct spi_device
*spi
)
3161 struct sja1105_tagger_data
*tagger_data
;
3162 struct device
*dev
= &spi
->dev
;
3163 struct sja1105_private
*priv
;
3164 size_t max_xfer
, max_msg
;
3165 struct dsa_switch
*ds
;
3168 if (!dev
->of_node
) {
3169 dev_err(dev
, "No DTS bindings for SJA1105 driver\n");
3173 priv
= devm_kzalloc(dev
, sizeof(struct sja1105_private
), GFP_KERNEL
);
3177 /* Configure the optional reset pin and bring up switch */
3178 priv
->reset_gpio
= devm_gpiod_get(dev
, "reset", GPIOD_OUT_HIGH
);
3179 if (IS_ERR(priv
->reset_gpio
))
3180 dev_dbg(dev
, "reset-gpios not defined, ignoring\n");
3182 sja1105_hw_reset(priv
->reset_gpio
, 1, 1);
3184 /* Populate our driver private structure (priv) based on
3185 * the device tree node that was probed (spi)
3188 spi_set_drvdata(spi
, priv
);
3190 /* Configure the SPI bus */
3191 spi
->bits_per_word
= 8;
3192 rc
= spi_setup(spi
);
3194 dev_err(dev
, "Could not init SPI\n");
3198 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3199 * a small one for the message header and another one for the current
3200 * chunk of the packed buffer.
3201 * Check that the restrictions imposed by the SPI controller are
3202 * respected: the chunk buffer is smaller than the max transfer size,
3203 * and the total length of the chunk plus its message header is smaller
3204 * than the max message size.
3205 * We do that during probe time since the maximum transfer size is a
3206 * runtime invariant.
3208 max_xfer
= spi_max_transfer_size(spi
);
3209 max_msg
= spi_max_message_size(spi
);
3211 /* We need to send at least one 64-bit word of SPI payload per message
3212 * in order to be able to make useful progress.
3214 if (max_msg
< SJA1105_SIZE_SPI_MSG_HEADER
+ 8) {
3215 dev_err(dev
, "SPI master cannot send large enough buffers, aborting\n");
3219 priv
->max_xfer_len
= SJA1105_SIZE_SPI_MSG_MAXLEN
;
3220 if (priv
->max_xfer_len
> max_xfer
)
3221 priv
->max_xfer_len
= max_xfer
;
3222 if (priv
->max_xfer_len
> max_msg
- SJA1105_SIZE_SPI_MSG_HEADER
)
3223 priv
->max_xfer_len
= max_msg
- SJA1105_SIZE_SPI_MSG_HEADER
;
3225 priv
->info
= of_device_get_match_data(dev
);
3227 /* Detect hardware device */
3228 rc
= sja1105_check_device_id(priv
);
3230 dev_err(dev
, "Device ID check failed: %d\n", rc
);
3234 dev_info(dev
, "Probed switch chip: %s\n", priv
->info
->name
);
3236 ds
= devm_kzalloc(dev
, sizeof(*ds
), GFP_KERNEL
);
3241 ds
->num_ports
= priv
->info
->num_ports
;
3242 ds
->ops
= &sja1105_switch_ops
;
3246 tagger_data
= &priv
->tagger_data
;
3248 mutex_init(&priv
->ptp_data
.lock
);
3249 mutex_init(&priv
->mgmt_lock
);
3251 sja1105_tas_setup(ds
);
3252 sja1105_flower_setup(ds
);
3254 rc
= dsa_register_switch(priv
->ds
);
3258 if (IS_ENABLED(CONFIG_NET_SCH_CBS
)) {
3259 priv
->cbs
= devm_kcalloc(dev
, priv
->info
->num_cbs_shapers
,
3260 sizeof(struct sja1105_cbs_entry
),
3264 goto out_unregister_switch
;
3268 /* Connections between dsa_port and sja1105_port */
3269 for (port
= 0; port
< ds
->num_ports
; port
++) {
3270 struct sja1105_port
*sp
= &priv
->ports
[port
];
3271 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
3272 struct net_device
*slave
;
3274 if (!dsa_is_user_port(ds
, port
))
3279 sp
->data
= tagger_data
;
3281 kthread_init_work(&sp
->xmit_work
, sja1105_port_deferred_xmit
);
3282 sp
->xmit_worker
= kthread_create_worker(0, "%s_xmit",
3284 if (IS_ERR(sp
->xmit_worker
)) {
3285 rc
= PTR_ERR(sp
->xmit_worker
);
3287 "failed to create deferred xmit thread: %d\n",
3289 goto out_destroy_workers
;
3291 skb_queue_head_init(&sp
->xmit_queue
);
3292 sp
->xmit_tpid
= ETH_P_SJA1105
;
3297 out_destroy_workers
:
3298 while (port
-- > 0) {
3299 struct sja1105_port
*sp
= &priv
->ports
[port
];
3301 if (!dsa_is_user_port(ds
, port
))
3304 kthread_destroy_worker(sp
->xmit_worker
);
3307 out_unregister_switch
:
3308 dsa_unregister_switch(ds
);
3313 static int sja1105_remove(struct spi_device
*spi
)
3315 struct sja1105_private
*priv
= spi_get_drvdata(spi
);
3316 struct dsa_switch
*ds
= priv
->ds
;
3318 dsa_unregister_switch(ds
);
3323 static const struct of_device_id sja1105_dt_ids
[] = {
3324 { .compatible
= "nxp,sja1105e", .data
= &sja1105e_info
},
3325 { .compatible
= "nxp,sja1105t", .data
= &sja1105t_info
},
3326 { .compatible
= "nxp,sja1105p", .data
= &sja1105p_info
},
3327 { .compatible
= "nxp,sja1105q", .data
= &sja1105q_info
},
3328 { .compatible
= "nxp,sja1105r", .data
= &sja1105r_info
},
3329 { .compatible
= "nxp,sja1105s", .data
= &sja1105s_info
},
3330 { .compatible
= "nxp,sja1110a", .data
= &sja1110a_info
},
3331 { .compatible
= "nxp,sja1110b", .data
= &sja1110b_info
},
3332 { .compatible
= "nxp,sja1110c", .data
= &sja1110c_info
},
3333 { .compatible
= "nxp,sja1110d", .data
= &sja1110d_info
},
3336 MODULE_DEVICE_TABLE(of
, sja1105_dt_ids
);
3338 static struct spi_driver sja1105_driver
= {
3341 .owner
= THIS_MODULE
,
3342 .of_match_table
= of_match_ptr(sja1105_dt_ids
),
3344 .probe
= sja1105_probe
,
3345 .remove
= sja1105_remove
,
3348 module_spi_driver(sja1105_driver
);
3350 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3351 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3352 MODULE_DESCRIPTION("SJA1105 Driver");
3353 MODULE_LICENSE("GPL v2");