1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/printk.h>
11 #include <linux/spi/spi.h>
12 #include <linux/errno.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/phylink.h>
16 #include <linux/of_net.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_device.h>
19 #include <linux/pcs/pcs-xpcs.h>
20 #include <linux/netdev_features.h>
21 #include <linux/netdevice.h>
22 #include <linux/if_bridge.h>
23 #include <linux/if_ether.h>
24 #include <linux/dsa/8021q.h>
26 #include "sja1105_tas.h"
28 #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
30 static void sja1105_hw_reset(struct gpio_desc
*gpio
, unsigned int pulse_len
,
31 unsigned int startup_delay
)
33 gpiod_set_value_cansleep(gpio
, 1);
34 /* Wait for minimum reset pulse length */
36 gpiod_set_value_cansleep(gpio
, 0);
37 /* Wait until chip is ready after reset */
38 msleep(startup_delay
);
42 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry
*l2_fwd
,
43 int from
, int to
, bool allow
)
46 l2_fwd
[from
].reach_port
|= BIT(to
);
48 l2_fwd
[from
].reach_port
&= ~BIT(to
);
51 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry
*l2_fwd
,
54 return !!(l2_fwd
[from
].reach_port
& BIT(to
));
57 static int sja1105_is_vlan_configured(struct sja1105_private
*priv
, u16 vid
)
59 struct sja1105_vlan_lookup_entry
*vlan
;
62 vlan
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entries
;
63 count
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entry_count
;
65 for (i
= 0; i
< count
; i
++)
66 if (vlan
[i
].vlanid
== vid
)
69 /* Return an invalid entry index if not found */
73 static int sja1105_drop_untagged(struct dsa_switch
*ds
, int port
, bool drop
)
75 struct sja1105_private
*priv
= ds
->priv
;
76 struct sja1105_mac_config_entry
*mac
;
78 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
80 if (mac
[port
].drpuntag
== drop
)
83 mac
[port
].drpuntag
= drop
;
85 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
89 static int sja1105_pvid_apply(struct sja1105_private
*priv
, int port
, u16 pvid
)
91 struct sja1105_mac_config_entry
*mac
;
93 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
95 if (mac
[port
].vlanid
== pvid
)
98 mac
[port
].vlanid
= pvid
;
100 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
104 static int sja1105_commit_pvid(struct dsa_switch
*ds
, int port
)
106 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
107 struct sja1105_private
*priv
= ds
->priv
;
108 struct sja1105_vlan_lookup_entry
*vlan
;
109 bool drop_untagged
= false;
113 if (dp
->bridge_dev
&& br_vlan_enabled(dp
->bridge_dev
))
114 pvid
= priv
->bridge_pvid
[port
];
116 pvid
= priv
->tag_8021q_pvid
[port
];
118 rc
= sja1105_pvid_apply(priv
, port
, pvid
);
122 /* Only force dropping of untagged packets when the port is under a
123 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
124 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
125 * to prevent DSA tag spoofing from the link partner. Untagged packets
126 * are the only ones that should be received with tag_8021q, so
127 * definitely don't drop them.
129 if (pvid
== priv
->bridge_pvid
[port
]) {
130 vlan
= priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
].entries
;
132 match
= sja1105_is_vlan_configured(priv
, pvid
);
134 if (match
< 0 || !(vlan
[match
].vmemb_port
& BIT(port
)))
135 drop_untagged
= true;
138 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
139 drop_untagged
= true;
141 return sja1105_drop_untagged(ds
, port
, drop_untagged
);
144 static int sja1105_init_mac_settings(struct sja1105_private
*priv
)
146 struct sja1105_mac_config_entry default_mac
= {
147 /* Enable all 8 priority queues on egress.
148 * Every queue i holds top[i] - base[i] frames.
149 * Sum of top[i] - base[i] is 511 (max hardware limit).
151 .top
= {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
152 .base
= {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
153 .enabled
= {true, true, true, true, true, true, true, true},
154 /* Keep standard IFG of 12 bytes on egress. */
156 /* Always put the MAC speed in automatic mode, where it can be
157 * adjusted at runtime by PHYLINK.
159 .speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
],
160 /* No static correction for 1-step 1588 events */
163 /* Disable aging for critical TTEthernet traffic */
165 /* Internal VLAN (pvid) to apply to untagged ingress */
170 /* Don't drop traffic with other EtherType than ETH_P_IP */
172 /* Don't drop double-tagged traffic */
174 /* Don't drop untagged traffic */
176 /* Don't retag 802.1p (VID 0) traffic with the pvid */
178 /* Disable learning and I/O on user ports by default -
179 * STP will enable it.
185 struct sja1105_mac_config_entry
*mac
;
186 struct dsa_switch
*ds
= priv
->ds
;
187 struct sja1105_table
*table
;
190 table
= &priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
];
192 /* Discard previous MAC Configuration Table */
193 if (table
->entry_count
) {
194 kfree(table
->entries
);
195 table
->entry_count
= 0;
198 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
199 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
203 table
->entry_count
= table
->ops
->max_entry_count
;
205 mac
= table
->entries
;
207 list_for_each_entry(dp
, &ds
->dst
->ports
, list
) {
211 mac
[dp
->index
] = default_mac
;
213 /* Let sja1105_bridge_stp_state_set() keep address learning
214 * enabled for the DSA ports. CPU ports use software-assisted
215 * learning to ensure that only FDB entries belonging to the
216 * bridge are learned, and that they are learned towards all
217 * CPU ports in a cross-chip topology if multiple CPU ports
220 if (dsa_port_is_dsa(dp
))
223 /* Disallow untagged packets from being received on the
226 if (dsa_port_is_cpu(dp
) || dsa_port_is_dsa(dp
))
227 mac
[dp
->index
].drpuntag
= true;
233 static int sja1105_init_mii_settings(struct sja1105_private
*priv
)
235 struct device
*dev
= &priv
->spidev
->dev
;
236 struct sja1105_xmii_params_entry
*mii
;
237 struct dsa_switch
*ds
= priv
->ds
;
238 struct sja1105_table
*table
;
241 table
= &priv
->static_config
.tables
[BLK_IDX_XMII_PARAMS
];
243 /* Discard previous xMII Mode Parameters Table */
244 if (table
->entry_count
) {
245 kfree(table
->entries
);
246 table
->entry_count
= 0;
249 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
250 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
254 /* Override table based on PHYLINK DT bindings */
255 table
->entry_count
= table
->ops
->max_entry_count
;
257 mii
= table
->entries
;
259 for (i
= 0; i
< ds
->num_ports
; i
++) {
260 sja1105_mii_role_t role
= XMII_MAC
;
262 if (dsa_is_unused_port(priv
->ds
, i
))
265 switch (priv
->phy_mode
[i
]) {
266 case PHY_INTERFACE_MODE_INTERNAL
:
267 if (priv
->info
->internal_phy
[i
] == SJA1105_NO_PHY
)
270 mii
->xmii_mode
[i
] = XMII_MODE_MII
;
271 if (priv
->info
->internal_phy
[i
] == SJA1105_PHY_BASE_TX
)
272 mii
->special
[i
] = true;
275 case PHY_INTERFACE_MODE_REVMII
:
278 case PHY_INTERFACE_MODE_MII
:
279 if (!priv
->info
->supports_mii
[i
])
282 mii
->xmii_mode
[i
] = XMII_MODE_MII
;
284 case PHY_INTERFACE_MODE_REVRMII
:
287 case PHY_INTERFACE_MODE_RMII
:
288 if (!priv
->info
->supports_rmii
[i
])
291 mii
->xmii_mode
[i
] = XMII_MODE_RMII
;
293 case PHY_INTERFACE_MODE_RGMII
:
294 case PHY_INTERFACE_MODE_RGMII_ID
:
295 case PHY_INTERFACE_MODE_RGMII_RXID
:
296 case PHY_INTERFACE_MODE_RGMII_TXID
:
297 if (!priv
->info
->supports_rgmii
[i
])
300 mii
->xmii_mode
[i
] = XMII_MODE_RGMII
;
302 case PHY_INTERFACE_MODE_SGMII
:
303 if (!priv
->info
->supports_sgmii
[i
])
306 mii
->xmii_mode
[i
] = XMII_MODE_SGMII
;
307 mii
->special
[i
] = true;
309 case PHY_INTERFACE_MODE_2500BASEX
:
310 if (!priv
->info
->supports_2500basex
[i
])
313 mii
->xmii_mode
[i
] = XMII_MODE_SGMII
;
314 mii
->special
[i
] = true;
318 dev_err(dev
, "Unsupported PHY mode %s on port %d!\n",
319 phy_modes(priv
->phy_mode
[i
]), i
);
323 mii
->phy_mac
[i
] = role
;
328 static int sja1105_init_static_fdb(struct sja1105_private
*priv
)
330 struct sja1105_l2_lookup_entry
*l2_lookup
;
331 struct sja1105_table
*table
;
334 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
336 /* We only populate the FDB table through dynamic L2 Address Lookup
337 * entries, except for a special entry at the end which is a catch-all
338 * for unknown multicast and will be used to control flooding domain.
340 if (table
->entry_count
) {
341 kfree(table
->entries
);
342 table
->entry_count
= 0;
345 if (!priv
->info
->can_limit_mcast_flood
)
348 table
->entries
= kcalloc(1, table
->ops
->unpacked_entry_size
,
353 table
->entry_count
= 1;
354 l2_lookup
= table
->entries
;
356 /* All L2 multicast addresses have an odd first octet */
357 l2_lookup
[0].macaddr
= SJA1105_UNKNOWN_MULTICAST
;
358 l2_lookup
[0].mask_macaddr
= SJA1105_UNKNOWN_MULTICAST
;
359 l2_lookup
[0].lockeds
= true;
360 l2_lookup
[0].index
= SJA1105_MAX_L2_LOOKUP_COUNT
- 1;
362 /* Flood multicast to every port by default */
363 for (port
= 0; port
< priv
->ds
->num_ports
; port
++)
364 if (!dsa_is_unused_port(priv
->ds
, port
))
365 l2_lookup
[0].destports
|= BIT(port
);
370 static int sja1105_init_l2_lookup_params(struct sja1105_private
*priv
)
372 struct sja1105_l2_lookup_params_entry default_l2_lookup_params
= {
373 /* Learned FDB entries are forgotten after 300 seconds */
374 .maxage
= SJA1105_AGEING_TIME_MS(300000),
375 /* All entries within a FDB bin are available for learning */
376 .dyn_tbsz
= SJA1105ET_FDB_BIN_SIZE
,
377 /* And the P/Q/R/S equivalent setting: */
379 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
381 /* This selects between Independent VLAN Learning (IVL) and
382 * Shared VLAN Learning (SVL)
384 .shared_learn
= true,
385 /* Don't discard management traffic based on ENFPORT -
386 * we don't perform SMAC port enforcement anyway, so
387 * what we are setting here doesn't matter.
389 .no_enf_hostprt
= false,
390 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
391 * Maybe correlate with no_linklocal_learn from bridge driver?
393 .no_mgmt_learn
= true,
396 /* Dynamically learned FDB entries can overwrite other (older)
397 * dynamic FDB entries
402 struct dsa_switch
*ds
= priv
->ds
;
403 int port
, num_used_ports
= 0;
404 struct sja1105_table
*table
;
407 for (port
= 0; port
< ds
->num_ports
; port
++)
408 if (!dsa_is_unused_port(ds
, port
))
411 max_fdb_entries
= SJA1105_MAX_L2_LOOKUP_COUNT
/ num_used_ports
;
413 for (port
= 0; port
< ds
->num_ports
; port
++) {
414 if (dsa_is_unused_port(ds
, port
))
417 default_l2_lookup_params
.maxaddrp
[port
] = max_fdb_entries
;
420 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
422 if (table
->entry_count
) {
423 kfree(table
->entries
);
424 table
->entry_count
= 0;
427 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
428 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
432 table
->entry_count
= table
->ops
->max_entry_count
;
434 /* This table only has a single entry */
435 ((struct sja1105_l2_lookup_params_entry
*)table
->entries
)[0] =
436 default_l2_lookup_params
;
441 /* Set up a default VLAN for untagged traffic injected from the CPU
442 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
443 * All DT-defined ports are members of this VLAN, and there are no
444 * restrictions on forwarding (since the CPU selects the destination).
445 * Frames from this VLAN will always be transmitted as untagged, and
446 * neither the bridge nor the 8021q module cannot create this VLAN ID.
448 static int sja1105_init_static_vlan(struct sja1105_private
*priv
)
450 struct sja1105_table
*table
;
451 struct sja1105_vlan_lookup_entry pvid
= {
452 .type_entry
= SJA1110_VLAN_D_TAG
,
458 .vlanid
= SJA1105_DEFAULT_VLAN
,
460 struct dsa_switch
*ds
= priv
->ds
;
463 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
465 if (table
->entry_count
) {
466 kfree(table
->entries
);
467 table
->entry_count
= 0;
470 table
->entries
= kzalloc(table
->ops
->unpacked_entry_size
,
475 table
->entry_count
= 1;
477 for (port
= 0; port
< ds
->num_ports
; port
++) {
478 if (dsa_is_unused_port(ds
, port
))
481 pvid
.vmemb_port
|= BIT(port
);
482 pvid
.vlan_bc
|= BIT(port
);
483 pvid
.tag_port
&= ~BIT(port
);
485 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
486 priv
->tag_8021q_pvid
[port
] = SJA1105_DEFAULT_VLAN
;
487 priv
->bridge_pvid
[port
] = SJA1105_DEFAULT_VLAN
;
491 ((struct sja1105_vlan_lookup_entry
*)table
->entries
)[0] = pvid
;
495 static int sja1105_init_l2_forwarding(struct sja1105_private
*priv
)
497 struct sja1105_l2_forwarding_entry
*l2fwd
;
498 struct dsa_switch
*ds
= priv
->ds
;
499 struct dsa_switch_tree
*dst
;
500 struct sja1105_table
*table
;
505 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
];
507 if (table
->entry_count
) {
508 kfree(table
->entries
);
509 table
->entry_count
= 0;
512 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
513 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
517 table
->entry_count
= table
->ops
->max_entry_count
;
519 l2fwd
= table
->entries
;
521 /* First 5 entries in the L2 Forwarding Table define the forwarding
522 * rules and the VLAN PCP to ingress queue mapping.
523 * Set up the ingress queue mapping first.
525 for (port
= 0; port
< ds
->num_ports
; port
++) {
526 if (dsa_is_unused_port(ds
, port
))
529 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
530 l2fwd
[port
].vlan_pmap
[tc
] = tc
;
533 /* Then manage the forwarding domain for user ports. These can forward
534 * only to the always-on domain (CPU port and DSA links)
536 for (from
= 0; from
< ds
->num_ports
; from
++) {
537 if (!dsa_is_user_port(ds
, from
))
540 for (to
= 0; to
< ds
->num_ports
; to
++) {
541 if (!dsa_is_cpu_port(ds
, to
) &&
542 !dsa_is_dsa_port(ds
, to
))
545 l2fwd
[from
].bc_domain
|= BIT(to
);
546 l2fwd
[from
].fl_domain
|= BIT(to
);
548 sja1105_port_allow_traffic(l2fwd
, from
, to
, true);
552 /* Then manage the forwarding domain for DSA links and CPU ports (the
553 * always-on domain). These can send packets to any enabled port except
556 for (from
= 0; from
< ds
->num_ports
; from
++) {
557 if (!dsa_is_cpu_port(ds
, from
) && !dsa_is_dsa_port(ds
, from
))
560 for (to
= 0; to
< ds
->num_ports
; to
++) {
561 if (dsa_is_unused_port(ds
, to
))
567 l2fwd
[from
].bc_domain
|= BIT(to
);
568 l2fwd
[from
].fl_domain
|= BIT(to
);
570 sja1105_port_allow_traffic(l2fwd
, from
, to
, true);
574 /* In odd topologies ("H" connections where there is a DSA link to
575 * another switch which also has its own CPU port), TX packets can loop
576 * back into the system (they are flooded from CPU port 1 to the DSA
577 * link, and from there to CPU port 2). Prevent this from happening by
578 * cutting RX from DSA links towards our CPU port, if the remote switch
579 * has its own CPU port and therefore doesn't need ours for network
584 list_for_each_entry(dl
, &dst
->rtable
, list
) {
585 if (dl
->dp
->ds
!= ds
|| dl
->link_dp
->cpu_dp
== dl
->dp
->cpu_dp
)
588 from
= dl
->dp
->index
;
589 to
= dsa_upstream_port(ds
, from
);
592 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
595 sja1105_port_allow_traffic(l2fwd
, from
, to
, false);
597 l2fwd
[from
].bc_domain
&= ~BIT(to
);
598 l2fwd
[from
].fl_domain
&= ~BIT(to
);
601 /* Finally, manage the egress flooding domain. All ports start up with
602 * flooding enabled, including the CPU port and DSA links.
604 for (port
= 0; port
< ds
->num_ports
; port
++) {
605 if (dsa_is_unused_port(ds
, port
))
608 priv
->ucast_egress_floods
|= BIT(port
);
609 priv
->bcast_egress_floods
|= BIT(port
);
612 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
613 * Create a one-to-one mapping.
615 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++) {
616 for (port
= 0; port
< ds
->num_ports
; port
++) {
617 if (dsa_is_unused_port(ds
, port
))
620 l2fwd
[ds
->num_ports
+ tc
].vlan_pmap
[port
] = tc
;
623 l2fwd
[ds
->num_ports
+ tc
].type_egrpcp2outputq
= true;
629 static int sja1110_init_pcp_remapping(struct sja1105_private
*priv
)
631 struct sja1110_pcp_remapping_entry
*pcp_remap
;
632 struct dsa_switch
*ds
= priv
->ds
;
633 struct sja1105_table
*table
;
636 table
= &priv
->static_config
.tables
[BLK_IDX_PCP_REMAPPING
];
638 /* Nothing to do for SJA1105 */
639 if (!table
->ops
->max_entry_count
)
642 if (table
->entry_count
) {
643 kfree(table
->entries
);
644 table
->entry_count
= 0;
647 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
648 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
652 table
->entry_count
= table
->ops
->max_entry_count
;
654 pcp_remap
= table
->entries
;
656 /* Repeat the configuration done for vlan_pmap */
657 for (port
= 0; port
< ds
->num_ports
; port
++) {
658 if (dsa_is_unused_port(ds
, port
))
661 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
662 pcp_remap
[port
].egrpcp
[tc
] = tc
;
668 static int sja1105_init_l2_forwarding_params(struct sja1105_private
*priv
)
670 struct sja1105_l2_forwarding_params_entry
*l2fwd_params
;
671 struct sja1105_table
*table
;
673 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING_PARAMS
];
675 if (table
->entry_count
) {
676 kfree(table
->entries
);
677 table
->entry_count
= 0;
680 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
681 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
685 table
->entry_count
= table
->ops
->max_entry_count
;
687 /* This table only has a single entry */
688 l2fwd_params
= table
->entries
;
690 /* Disallow dynamic reconfiguration of vlan_pmap */
691 l2fwd_params
->max_dynp
= 0;
692 /* Use a single memory partition for all ingress queues */
693 l2fwd_params
->part_spc
[0] = priv
->info
->max_frame_mem
;
698 void sja1105_frame_memory_partitioning(struct sja1105_private
*priv
)
700 struct sja1105_l2_forwarding_params_entry
*l2_fwd_params
;
701 struct sja1105_vl_forwarding_params_entry
*vl_fwd_params
;
702 struct sja1105_table
*table
;
704 table
= &priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING_PARAMS
];
705 l2_fwd_params
= table
->entries
;
706 l2_fwd_params
->part_spc
[0] = SJA1105_MAX_FRAME_MEMORY
;
708 /* If we have any critical-traffic virtual links, we need to reserve
709 * some frame buffer memory for them. At the moment, hardcode the value
710 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
711 * remaining for best-effort traffic. TODO: figure out a more flexible
712 * way to perform the frame buffer partitioning.
714 if (!priv
->static_config
.tables
[BLK_IDX_VL_FORWARDING
].entry_count
)
717 table
= &priv
->static_config
.tables
[BLK_IDX_VL_FORWARDING_PARAMS
];
718 vl_fwd_params
= table
->entries
;
720 l2_fwd_params
->part_spc
[0] -= SJA1105_VL_FRAME_MEMORY
;
721 vl_fwd_params
->partspc
[0] = SJA1105_VL_FRAME_MEMORY
;
724 /* SJA1110 TDMACONFIGIDX values:
726 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
727 * -----+----------------+---------------+---------------+---------------
728 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
729 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
730 * 2 | 0, [5:10] | [1:3], retag | 4 | -
731 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
732 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
733 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
734 * 14 | 0, [5:10] | [1:4], retag | - | -
735 * 15 | [5:10] | [0:4], retag | - | -
737 static void sja1110_select_tdmaconfigidx(struct sja1105_private
*priv
)
739 struct sja1105_general_params_entry
*general_params
;
740 struct sja1105_table
*table
;
741 bool port_1_is_base_tx
;
746 if (priv
->info
->device_id
!= SJA1110_DEVICE_ID
)
749 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
750 general_params
= table
->entries
;
752 /* All the settings below are "as opposed to SGMII", which is the
753 * other pinmuxing option.
755 port_1_is_base_tx
= priv
->phy_mode
[1] == PHY_INTERFACE_MODE_INTERNAL
;
756 port_3_is_2500
= priv
->phy_mode
[3] == PHY_INTERFACE_MODE_2500BASEX
;
757 port_4_is_2500
= priv
->phy_mode
[4] == PHY_INTERFACE_MODE_2500BASEX
;
759 if (port_1_is_base_tx
)
760 /* Retagging port will operate at 1 Gbps */
762 else if (port_3_is_2500
&& port_4_is_2500
)
763 /* Retagging port will operate at 100 Mbps */
765 else if (port_3_is_2500
)
766 /* Retagging port will operate at 1 Gbps */
768 else if (port_4_is_2500
)
769 /* Retagging port will operate at 1 Gbps */
772 /* Retagging port will operate at 1 Gbps */
775 general_params
->tdmaconfigidx
= tdmaconfigidx
;
778 static int sja1105_init_topology(struct sja1105_private
*priv
,
779 struct sja1105_general_params_entry
*general_params
)
781 struct dsa_switch
*ds
= priv
->ds
;
784 /* The host port is the destination for traffic matching mac_fltres1
785 * and mac_fltres0 on all ports except itself. Default to an invalid
788 general_params
->host_port
= ds
->num_ports
;
790 /* Link-local traffic received on casc_port will be forwarded
791 * to host_port without embedding the source port and device ID
792 * info in the destination MAC address, and no RX timestamps will be
793 * taken either (presumably because it is a cascaded port and a
794 * downstream SJA switch already did that).
795 * To disable the feature, we need to do different things depending on
796 * switch generation. On SJA1105 we need to set an invalid port, while
797 * on SJA1110 which support multiple cascaded ports, this field is a
798 * bitmask so it must be left zero.
800 if (!priv
->info
->multiple_cascade_ports
)
801 general_params
->casc_port
= ds
->num_ports
;
803 for (port
= 0; port
< ds
->num_ports
; port
++) {
804 bool is_upstream
= dsa_is_upstream_port(ds
, port
);
805 bool is_dsa_link
= dsa_is_dsa_port(ds
, port
);
807 /* Upstream ports can be dedicated CPU ports or
808 * upstream-facing DSA links
811 if (general_params
->host_port
== ds
->num_ports
) {
812 general_params
->host_port
= port
;
815 "Port %llu is already a host port, configuring %d as one too is not supported\n",
816 general_params
->host_port
, port
);
821 /* Cascade ports are downstream-facing DSA links */
822 if (is_dsa_link
&& !is_upstream
) {
823 if (priv
->info
->multiple_cascade_ports
) {
824 general_params
->casc_port
|= BIT(port
);
825 } else if (general_params
->casc_port
== ds
->num_ports
) {
826 general_params
->casc_port
= port
;
829 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
830 general_params
->casc_port
, port
);
836 if (general_params
->host_port
== ds
->num_ports
) {
837 dev_err(ds
->dev
, "No host port configured\n");
844 static int sja1105_init_general_params(struct sja1105_private
*priv
)
846 struct sja1105_general_params_entry default_general_params
= {
847 /* Allow dynamic changing of the mirror port */
849 .switchid
= priv
->ds
->index
,
850 /* Priority queue for link-local management frames
851 * (both ingress to and egress from CPU - PTP, STP etc)
854 .mac_fltres1
= SJA1105_LINKLOCAL_FILTER_A
,
855 .mac_flt1
= SJA1105_LINKLOCAL_FILTER_A_MASK
,
856 .incl_srcpt1
= false,
858 .mac_fltres0
= SJA1105_LINKLOCAL_FILTER_B
,
859 .mac_flt0
= SJA1105_LINKLOCAL_FILTER_B_MASK
,
860 .incl_srcpt0
= false,
862 /* Default to an invalid value */
863 .mirr_port
= priv
->ds
->num_ports
,
865 .vllupformat
= SJA1105_VL_FORMAT_PSFP
,
868 /* Only update correctionField for 1-step PTP (L2 transport) */
870 /* Forcefully disable VLAN filtering by telling
871 * the switch that VLAN has a different EtherType.
873 .tpid
= ETH_P_SJA1105
,
874 .tpid2
= ETH_P_SJA1105
,
875 /* Enable the TTEthernet engine on SJA1110 */
877 /* Set up the EtherType for control packets on SJA1110 */
878 .header_type
= ETH_P_SJA1110
,
880 struct sja1105_general_params_entry
*general_params
;
881 struct sja1105_table
*table
;
884 rc
= sja1105_init_topology(priv
, &default_general_params
);
888 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
890 if (table
->entry_count
) {
891 kfree(table
->entries
);
892 table
->entry_count
= 0;
895 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
896 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
900 table
->entry_count
= table
->ops
->max_entry_count
;
902 general_params
= table
->entries
;
904 /* This table only has a single entry */
905 general_params
[0] = default_general_params
;
907 sja1110_select_tdmaconfigidx(priv
);
912 static int sja1105_init_avb_params(struct sja1105_private
*priv
)
914 struct sja1105_avb_params_entry
*avb
;
915 struct sja1105_table
*table
;
917 table
= &priv
->static_config
.tables
[BLK_IDX_AVB_PARAMS
];
919 /* Discard previous AVB Parameters Table */
920 if (table
->entry_count
) {
921 kfree(table
->entries
);
922 table
->entry_count
= 0;
925 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
926 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
930 table
->entry_count
= table
->ops
->max_entry_count
;
932 avb
= table
->entries
;
934 /* Configure the MAC addresses for meta frames */
935 avb
->destmeta
= SJA1105_META_DMAC
;
936 avb
->srcmeta
= SJA1105_META_SMAC
;
937 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
938 * default. This is because there might be boards with a hardware
939 * layout where enabling the pin as output might cause an electrical
940 * clash. On E/T the pin is always an output, which the board designers
941 * probably already knew, so even if there are going to be electrical
942 * issues, there's nothing we can do.
944 avb
->cas_master
= false;
949 /* The L2 policing table is 2-stage. The table is looked up for each frame
950 * according to the ingress port, whether it was broadcast or not, and the
951 * classified traffic class (given by VLAN PCP). This portion of the lookup is
952 * fixed, and gives access to the SHARINDX, an indirection register pointing
953 * within the policing table itself, which is used to resolve the policer that
954 * will be used for this frame.
957 * +------------+--------+ +---------------------------------+
958 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
959 * +------------+--------+ +---------------------------------+
960 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
961 * +------------+--------+ +---------------------------------+
962 * ... | Policer 2: Rate, Burst, MTU |
963 * +------------+--------+ +---------------------------------+
964 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
965 * +------------+--------+ +---------------------------------+
966 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
967 * +------------+--------+ +---------------------------------+
968 * ... | Policer 5: Rate, Burst, MTU |
969 * +------------+--------+ +---------------------------------+
970 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
971 * +------------+--------+ +---------------------------------+
972 * ... | Policer 7: Rate, Burst, MTU |
973 * +------------+--------+ +---------------------------------+
974 * |Port 4 TC 7 |SHARINDX| ...
975 * +------------+--------+
976 * |Port 0 BCAST|SHARINDX| ...
977 * +------------+--------+
978 * |Port 1 BCAST|SHARINDX| ...
979 * +------------+--------+
981 * +------------+--------+ +---------------------------------+
982 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
983 * +------------+--------+ +---------------------------------+
985 * In this driver, we shall use policers 0-4 as statically alocated port
986 * (matchall) policers. So we need to make the SHARINDX for all lookups
987 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
989 * The remaining policers (40) shall be dynamically allocated for flower
990 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
992 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
994 static int sja1105_init_l2_policing(struct sja1105_private
*priv
)
996 struct sja1105_l2_policing_entry
*policing
;
997 struct dsa_switch
*ds
= priv
->ds
;
998 struct sja1105_table
*table
;
1001 table
= &priv
->static_config
.tables
[BLK_IDX_L2_POLICING
];
1003 /* Discard previous L2 Policing Table */
1004 if (table
->entry_count
) {
1005 kfree(table
->entries
);
1006 table
->entry_count
= 0;
1009 table
->entries
= kcalloc(table
->ops
->max_entry_count
,
1010 table
->ops
->unpacked_entry_size
, GFP_KERNEL
);
1011 if (!table
->entries
)
1014 table
->entry_count
= table
->ops
->max_entry_count
;
1016 policing
= table
->entries
;
1018 /* Setup shared indices for the matchall policers */
1019 for (port
= 0; port
< ds
->num_ports
; port
++) {
1020 int mcast
= (ds
->num_ports
* (SJA1105_NUM_TC
+ 1)) + port
;
1021 int bcast
= (ds
->num_ports
* SJA1105_NUM_TC
) + port
;
1023 for (tc
= 0; tc
< SJA1105_NUM_TC
; tc
++)
1024 policing
[port
* SJA1105_NUM_TC
+ tc
].sharindx
= port
;
1026 policing
[bcast
].sharindx
= port
;
1027 /* Only SJA1110 has multicast policers */
1028 if (mcast
<= table
->ops
->max_entry_count
)
1029 policing
[mcast
].sharindx
= port
;
1032 /* Setup the matchall policer parameters */
1033 for (port
= 0; port
< ds
->num_ports
; port
++) {
1034 int mtu
= VLAN_ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1036 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
1039 policing
[port
].smax
= 65535; /* Burst size in bytes */
1040 policing
[port
].rate
= SJA1105_RATE_MBPS(1000);
1041 policing
[port
].maxlen
= mtu
;
1042 policing
[port
].partition
= 0;
1048 static int sja1105_static_config_load(struct sja1105_private
*priv
)
1052 sja1105_static_config_free(&priv
->static_config
);
1053 rc
= sja1105_static_config_init(&priv
->static_config
,
1054 priv
->info
->static_ops
,
1055 priv
->info
->device_id
);
1059 /* Build static configuration */
1060 rc
= sja1105_init_mac_settings(priv
);
1063 rc
= sja1105_init_mii_settings(priv
);
1066 rc
= sja1105_init_static_fdb(priv
);
1069 rc
= sja1105_init_static_vlan(priv
);
1072 rc
= sja1105_init_l2_lookup_params(priv
);
1075 rc
= sja1105_init_l2_forwarding(priv
);
1078 rc
= sja1105_init_l2_forwarding_params(priv
);
1081 rc
= sja1105_init_l2_policing(priv
);
1084 rc
= sja1105_init_general_params(priv
);
1087 rc
= sja1105_init_avb_params(priv
);
1090 rc
= sja1110_init_pcp_remapping(priv
);
1094 /* Send initial configuration to hardware via SPI */
1095 return sja1105_static_config_upload(priv
);
1098 static int sja1105_parse_rgmii_delays(struct sja1105_private
*priv
)
1100 struct dsa_switch
*ds
= priv
->ds
;
1103 for (port
= 0; port
< ds
->num_ports
; port
++) {
1104 if (!priv
->fixed_link
[port
])
1107 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_RXID
||
1108 priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_ID
)
1109 priv
->rgmii_rx_delay
[port
] = true;
1111 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_TXID
||
1112 priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_RGMII_ID
)
1113 priv
->rgmii_tx_delay
[port
] = true;
1115 if ((priv
->rgmii_rx_delay
[port
] || priv
->rgmii_tx_delay
[port
]) &&
1116 !priv
->info
->setup_rgmii_delay
)
1122 static int sja1105_parse_ports_node(struct sja1105_private
*priv
,
1123 struct device_node
*ports_node
)
1125 struct device
*dev
= &priv
->spidev
->dev
;
1126 struct device_node
*child
;
1128 for_each_available_child_of_node(ports_node
, child
) {
1129 struct device_node
*phy_node
;
1130 phy_interface_t phy_mode
;
1134 /* Get switch port number from DT */
1135 if (of_property_read_u32(child
, "reg", &index
) < 0) {
1136 dev_err(dev
, "Port number not defined in device tree "
1137 "(property \"reg\")\n");
1142 /* Get PHY mode from DT */
1143 err
= of_get_phy_mode(child
, &phy_mode
);
1145 dev_err(dev
, "Failed to read phy-mode or "
1146 "phy-interface-type property for port %d\n",
1152 phy_node
= of_parse_phandle(child
, "phy-handle", 0);
1154 if (!of_phy_is_fixed_link(child
)) {
1155 dev_err(dev
, "phy-handle or fixed-link "
1156 "properties missing!\n");
1160 /* phy-handle is missing, but fixed-link isn't.
1161 * So it's a fixed link. Default to PHY role.
1163 priv
->fixed_link
[index
] = true;
1165 of_node_put(phy_node
);
1168 priv
->phy_mode
[index
] = phy_mode
;
1174 static int sja1105_parse_dt(struct sja1105_private
*priv
)
1176 struct device
*dev
= &priv
->spidev
->dev
;
1177 struct device_node
*switch_node
= dev
->of_node
;
1178 struct device_node
*ports_node
;
1181 ports_node
= of_get_child_by_name(switch_node
, "ports");
1183 ports_node
= of_get_child_by_name(switch_node
, "ethernet-ports");
1185 dev_err(dev
, "Incorrect bindings: absent \"ports\" node\n");
1189 rc
= sja1105_parse_ports_node(priv
, ports_node
);
1190 of_node_put(ports_node
);
1195 /* Convert link speed from SJA1105 to ethtool encoding */
1196 static int sja1105_port_speed_to_ethtool(struct sja1105_private
*priv
,
1199 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_10MBPS
])
1201 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_100MBPS
])
1203 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
])
1205 if (speed
== priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
])
1207 return SPEED_UNKNOWN
;
1210 /* Set link speed in the MAC configuration for a specific port. */
1211 static int sja1105_adjust_port_config(struct sja1105_private
*priv
, int port
,
1214 struct sja1105_mac_config_entry
*mac
;
1215 struct device
*dev
= priv
->ds
->dev
;
1219 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1220 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1221 * We have to *know* what the MAC looks like. For the sake of keeping
1222 * the code common, we'll use the static configuration tables as a
1223 * reasonable approximation for both E/T and P/Q/R/S.
1225 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
1227 switch (speed_mbps
) {
1229 /* PHYLINK called sja1105_mac_config() to inform us about
1230 * the state->interface, but AN has not completed and the
1231 * speed is not yet valid. UM10944.pdf says that setting
1232 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1233 * ok for power consumption in case AN will never complete -
1234 * otherwise PHYLINK should come back with a new update.
1236 speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
];
1239 speed
= priv
->info
->port_speed
[SJA1105_SPEED_10MBPS
];
1242 speed
= priv
->info
->port_speed
[SJA1105_SPEED_100MBPS
];
1245 speed
= priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
];
1248 speed
= priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
];
1251 dev_err(dev
, "Invalid speed %iMbps\n", speed_mbps
);
1255 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1256 * table, since this will be used for the clocking setup, and we no
1257 * longer need to store it in the static config (already told hardware
1258 * we want auto during upload phase).
1259 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1260 * we need to configure the PCS only (if even that).
1262 if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_SGMII
)
1263 mac
[port
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_1000MBPS
];
1264 else if (priv
->phy_mode
[port
] == PHY_INTERFACE_MODE_2500BASEX
)
1265 mac
[port
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_2500MBPS
];
1267 mac
[port
].speed
= speed
;
1269 /* Write to the dynamic reconfiguration tables */
1270 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
1273 dev_err(dev
, "Failed to write MAC config: %d\n", rc
);
1277 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1278 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1279 * RMII no change of the clock setup is required. Actually, changing
1280 * the clock setup does interrupt the clock signal for a certain time
1281 * which causes trouble for all PHYs relying on this signal.
1283 if (!phy_interface_mode_is_rgmii(priv
->phy_mode
[port
]))
1286 return sja1105_clocking_setup_port(priv
, port
);
1289 /* The SJA1105 MAC programming model is through the static config (the xMII
1290 * Mode table cannot be dynamically reconfigured), and we have to program
1291 * that early (earlier than PHYLINK calls us, anyway).
1292 * So just error out in case the connected PHY attempts to change the initial
1293 * system interface MII protocol from what is defined in the DT, at least for
1296 static bool sja1105_phy_mode_mismatch(struct sja1105_private
*priv
, int port
,
1297 phy_interface_t interface
)
1299 return priv
->phy_mode
[port
] != interface
;
1302 static void sja1105_mac_config(struct dsa_switch
*ds
, int port
,
1304 const struct phylink_link_state
*state
)
1306 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
1307 struct sja1105_private
*priv
= ds
->priv
;
1308 struct dw_xpcs
*xpcs
;
1310 if (sja1105_phy_mode_mismatch(priv
, port
, state
->interface
)) {
1311 dev_err(ds
->dev
, "Changing PHY mode to %s not supported!\n",
1312 phy_modes(state
->interface
));
1316 xpcs
= priv
->xpcs
[port
];
1319 phylink_set_pcs(dp
->pl
, &xpcs
->pcs
);
1322 static void sja1105_mac_link_down(struct dsa_switch
*ds
, int port
,
1324 phy_interface_t interface
)
1326 sja1105_inhibit_tx(ds
->priv
, BIT(port
), true);
1329 static void sja1105_mac_link_up(struct dsa_switch
*ds
, int port
,
1331 phy_interface_t interface
,
1332 struct phy_device
*phydev
,
1333 int speed
, int duplex
,
1334 bool tx_pause
, bool rx_pause
)
1336 struct sja1105_private
*priv
= ds
->priv
;
1338 sja1105_adjust_port_config(priv
, port
, speed
);
1340 sja1105_inhibit_tx(priv
, BIT(port
), false);
1343 static void sja1105_phylink_validate(struct dsa_switch
*ds
, int port
,
1344 unsigned long *supported
,
1345 struct phylink_link_state
*state
)
1347 /* Construct a new mask which exhaustively contains all link features
1348 * supported by the MAC, and then apply that (logical AND) to what will
1349 * be sent to the PHY for "marketing".
1351 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1352 struct sja1105_private
*priv
= ds
->priv
;
1353 struct sja1105_xmii_params_entry
*mii
;
1355 mii
= priv
->static_config
.tables
[BLK_IDX_XMII_PARAMS
].entries
;
1357 /* include/linux/phylink.h says:
1358 * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1359 * expects the MAC driver to return all supported link modes.
1361 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1362 sja1105_phy_mode_mismatch(priv
, port
, state
->interface
)) {
1363 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1367 /* The MAC does not support pause frames, and also doesn't
1368 * support half-duplex traffic modes.
1370 phylink_set(mask
, Autoneg
);
1371 phylink_set(mask
, MII
);
1372 phylink_set(mask
, 10baseT_Full
);
1373 phylink_set(mask
, 100baseT_Full
);
1374 phylink_set(mask
, 100baseT1_Full
);
1375 if (mii
->xmii_mode
[port
] == XMII_MODE_RGMII
||
1376 mii
->xmii_mode
[port
] == XMII_MODE_SGMII
)
1377 phylink_set(mask
, 1000baseT_Full
);
1378 if (priv
->info
->supports_2500basex
[port
]) {
1379 phylink_set(mask
, 2500baseT_Full
);
1380 phylink_set(mask
, 2500baseX_Full
);
1383 bitmap_and(supported
, supported
, mask
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1384 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1385 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1389 sja1105_find_static_fdb_entry(struct sja1105_private
*priv
, int port
,
1390 const struct sja1105_l2_lookup_entry
*requested
)
1392 struct sja1105_l2_lookup_entry
*l2_lookup
;
1393 struct sja1105_table
*table
;
1396 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
1397 l2_lookup
= table
->entries
;
1399 for (i
= 0; i
< table
->entry_count
; i
++)
1400 if (l2_lookup
[i
].macaddr
== requested
->macaddr
&&
1401 l2_lookup
[i
].vlanid
== requested
->vlanid
&&
1402 l2_lookup
[i
].destports
& BIT(port
))
1408 /* We want FDB entries added statically through the bridge command to persist
1409 * across switch resets, which are a common thing during normal SJA1105
1410 * operation. So we have to back them up in the static configuration tables
1411 * and hence apply them on next static config upload... yay!
1414 sja1105_static_fdb_change(struct sja1105_private
*priv
, int port
,
1415 const struct sja1105_l2_lookup_entry
*requested
,
1418 struct sja1105_l2_lookup_entry
*l2_lookup
;
1419 struct sja1105_table
*table
;
1422 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
1424 match
= sja1105_find_static_fdb_entry(priv
, port
, requested
);
1426 /* Can't delete a missing entry. */
1430 /* No match => new entry */
1431 rc
= sja1105_table_resize(table
, table
->entry_count
+ 1);
1435 match
= table
->entry_count
- 1;
1438 /* Assign pointer after the resize (it may be new memory) */
1439 l2_lookup
= table
->entries
;
1442 * If the job was to add this FDB entry, it's already done (mostly
1443 * anyway, since the port forwarding mask may have changed, case in
1444 * which we update it).
1445 * Otherwise we have to delete it.
1448 l2_lookup
[match
] = *requested
;
1452 /* To remove, the strategy is to overwrite the element with
1453 * the last one, and then reduce the array size by 1
1455 l2_lookup
[match
] = l2_lookup
[table
->entry_count
- 1];
1456 return sja1105_table_resize(table
, table
->entry_count
- 1);
1459 /* First-generation switches have a 4-way set associative TCAM that
1460 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1461 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1462 * For the placement of a newly learnt FDB entry, the switch selects the bin
1463 * based on a hash function, and the way within that bin incrementally.
1465 static int sja1105et_fdb_index(int bin
, int way
)
1467 return bin
* SJA1105ET_FDB_BIN_SIZE
+ way
;
1470 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private
*priv
, int bin
,
1471 const u8
*addr
, u16 vid
,
1472 struct sja1105_l2_lookup_entry
*match
,
1477 for (way
= 0; way
< SJA1105ET_FDB_BIN_SIZE
; way
++) {
1478 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1479 int index
= sja1105et_fdb_index(bin
, way
);
1481 /* Skip unused entries, optionally marking them
1482 * into the return value
1484 if (sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1485 index
, &l2_lookup
)) {
1491 if (l2_lookup
.macaddr
== ether_addr_to_u64(addr
) &&
1492 l2_lookup
.vlanid
== vid
) {
1498 /* Return an invalid entry index if not found */
1502 int sja1105et_fdb_add(struct dsa_switch
*ds
, int port
,
1503 const unsigned char *addr
, u16 vid
)
1505 struct sja1105_l2_lookup_entry l2_lookup
= {0}, tmp
;
1506 struct sja1105_private
*priv
= ds
->priv
;
1507 struct device
*dev
= ds
->dev
;
1508 int last_unused
= -1;
1512 bin
= sja1105et_fdb_hash(priv
, addr
, vid
);
1514 way
= sja1105et_is_fdb_entry_in_bin(priv
, bin
, addr
, vid
,
1515 &l2_lookup
, &last_unused
);
1517 /* We have an FDB entry. Is our port in the destination
1518 * mask? If yes, we need to do nothing. If not, we need
1519 * to rewrite the entry by adding this port to it.
1521 if ((l2_lookup
.destports
& BIT(port
)) && l2_lookup
.lockeds
)
1523 l2_lookup
.destports
|= BIT(port
);
1525 int index
= sja1105et_fdb_index(bin
, way
);
1527 /* We don't have an FDB entry. We construct a new one and
1528 * try to find a place for it within the FDB table.
1530 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1531 l2_lookup
.destports
= BIT(port
);
1532 l2_lookup
.vlanid
= vid
;
1534 if (last_unused
>= 0) {
1537 /* Bin is full, need to evict somebody.
1538 * Choose victim at random. If you get these messages
1539 * often, you may need to consider changing the
1540 * distribution function:
1541 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1543 get_random_bytes(&way
, sizeof(u8
));
1544 way
%= SJA1105ET_FDB_BIN_SIZE
;
1545 dev_warn(dev
, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1548 sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1549 index
, NULL
, false);
1552 l2_lookup
.lockeds
= true;
1553 l2_lookup
.index
= sja1105et_fdb_index(bin
, way
);
1555 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1556 l2_lookup
.index
, &l2_lookup
,
1561 /* Invalidate a dynamically learned entry if that exists */
1562 start
= sja1105et_fdb_index(bin
, 0);
1563 end
= sja1105et_fdb_index(bin
, way
);
1565 for (i
= start
; i
< end
; i
++) {
1566 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1573 if (tmp
.macaddr
!= ether_addr_to_u64(addr
) || tmp
.vlanid
!= vid
)
1576 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1584 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, true);
1587 int sja1105et_fdb_del(struct dsa_switch
*ds
, int port
,
1588 const unsigned char *addr
, u16 vid
)
1590 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1591 struct sja1105_private
*priv
= ds
->priv
;
1592 int index
, bin
, way
, rc
;
1595 bin
= sja1105et_fdb_hash(priv
, addr
, vid
);
1596 way
= sja1105et_is_fdb_entry_in_bin(priv
, bin
, addr
, vid
,
1600 index
= sja1105et_fdb_index(bin
, way
);
1602 /* We have an FDB entry. Is our port in the destination mask? If yes,
1603 * we need to remove it. If the resulting port mask becomes empty, we
1604 * need to completely evict the FDB entry.
1605 * Otherwise we just write it back.
1607 l2_lookup
.destports
&= ~BIT(port
);
1609 if (l2_lookup
.destports
)
1614 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1615 index
, &l2_lookup
, keep
);
1619 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, keep
);
1622 int sja1105pqrs_fdb_add(struct dsa_switch
*ds
, int port
,
1623 const unsigned char *addr
, u16 vid
)
1625 struct sja1105_l2_lookup_entry l2_lookup
= {0}, tmp
;
1626 struct sja1105_private
*priv
= ds
->priv
;
1629 /* Search for an existing entry in the FDB table */
1630 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1631 l2_lookup
.vlanid
= vid
;
1632 l2_lookup
.mask_macaddr
= GENMASK_ULL(ETH_ALEN
* 8 - 1, 0);
1633 l2_lookup
.mask_vlanid
= VLAN_VID_MASK
;
1634 l2_lookup
.destports
= BIT(port
);
1638 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1639 SJA1105_SEARCH
, &tmp
);
1640 if (rc
== 0 && tmp
.index
!= SJA1105_MAX_L2_LOOKUP_COUNT
- 1) {
1641 /* Found a static entry and this port is already in the entry's
1642 * port mask => job done
1644 if ((tmp
.destports
& BIT(port
)) && tmp
.lockeds
)
1649 /* l2_lookup.index is populated by the switch in case it
1652 l2_lookup
.destports
|= BIT(port
);
1653 goto skip_finding_an_index
;
1656 /* Not found, so try to find an unused spot in the FDB.
1657 * This is slightly inefficient because the strategy is knock-knock at
1658 * every possible position from 0 to 1023.
1660 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1661 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1666 if (i
== SJA1105_MAX_L2_LOOKUP_COUNT
) {
1667 dev_err(ds
->dev
, "FDB is full, cannot add entry.\n");
1670 l2_lookup
.index
= i
;
1672 skip_finding_an_index
:
1673 l2_lookup
.lockeds
= true;
1675 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1676 l2_lookup
.index
, &l2_lookup
,
1681 /* The switch learns dynamic entries and looks up the FDB left to
1682 * right. It is possible that our addition was concurrent with the
1683 * dynamic learning of the same address, so now that the static entry
1684 * has been installed, we are certain that address learning for this
1685 * particular address has been turned off, so the dynamic entry either
1686 * is in the FDB at an index smaller than the static one, or isn't (it
1687 * can also be at a larger index, but in that case it is inactive
1688 * because the static FDB entry will match first, and the dynamic one
1689 * will eventually age out). Search for a dynamically learned address
1690 * prior to our static one and invalidate it.
1694 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1695 SJA1105_SEARCH
, &tmp
);
1698 "port %d failed to read back entry for %pM vid %d: %pe\n",
1699 port
, addr
, vid
, ERR_PTR(rc
));
1703 if (tmp
.index
< l2_lookup
.index
) {
1704 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1705 tmp
.index
, NULL
, false);
1710 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, true);
1713 int sja1105pqrs_fdb_del(struct dsa_switch
*ds
, int port
,
1714 const unsigned char *addr
, u16 vid
)
1716 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1717 struct sja1105_private
*priv
= ds
->priv
;
1721 l2_lookup
.macaddr
= ether_addr_to_u64(addr
);
1722 l2_lookup
.vlanid
= vid
;
1723 l2_lookup
.mask_macaddr
= GENMASK_ULL(ETH_ALEN
* 8 - 1, 0);
1724 l2_lookup
.mask_vlanid
= VLAN_VID_MASK
;
1725 l2_lookup
.destports
= BIT(port
);
1727 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1728 SJA1105_SEARCH
, &l2_lookup
);
1732 l2_lookup
.destports
&= ~BIT(port
);
1734 /* Decide whether we remove just this port from the FDB entry,
1735 * or if we remove it completely.
1737 if (l2_lookup
.destports
)
1742 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
1743 l2_lookup
.index
, &l2_lookup
, keep
);
1747 return sja1105_static_fdb_change(priv
, port
, &l2_lookup
, keep
);
1750 static int sja1105_fdb_add(struct dsa_switch
*ds
, int port
,
1751 const unsigned char *addr
, u16 vid
)
1753 struct sja1105_private
*priv
= ds
->priv
;
1755 return priv
->info
->fdb_add_cmd(ds
, port
, addr
, vid
);
1758 static int sja1105_fdb_del(struct dsa_switch
*ds
, int port
,
1759 const unsigned char *addr
, u16 vid
)
1761 struct sja1105_private
*priv
= ds
->priv
;
1763 return priv
->info
->fdb_del_cmd(ds
, port
, addr
, vid
);
1766 static int sja1105_fdb_dump(struct dsa_switch
*ds
, int port
,
1767 dsa_fdb_dump_cb_t
*cb
, void *data
)
1769 struct sja1105_private
*priv
= ds
->priv
;
1770 struct device
*dev
= ds
->dev
;
1773 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1774 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1775 u8 macaddr
[ETH_ALEN
];
1778 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1780 /* No fdb entry at i, not an issue */
1784 dev_err(dev
, "Failed to dump FDB: %d\n", rc
);
1788 /* FDB dump callback is per port. This means we have to
1789 * disregard a valid entry if it's not for this port, even if
1790 * only to revisit it later. This is inefficient because the
1791 * 1024-sized FDB table needs to be traversed 4 times through
1792 * SPI during a 'bridge fdb show' command.
1794 if (!(l2_lookup
.destports
& BIT(port
)))
1797 /* We need to hide the FDB entry for unknown multicast */
1798 if (l2_lookup
.macaddr
== SJA1105_UNKNOWN_MULTICAST
&&
1799 l2_lookup
.mask_macaddr
== SJA1105_UNKNOWN_MULTICAST
)
1802 u64_to_ether_addr(l2_lookup
.macaddr
, macaddr
);
1804 /* We need to hide the dsa_8021q VLANs from the user. */
1805 if (!priv
->vlan_aware
)
1806 l2_lookup
.vlanid
= 0;
1807 rc
= cb(macaddr
, l2_lookup
.vlanid
, l2_lookup
.lockeds
, data
);
1814 static void sja1105_fast_age(struct dsa_switch
*ds
, int port
)
1816 struct sja1105_private
*priv
= ds
->priv
;
1819 for (i
= 0; i
< SJA1105_MAX_L2_LOOKUP_COUNT
; i
++) {
1820 struct sja1105_l2_lookup_entry l2_lookup
= {0};
1821 u8 macaddr
[ETH_ALEN
];
1824 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_L2_LOOKUP
,
1826 /* No fdb entry at i, not an issue */
1830 dev_err(ds
->dev
, "Failed to read FDB: %pe\n",
1835 if (!(l2_lookup
.destports
& BIT(port
)))
1838 /* Don't delete static FDB entries */
1839 if (l2_lookup
.lockeds
)
1842 u64_to_ether_addr(l2_lookup
.macaddr
, macaddr
);
1844 rc
= sja1105_fdb_del(ds
, port
, macaddr
, l2_lookup
.vlanid
);
1847 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1848 macaddr
, l2_lookup
.vlanid
, ERR_PTR(rc
));
1854 static int sja1105_mdb_add(struct dsa_switch
*ds
, int port
,
1855 const struct switchdev_obj_port_mdb
*mdb
)
1857 return sja1105_fdb_add(ds
, port
, mdb
->addr
, mdb
->vid
);
1860 static int sja1105_mdb_del(struct dsa_switch
*ds
, int port
,
1861 const struct switchdev_obj_port_mdb
*mdb
)
1863 return sja1105_fdb_del(ds
, port
, mdb
->addr
, mdb
->vid
);
1866 /* Common function for unicast and broadcast flood configuration.
1867 * Flooding is configured between each {ingress, egress} port pair, and since
1868 * the bridge's semantics are those of "egress flooding", it means we must
1869 * enable flooding towards this port from all ingress ports that are in the
1870 * same forwarding domain.
1872 static int sja1105_manage_flood_domains(struct sja1105_private
*priv
)
1874 struct sja1105_l2_forwarding_entry
*l2_fwd
;
1875 struct dsa_switch
*ds
= priv
->ds
;
1878 l2_fwd
= priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
].entries
;
1880 for (from
= 0; from
< ds
->num_ports
; from
++) {
1881 u64 fl_domain
= 0, bc_domain
= 0;
1883 for (to
= 0; to
< priv
->ds
->num_ports
; to
++) {
1884 if (!sja1105_can_forward(l2_fwd
, from
, to
))
1887 if (priv
->ucast_egress_floods
& BIT(to
))
1888 fl_domain
|= BIT(to
);
1889 if (priv
->bcast_egress_floods
& BIT(to
))
1890 bc_domain
|= BIT(to
);
1893 /* Nothing changed, nothing to do */
1894 if (l2_fwd
[from
].fl_domain
== fl_domain
&&
1895 l2_fwd
[from
].bc_domain
== bc_domain
)
1898 l2_fwd
[from
].fl_domain
= fl_domain
;
1899 l2_fwd
[from
].bc_domain
= bc_domain
;
1901 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1902 from
, &l2_fwd
[from
], true);
1910 static int sja1105_bridge_member(struct dsa_switch
*ds
, int port
,
1911 struct net_device
*br
, bool member
)
1913 struct sja1105_l2_forwarding_entry
*l2_fwd
;
1914 struct sja1105_private
*priv
= ds
->priv
;
1917 l2_fwd
= priv
->static_config
.tables
[BLK_IDX_L2_FORWARDING
].entries
;
1919 for (i
= 0; i
< ds
->num_ports
; i
++) {
1920 /* Add this port to the forwarding matrix of the
1921 * other ports in the same bridge, and viceversa.
1923 if (!dsa_is_user_port(ds
, i
))
1925 /* For the ports already under the bridge, only one thing needs
1926 * to be done, and that is to add this port to their
1927 * reachability domain. So we can perform the SPI write for
1928 * them immediately. However, for this port itself (the one
1929 * that is new to the bridge), we need to add all other ports
1930 * to its reachability domain. So we do that incrementally in
1931 * this loop, and perform the SPI write only at the end, once
1932 * the domain contains all other bridge ports.
1936 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1938 sja1105_port_allow_traffic(l2_fwd
, i
, port
, member
);
1939 sja1105_port_allow_traffic(l2_fwd
, port
, i
, member
);
1941 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1942 i
, &l2_fwd
[i
], true);
1947 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_L2_FORWARDING
,
1948 port
, &l2_fwd
[port
], true);
1952 rc
= sja1105_commit_pvid(ds
, port
);
1956 return sja1105_manage_flood_domains(priv
);
1959 static void sja1105_bridge_stp_state_set(struct dsa_switch
*ds
, int port
,
1962 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
1963 struct sja1105_private
*priv
= ds
->priv
;
1964 struct sja1105_mac_config_entry
*mac
;
1966 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
1969 case BR_STATE_DISABLED
:
1970 case BR_STATE_BLOCKING
:
1971 /* From UM10944 description of DRPDTAG (why put this there?):
1972 * "Management traffic flows to the port regardless of the state
1973 * of the INGRESS flag". So BPDUs are still be allowed to pass.
1974 * At the moment no difference between DISABLED and BLOCKING.
1976 mac
[port
].ingress
= false;
1977 mac
[port
].egress
= false;
1978 mac
[port
].dyn_learn
= false;
1980 case BR_STATE_LISTENING
:
1981 mac
[port
].ingress
= true;
1982 mac
[port
].egress
= false;
1983 mac
[port
].dyn_learn
= false;
1985 case BR_STATE_LEARNING
:
1986 mac
[port
].ingress
= true;
1987 mac
[port
].egress
= false;
1988 mac
[port
].dyn_learn
= dp
->learning
;
1990 case BR_STATE_FORWARDING
:
1991 mac
[port
].ingress
= true;
1992 mac
[port
].egress
= true;
1993 mac
[port
].dyn_learn
= dp
->learning
;
1996 dev_err(ds
->dev
, "invalid STP state: %d\n", state
);
2000 sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
2004 static int sja1105_bridge_join(struct dsa_switch
*ds
, int port
,
2005 struct net_device
*br
)
2007 return sja1105_bridge_member(ds
, port
, br
, true);
2010 static void sja1105_bridge_leave(struct dsa_switch
*ds
, int port
,
2011 struct net_device
*br
)
2013 sja1105_bridge_member(ds
, port
, br
, false);
2016 #define BYTES_PER_KBIT (1000LL / 8)
2018 static int sja1105_find_unused_cbs_shaper(struct sja1105_private
*priv
)
2022 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++)
2023 if (!priv
->cbs
[i
].idle_slope
&& !priv
->cbs
[i
].send_slope
)
2029 static int sja1105_delete_cbs_shaper(struct sja1105_private
*priv
, int port
,
2034 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++) {
2035 struct sja1105_cbs_entry
*cbs
= &priv
->cbs
[i
];
2037 if (cbs
->port
== port
&& cbs
->prio
== prio
) {
2038 memset(cbs
, 0, sizeof(*cbs
));
2039 return sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
,
2047 static int sja1105_setup_tc_cbs(struct dsa_switch
*ds
, int port
,
2048 struct tc_cbs_qopt_offload
*offload
)
2050 struct sja1105_private
*priv
= ds
->priv
;
2051 struct sja1105_cbs_entry
*cbs
;
2054 if (!offload
->enable
)
2055 return sja1105_delete_cbs_shaper(priv
, port
, offload
->queue
);
2057 index
= sja1105_find_unused_cbs_shaper(priv
);
2061 cbs
= &priv
->cbs
[index
];
2063 cbs
->prio
= offload
->queue
;
2064 /* locredit and sendslope are negative by definition. In hardware,
2065 * positive values must be provided, and the negative sign is implicit.
2067 cbs
->credit_hi
= offload
->hicredit
;
2068 cbs
->credit_lo
= abs(offload
->locredit
);
2069 /* User space is in kbits/sec, hardware in bytes/sec */
2070 cbs
->idle_slope
= offload
->idleslope
* BYTES_PER_KBIT
;
2071 cbs
->send_slope
= abs(offload
->sendslope
* BYTES_PER_KBIT
);
2072 /* Convert the negative values from 64-bit 2's complement
2073 * to 32-bit 2's complement (for the case of 0x80000000 whose
2074 * negative is still negative).
2076 cbs
->credit_lo
&= GENMASK_ULL(31, 0);
2077 cbs
->send_slope
&= GENMASK_ULL(31, 0);
2079 return sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
, index
, cbs
,
2083 static int sja1105_reload_cbs(struct sja1105_private
*priv
)
2087 /* The credit based shapers are only allocated if
2088 * CONFIG_NET_SCH_CBS is enabled.
2093 for (i
= 0; i
< priv
->info
->num_cbs_shapers
; i
++) {
2094 struct sja1105_cbs_entry
*cbs
= &priv
->cbs
[i
];
2096 if (!cbs
->idle_slope
&& !cbs
->send_slope
)
2099 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_CBS
, i
, cbs
,
2108 static const char * const sja1105_reset_reasons
[] = {
2109 [SJA1105_VLAN_FILTERING
] = "VLAN filtering",
2110 [SJA1105_RX_HWTSTAMPING
] = "RX timestamping",
2111 [SJA1105_AGEING_TIME
] = "Ageing time",
2112 [SJA1105_SCHEDULING
] = "Time-aware scheduling",
2113 [SJA1105_BEST_EFFORT_POLICING
] = "Best-effort policing",
2114 [SJA1105_VIRTUAL_LINKS
] = "Virtual links",
2117 /* For situations where we need to change a setting at runtime that is only
2118 * available through the static configuration, resetting the switch in order
2119 * to upload the new static config is unavoidable. Back up the settings we
2120 * modify at runtime (currently only MAC) and restore them after uploading,
2121 * such that this operation is relatively seamless.
2123 int sja1105_static_config_reload(struct sja1105_private
*priv
,
2124 enum sja1105_reset_reason reason
)
2126 struct ptp_system_timestamp ptp_sts_before
;
2127 struct ptp_system_timestamp ptp_sts_after
;
2128 int speed_mbps
[SJA1105_MAX_NUM_PORTS
];
2129 u16 bmcr
[SJA1105_MAX_NUM_PORTS
] = {0};
2130 struct sja1105_mac_config_entry
*mac
;
2131 struct dsa_switch
*ds
= priv
->ds
;
2137 mutex_lock(&priv
->mgmt_lock
);
2139 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2141 /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2142 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2143 * switch wants to see in the static config in order to allow us to
2144 * change it through the dynamic interface later.
2146 for (i
= 0; i
< ds
->num_ports
; i
++) {
2147 u32 reg_addr
= mdiobus_c45_addr(MDIO_MMD_VEND2
, MDIO_CTRL1
);
2149 speed_mbps
[i
] = sja1105_port_speed_to_ethtool(priv
,
2151 mac
[i
].speed
= priv
->info
->port_speed
[SJA1105_SPEED_AUTO
];
2154 bmcr
[i
] = mdiobus_read(priv
->mdio_pcs
, i
, reg_addr
);
2157 /* No PTP operations can run right now */
2158 mutex_lock(&priv
->ptp_data
.lock
);
2160 rc
= __sja1105_ptp_gettimex(ds
, &now
, &ptp_sts_before
);
2162 mutex_unlock(&priv
->ptp_data
.lock
);
2166 /* Reset switch and send updated static configuration */
2167 rc
= sja1105_static_config_upload(priv
);
2169 mutex_unlock(&priv
->ptp_data
.lock
);
2173 rc
= __sja1105_ptp_settime(ds
, 0, &ptp_sts_after
);
2175 mutex_unlock(&priv
->ptp_data
.lock
);
2179 t1
= timespec64_to_ns(&ptp_sts_before
.pre_ts
);
2180 t2
= timespec64_to_ns(&ptp_sts_before
.post_ts
);
2181 t3
= timespec64_to_ns(&ptp_sts_after
.pre_ts
);
2182 t4
= timespec64_to_ns(&ptp_sts_after
.post_ts
);
2183 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2184 t12
= t1
+ (t2
- t1
) / 2;
2185 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2186 t34
= t3
+ (t4
- t3
) / 2;
2187 /* Advance PTPCLKVAL by the time it took since its readout */
2190 __sja1105_ptp_adjtime(ds
, now
);
2192 mutex_unlock(&priv
->ptp_data
.lock
);
2194 dev_info(priv
->ds
->dev
,
2195 "Reset switch and programmed static config. Reason: %s\n",
2196 sja1105_reset_reasons
[reason
]);
2198 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2199 * For these interfaces there is no dynamic configuration
2200 * needed, since PLLs have same settings at all speeds.
2202 if (priv
->info
->clocking_setup
) {
2203 rc
= priv
->info
->clocking_setup(priv
);
2208 for (i
= 0; i
< ds
->num_ports
; i
++) {
2209 struct dw_xpcs
*xpcs
= priv
->xpcs
[i
];
2212 rc
= sja1105_adjust_port_config(priv
, i
, speed_mbps
[i
]);
2219 if (bmcr
[i
] & BMCR_ANENABLE
)
2220 mode
= MLO_AN_INBAND
;
2221 else if (priv
->fixed_link
[i
])
2222 mode
= MLO_AN_FIXED
;
2226 rc
= xpcs_do_config(xpcs
, priv
->phy_mode
[i
], mode
);
2230 if (!phylink_autoneg_inband(mode
)) {
2231 int speed
= SPEED_UNKNOWN
;
2233 if (priv
->phy_mode
[i
] == PHY_INTERFACE_MODE_2500BASEX
)
2235 else if (bmcr
[i
] & BMCR_SPEED1000
)
2237 else if (bmcr
[i
] & BMCR_SPEED100
)
2242 xpcs_link_up(&xpcs
->pcs
, mode
, priv
->phy_mode
[i
],
2243 speed
, DUPLEX_FULL
);
2247 rc
= sja1105_reload_cbs(priv
);
2251 mutex_unlock(&priv
->mgmt_lock
);
2256 static enum dsa_tag_protocol
2257 sja1105_get_tag_protocol(struct dsa_switch
*ds
, int port
,
2258 enum dsa_tag_protocol mp
)
2260 struct sja1105_private
*priv
= ds
->priv
;
2262 return priv
->info
->tag_proto
;
2265 /* The TPID setting belongs to the General Parameters table,
2266 * which can only be partially reconfigured at runtime (and not the TPID).
2267 * So a switch reset is required.
2269 int sja1105_vlan_filtering(struct dsa_switch
*ds
, int port
, bool enabled
,
2270 struct netlink_ext_ack
*extack
)
2272 struct sja1105_l2_lookup_params_entry
*l2_lookup_params
;
2273 struct sja1105_general_params_entry
*general_params
;
2274 struct sja1105_private
*priv
= ds
->priv
;
2275 struct sja1105_table
*table
;
2276 struct sja1105_rule
*rule
;
2280 list_for_each_entry(rule
, &priv
->flow_block
.rules
, list
) {
2281 if (rule
->type
== SJA1105_RULE_VL
) {
2282 NL_SET_ERR_MSG_MOD(extack
,
2283 "Cannot change VLAN filtering with active VL rules");
2289 /* Enable VLAN filtering. */
2291 tpid2
= ETH_P_8021AD
;
2293 /* Disable VLAN filtering. */
2294 tpid
= ETH_P_SJA1105
;
2295 tpid2
= ETH_P_SJA1105
;
2298 if (priv
->vlan_aware
== enabled
)
2301 priv
->vlan_aware
= enabled
;
2303 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
2304 general_params
= table
->entries
;
2305 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2306 general_params
->tpid
= tpid
;
2307 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2308 general_params
->tpid2
= tpid2
;
2309 /* When VLAN filtering is on, we need to at least be able to
2310 * decode management traffic through the "backup plan".
2312 general_params
->incl_srcpt1
= enabled
;
2313 general_params
->incl_srcpt0
= enabled
;
2315 /* VLAN filtering => independent VLAN learning.
2316 * No VLAN filtering (or best effort) => shared VLAN learning.
2318 * In shared VLAN learning mode, untagged traffic still gets
2319 * pvid-tagged, and the FDB table gets populated with entries
2320 * containing the "real" (pvid or from VLAN tag) VLAN ID.
2321 * However the switch performs a masked L2 lookup in the FDB,
2322 * effectively only looking up a frame's DMAC (and not VID) for the
2323 * forwarding decision.
2325 * This is extremely convenient for us, because in modes with
2326 * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2327 * each front panel port. This is good for identification but breaks
2328 * learning badly - the VID of the learnt FDB entry is unique, aka
2329 * no frames coming from any other port are going to have it. So
2330 * for forwarding purposes, this is as though learning was broken
2331 * (all frames get flooded).
2333 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
2334 l2_lookup_params
= table
->entries
;
2335 l2_lookup_params
->shared_learn
= !priv
->vlan_aware
;
2337 for (port
= 0; port
< ds
->num_ports
; port
++) {
2338 if (dsa_is_unused_port(ds
, port
))
2341 rc
= sja1105_commit_pvid(ds
, port
);
2346 rc
= sja1105_static_config_reload(priv
, SJA1105_VLAN_FILTERING
);
2348 NL_SET_ERR_MSG_MOD(extack
, "Failed to change VLAN Ethertype");
2353 static int sja1105_vlan_add(struct sja1105_private
*priv
, int port
, u16 vid
,
2354 u16 flags
, bool allowed_ingress
)
2356 struct sja1105_vlan_lookup_entry
*vlan
;
2357 struct sja1105_table
*table
;
2360 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
2362 match
= sja1105_is_vlan_configured(priv
, vid
);
2364 rc
= sja1105_table_resize(table
, table
->entry_count
+ 1);
2367 match
= table
->entry_count
- 1;
2370 /* Assign pointer after the resize (it's new memory) */
2371 vlan
= table
->entries
;
2373 vlan
[match
].type_entry
= SJA1110_VLAN_D_TAG
;
2374 vlan
[match
].vlanid
= vid
;
2375 vlan
[match
].vlan_bc
|= BIT(port
);
2377 if (allowed_ingress
)
2378 vlan
[match
].vmemb_port
|= BIT(port
);
2380 vlan
[match
].vmemb_port
&= ~BIT(port
);
2382 if (flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
2383 vlan
[match
].tag_port
&= ~BIT(port
);
2385 vlan
[match
].tag_port
|= BIT(port
);
2387 return sja1105_dynamic_config_write(priv
, BLK_IDX_VLAN_LOOKUP
, vid
,
2388 &vlan
[match
], true);
2391 static int sja1105_vlan_del(struct sja1105_private
*priv
, int port
, u16 vid
)
2393 struct sja1105_vlan_lookup_entry
*vlan
;
2394 struct sja1105_table
*table
;
2398 table
= &priv
->static_config
.tables
[BLK_IDX_VLAN_LOOKUP
];
2400 match
= sja1105_is_vlan_configured(priv
, vid
);
2401 /* Can't delete a missing entry. */
2405 /* Assign pointer after the resize (it's new memory) */
2406 vlan
= table
->entries
;
2408 vlan
[match
].vlanid
= vid
;
2409 vlan
[match
].vlan_bc
&= ~BIT(port
);
2410 vlan
[match
].vmemb_port
&= ~BIT(port
);
2411 /* Also unset tag_port, just so we don't have a confusing bitmap
2412 * (no practical purpose).
2414 vlan
[match
].tag_port
&= ~BIT(port
);
2416 /* If there's no port left as member of this VLAN,
2417 * it's time for it to go.
2419 if (!vlan
[match
].vmemb_port
)
2422 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_VLAN_LOOKUP
, vid
,
2423 &vlan
[match
], keep
);
2428 return sja1105_table_delete_entry(table
, match
);
2433 static int sja1105_bridge_vlan_add(struct dsa_switch
*ds
, int port
,
2434 const struct switchdev_obj_port_vlan
*vlan
,
2435 struct netlink_ext_ack
*extack
)
2437 struct sja1105_private
*priv
= ds
->priv
;
2438 u16 flags
= vlan
->flags
;
2441 /* Be sure to deny alterations to the configuration done by tag_8021q.
2443 if (vid_is_dsa_8021q(vlan
->vid
)) {
2444 NL_SET_ERR_MSG_MOD(extack
,
2445 "Range 1024-3071 reserved for dsa_8021q operation");
2449 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2450 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
2453 rc
= sja1105_vlan_add(priv
, port
, vlan
->vid
, flags
, true);
2457 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
)
2458 priv
->bridge_pvid
[port
] = vlan
->vid
;
2460 return sja1105_commit_pvid(ds
, port
);
2463 static int sja1105_bridge_vlan_del(struct dsa_switch
*ds
, int port
,
2464 const struct switchdev_obj_port_vlan
*vlan
)
2466 struct sja1105_private
*priv
= ds
->priv
;
2469 rc
= sja1105_vlan_del(priv
, port
, vlan
->vid
);
2473 /* In case the pvid was deleted, make sure that untagged packets will
2476 return sja1105_commit_pvid(ds
, port
);
2479 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch
*ds
, int port
, u16 vid
,
2482 struct sja1105_private
*priv
= ds
->priv
;
2483 bool allowed_ingress
= true;
2486 /* Prevent attackers from trying to inject a DSA tag from
2487 * the outside world.
2489 if (dsa_is_user_port(ds
, port
))
2490 allowed_ingress
= false;
2492 rc
= sja1105_vlan_add(priv
, port
, vid
, flags
, allowed_ingress
);
2496 if (flags
& BRIDGE_VLAN_INFO_PVID
)
2497 priv
->tag_8021q_pvid
[port
] = vid
;
2499 return sja1105_commit_pvid(ds
, port
);
2502 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch
*ds
, int port
, u16 vid
)
2504 struct sja1105_private
*priv
= ds
->priv
;
2506 return sja1105_vlan_del(priv
, port
, vid
);
2509 static int sja1105_prechangeupper(struct dsa_switch
*ds
, int port
,
2510 struct netdev_notifier_changeupper_info
*info
)
2512 struct netlink_ext_ack
*extack
= info
->info
.extack
;
2513 struct net_device
*upper
= info
->upper_dev
;
2514 struct dsa_switch_tree
*dst
= ds
->dst
;
2515 struct dsa_port
*dp
;
2517 if (is_vlan_dev(upper
)) {
2518 NL_SET_ERR_MSG_MOD(extack
, "8021q uppers are not supported");
2522 if (netif_is_bridge_master(upper
)) {
2523 list_for_each_entry(dp
, &dst
->ports
, list
) {
2524 if (dp
->bridge_dev
&& dp
->bridge_dev
!= upper
&&
2525 br_vlan_enabled(dp
->bridge_dev
)) {
2526 NL_SET_ERR_MSG_MOD(extack
,
2527 "Only one VLAN-aware bridge is supported");
2536 static void sja1105_port_disable(struct dsa_switch
*ds
, int port
)
2538 struct sja1105_private
*priv
= ds
->priv
;
2539 struct sja1105_port
*sp
= &priv
->ports
[port
];
2541 if (!dsa_is_user_port(ds
, port
))
2544 kthread_cancel_work_sync(&sp
->xmit_work
);
2545 skb_queue_purge(&sp
->xmit_queue
);
2548 static int sja1105_mgmt_xmit(struct dsa_switch
*ds
, int port
, int slot
,
2549 struct sk_buff
*skb
, bool takets
)
2551 struct sja1105_mgmt_entry mgmt_route
= {0};
2552 struct sja1105_private
*priv
= ds
->priv
;
2559 mgmt_route
.macaddr
= ether_addr_to_u64(hdr
->h_dest
);
2560 mgmt_route
.destports
= BIT(port
);
2561 mgmt_route
.enfport
= 1;
2562 mgmt_route
.tsreg
= 0;
2563 mgmt_route
.takets
= takets
;
2565 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_MGMT_ROUTE
,
2566 slot
, &mgmt_route
, true);
2572 /* Transfer skb to the host port. */
2573 dsa_enqueue_skb(skb
, dsa_to_port(ds
, port
)->slave
);
2575 /* Wait until the switch has processed the frame */
2577 rc
= sja1105_dynamic_config_read(priv
, BLK_IDX_MGMT_ROUTE
,
2580 dev_err_ratelimited(priv
->ds
->dev
,
2581 "failed to poll for mgmt route\n");
2585 /* UM10944: The ENFPORT flag of the respective entry is
2586 * cleared when a match is found. The host can use this
2587 * flag as an acknowledgment.
2590 } while (mgmt_route
.enfport
&& --timeout
);
2593 /* Clean up the management route so that a follow-up
2594 * frame may not match on it by mistake.
2595 * This is only hardware supported on P/Q/R/S - on E/T it is
2596 * a no-op and we are silently discarding the -EOPNOTSUPP.
2598 sja1105_dynamic_config_write(priv
, BLK_IDX_MGMT_ROUTE
,
2599 slot
, &mgmt_route
, false);
2600 dev_err_ratelimited(priv
->ds
->dev
, "xmit timed out\n");
2603 return NETDEV_TX_OK
;
2606 #define work_to_port(work) \
2607 container_of((work), struct sja1105_port, xmit_work)
2608 #define tagger_to_sja1105(t) \
2609 container_of((t), struct sja1105_private, tagger_data)
2611 /* Deferred work is unfortunately necessary because setting up the management
2612 * route cannot be done from atomit context (SPI transfer takes a sleepable
2615 static void sja1105_port_deferred_xmit(struct kthread_work
*work
)
2617 struct sja1105_port
*sp
= work_to_port(work
);
2618 struct sja1105_tagger_data
*tagger_data
= sp
->data
;
2619 struct sja1105_private
*priv
= tagger_to_sja1105(tagger_data
);
2620 int port
= sp
- priv
->ports
;
2621 struct sk_buff
*skb
;
2623 while ((skb
= skb_dequeue(&sp
->xmit_queue
)) != NULL
) {
2624 struct sk_buff
*clone
= SJA1105_SKB_CB(skb
)->clone
;
2626 mutex_lock(&priv
->mgmt_lock
);
2628 sja1105_mgmt_xmit(priv
->ds
, port
, 0, skb
, !!clone
);
2630 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2632 sja1105_ptp_txtstamp_skb(priv
->ds
, port
, clone
);
2634 mutex_unlock(&priv
->mgmt_lock
);
2638 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2639 * which cannot be reconfigured at runtime. So a switch reset is required.
2641 static int sja1105_set_ageing_time(struct dsa_switch
*ds
,
2642 unsigned int ageing_time
)
2644 struct sja1105_l2_lookup_params_entry
*l2_lookup_params
;
2645 struct sja1105_private
*priv
= ds
->priv
;
2646 struct sja1105_table
*table
;
2647 unsigned int maxage
;
2649 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP_PARAMS
];
2650 l2_lookup_params
= table
->entries
;
2652 maxage
= SJA1105_AGEING_TIME_MS(ageing_time
);
2654 if (l2_lookup_params
->maxage
== maxage
)
2657 l2_lookup_params
->maxage
= maxage
;
2659 return sja1105_static_config_reload(priv
, SJA1105_AGEING_TIME
);
2662 static int sja1105_change_mtu(struct dsa_switch
*ds
, int port
, int new_mtu
)
2664 struct sja1105_l2_policing_entry
*policing
;
2665 struct sja1105_private
*priv
= ds
->priv
;
2667 new_mtu
+= VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
2669 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
))
2670 new_mtu
+= VLAN_HLEN
;
2672 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2674 if (policing
[port
].maxlen
== new_mtu
)
2677 policing
[port
].maxlen
= new_mtu
;
2679 return sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2682 static int sja1105_get_max_mtu(struct dsa_switch
*ds
, int port
)
2684 return 2043 - VLAN_ETH_HLEN
- ETH_FCS_LEN
;
2687 static int sja1105_port_setup_tc(struct dsa_switch
*ds
, int port
,
2688 enum tc_setup_type type
,
2692 case TC_SETUP_QDISC_TAPRIO
:
2693 return sja1105_setup_tc_taprio(ds
, port
, type_data
);
2694 case TC_SETUP_QDISC_CBS
:
2695 return sja1105_setup_tc_cbs(ds
, port
, type_data
);
2701 /* We have a single mirror (@to) port, but can configure ingress and egress
2702 * mirroring on all other (@from) ports.
2703 * We need to allow mirroring rules only as long as the @to port is always the
2704 * same, and we need to unset the @to port from mirr_port only when there is no
2705 * mirroring rule that references it.
2707 static int sja1105_mirror_apply(struct sja1105_private
*priv
, int from
, int to
,
2708 bool ingress
, bool enabled
)
2710 struct sja1105_general_params_entry
*general_params
;
2711 struct sja1105_mac_config_entry
*mac
;
2712 struct dsa_switch
*ds
= priv
->ds
;
2713 struct sja1105_table
*table
;
2714 bool already_enabled
;
2718 table
= &priv
->static_config
.tables
[BLK_IDX_GENERAL_PARAMS
];
2719 general_params
= table
->entries
;
2721 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2723 already_enabled
= (general_params
->mirr_port
!= ds
->num_ports
);
2724 if (already_enabled
&& enabled
&& general_params
->mirr_port
!= to
) {
2725 dev_err(priv
->ds
->dev
,
2726 "Delete mirroring rules towards port %llu first\n",
2727 general_params
->mirr_port
);
2736 /* Anybody still referencing mirr_port? */
2737 for (port
= 0; port
< ds
->num_ports
; port
++) {
2738 if (mac
[port
].ing_mirr
|| mac
[port
].egr_mirr
) {
2743 /* Unset already_enabled for next time */
2745 new_mirr_port
= ds
->num_ports
;
2747 if (new_mirr_port
!= general_params
->mirr_port
) {
2748 general_params
->mirr_port
= new_mirr_port
;
2750 rc
= sja1105_dynamic_config_write(priv
, BLK_IDX_GENERAL_PARAMS
,
2751 0, general_params
, true);
2757 mac
[from
].ing_mirr
= enabled
;
2759 mac
[from
].egr_mirr
= enabled
;
2761 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, from
,
2765 static int sja1105_mirror_add(struct dsa_switch
*ds
, int port
,
2766 struct dsa_mall_mirror_tc_entry
*mirror
,
2769 return sja1105_mirror_apply(ds
->priv
, port
, mirror
->to_local_port
,
2773 static void sja1105_mirror_del(struct dsa_switch
*ds
, int port
,
2774 struct dsa_mall_mirror_tc_entry
*mirror
)
2776 sja1105_mirror_apply(ds
->priv
, port
, mirror
->to_local_port
,
2777 mirror
->ingress
, false);
2780 static int sja1105_port_policer_add(struct dsa_switch
*ds
, int port
,
2781 struct dsa_mall_policer_tc_entry
*policer
)
2783 struct sja1105_l2_policing_entry
*policing
;
2784 struct sja1105_private
*priv
= ds
->priv
;
2786 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2788 /* In hardware, every 8 microseconds the credit level is incremented by
2789 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2792 policing
[port
].rate
= div_u64(512 * policer
->rate_bytes_per_sec
,
2794 policing
[port
].smax
= policer
->burst
;
2796 return sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2799 static void sja1105_port_policer_del(struct dsa_switch
*ds
, int port
)
2801 struct sja1105_l2_policing_entry
*policing
;
2802 struct sja1105_private
*priv
= ds
->priv
;
2804 policing
= priv
->static_config
.tables
[BLK_IDX_L2_POLICING
].entries
;
2806 policing
[port
].rate
= SJA1105_RATE_MBPS(1000);
2807 policing
[port
].smax
= 65535;
2809 sja1105_static_config_reload(priv
, SJA1105_BEST_EFFORT_POLICING
);
2812 static int sja1105_port_set_learning(struct sja1105_private
*priv
, int port
,
2815 struct sja1105_mac_config_entry
*mac
;
2817 mac
= priv
->static_config
.tables
[BLK_IDX_MAC_CONFIG
].entries
;
2819 mac
[port
].dyn_learn
= enabled
;
2821 return sja1105_dynamic_config_write(priv
, BLK_IDX_MAC_CONFIG
, port
,
2825 static int sja1105_port_ucast_bcast_flood(struct sja1105_private
*priv
, int to
,
2826 struct switchdev_brport_flags flags
)
2828 if (flags
.mask
& BR_FLOOD
) {
2829 if (flags
.val
& BR_FLOOD
)
2830 priv
->ucast_egress_floods
|= BIT(to
);
2832 priv
->ucast_egress_floods
&= ~BIT(to
);
2835 if (flags
.mask
& BR_BCAST_FLOOD
) {
2836 if (flags
.val
& BR_BCAST_FLOOD
)
2837 priv
->bcast_egress_floods
|= BIT(to
);
2839 priv
->bcast_egress_floods
&= ~BIT(to
);
2842 return sja1105_manage_flood_domains(priv
);
2845 static int sja1105_port_mcast_flood(struct sja1105_private
*priv
, int to
,
2846 struct switchdev_brport_flags flags
,
2847 struct netlink_ext_ack
*extack
)
2849 struct sja1105_l2_lookup_entry
*l2_lookup
;
2850 struct sja1105_table
*table
;
2853 table
= &priv
->static_config
.tables
[BLK_IDX_L2_LOOKUP
];
2854 l2_lookup
= table
->entries
;
2856 for (match
= 0; match
< table
->entry_count
; match
++)
2857 if (l2_lookup
[match
].macaddr
== SJA1105_UNKNOWN_MULTICAST
&&
2858 l2_lookup
[match
].mask_macaddr
== SJA1105_UNKNOWN_MULTICAST
)
2861 if (match
== table
->entry_count
) {
2862 NL_SET_ERR_MSG_MOD(extack
,
2863 "Could not find FDB entry for unknown multicast");
2867 if (flags
.val
& BR_MCAST_FLOOD
)
2868 l2_lookup
[match
].destports
|= BIT(to
);
2870 l2_lookup
[match
].destports
&= ~BIT(to
);
2872 return sja1105_dynamic_config_write(priv
, BLK_IDX_L2_LOOKUP
,
2873 l2_lookup
[match
].index
,
2878 static int sja1105_port_pre_bridge_flags(struct dsa_switch
*ds
, int port
,
2879 struct switchdev_brport_flags flags
,
2880 struct netlink_ext_ack
*extack
)
2882 struct sja1105_private
*priv
= ds
->priv
;
2884 if (flags
.mask
& ~(BR_LEARNING
| BR_FLOOD
| BR_MCAST_FLOOD
|
2888 if (flags
.mask
& (BR_FLOOD
| BR_MCAST_FLOOD
) &&
2889 !priv
->info
->can_limit_mcast_flood
) {
2890 bool multicast
= !!(flags
.val
& BR_MCAST_FLOOD
);
2891 bool unicast
= !!(flags
.val
& BR_FLOOD
);
2893 if (unicast
!= multicast
) {
2894 NL_SET_ERR_MSG_MOD(extack
,
2895 "This chip cannot configure multicast flooding independently of unicast");
2903 static int sja1105_port_bridge_flags(struct dsa_switch
*ds
, int port
,
2904 struct switchdev_brport_flags flags
,
2905 struct netlink_ext_ack
*extack
)
2907 struct sja1105_private
*priv
= ds
->priv
;
2910 if (flags
.mask
& BR_LEARNING
) {
2911 bool learn_ena
= !!(flags
.val
& BR_LEARNING
);
2913 rc
= sja1105_port_set_learning(priv
, port
, learn_ena
);
2918 if (flags
.mask
& (BR_FLOOD
| BR_BCAST_FLOOD
)) {
2919 rc
= sja1105_port_ucast_bcast_flood(priv
, port
, flags
);
2924 /* For chips that can't offload BR_MCAST_FLOOD independently, there
2925 * is nothing to do here, we ensured the configuration is in sync by
2926 * offloading BR_FLOOD.
2928 if (flags
.mask
& BR_MCAST_FLOOD
&& priv
->info
->can_limit_mcast_flood
) {
2929 rc
= sja1105_port_mcast_flood(priv
, port
, flags
,
2938 static void sja1105_teardown_ports(struct sja1105_private
*priv
)
2940 struct dsa_switch
*ds
= priv
->ds
;
2943 for (port
= 0; port
< ds
->num_ports
; port
++) {
2944 struct sja1105_port
*sp
= &priv
->ports
[port
];
2946 if (sp
->xmit_worker
)
2947 kthread_destroy_worker(sp
->xmit_worker
);
2951 static int sja1105_setup_ports(struct sja1105_private
*priv
)
2953 struct sja1105_tagger_data
*tagger_data
= &priv
->tagger_data
;
2954 struct dsa_switch
*ds
= priv
->ds
;
2957 /* Connections between dsa_port and sja1105_port */
2958 for (port
= 0; port
< ds
->num_ports
; port
++) {
2959 struct sja1105_port
*sp
= &priv
->ports
[port
];
2960 struct dsa_port
*dp
= dsa_to_port(ds
, port
);
2961 struct kthread_worker
*worker
;
2962 struct net_device
*slave
;
2964 if (!dsa_port_is_user(dp
))
2969 sp
->data
= tagger_data
;
2971 kthread_init_work(&sp
->xmit_work
, sja1105_port_deferred_xmit
);
2972 worker
= kthread_create_worker(0, "%s_xmit", slave
->name
);
2973 if (IS_ERR(worker
)) {
2974 rc
= PTR_ERR(worker
);
2976 "failed to create deferred xmit thread: %d\n",
2978 goto out_destroy_workers
;
2980 sp
->xmit_worker
= worker
;
2981 skb_queue_head_init(&sp
->xmit_queue
);
2986 out_destroy_workers
:
2987 sja1105_teardown_ports(priv
);
2991 /* The programming model for the SJA1105 switch is "all-at-once" via static
2992 * configuration tables. Some of these can be dynamically modified at runtime,
2993 * but not the xMII mode parameters table.
2994 * Furthermode, some PHYs may not have crystals for generating their clocks
2995 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
2996 * ref_clk pin. So port clocking needs to be initialized early, before
2997 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
2998 * Setting correct PHY link speed does not matter now.
2999 * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3000 * bindings are not yet parsed by DSA core. We need to parse early so that we
3001 * can populate the xMII mode parameters table.
3003 static int sja1105_setup(struct dsa_switch
*ds
)
3005 struct sja1105_private
*priv
= ds
->priv
;
3008 if (priv
->info
->disable_microcontroller
) {
3009 rc
= priv
->info
->disable_microcontroller(priv
);
3012 "Failed to disable microcontroller: %pe\n",
3018 /* Create and send configuration down to device */
3019 rc
= sja1105_static_config_load(priv
);
3021 dev_err(ds
->dev
, "Failed to load static config: %d\n", rc
);
3025 /* Configure the CGU (PHY link modes and speeds) */
3026 if (priv
->info
->clocking_setup
) {
3027 rc
= priv
->info
->clocking_setup(priv
);
3030 "Failed to configure MII clocking: %pe\n",
3032 goto out_static_config_free
;
3036 rc
= sja1105_setup_ports(priv
);
3038 goto out_static_config_free
;
3040 sja1105_tas_setup(ds
);
3041 sja1105_flower_setup(ds
);
3043 rc
= sja1105_ptp_clock_register(ds
);
3045 dev_err(ds
->dev
, "Failed to register PTP clock: %d\n", rc
);
3046 goto out_flower_teardown
;
3049 rc
= sja1105_mdiobus_register(ds
);
3051 dev_err(ds
->dev
, "Failed to register MDIO bus: %pe\n",
3053 goto out_ptp_clock_unregister
;
3056 rc
= sja1105_devlink_setup(ds
);
3058 goto out_mdiobus_unregister
;
3061 rc
= dsa_tag_8021q_register(ds
, htons(ETH_P_8021Q
));
3064 goto out_devlink_teardown
;
3066 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3067 * The only thing we can do to disable it is lie about what the 802.1Q
3069 * So it will still try to apply VLAN filtering, but all ingress
3070 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3071 * will be internally tagged with a distorted VLAN header where the
3072 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3074 ds
->vlan_filtering_is_global
= true;
3075 ds
->untag_bridge_pvid
= true;
3076 /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3077 ds
->num_fwd_offloading_bridges
= 7;
3079 /* Advertise the 8 egress queues */
3080 ds
->num_tx_queues
= SJA1105_NUM_TC
;
3082 ds
->mtu_enforcement_ingress
= true;
3083 ds
->assisted_learning_on_cpu_port
= true;
3087 out_devlink_teardown
:
3088 sja1105_devlink_teardown(ds
);
3089 out_mdiobus_unregister
:
3090 sja1105_mdiobus_unregister(ds
);
3091 out_ptp_clock_unregister
:
3092 sja1105_ptp_clock_unregister(ds
);
3093 out_flower_teardown
:
3094 sja1105_flower_teardown(ds
);
3095 sja1105_tas_teardown(ds
);
3096 sja1105_teardown_ports(priv
);
3097 out_static_config_free
:
3098 sja1105_static_config_free(&priv
->static_config
);
3103 static void sja1105_teardown(struct dsa_switch
*ds
)
3105 struct sja1105_private
*priv
= ds
->priv
;
3108 dsa_tag_8021q_unregister(ds
);
3111 sja1105_devlink_teardown(ds
);
3112 sja1105_mdiobus_unregister(ds
);
3113 sja1105_ptp_clock_unregister(ds
);
3114 sja1105_flower_teardown(ds
);
3115 sja1105_tas_teardown(ds
);
3116 sja1105_teardown_ports(priv
);
3117 sja1105_static_config_free(&priv
->static_config
);
3120 const struct dsa_switch_ops sja1105_switch_ops
= {
3121 .get_tag_protocol
= sja1105_get_tag_protocol
,
3122 .setup
= sja1105_setup
,
3123 .teardown
= sja1105_teardown
,
3124 .set_ageing_time
= sja1105_set_ageing_time
,
3125 .port_change_mtu
= sja1105_change_mtu
,
3126 .port_max_mtu
= sja1105_get_max_mtu
,
3127 .phylink_validate
= sja1105_phylink_validate
,
3128 .phylink_mac_config
= sja1105_mac_config
,
3129 .phylink_mac_link_up
= sja1105_mac_link_up
,
3130 .phylink_mac_link_down
= sja1105_mac_link_down
,
3131 .get_strings
= sja1105_get_strings
,
3132 .get_ethtool_stats
= sja1105_get_ethtool_stats
,
3133 .get_sset_count
= sja1105_get_sset_count
,
3134 .get_ts_info
= sja1105_get_ts_info
,
3135 .port_disable
= sja1105_port_disable
,
3136 .port_fdb_dump
= sja1105_fdb_dump
,
3137 .port_fdb_add
= sja1105_fdb_add
,
3138 .port_fdb_del
= sja1105_fdb_del
,
3139 .port_fast_age
= sja1105_fast_age
,
3140 .port_bridge_join
= sja1105_bridge_join
,
3141 .port_bridge_leave
= sja1105_bridge_leave
,
3142 .port_pre_bridge_flags
= sja1105_port_pre_bridge_flags
,
3143 .port_bridge_flags
= sja1105_port_bridge_flags
,
3144 .port_stp_state_set
= sja1105_bridge_stp_state_set
,
3145 .port_vlan_filtering
= sja1105_vlan_filtering
,
3146 .port_vlan_add
= sja1105_bridge_vlan_add
,
3147 .port_vlan_del
= sja1105_bridge_vlan_del
,
3148 .port_mdb_add
= sja1105_mdb_add
,
3149 .port_mdb_del
= sja1105_mdb_del
,
3150 .port_hwtstamp_get
= sja1105_hwtstamp_get
,
3151 .port_hwtstamp_set
= sja1105_hwtstamp_set
,
3152 .port_rxtstamp
= sja1105_port_rxtstamp
,
3153 .port_txtstamp
= sja1105_port_txtstamp
,
3154 .port_setup_tc
= sja1105_port_setup_tc
,
3155 .port_mirror_add
= sja1105_mirror_add
,
3156 .port_mirror_del
= sja1105_mirror_del
,
3157 .port_policer_add
= sja1105_port_policer_add
,
3158 .port_policer_del
= sja1105_port_policer_del
,
3159 .cls_flower_add
= sja1105_cls_flower_add
,
3160 .cls_flower_del
= sja1105_cls_flower_del
,
3161 .cls_flower_stats
= sja1105_cls_flower_stats
,
3162 .devlink_info_get
= sja1105_devlink_info_get
,
3163 .tag_8021q_vlan_add
= sja1105_dsa_8021q_vlan_add
,
3164 .tag_8021q_vlan_del
= sja1105_dsa_8021q_vlan_del
,
3165 .port_prechangeupper
= sja1105_prechangeupper
,
3166 .port_bridge_tx_fwd_offload
= dsa_tag_8021q_bridge_tx_fwd_offload
,
3167 .port_bridge_tx_fwd_unoffload
= dsa_tag_8021q_bridge_tx_fwd_unoffload
,
3169 EXPORT_SYMBOL_GPL(sja1105_switch_ops
);
3171 static const struct of_device_id sja1105_dt_ids
[];
3173 static int sja1105_check_device_id(struct sja1105_private
*priv
)
3175 const struct sja1105_regs
*regs
= priv
->info
->regs
;
3176 u8 prod_id
[SJA1105_SIZE_DEVICE_ID
] = {0};
3177 struct device
*dev
= &priv
->spidev
->dev
;
3178 const struct of_device_id
*match
;
3183 rc
= sja1105_xfer_u32(priv
, SPI_READ
, regs
->device_id
, &device_id
,
3188 rc
= sja1105_xfer_buf(priv
, SPI_READ
, regs
->prod_id
, prod_id
,
3189 SJA1105_SIZE_DEVICE_ID
);
3193 sja1105_unpack(prod_id
, &part_no
, 19, 4, SJA1105_SIZE_DEVICE_ID
);
3195 for (match
= sja1105_dt_ids
; match
->compatible
[0]; match
++) {
3196 const struct sja1105_info
*info
= match
->data
;
3198 /* Is what's been probed in our match table at all? */
3199 if (info
->device_id
!= device_id
|| info
->part_no
!= part_no
)
3202 /* But is it what's in the device tree? */
3203 if (priv
->info
->device_id
!= device_id
||
3204 priv
->info
->part_no
!= part_no
) {
3205 dev_warn(dev
, "Device tree specifies chip %s but found %s, please fix it!\n",
3206 priv
->info
->name
, info
->name
);
3207 /* It isn't. No problem, pick that up. */
3214 dev_err(dev
, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3215 device_id
, part_no
);
3220 static int sja1105_probe(struct spi_device
*spi
)
3222 struct device
*dev
= &spi
->dev
;
3223 struct sja1105_private
*priv
;
3224 size_t max_xfer
, max_msg
;
3225 struct dsa_switch
*ds
;
3228 if (!dev
->of_node
) {
3229 dev_err(dev
, "No DTS bindings for SJA1105 driver\n");
3233 priv
= devm_kzalloc(dev
, sizeof(struct sja1105_private
), GFP_KERNEL
);
3237 /* Configure the optional reset pin and bring up switch */
3238 priv
->reset_gpio
= devm_gpiod_get(dev
, "reset", GPIOD_OUT_HIGH
);
3239 if (IS_ERR(priv
->reset_gpio
))
3240 dev_dbg(dev
, "reset-gpios not defined, ignoring\n");
3242 sja1105_hw_reset(priv
->reset_gpio
, 1, 1);
3244 /* Populate our driver private structure (priv) based on
3245 * the device tree node that was probed (spi)
3248 spi_set_drvdata(spi
, priv
);
3250 /* Configure the SPI bus */
3251 spi
->bits_per_word
= 8;
3252 rc
= spi_setup(spi
);
3254 dev_err(dev
, "Could not init SPI\n");
3258 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3259 * a small one for the message header and another one for the current
3260 * chunk of the packed buffer.
3261 * Check that the restrictions imposed by the SPI controller are
3262 * respected: the chunk buffer is smaller than the max transfer size,
3263 * and the total length of the chunk plus its message header is smaller
3264 * than the max message size.
3265 * We do that during probe time since the maximum transfer size is a
3266 * runtime invariant.
3268 max_xfer
= spi_max_transfer_size(spi
);
3269 max_msg
= spi_max_message_size(spi
);
3271 /* We need to send at least one 64-bit word of SPI payload per message
3272 * in order to be able to make useful progress.
3274 if (max_msg
< SJA1105_SIZE_SPI_MSG_HEADER
+ 8) {
3275 dev_err(dev
, "SPI master cannot send large enough buffers, aborting\n");
3279 priv
->max_xfer_len
= SJA1105_SIZE_SPI_MSG_MAXLEN
;
3280 if (priv
->max_xfer_len
> max_xfer
)
3281 priv
->max_xfer_len
= max_xfer
;
3282 if (priv
->max_xfer_len
> max_msg
- SJA1105_SIZE_SPI_MSG_HEADER
)
3283 priv
->max_xfer_len
= max_msg
- SJA1105_SIZE_SPI_MSG_HEADER
;
3285 priv
->info
= of_device_get_match_data(dev
);
3287 /* Detect hardware device */
3288 rc
= sja1105_check_device_id(priv
);
3290 dev_err(dev
, "Device ID check failed: %d\n", rc
);
3294 dev_info(dev
, "Probed switch chip: %s\n", priv
->info
->name
);
3296 ds
= devm_kzalloc(dev
, sizeof(*ds
), GFP_KERNEL
);
3301 ds
->num_ports
= priv
->info
->num_ports
;
3302 ds
->ops
= &sja1105_switch_ops
;
3306 mutex_init(&priv
->ptp_data
.lock
);
3307 mutex_init(&priv
->mgmt_lock
);
3309 rc
= sja1105_parse_dt(priv
);
3311 dev_err(ds
->dev
, "Failed to parse DT: %d\n", rc
);
3315 /* Error out early if internal delays are required through DT
3316 * and we can't apply them.
3318 rc
= sja1105_parse_rgmii_delays(priv
);
3320 dev_err(ds
->dev
, "RGMII delay not supported\n");
3324 if (IS_ENABLED(CONFIG_NET_SCH_CBS
)) {
3325 priv
->cbs
= devm_kcalloc(dev
, priv
->info
->num_cbs_shapers
,
3326 sizeof(struct sja1105_cbs_entry
),
3332 return dsa_register_switch(priv
->ds
);
3335 static int sja1105_remove(struct spi_device
*spi
)
3337 struct sja1105_private
*priv
= spi_get_drvdata(spi
);
3342 dsa_unregister_switch(priv
->ds
);
3344 spi_set_drvdata(spi
, NULL
);
3349 static void sja1105_shutdown(struct spi_device
*spi
)
3351 struct sja1105_private
*priv
= spi_get_drvdata(spi
);
3356 dsa_switch_shutdown(priv
->ds
);
3358 spi_set_drvdata(spi
, NULL
);
3361 static const struct of_device_id sja1105_dt_ids
[] = {
3362 { .compatible
= "nxp,sja1105e", .data
= &sja1105e_info
},
3363 { .compatible
= "nxp,sja1105t", .data
= &sja1105t_info
},
3364 { .compatible
= "nxp,sja1105p", .data
= &sja1105p_info
},
3365 { .compatible
= "nxp,sja1105q", .data
= &sja1105q_info
},
3366 { .compatible
= "nxp,sja1105r", .data
= &sja1105r_info
},
3367 { .compatible
= "nxp,sja1105s", .data
= &sja1105s_info
},
3368 { .compatible
= "nxp,sja1110a", .data
= &sja1110a_info
},
3369 { .compatible
= "nxp,sja1110b", .data
= &sja1110b_info
},
3370 { .compatible
= "nxp,sja1110c", .data
= &sja1110c_info
},
3371 { .compatible
= "nxp,sja1110d", .data
= &sja1110d_info
},
3374 MODULE_DEVICE_TABLE(of
, sja1105_dt_ids
);
3376 static struct spi_driver sja1105_driver
= {
3379 .owner
= THIS_MODULE
,
3380 .of_match_table
= of_match_ptr(sja1105_dt_ids
),
3382 .probe
= sja1105_probe
,
3383 .remove
= sja1105_remove
,
3384 .shutdown
= sja1105_shutdown
,
3387 module_spi_driver(sja1105_driver
);
3389 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3390 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3391 MODULE_DESCRIPTION("SJA1105 Driver");
3392 MODULE_LICENSE("GPL v2");