1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw
*hw
);
36 static void e1000_phy_init_script(struct e1000_hw
*hw
);
37 static int32_t e1000_setup_copper_link(struct e1000_hw
*hw
);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw
*hw
);
42 static void e1000_raise_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
43 static void e1000_lower_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw
*hw
, uint32_t data
,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw
*hw
);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw
*hw
);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw
*hw
, uint16_t offset
,
49 uint16_t words
, uint16_t *data
);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
51 uint16_t offset
, uint16_t words
,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw
*hw
);
54 static void e1000_raise_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
55 static void e1000_lower_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
56 static void e1000_shift_out_ee_bits(struct e1000_hw
*hw
, uint16_t data
,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw
*hw
, uint32_t reg_addr
,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw
*hw
,uint32_t reg_addr
,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw
*hw
, uint16_t count
);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw
*hw
);
64 static void e1000_release_eeprom(struct e1000_hw
*hw
);
65 static void e1000_standby_eeprom(struct e1000_hw
*hw
);
66 static int32_t e1000_set_vco_speed(struct e1000_hw
*hw
);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw
*hw
);
68 static int32_t e1000_set_phy_mode(struct e1000_hw
*hw
);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw
*hw
, uint8_t *buffer
);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer
, uint32_t length
);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw
*hw
);
72 static int32_t e1000_check_downshift(struct e1000_hw
*hw
);
73 static int32_t e1000_check_polarity(struct e1000_hw
*hw
, uint16_t *polarity
);
74 static void e1000_clear_hw_cntrs(struct e1000_hw
*hw
);
75 static void e1000_clear_vfta(struct e1000_hw
*hw
);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw
*hw
);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw
*hw
);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw
*hw
);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw
*hw
);
82 static int32_t e1000_get_cable_length(struct e1000_hw
*hw
,
84 uint16_t *max_length
);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
87 static int32_t e1000_id_led_init(struct e1000_hw
* hw
);
88 static void e1000_init_rx_addrs(struct e1000_hw
*hw
);
89 static boolean_t
e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw
*hw
, uint16_t offset
,
93 uint16_t words
, uint16_t *data
);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
96 static int32_t e1000_wait_autoneg(struct e1000_hw
*hw
);
98 static void e1000_write_reg_io(struct e1000_hw
*hw
, uint32_t offset
,
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
104 /* IGP cable length table */
106 uint16_t e1000_igp_cable_length_table
[IGP01E1000_AGC_LENGTH_TABLE_SIZE
] =
107 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
108 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
109 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
110 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
111 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
112 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
113 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
114 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117 uint16_t e1000_igp_2_cable_length_table
[IGP02E1000_AGC_LENGTH_TABLE_SIZE
] =
118 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
119 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
120 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
121 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
122 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
123 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
124 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
125 104, 109, 114, 118, 121, 124};
128 /******************************************************************************
129 * Set the phy type member in the hw struct.
131 * hw - Struct containing variables accessed by shared code
132 *****************************************************************************/
134 e1000_set_phy_type(struct e1000_hw
*hw
)
136 DEBUGFUNC("e1000_set_phy_type");
138 if(hw
->mac_type
== e1000_undefined
)
139 return -E1000_ERR_PHY_TYPE
;
142 case M88E1000_E_PHY_ID
:
143 case M88E1000_I_PHY_ID
:
144 case M88E1011_I_PHY_ID
:
145 case M88E1111_I_PHY_ID
:
146 hw
->phy_type
= e1000_phy_m88
;
148 case IGP01E1000_I_PHY_ID
:
149 if(hw
->mac_type
== e1000_82541
||
150 hw
->mac_type
== e1000_82541_rev_2
||
151 hw
->mac_type
== e1000_82547
||
152 hw
->mac_type
== e1000_82547_rev_2
) {
153 hw
->phy_type
= e1000_phy_igp
;
158 /* Should never have loaded on this device */
159 hw
->phy_type
= e1000_phy_undefined
;
160 return -E1000_ERR_PHY_TYPE
;
163 return E1000_SUCCESS
;
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 e1000_phy_init_script(struct e1000_hw
*hw
)
175 uint16_t phy_saved_data
;
177 DEBUGFUNC("e1000_phy_init_script");
179 if(hw
->phy_init_script
) {
182 /* Save off the current value of register 0x2F5B to be restored at
183 * the end of this routine. */
184 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
186 /* Disabled the PHY transmitter */
187 e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
191 e1000_write_phy_reg(hw
,0x0000,0x0140);
195 switch(hw
->mac_type
) {
198 e1000_write_phy_reg(hw
, 0x1F95, 0x0001);
200 e1000_write_phy_reg(hw
, 0x1F71, 0xBD21);
202 e1000_write_phy_reg(hw
, 0x1F79, 0x0018);
204 e1000_write_phy_reg(hw
, 0x1F30, 0x1600);
206 e1000_write_phy_reg(hw
, 0x1F31, 0x0014);
208 e1000_write_phy_reg(hw
, 0x1F32, 0x161C);
210 e1000_write_phy_reg(hw
, 0x1F94, 0x0003);
212 e1000_write_phy_reg(hw
, 0x1F96, 0x003F);
214 e1000_write_phy_reg(hw
, 0x2010, 0x0008);
217 case e1000_82541_rev_2
:
218 case e1000_82547_rev_2
:
219 e1000_write_phy_reg(hw
, 0x1F73, 0x0099);
225 e1000_write_phy_reg(hw
, 0x0000, 0x3300);
229 /* Now enable the transmitter */
230 e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
232 if(hw
->mac_type
== e1000_82547
) {
233 uint16_t fused
, fine
, coarse
;
235 /* Move to analog registers page */
236 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_SPARE_FUSE_STATUS
, &fused
);
238 if(!(fused
& IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
)) {
239 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_STATUS
, &fused
);
241 fine
= fused
& IGP01E1000_ANALOG_FUSE_FINE_MASK
;
242 coarse
= fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
;
244 if(coarse
> IGP01E1000_ANALOG_FUSE_COARSE_THRESH
) {
245 coarse
-= IGP01E1000_ANALOG_FUSE_COARSE_10
;
246 fine
-= IGP01E1000_ANALOG_FUSE_FINE_1
;
247 } else if(coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH
)
248 fine
-= IGP01E1000_ANALOG_FUSE_FINE_10
;
250 fused
= (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK
) |
251 (fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK
) |
252 (coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
);
254 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_CONTROL
, fused
);
255 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_BYPASS
,
256 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
);
262 /******************************************************************************
263 * Set the mac type member in the hw struct.
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
268 e1000_set_mac_type(struct e1000_hw
*hw
)
270 DEBUGFUNC("e1000_set_mac_type");
272 switch (hw
->device_id
) {
273 case E1000_DEV_ID_82542
:
274 switch (hw
->revision_id
) {
275 case E1000_82542_2_0_REV_ID
:
276 hw
->mac_type
= e1000_82542_rev2_0
;
278 case E1000_82542_2_1_REV_ID
:
279 hw
->mac_type
= e1000_82542_rev2_1
;
282 /* Invalid 82542 revision ID */
283 return -E1000_ERR_MAC_TYPE
;
286 case E1000_DEV_ID_82543GC_FIBER
:
287 case E1000_DEV_ID_82543GC_COPPER
:
288 hw
->mac_type
= e1000_82543
;
290 case E1000_DEV_ID_82544EI_COPPER
:
291 case E1000_DEV_ID_82544EI_FIBER
:
292 case E1000_DEV_ID_82544GC_COPPER
:
293 case E1000_DEV_ID_82544GC_LOM
:
294 hw
->mac_type
= e1000_82544
;
296 case E1000_DEV_ID_82540EM
:
297 case E1000_DEV_ID_82540EM_LOM
:
298 case E1000_DEV_ID_82540EP
:
299 case E1000_DEV_ID_82540EP_LOM
:
300 case E1000_DEV_ID_82540EP_LP
:
301 hw
->mac_type
= e1000_82540
;
303 case E1000_DEV_ID_82545EM_COPPER
:
304 case E1000_DEV_ID_82545EM_FIBER
:
305 hw
->mac_type
= e1000_82545
;
307 case E1000_DEV_ID_82545GM_COPPER
:
308 case E1000_DEV_ID_82545GM_FIBER
:
309 case E1000_DEV_ID_82545GM_SERDES
:
310 hw
->mac_type
= e1000_82545_rev_3
;
312 case E1000_DEV_ID_82546EB_COPPER
:
313 case E1000_DEV_ID_82546EB_FIBER
:
314 case E1000_DEV_ID_82546EB_QUAD_COPPER
:
315 hw
->mac_type
= e1000_82546
;
317 case E1000_DEV_ID_82546GB_COPPER
:
318 case E1000_DEV_ID_82546GB_FIBER
:
319 case E1000_DEV_ID_82546GB_SERDES
:
320 case E1000_DEV_ID_82546GB_PCIE
:
321 hw
->mac_type
= e1000_82546_rev_3
;
323 case E1000_DEV_ID_82541EI
:
324 case E1000_DEV_ID_82541EI_MOBILE
:
325 hw
->mac_type
= e1000_82541
;
327 case E1000_DEV_ID_82541ER
:
328 case E1000_DEV_ID_82541GI
:
329 case E1000_DEV_ID_82541GI_LF
:
330 case E1000_DEV_ID_82541GI_MOBILE
:
331 hw
->mac_type
= e1000_82541_rev_2
;
333 case E1000_DEV_ID_82547EI
:
334 hw
->mac_type
= e1000_82547
;
336 case E1000_DEV_ID_82547GI
:
337 hw
->mac_type
= e1000_82547_rev_2
;
339 case E1000_DEV_ID_82571EB_COPPER
:
340 case E1000_DEV_ID_82571EB_FIBER
:
341 case E1000_DEV_ID_82571EB_SERDES
:
342 hw
->mac_type
= e1000_82571
;
344 case E1000_DEV_ID_82572EI_COPPER
:
345 case E1000_DEV_ID_82572EI_FIBER
:
346 case E1000_DEV_ID_82572EI_SERDES
:
347 hw
->mac_type
= e1000_82572
;
349 case E1000_DEV_ID_82573E
:
350 case E1000_DEV_ID_82573E_IAMT
:
351 case E1000_DEV_ID_82573L
:
352 hw
->mac_type
= e1000_82573
;
355 /* Should never have loaded on this device */
356 return -E1000_ERR_MAC_TYPE
;
359 switch(hw
->mac_type
) {
363 hw
->eeprom_semaphore_present
= TRUE
;
367 case e1000_82541_rev_2
:
368 case e1000_82547_rev_2
:
369 hw
->asf_firmware_present
= TRUE
;
375 return E1000_SUCCESS
;
378 /*****************************************************************************
379 * Set media type and TBI compatibility.
381 * hw - Struct containing variables accessed by shared code
382 * **************************************************************************/
384 e1000_set_media_type(struct e1000_hw
*hw
)
388 DEBUGFUNC("e1000_set_media_type");
390 if(hw
->mac_type
!= e1000_82543
) {
391 /* tbi_compatibility is only valid on 82543 */
392 hw
->tbi_compatibility_en
= FALSE
;
395 switch (hw
->device_id
) {
396 case E1000_DEV_ID_82545GM_SERDES
:
397 case E1000_DEV_ID_82546GB_SERDES
:
398 case E1000_DEV_ID_82571EB_SERDES
:
399 case E1000_DEV_ID_82572EI_SERDES
:
400 hw
->media_type
= e1000_media_type_internal_serdes
;
403 switch (hw
->mac_type
) {
404 case e1000_82542_rev2_0
:
405 case e1000_82542_rev2_1
:
406 hw
->media_type
= e1000_media_type_fiber
;
409 /* The STATUS_TBIMODE bit is reserved or reused for the this
412 hw
->media_type
= e1000_media_type_copper
;
415 status
= E1000_READ_REG(hw
, STATUS
);
416 if (status
& E1000_STATUS_TBIMODE
) {
417 hw
->media_type
= e1000_media_type_fiber
;
418 /* tbi_compatibility not valid on fiber */
419 hw
->tbi_compatibility_en
= FALSE
;
421 hw
->media_type
= e1000_media_type_copper
;
428 /******************************************************************************
429 * Reset the transmit and receive units; mask and clear all interrupts.
431 * hw - Struct containing variables accessed by shared code
432 *****************************************************************************/
434 e1000_reset_hw(struct e1000_hw
*hw
)
442 uint32_t extcnf_ctrl
;
445 DEBUGFUNC("e1000_reset_hw");
447 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
448 if(hw
->mac_type
== e1000_82542_rev2_0
) {
449 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
450 e1000_pci_clear_mwi(hw
);
453 if(hw
->bus_type
== e1000_bus_type_pci_express
) {
454 /* Prevent the PCI-E bus from sticking if there is no TLP connection
455 * on the last TLP read/write transaction when MAC is reset.
457 if(e1000_disable_pciex_master(hw
) != E1000_SUCCESS
) {
458 DEBUGOUT("PCI-E Master disable polling has failed.\n");
462 /* Clear interrupt mask to stop board from generating interrupts */
463 DEBUGOUT("Masking off all interrupts\n");
464 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
466 /* Disable the Transmit and Receive units. Then delay to allow
467 * any pending transactions to complete before we hit the MAC with
470 E1000_WRITE_REG(hw
, RCTL
, 0);
471 E1000_WRITE_REG(hw
, TCTL
, E1000_TCTL_PSP
);
472 E1000_WRITE_FLUSH(hw
);
474 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
475 hw
->tbi_compatibility_on
= FALSE
;
477 /* Delay to allow any outstanding PCI transactions to complete before
478 * resetting the device
482 ctrl
= E1000_READ_REG(hw
, CTRL
);
484 /* Must reset the PHY before resetting the MAC */
485 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
486 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_PHY_RST
));
490 /* Must acquire the MDIO ownership before MAC reset.
491 * Ownership defaults to firmware after a reset. */
492 if(hw
->mac_type
== e1000_82573
) {
495 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
496 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
499 E1000_WRITE_REG(hw
, EXTCNF_CTRL
, extcnf_ctrl
);
500 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
502 if(extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
505 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
512 /* Issue a global reset to the MAC. This will reset the chip's
513 * transmit, receive, DMA, and link units. It will not effect
514 * the current PCI configuration. The global reset bit is self-
515 * clearing, and should clear within a microsecond.
517 DEBUGOUT("Issuing a global reset to MAC\n");
519 switch(hw
->mac_type
) {
525 case e1000_82541_rev_2
:
526 /* These controllers can't ack the 64-bit write when issuing the
527 * reset, so use IO-mapping as a workaround to issue the reset */
528 E1000_WRITE_REG_IO(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
530 case e1000_82545_rev_3
:
531 case e1000_82546_rev_3
:
532 /* Reset is performed on a shadow of the control register */
533 E1000_WRITE_REG(hw
, CTRL_DUP
, (ctrl
| E1000_CTRL_RST
));
536 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
540 /* After MAC reset, force reload of EEPROM to restore power-on settings to
541 * device. Later controllers reload the EEPROM automatically, so just wait
542 * for reload to complete.
544 switch(hw
->mac_type
) {
545 case e1000_82542_rev2_0
:
546 case e1000_82542_rev2_1
:
549 /* Wait for reset to complete */
551 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
552 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
553 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
554 E1000_WRITE_FLUSH(hw
);
555 /* Wait for EEPROM reload */
559 case e1000_82541_rev_2
:
561 case e1000_82547_rev_2
:
562 /* Wait for EEPROM reload */
566 if (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
568 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
569 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
570 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
571 E1000_WRITE_FLUSH(hw
);
576 ret_val
= e1000_get_auto_rd_done(hw
);
578 /* We don't want to continue accessing MAC registers. */
582 /* Wait for EEPROM reload (it happens automatically) */
587 /* Disable HW ARPs on ASF enabled adapters */
588 if(hw
->mac_type
>= e1000_82540
&& hw
->mac_type
<= e1000_82547_rev_2
) {
589 manc
= E1000_READ_REG(hw
, MANC
);
590 manc
&= ~(E1000_MANC_ARP_EN
);
591 E1000_WRITE_REG(hw
, MANC
, manc
);
594 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
595 e1000_phy_init_script(hw
);
597 /* Configure activity LED after PHY reset */
598 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
599 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
600 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
601 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
604 /* Clear interrupt mask to stop board from generating interrupts */
605 DEBUGOUT("Masking off all interrupts\n");
606 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
608 /* Clear any pending interrupt events. */
609 icr
= E1000_READ_REG(hw
, ICR
);
611 /* If MWI was previously enabled, reenable it. */
612 if(hw
->mac_type
== e1000_82542_rev2_0
) {
613 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
614 e1000_pci_set_mwi(hw
);
617 return E1000_SUCCESS
;
620 /******************************************************************************
621 * Performs basic configuration of the adapter.
623 * hw - Struct containing variables accessed by shared code
625 * Assumes that the controller has previously been reset and is in a
626 * post-reset uninitialized state. Initializes the receive address registers,
627 * multicast table, and VLAN filter table. Calls routines to setup link
628 * configuration and flow control settings. Clears all on-chip counters. Leaves
629 * the transmit and receive units disabled and uninitialized.
630 *****************************************************************************/
632 e1000_init_hw(struct e1000_hw
*hw
)
637 uint16_t pcix_cmd_word
;
638 uint16_t pcix_stat_hi_word
;
643 DEBUGFUNC("e1000_init_hw");
645 /* Initialize Identification LED */
646 ret_val
= e1000_id_led_init(hw
);
648 DEBUGOUT("Error Initializing Identification LED\n");
652 /* Set the media type and TBI compatibility */
653 e1000_set_media_type(hw
);
655 /* Disabling VLAN filtering. */
656 DEBUGOUT("Initializing the IEEE VLAN\n");
657 if (hw
->mac_type
< e1000_82545_rev_3
)
658 E1000_WRITE_REG(hw
, VET
, 0);
659 e1000_clear_vfta(hw
);
661 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
662 if(hw
->mac_type
== e1000_82542_rev2_0
) {
663 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
664 e1000_pci_clear_mwi(hw
);
665 E1000_WRITE_REG(hw
, RCTL
, E1000_RCTL_RST
);
666 E1000_WRITE_FLUSH(hw
);
670 /* Setup the receive address. This involves initializing all of the Receive
671 * Address Registers (RARs 0 - 15).
673 e1000_init_rx_addrs(hw
);
675 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
676 if(hw
->mac_type
== e1000_82542_rev2_0
) {
677 E1000_WRITE_REG(hw
, RCTL
, 0);
678 E1000_WRITE_FLUSH(hw
);
680 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
681 e1000_pci_set_mwi(hw
);
684 /* Zero out the Multicast HASH table */
685 DEBUGOUT("Zeroing the MTA\n");
686 mta_size
= E1000_MC_TBL_SIZE
;
687 for(i
= 0; i
< mta_size
; i
++)
688 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
690 /* Set the PCI priority bit correctly in the CTRL register. This
691 * determines if the adapter gives priority to receives, or if it
692 * gives equal priority to transmits and receives. Valid only on
693 * 82542 and 82543 silicon.
695 if(hw
->dma_fairness
&& hw
->mac_type
<= e1000_82543
) {
696 ctrl
= E1000_READ_REG(hw
, CTRL
);
697 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PRIOR
);
700 switch(hw
->mac_type
) {
701 case e1000_82545_rev_3
:
702 case e1000_82546_rev_3
:
705 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
706 if(hw
->bus_type
== e1000_bus_type_pcix
) {
707 e1000_read_pci_cfg(hw
, PCIX_COMMAND_REGISTER
, &pcix_cmd_word
);
708 e1000_read_pci_cfg(hw
, PCIX_STATUS_REGISTER_HI
,
710 cmd_mmrbc
= (pcix_cmd_word
& PCIX_COMMAND_MMRBC_MASK
) >>
711 PCIX_COMMAND_MMRBC_SHIFT
;
712 stat_mmrbc
= (pcix_stat_hi_word
& PCIX_STATUS_HI_MMRBC_MASK
) >>
713 PCIX_STATUS_HI_MMRBC_SHIFT
;
714 if(stat_mmrbc
== PCIX_STATUS_HI_MMRBC_4K
)
715 stat_mmrbc
= PCIX_STATUS_HI_MMRBC_2K
;
716 if(cmd_mmrbc
> stat_mmrbc
) {
717 pcix_cmd_word
&= ~PCIX_COMMAND_MMRBC_MASK
;
718 pcix_cmd_word
|= stat_mmrbc
<< PCIX_COMMAND_MMRBC_SHIFT
;
719 e1000_write_pci_cfg(hw
, PCIX_COMMAND_REGISTER
,
726 /* Call a subroutine to configure the link and setup flow control. */
727 ret_val
= e1000_setup_link(hw
);
729 /* Set the transmit descriptor write-back policy */
730 if(hw
->mac_type
> e1000_82544
) {
731 ctrl
= E1000_READ_REG(hw
, TXDCTL
);
732 ctrl
= (ctrl
& ~E1000_TXDCTL_WTHRESH
) | E1000_TXDCTL_FULL_TX_DESC_WB
;
733 switch (hw
->mac_type
) {
739 ctrl
|= E1000_TXDCTL_COUNT_DESC
;
742 E1000_WRITE_REG(hw
, TXDCTL
, ctrl
);
745 if (hw
->mac_type
== e1000_82573
) {
746 e1000_enable_tx_pkt_filtering(hw
);
749 switch (hw
->mac_type
) {
754 ctrl
= E1000_READ_REG(hw
, TXDCTL1
);
755 ctrl
&= ~E1000_TXDCTL_WTHRESH
;
756 ctrl
|= E1000_TXDCTL_COUNT_DESC
| E1000_TXDCTL_FULL_TX_DESC_WB
;
758 E1000_WRITE_REG(hw
, TXDCTL1
, ctrl
);
764 if (hw
->mac_type
== e1000_82573
) {
765 uint32_t gcr
= E1000_READ_REG(hw
, GCR
);
766 gcr
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
767 E1000_WRITE_REG(hw
, GCR
, gcr
);
770 /* Clear all of the statistics registers (clear on read). It is
771 * important that we do this after we have tried to establish link
772 * because the symbol error count will increment wildly if there
775 e1000_clear_hw_cntrs(hw
);
780 /******************************************************************************
781 * Adjust SERDES output amplitude based on EEPROM setting.
783 * hw - Struct containing variables accessed by shared code.
784 *****************************************************************************/
786 e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
)
788 uint16_t eeprom_data
;
791 DEBUGFUNC("e1000_adjust_serdes_amplitude");
793 if(hw
->media_type
!= e1000_media_type_internal_serdes
)
794 return E1000_SUCCESS
;
796 switch(hw
->mac_type
) {
797 case e1000_82545_rev_3
:
798 case e1000_82546_rev_3
:
801 return E1000_SUCCESS
;
804 ret_val
= e1000_read_eeprom(hw
, EEPROM_SERDES_AMPLITUDE
, 1, &eeprom_data
);
809 if(eeprom_data
!= EEPROM_RESERVED_WORD
) {
810 /* Adjust SERDES output amplitude only. */
811 eeprom_data
&= EEPROM_SERDES_AMPLITUDE_MASK
;
812 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_EXT_CTRL
, eeprom_data
);
817 return E1000_SUCCESS
;
820 /******************************************************************************
821 * Configures flow control and link settings.
823 * hw - Struct containing variables accessed by shared code
825 * Determines which flow control settings to use. Calls the apropriate media-
826 * specific link configuration function. Configures the flow control settings.
827 * Assuming the adapter has a valid link partner, a valid link should be
828 * established. Assumes the hardware has previously been reset and the
829 * transmitter and receiver are not enabled.
830 *****************************************************************************/
832 e1000_setup_link(struct e1000_hw
*hw
)
836 uint16_t eeprom_data
;
838 DEBUGFUNC("e1000_setup_link");
840 /* In the case of the phy reset being blocked, we already have a link.
841 * We do not have to set it up again. */
842 if (e1000_check_phy_reset_block(hw
))
843 return E1000_SUCCESS
;
845 /* Read and store word 0x0F of the EEPROM. This word contains bits
846 * that determine the hardware's default PAUSE (flow control) mode,
847 * a bit that determines whether the HW defaults to enabling or
848 * disabling auto-negotiation, and the direction of the
849 * SW defined pins. If there is no SW over-ride of the flow
850 * control setting, then the variable hw->fc will
851 * be initialized based on a value in the EEPROM.
853 if (hw
->fc
== e1000_fc_default
) {
854 switch (hw
->mac_type
) {
856 hw
->fc
= e1000_fc_full
;
859 ret_val
= e1000_read_eeprom(hw
, EEPROM_INIT_CONTROL2_REG
,
862 DEBUGOUT("EEPROM Read Error\n");
863 return -E1000_ERR_EEPROM
;
865 if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) == 0)
866 hw
->fc
= e1000_fc_none
;
867 else if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) ==
868 EEPROM_WORD0F_ASM_DIR
)
869 hw
->fc
= e1000_fc_tx_pause
;
871 hw
->fc
= e1000_fc_full
;
876 /* We want to save off the original Flow Control configuration just
877 * in case we get disconnected and then reconnected into a different
878 * hub or switch with different Flow Control capabilities.
880 if(hw
->mac_type
== e1000_82542_rev2_0
)
881 hw
->fc
&= (~e1000_fc_tx_pause
);
883 if((hw
->mac_type
< e1000_82543
) && (hw
->report_tx_early
== 1))
884 hw
->fc
&= (~e1000_fc_rx_pause
);
886 hw
->original_fc
= hw
->fc
;
888 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw
->fc
);
890 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
891 * polarity value for the SW controlled pins, and setup the
892 * Extended Device Control reg with that info.
893 * This is needed because one of the SW controlled pins is used for
894 * signal detection. So this should be done before e1000_setup_pcs_link()
895 * or e1000_phy_setup() is called.
897 if(hw
->mac_type
== e1000_82543
) {
898 ctrl_ext
= ((eeprom_data
& EEPROM_WORD0F_SWPDIO_EXT
) <<
900 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
903 /* Call the necessary subroutine to configure the link. */
904 ret_val
= (hw
->media_type
== e1000_media_type_copper
) ?
905 e1000_setup_copper_link(hw
) :
906 e1000_setup_fiber_serdes_link(hw
);
908 /* Initialize the flow control address, type, and PAUSE timer
909 * registers to their default values. This is done even if flow
910 * control is disabled, because it does not hurt anything to
911 * initialize these registers.
913 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
915 E1000_WRITE_REG(hw
, FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
916 E1000_WRITE_REG(hw
, FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
917 E1000_WRITE_REG(hw
, FCT
, FLOW_CONTROL_TYPE
);
919 E1000_WRITE_REG(hw
, FCTTV
, hw
->fc_pause_time
);
921 /* Set the flow control receive threshold registers. Normally,
922 * these registers will be set to a default threshold that may be
923 * adjusted later by the driver's runtime code. However, if the
924 * ability to transmit pause frames in not enabled, then these
925 * registers will be set to 0.
927 if(!(hw
->fc
& e1000_fc_tx_pause
)) {
928 E1000_WRITE_REG(hw
, FCRTL
, 0);
929 E1000_WRITE_REG(hw
, FCRTH
, 0);
931 /* We need to set up the Receive Threshold high and low water marks
932 * as well as (optionally) enabling the transmission of XON frames.
934 if(hw
->fc_send_xon
) {
935 E1000_WRITE_REG(hw
, FCRTL
, (hw
->fc_low_water
| E1000_FCRTL_XONE
));
936 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
938 E1000_WRITE_REG(hw
, FCRTL
, hw
->fc_low_water
);
939 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
945 /******************************************************************************
946 * Sets up link for a fiber based or serdes based adapter
948 * hw - Struct containing variables accessed by shared code
950 * Manipulates Physical Coding Sublayer functions in order to configure
951 * link. Assumes the hardware has been previously reset and the transmitter
952 * and receiver are not enabled.
953 *****************************************************************************/
955 e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
)
964 DEBUGFUNC("e1000_setup_fiber_serdes_link");
966 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
967 * until explicitly turned off or a power cycle is performed. A read to
968 * the register does not indicate its status. Therefore, we ensure
969 * loopback mode is disabled during initialization.
971 if (hw
->mac_type
== e1000_82571
|| hw
->mac_type
== e1000_82572
)
972 E1000_WRITE_REG(hw
, SCTL
, E1000_DISABLE_SERDES_LOOPBACK
);
974 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
975 * set when the optics detect a signal. On older adapters, it will be
976 * cleared when there is a signal. This applies to fiber media only.
977 * If we're on serdes media, adjust the output amplitude to value set in
980 ctrl
= E1000_READ_REG(hw
, CTRL
);
981 if(hw
->media_type
== e1000_media_type_fiber
)
982 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
984 ret_val
= e1000_adjust_serdes_amplitude(hw
);
988 /* Take the link out of reset */
989 ctrl
&= ~(E1000_CTRL_LRST
);
991 /* Adjust VCO speed to improve BER performance */
992 ret_val
= e1000_set_vco_speed(hw
);
996 e1000_config_collision_dist(hw
);
998 /* Check for a software override of the flow control settings, and setup
999 * the device accordingly. If auto-negotiation is enabled, then software
1000 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1001 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1002 * auto-negotiation is disabled, then software will have to manually
1003 * configure the two flow control enable bits in the CTRL register.
1005 * The possible values of the "fc" parameter are:
1006 * 0: Flow control is completely disabled
1007 * 1: Rx flow control is enabled (we can receive pause frames, but
1008 * not send pause frames).
1009 * 2: Tx flow control is enabled (we can send pause frames but we do
1010 * not support receiving pause frames).
1011 * 3: Both Rx and TX flow control (symmetric) are enabled.
1015 /* Flow control is completely disabled by a software over-ride. */
1016 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
1018 case e1000_fc_rx_pause
:
1019 /* RX Flow control is enabled and TX Flow control is disabled by a
1020 * software over-ride. Since there really isn't a way to advertise
1021 * that we are capable of RX Pause ONLY, we will advertise that we
1022 * support both symmetric and asymmetric RX PAUSE. Later, we will
1023 * disable the adapter's ability to send PAUSE frames.
1025 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1027 case e1000_fc_tx_pause
:
1028 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1029 * software over-ride.
1031 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
1034 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1035 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1038 DEBUGOUT("Flow control param set incorrectly\n");
1039 return -E1000_ERR_CONFIG
;
1043 /* Since auto-negotiation is enabled, take the link out of reset (the link
1044 * will be in reset, because we previously reset the chip). This will
1045 * restart auto-negotiation. If auto-neogtiation is successful then the
1046 * link-up status bit will be set and the flow control enable bits (RFCE
1047 * and TFCE) will be set according to their negotiated value.
1049 DEBUGOUT("Auto-negotiation enabled\n");
1051 E1000_WRITE_REG(hw
, TXCW
, txcw
);
1052 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1053 E1000_WRITE_FLUSH(hw
);
1058 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1059 * indication in the Device Status Register. Time-out if a link isn't
1060 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1061 * less than 500 milliseconds even if the other end is doing it in SW).
1062 * For internal serdes, we just assume a signal is present, then poll.
1064 if(hw
->media_type
== e1000_media_type_internal_serdes
||
1065 (E1000_READ_REG(hw
, CTRL
) & E1000_CTRL_SWDPIN1
) == signal
) {
1066 DEBUGOUT("Looking for Link\n");
1067 for(i
= 0; i
< (LINK_UP_TIMEOUT
/ 10); i
++) {
1069 status
= E1000_READ_REG(hw
, STATUS
);
1070 if(status
& E1000_STATUS_LU
) break;
1072 if(i
== (LINK_UP_TIMEOUT
/ 10)) {
1073 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1074 hw
->autoneg_failed
= 1;
1075 /* AutoNeg failed to achieve a link, so we'll call
1076 * e1000_check_for_link. This routine will force the link up if
1077 * we detect a signal. This will allow us to communicate with
1078 * non-autonegotiating link partners.
1080 ret_val
= e1000_check_for_link(hw
);
1082 DEBUGOUT("Error while checking for link\n");
1085 hw
->autoneg_failed
= 0;
1087 hw
->autoneg_failed
= 0;
1088 DEBUGOUT("Valid Link Found\n");
1091 DEBUGOUT("No Signal Detected\n");
1093 return E1000_SUCCESS
;
1096 /******************************************************************************
1097 * Make sure we have a valid PHY and change PHY mode before link setup.
1099 * hw - Struct containing variables accessed by shared code
1100 ******************************************************************************/
1102 e1000_copper_link_preconfig(struct e1000_hw
*hw
)
1108 DEBUGFUNC("e1000_copper_link_preconfig");
1110 ctrl
= E1000_READ_REG(hw
, CTRL
);
1111 /* With 82543, we need to force speed and duplex on the MAC equal to what
1112 * the PHY speed and duplex configuration is. In addition, we need to
1113 * perform a hardware reset on the PHY to take it out of reset.
1115 if(hw
->mac_type
> e1000_82543
) {
1116 ctrl
|= E1000_CTRL_SLU
;
1117 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1118 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1120 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
| E1000_CTRL_SLU
);
1121 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1122 ret_val
= e1000_phy_hw_reset(hw
);
1127 /* Make sure we have a valid PHY */
1128 ret_val
= e1000_detect_gig_phy(hw
);
1130 DEBUGOUT("Error, did not detect valid phy.\n");
1133 DEBUGOUT1("Phy ID = %x \n", hw
->phy_id
);
1135 /* Set PHY to class A mode (if necessary) */
1136 ret_val
= e1000_set_phy_mode(hw
);
1140 if((hw
->mac_type
== e1000_82545_rev_3
) ||
1141 (hw
->mac_type
== e1000_82546_rev_3
)) {
1142 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1143 phy_data
|= 0x00000008;
1144 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1147 if(hw
->mac_type
<= e1000_82543
||
1148 hw
->mac_type
== e1000_82541
|| hw
->mac_type
== e1000_82547
||
1149 hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
)
1150 hw
->phy_reset_disable
= FALSE
;
1152 return E1000_SUCCESS
;
1156 /********************************************************************
1157 * Copper link setup for e1000_phy_igp series.
1159 * hw - Struct containing variables accessed by shared code
1160 *********************************************************************/
1162 e1000_copper_link_igp_setup(struct e1000_hw
*hw
)
1168 DEBUGFUNC("e1000_copper_link_igp_setup");
1170 if (hw
->phy_reset_disable
)
1171 return E1000_SUCCESS
;
1173 ret_val
= e1000_phy_reset(hw
);
1175 DEBUGOUT("Error Resetting the PHY\n");
1179 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1182 /* Configure activity LED after PHY reset */
1183 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
1184 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1185 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1186 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
1188 /* disable lplu d3 during driver init */
1189 ret_val
= e1000_set_d3_lplu_state(hw
, FALSE
);
1191 DEBUGOUT("Error Disabling LPLU D3\n");
1195 /* disable lplu d0 during driver init */
1196 ret_val
= e1000_set_d0_lplu_state(hw
, FALSE
);
1198 DEBUGOUT("Error Disabling LPLU D0\n");
1201 /* Configure mdi-mdix settings */
1202 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1206 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
1207 hw
->dsp_config_state
= e1000_dsp_config_disabled
;
1208 /* Force MDI for earlier revs of the IGP PHY */
1209 phy_data
&= ~(IGP01E1000_PSCR_AUTO_MDIX
| IGP01E1000_PSCR_FORCE_MDI_MDIX
);
1213 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1214 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1218 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1221 phy_data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1225 phy_data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1229 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1233 /* set auto-master slave resolution settings */
1235 e1000_ms_type phy_ms_setting
= hw
->master_slave
;
1237 if(hw
->ffe_config_state
== e1000_ffe_config_active
)
1238 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
1240 if(hw
->dsp_config_state
== e1000_dsp_config_activated
)
1241 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1243 /* when autonegotiation advertisment is only 1000Mbps then we
1244 * should disable SmartSpeed and enable Auto MasterSlave
1245 * resolution as hardware default. */
1246 if(hw
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1247 /* Disable SmartSpeed */
1248 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
1251 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1252 ret_val
= e1000_write_phy_reg(hw
,
1253 IGP01E1000_PHY_PORT_CONFIG
,
1257 /* Set auto Master/Slave resolution process */
1258 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1261 phy_data
&= ~CR_1000T_MS_ENABLE
;
1262 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1267 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1271 /* load defaults for future use */
1272 hw
->original_master_slave
= (phy_data
& CR_1000T_MS_ENABLE
) ?
1273 ((phy_data
& CR_1000T_MS_VALUE
) ?
1274 e1000_ms_force_master
:
1275 e1000_ms_force_slave
) :
1278 switch (phy_ms_setting
) {
1279 case e1000_ms_force_master
:
1280 phy_data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1282 case e1000_ms_force_slave
:
1283 phy_data
|= CR_1000T_MS_ENABLE
;
1284 phy_data
&= ~(CR_1000T_MS_VALUE
);
1287 phy_data
&= ~CR_1000T_MS_ENABLE
;
1291 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1296 return E1000_SUCCESS
;
1300 /********************************************************************
1301 * Copper link setup for e1000_phy_m88 series.
1303 * hw - Struct containing variables accessed by shared code
1304 *********************************************************************/
1306 e1000_copper_link_mgp_setup(struct e1000_hw
*hw
)
1311 DEBUGFUNC("e1000_copper_link_mgp_setup");
1313 if(hw
->phy_reset_disable
)
1314 return E1000_SUCCESS
;
1316 /* Enable CRS on TX. This must be set for half-duplex operation. */
1317 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1321 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1324 * MDI/MDI-X = 0 (default)
1325 * 0 - Auto for all speeds
1328 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1330 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1334 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
1337 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
1340 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
1344 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
1349 * disable_polarity_correction = 0 (default)
1350 * Automatic Correction for Reversed Cable Polarity
1354 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
1355 if(hw
->disable_polarity_correction
== 1)
1356 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
1357 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1361 /* Force TX_CLK in the Extended PHY Specific Control Register
1364 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1368 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1370 if (hw
->phy_revision
< M88E1011_I_REV_4
) {
1371 /* Configure Master and Slave downshift values */
1372 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
1373 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
1374 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
1375 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
1376 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1381 /* SW Reset the PHY so all changes take effect */
1382 ret_val
= e1000_phy_reset(hw
);
1384 DEBUGOUT("Error Resetting the PHY\n");
1388 return E1000_SUCCESS
;
1391 /********************************************************************
1392 * Setup auto-negotiation and flow control advertisements,
1393 * and then perform auto-negotiation.
1395 * hw - Struct containing variables accessed by shared code
1396 *********************************************************************/
1398 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1403 DEBUGFUNC("e1000_copper_link_autoneg");
1405 /* Perform some bounds checking on the hw->autoneg_advertised
1406 * parameter. If this variable is zero, then set it to the default.
1408 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1410 /* If autoneg_advertised is zero, we assume it was not defaulted
1411 * by the calling code so we set to advertise full capability.
1413 if(hw
->autoneg_advertised
== 0)
1414 hw
->autoneg_advertised
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1416 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1417 ret_val
= e1000_phy_setup_autoneg(hw
);
1419 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1422 DEBUGOUT("Restarting Auto-Neg\n");
1424 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1425 * the Auto Neg Restart bit in the PHY control register.
1427 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
1431 phy_data
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1432 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
1436 /* Does the user want to wait for Auto-Neg to complete here, or
1437 * check at a later time (for example, callback routine).
1439 if(hw
->wait_autoneg_complete
) {
1440 ret_val
= e1000_wait_autoneg(hw
);
1442 DEBUGOUT("Error while waiting for autoneg to complete\n");
1447 hw
->get_link_status
= TRUE
;
1449 return E1000_SUCCESS
;
1453 /******************************************************************************
1454 * Config the MAC and the PHY after link is up.
1455 * 1) Set up the MAC to the current PHY speed/duplex
1456 * if we are on 82543. If we
1457 * are on newer silicon, we only need to configure
1458 * collision distance in the Transmit Control Register.
1459 * 2) Set up flow control on the MAC to that established with
1461 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1463 * hw - Struct containing variables accessed by shared code
1464 ******************************************************************************/
1466 e1000_copper_link_postconfig(struct e1000_hw
*hw
)
1469 DEBUGFUNC("e1000_copper_link_postconfig");
1471 if(hw
->mac_type
>= e1000_82544
) {
1472 e1000_config_collision_dist(hw
);
1474 ret_val
= e1000_config_mac_to_phy(hw
);
1476 DEBUGOUT("Error configuring MAC to PHY settings\n");
1480 ret_val
= e1000_config_fc_after_link_up(hw
);
1482 DEBUGOUT("Error Configuring Flow Control\n");
1486 /* Config DSP to improve Giga link quality */
1487 if(hw
->phy_type
== e1000_phy_igp
) {
1488 ret_val
= e1000_config_dsp_after_link_change(hw
, TRUE
);
1490 DEBUGOUT("Error Configuring DSP after link up\n");
1495 return E1000_SUCCESS
;
1498 /******************************************************************************
1499 * Detects which PHY is present and setup the speed and duplex
1501 * hw - Struct containing variables accessed by shared code
1502 ******************************************************************************/
1504 e1000_setup_copper_link(struct e1000_hw
*hw
)
1510 DEBUGFUNC("e1000_setup_copper_link");
1512 /* Check if it is a valid PHY and set PHY mode if necessary. */
1513 ret_val
= e1000_copper_link_preconfig(hw
);
1517 if (hw
->phy_type
== e1000_phy_igp
||
1518 hw
->phy_type
== e1000_phy_igp_2
) {
1519 ret_val
= e1000_copper_link_igp_setup(hw
);
1522 } else if (hw
->phy_type
== e1000_phy_m88
) {
1523 ret_val
= e1000_copper_link_mgp_setup(hw
);
1529 /* Setup autoneg and flow control advertisement
1530 * and perform autonegotiation */
1531 ret_val
= e1000_copper_link_autoneg(hw
);
1535 /* PHY will be set to 10H, 10F, 100H,or 100F
1536 * depending on value from forced_speed_duplex. */
1537 DEBUGOUT("Forcing speed and duplex\n");
1538 ret_val
= e1000_phy_force_speed_duplex(hw
);
1540 DEBUGOUT("Error Forcing Speed and Duplex\n");
1545 /* Check link status. Wait up to 100 microseconds for link to become
1548 for(i
= 0; i
< 10; i
++) {
1549 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1552 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1556 if(phy_data
& MII_SR_LINK_STATUS
) {
1557 /* Config the MAC and PHY after link is up */
1558 ret_val
= e1000_copper_link_postconfig(hw
);
1562 DEBUGOUT("Valid link established!!!\n");
1563 return E1000_SUCCESS
;
1568 DEBUGOUT("Unable to establish link!!!\n");
1569 return E1000_SUCCESS
;
1572 /******************************************************************************
1573 * Configures PHY autoneg and flow control advertisement settings
1575 * hw - Struct containing variables accessed by shared code
1576 ******************************************************************************/
1578 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1581 uint16_t mii_autoneg_adv_reg
;
1582 uint16_t mii_1000t_ctrl_reg
;
1584 DEBUGFUNC("e1000_phy_setup_autoneg");
1586 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1587 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1591 /* Read the MII 1000Base-T Control Register (Address 9). */
1592 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
1596 /* Need to parse both autoneg_advertised and fc and set up
1597 * the appropriate PHY registers. First we will parse for
1598 * autoneg_advertised software override. Since we can advertise
1599 * a plethora of combinations, we need to check each bit
1603 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1604 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1605 * the 1000Base-T Control Register (Address 9).
1607 mii_autoneg_adv_reg
&= ~REG4_SPEED_MASK
;
1608 mii_1000t_ctrl_reg
&= ~REG9_SPEED_MASK
;
1610 DEBUGOUT1("autoneg_advertised %x\n", hw
->autoneg_advertised
);
1612 /* Do we want to advertise 10 Mb Half Duplex? */
1613 if(hw
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1614 DEBUGOUT("Advertise 10mb Half duplex\n");
1615 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1618 /* Do we want to advertise 10 Mb Full Duplex? */
1619 if(hw
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1620 DEBUGOUT("Advertise 10mb Full duplex\n");
1621 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1624 /* Do we want to advertise 100 Mb Half Duplex? */
1625 if(hw
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1626 DEBUGOUT("Advertise 100mb Half duplex\n");
1627 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1630 /* Do we want to advertise 100 Mb Full Duplex? */
1631 if(hw
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1632 DEBUGOUT("Advertise 100mb Full duplex\n");
1633 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1636 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1637 if(hw
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
1638 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1641 /* Do we want to advertise 1000 Mb Full Duplex? */
1642 if(hw
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1643 DEBUGOUT("Advertise 1000mb Full duplex\n");
1644 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1647 /* Check for a software override of the flow control settings, and
1648 * setup the PHY advertisement registers accordingly. If
1649 * auto-negotiation is enabled, then software will have to set the
1650 * "PAUSE" bits to the correct value in the Auto-Negotiation
1651 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1653 * The possible values of the "fc" parameter are:
1654 * 0: Flow control is completely disabled
1655 * 1: Rx flow control is enabled (we can receive pause frames
1656 * but not send pause frames).
1657 * 2: Tx flow control is enabled (we can send pause frames
1658 * but we do not support receiving pause frames).
1659 * 3: Both Rx and TX flow control (symmetric) are enabled.
1660 * other: No software override. The flow control configuration
1661 * in the EEPROM is used.
1664 case e1000_fc_none
: /* 0 */
1665 /* Flow control (RX & TX) is completely disabled by a
1666 * software over-ride.
1668 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1670 case e1000_fc_rx_pause
: /* 1 */
1671 /* RX Flow control is enabled, and TX Flow control is
1672 * disabled, by a software over-ride.
1674 /* Since there really isn't a way to advertise that we are
1675 * capable of RX Pause ONLY, we will advertise that we
1676 * support both symmetric and asymmetric RX PAUSE. Later
1677 * (in e1000_config_fc_after_link_up) we will disable the
1678 *hw's ability to send PAUSE frames.
1680 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1682 case e1000_fc_tx_pause
: /* 2 */
1683 /* TX Flow control is enabled, and RX Flow control is
1684 * disabled, by a software over-ride.
1686 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1687 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1689 case e1000_fc_full
: /* 3 */
1690 /* Flow control (both RX and TX) is enabled by a software
1693 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1696 DEBUGOUT("Flow control param set incorrectly\n");
1697 return -E1000_ERR_CONFIG
;
1700 ret_val
= e1000_write_phy_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1704 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1706 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1710 return E1000_SUCCESS
;
1713 /******************************************************************************
1714 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1716 * hw - Struct containing variables accessed by shared code
1717 ******************************************************************************/
1719 e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1723 uint16_t mii_ctrl_reg
;
1724 uint16_t mii_status_reg
;
1728 DEBUGFUNC("e1000_phy_force_speed_duplex");
1730 /* Turn off Flow control if we are forcing speed and duplex. */
1731 hw
->fc
= e1000_fc_none
;
1733 DEBUGOUT1("hw->fc = %d\n", hw
->fc
);
1735 /* Read the Device Control Register. */
1736 ctrl
= E1000_READ_REG(hw
, CTRL
);
1738 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1739 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1740 ctrl
&= ~(DEVICE_SPEED_MASK
);
1742 /* Clear the Auto Speed Detect Enable bit. */
1743 ctrl
&= ~E1000_CTRL_ASDE
;
1745 /* Read the MII Control Register. */
1746 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &mii_ctrl_reg
);
1750 /* We need to disable autoneg in order to force link and duplex. */
1752 mii_ctrl_reg
&= ~MII_CR_AUTO_NEG_EN
;
1754 /* Are we forcing Full or Half Duplex? */
1755 if(hw
->forced_speed_duplex
== e1000_100_full
||
1756 hw
->forced_speed_duplex
== e1000_10_full
) {
1757 /* We want to force full duplex so we SET the full duplex bits in the
1758 * Device and MII Control Registers.
1760 ctrl
|= E1000_CTRL_FD
;
1761 mii_ctrl_reg
|= MII_CR_FULL_DUPLEX
;
1762 DEBUGOUT("Full Duplex\n");
1764 /* We want to force half duplex so we CLEAR the full duplex bits in
1765 * the Device and MII Control Registers.
1767 ctrl
&= ~E1000_CTRL_FD
;
1768 mii_ctrl_reg
&= ~MII_CR_FULL_DUPLEX
;
1769 DEBUGOUT("Half Duplex\n");
1772 /* Are we forcing 100Mbps??? */
1773 if(hw
->forced_speed_duplex
== e1000_100_full
||
1774 hw
->forced_speed_duplex
== e1000_100_half
) {
1775 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1776 ctrl
|= E1000_CTRL_SPD_100
;
1777 mii_ctrl_reg
|= MII_CR_SPEED_100
;
1778 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1779 DEBUGOUT("Forcing 100mb ");
1781 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1782 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1783 mii_ctrl_reg
|= MII_CR_SPEED_10
;
1784 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1785 DEBUGOUT("Forcing 10mb ");
1788 e1000_config_collision_dist(hw
);
1790 /* Write the configured values back to the Device Control Reg. */
1791 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1793 if (hw
->phy_type
== e1000_phy_m88
) {
1794 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1798 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1799 * forced whenever speed are duplex are forced.
1801 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1802 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1806 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data
);
1808 /* Need to reset the PHY or these changes will be ignored */
1809 mii_ctrl_reg
|= MII_CR_RESET
;
1811 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1812 * forced whenever speed or duplex are forced.
1814 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1818 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1819 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1821 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1826 /* Write back the modified PHY MII control register. */
1827 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, mii_ctrl_reg
);
1833 /* The wait_autoneg_complete flag may be a little misleading here.
1834 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1835 * But we do want to delay for a period while forcing only so we
1836 * don't generate false No Link messages. So we will wait here
1837 * only if the user has set wait_autoneg_complete to 1, which is
1840 if(hw
->wait_autoneg_complete
) {
1841 /* We will wait for autoneg to complete. */
1842 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1845 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1846 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1847 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1850 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1854 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1858 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1862 (hw
->phy_type
== e1000_phy_m88
)) {
1863 /* We didn't get link. Reset the DSP and wait again for link. */
1864 ret_val
= e1000_phy_reset_dsp(hw
);
1866 DEBUGOUT("Error Resetting PHY DSP\n");
1870 /* This loop will early-out if the link condition has been met. */
1871 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1872 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1874 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1877 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1881 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1887 if (hw
->phy_type
== e1000_phy_m88
) {
1888 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1889 * Extended PHY Specific Control Register to 25MHz clock. This value
1890 * defaults back to a 2.5MHz clock when the PHY is reset.
1892 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1896 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1897 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1901 /* In addition, because of the s/w reset above, we need to enable CRS on
1902 * TX. This must be set for both full and half duplex operation.
1904 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1908 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1909 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1913 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
1915 (hw
->forced_speed_duplex
== e1000_10_full
||
1916 hw
->forced_speed_duplex
== e1000_10_half
)) {
1917 ret_val
= e1000_polarity_reversal_workaround(hw
);
1922 return E1000_SUCCESS
;
1925 /******************************************************************************
1926 * Sets the collision distance in the Transmit Control register
1928 * hw - Struct containing variables accessed by shared code
1930 * Link should have been established previously. Reads the speed and duplex
1931 * information from the Device Status register.
1932 ******************************************************************************/
1934 e1000_config_collision_dist(struct e1000_hw
*hw
)
1936 uint32_t tctl
, coll_dist
;
1938 DEBUGFUNC("e1000_config_collision_dist");
1940 if (hw
->mac_type
< e1000_82543
)
1941 coll_dist
= E1000_COLLISION_DISTANCE_82542
;
1943 coll_dist
= E1000_COLLISION_DISTANCE
;
1945 tctl
= E1000_READ_REG(hw
, TCTL
);
1947 tctl
&= ~E1000_TCTL_COLD
;
1948 tctl
|= coll_dist
<< E1000_COLD_SHIFT
;
1950 E1000_WRITE_REG(hw
, TCTL
, tctl
);
1951 E1000_WRITE_FLUSH(hw
);
1954 /******************************************************************************
1955 * Sets MAC speed and duplex settings to reflect the those in the PHY
1957 * hw - Struct containing variables accessed by shared code
1958 * mii_reg - data to write to the MII control register
1960 * The contents of the PHY register containing the needed information need to
1962 ******************************************************************************/
1964 e1000_config_mac_to_phy(struct e1000_hw
*hw
)
1970 DEBUGFUNC("e1000_config_mac_to_phy");
1972 /* 82544 or newer MAC, Auto Speed Detection takes care of
1973 * MAC speed/duplex configuration.*/
1974 if (hw
->mac_type
>= e1000_82544
)
1975 return E1000_SUCCESS
;
1977 /* Read the Device Control Register and set the bits to Force Speed
1980 ctrl
= E1000_READ_REG(hw
, CTRL
);
1981 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1982 ctrl
&= ~(E1000_CTRL_SPD_SEL
| E1000_CTRL_ILOS
);
1984 /* Set up duplex in the Device Control and Transmit Control
1985 * registers depending on negotiated values.
1987 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1991 if(phy_data
& M88E1000_PSSR_DPLX
)
1992 ctrl
|= E1000_CTRL_FD
;
1994 ctrl
&= ~E1000_CTRL_FD
;
1996 e1000_config_collision_dist(hw
);
1998 /* Set up speed in the Device Control register depending on
1999 * negotiated values.
2001 if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
2002 ctrl
|= E1000_CTRL_SPD_1000
;
2003 else if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
2004 ctrl
|= E1000_CTRL_SPD_100
;
2006 /* Write the configured values back to the Device Control Reg. */
2007 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2008 return E1000_SUCCESS
;
2011 /******************************************************************************
2012 * Forces the MAC's flow control settings.
2014 * hw - Struct containing variables accessed by shared code
2016 * Sets the TFCE and RFCE bits in the device control register to reflect
2017 * the adapter settings. TFCE and RFCE need to be explicitly set by
2018 * software when a Copper PHY is used because autonegotiation is managed
2019 * by the PHY rather than the MAC. Software must also configure these
2020 * bits when link is forced on a fiber connection.
2021 *****************************************************************************/
2023 e1000_force_mac_fc(struct e1000_hw
*hw
)
2027 DEBUGFUNC("e1000_force_mac_fc");
2029 /* Get the current configuration of the Device Control Register */
2030 ctrl
= E1000_READ_REG(hw
, CTRL
);
2032 /* Because we didn't get link via the internal auto-negotiation
2033 * mechanism (we either forced link or we got link via PHY
2034 * auto-neg), we have to manually enable/disable transmit an
2035 * receive flow control.
2037 * The "Case" statement below enables/disable flow control
2038 * according to the "hw->fc" parameter.
2040 * The possible values of the "fc" parameter are:
2041 * 0: Flow control is completely disabled
2042 * 1: Rx flow control is enabled (we can receive pause
2043 * frames but not send pause frames).
2044 * 2: Tx flow control is enabled (we can send pause frames
2045 * frames but we do not receive pause frames).
2046 * 3: Both Rx and TX flow control (symmetric) is enabled.
2047 * other: No other values should be possible at this point.
2052 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
2054 case e1000_fc_rx_pause
:
2055 ctrl
&= (~E1000_CTRL_TFCE
);
2056 ctrl
|= E1000_CTRL_RFCE
;
2058 case e1000_fc_tx_pause
:
2059 ctrl
&= (~E1000_CTRL_RFCE
);
2060 ctrl
|= E1000_CTRL_TFCE
;
2063 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
2066 DEBUGOUT("Flow control param set incorrectly\n");
2067 return -E1000_ERR_CONFIG
;
2070 /* Disable TX Flow Control for 82542 (rev 2.0) */
2071 if(hw
->mac_type
== e1000_82542_rev2_0
)
2072 ctrl
&= (~E1000_CTRL_TFCE
);
2074 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2075 return E1000_SUCCESS
;
2078 /******************************************************************************
2079 * Configures flow control settings after link is established
2081 * hw - Struct containing variables accessed by shared code
2083 * Should be called immediately after a valid link has been established.
2084 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2085 * and autonegotiation is enabled, the MAC flow control settings will be set
2086 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2087 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2088 *****************************************************************************/
2090 e1000_config_fc_after_link_up(struct e1000_hw
*hw
)
2093 uint16_t mii_status_reg
;
2094 uint16_t mii_nway_adv_reg
;
2095 uint16_t mii_nway_lp_ability_reg
;
2099 DEBUGFUNC("e1000_config_fc_after_link_up");
2101 /* Check for the case where we have fiber media and auto-neg failed
2102 * so we had to force link. In this case, we need to force the
2103 * configuration of the MAC to match the "fc" parameter.
2105 if(((hw
->media_type
== e1000_media_type_fiber
) && (hw
->autoneg_failed
)) ||
2106 ((hw
->media_type
== e1000_media_type_internal_serdes
) && (hw
->autoneg_failed
)) ||
2107 ((hw
->media_type
== e1000_media_type_copper
) && (!hw
->autoneg
))) {
2108 ret_val
= e1000_force_mac_fc(hw
);
2110 DEBUGOUT("Error forcing flow control settings\n");
2115 /* Check for the case where we have copper media and auto-neg is
2116 * enabled. In this case, we need to check and see if Auto-Neg
2117 * has completed, and if so, how the PHY and link partner has
2118 * flow control configured.
2120 if((hw
->media_type
== e1000_media_type_copper
) && hw
->autoneg
) {
2121 /* Read the MII Status Register and check to see if AutoNeg
2122 * has completed. We read this twice because this reg has
2123 * some "sticky" (latched) bits.
2125 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2128 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2132 if(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
) {
2133 /* The AutoNeg process has completed, so we now need to
2134 * read both the Auto Negotiation Advertisement Register
2135 * (Address 4) and the Auto_Negotiation Base Page Ability
2136 * Register (Address 5) to determine how flow control was
2139 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
,
2143 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
,
2144 &mii_nway_lp_ability_reg
);
2148 /* Two bits in the Auto Negotiation Advertisement Register
2149 * (Address 4) and two bits in the Auto Negotiation Base
2150 * Page Ability Register (Address 5) determine flow control
2151 * for both the PHY and the link partner. The following
2152 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2153 * 1999, describes these PAUSE resolution bits and how flow
2154 * control is determined based upon these settings.
2155 * NOTE: DC = Don't Care
2157 * LOCAL DEVICE | LINK PARTNER
2158 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2159 *-------|---------|-------|---------|--------------------
2160 * 0 | 0 | DC | DC | e1000_fc_none
2161 * 0 | 1 | 0 | DC | e1000_fc_none
2162 * 0 | 1 | 1 | 0 | e1000_fc_none
2163 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2164 * 1 | 0 | 0 | DC | e1000_fc_none
2165 * 1 | DC | 1 | DC | e1000_fc_full
2166 * 1 | 1 | 0 | 0 | e1000_fc_none
2167 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2170 /* Are both PAUSE bits set to 1? If so, this implies
2171 * Symmetric Flow Control is enabled at both ends. The
2172 * ASM_DIR bits are irrelevant per the spec.
2174 * For Symmetric Flow Control:
2176 * LOCAL DEVICE | LINK PARTNER
2177 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2178 *-------|---------|-------|---------|--------------------
2179 * 1 | DC | 1 | DC | e1000_fc_full
2182 if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2183 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
2184 /* Now we need to check if the user selected RX ONLY
2185 * of pause frames. In this case, we had to advertise
2186 * FULL flow control because we could not advertise RX
2187 * ONLY. Hence, we must now check to see if we need to
2188 * turn OFF the TRANSMISSION of PAUSE frames.
2190 if(hw
->original_fc
== e1000_fc_full
) {
2191 hw
->fc
= e1000_fc_full
;
2192 DEBUGOUT("Flow Control = FULL.\r\n");
2194 hw
->fc
= e1000_fc_rx_pause
;
2195 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2198 /* For receiving PAUSE frames ONLY.
2200 * LOCAL DEVICE | LINK PARTNER
2201 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2202 *-------|---------|-------|---------|--------------------
2203 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2206 else if(!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2207 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2208 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2209 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2210 hw
->fc
= e1000_fc_tx_pause
;
2211 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2213 /* For transmitting PAUSE frames ONLY.
2215 * LOCAL DEVICE | LINK PARTNER
2216 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2217 *-------|---------|-------|---------|--------------------
2218 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2221 else if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2222 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2223 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2224 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2225 hw
->fc
= e1000_fc_rx_pause
;
2226 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2228 /* Per the IEEE spec, at this point flow control should be
2229 * disabled. However, we want to consider that we could
2230 * be connected to a legacy switch that doesn't advertise
2231 * desired flow control, but can be forced on the link
2232 * partner. So if we advertised no flow control, that is
2233 * what we will resolve to. If we advertised some kind of
2234 * receive capability (Rx Pause Only or Full Flow Control)
2235 * and the link partner advertised none, we will configure
2236 * ourselves to enable Rx Flow Control only. We can do
2237 * this safely for two reasons: If the link partner really
2238 * didn't want flow control enabled, and we enable Rx, no
2239 * harm done since we won't be receiving any PAUSE frames
2240 * anyway. If the intent on the link partner was to have
2241 * flow control enabled, then by us enabling RX only, we
2242 * can at least receive pause frames and process them.
2243 * This is a good idea because in most cases, since we are
2244 * predominantly a server NIC, more times than not we will
2245 * be asked to delay transmission of packets than asking
2246 * our link partner to pause transmission of frames.
2248 else if((hw
->original_fc
== e1000_fc_none
||
2249 hw
->original_fc
== e1000_fc_tx_pause
) ||
2250 hw
->fc_strict_ieee
) {
2251 hw
->fc
= e1000_fc_none
;
2252 DEBUGOUT("Flow Control = NONE.\r\n");
2254 hw
->fc
= e1000_fc_rx_pause
;
2255 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2258 /* Now we need to do one last check... If we auto-
2259 * negotiated to HALF DUPLEX, flow control should not be
2260 * enabled per IEEE 802.3 spec.
2262 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2264 DEBUGOUT("Error getting link speed and duplex\n");
2268 if(duplex
== HALF_DUPLEX
)
2269 hw
->fc
= e1000_fc_none
;
2271 /* Now we call a subroutine to actually force the MAC
2272 * controller to use the correct flow control settings.
2274 ret_val
= e1000_force_mac_fc(hw
);
2276 DEBUGOUT("Error forcing flow control settings\n");
2280 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2283 return E1000_SUCCESS
;
2286 /******************************************************************************
2287 * Checks to see if the link status of the hardware has changed.
2289 * hw - Struct containing variables accessed by shared code
2291 * Called by any function that needs to check the link status of the adapter.
2292 *****************************************************************************/
2294 e1000_check_for_link(struct e1000_hw
*hw
)
2301 uint32_t signal
= 0;
2305 DEBUGFUNC("e1000_check_for_link");
2307 ctrl
= E1000_READ_REG(hw
, CTRL
);
2308 status
= E1000_READ_REG(hw
, STATUS
);
2310 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2311 * set when the optics detect a signal. On older adapters, it will be
2312 * cleared when there is a signal. This applies to fiber media only.
2314 if((hw
->media_type
== e1000_media_type_fiber
) ||
2315 (hw
->media_type
== e1000_media_type_internal_serdes
)) {
2316 rxcw
= E1000_READ_REG(hw
, RXCW
);
2318 if(hw
->media_type
== e1000_media_type_fiber
) {
2319 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
2320 if(status
& E1000_STATUS_LU
)
2321 hw
->get_link_status
= FALSE
;
2325 /* If we have a copper PHY then we only want to go out to the PHY
2326 * registers to see if Auto-Neg has completed and/or if our link
2327 * status has changed. The get_link_status flag will be set if we
2328 * receive a Link Status Change interrupt or we have Rx Sequence
2331 if((hw
->media_type
== e1000_media_type_copper
) && hw
->get_link_status
) {
2332 /* First we want to see if the MII Status Register reports
2333 * link. If so, then we want to get the current speed/duplex
2335 * Read the register twice since the link bit is sticky.
2337 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2340 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2344 if(phy_data
& MII_SR_LINK_STATUS
) {
2345 hw
->get_link_status
= FALSE
;
2346 /* Check if there was DownShift, must be checked immediately after
2348 e1000_check_downshift(hw
);
2350 /* If we are on 82544 or 82543 silicon and speed/duplex
2351 * are forced to 10H or 10F, then we will implement the polarity
2352 * reversal workaround. We disable interrupts first, and upon
2353 * returning, place the devices interrupt state to its previous
2354 * value except for the link status change interrupt which will
2355 * happen due to the execution of this workaround.
2358 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
2360 (hw
->forced_speed_duplex
== e1000_10_full
||
2361 hw
->forced_speed_duplex
== e1000_10_half
)) {
2362 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
2363 ret_val
= e1000_polarity_reversal_workaround(hw
);
2364 icr
= E1000_READ_REG(hw
, ICR
);
2365 E1000_WRITE_REG(hw
, ICS
, (icr
& ~E1000_ICS_LSC
));
2366 E1000_WRITE_REG(hw
, IMS
, IMS_ENABLE_MASK
);
2370 /* No link detected */
2371 e1000_config_dsp_after_link_change(hw
, FALSE
);
2375 /* If we are forcing speed/duplex, then we simply return since
2376 * we have already determined whether we have link or not.
2378 if(!hw
->autoneg
) return -E1000_ERR_CONFIG
;
2380 /* optimize the dsp settings for the igp phy */
2381 e1000_config_dsp_after_link_change(hw
, TRUE
);
2383 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2384 * have Si on board that is 82544 or newer, Auto
2385 * Speed Detection takes care of MAC speed/duplex
2386 * configuration. So we only need to configure Collision
2387 * Distance in the MAC. Otherwise, we need to force
2388 * speed/duplex on the MAC to the current PHY speed/duplex
2391 if(hw
->mac_type
>= e1000_82544
)
2392 e1000_config_collision_dist(hw
);
2394 ret_val
= e1000_config_mac_to_phy(hw
);
2396 DEBUGOUT("Error configuring MAC to PHY settings\n");
2401 /* Configure Flow Control now that Auto-Neg has completed. First, we
2402 * need to restore the desired flow control settings because we may
2403 * have had to re-autoneg with a different link partner.
2405 ret_val
= e1000_config_fc_after_link_up(hw
);
2407 DEBUGOUT("Error configuring flow control\n");
2411 /* At this point we know that we are on copper and we have
2412 * auto-negotiated link. These are conditions for checking the link
2413 * partner capability register. We use the link speed to determine if
2414 * TBI compatibility needs to be turned on or off. If the link is not
2415 * at gigabit speed, then TBI compatibility is not needed. If we are
2416 * at gigabit speed, we turn on TBI compatibility.
2418 if(hw
->tbi_compatibility_en
) {
2419 uint16_t speed
, duplex
;
2420 e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2421 if(speed
!= SPEED_1000
) {
2422 /* If link speed is not set to gigabit speed, we do not need
2423 * to enable TBI compatibility.
2425 if(hw
->tbi_compatibility_on
) {
2426 /* If we previously were in the mode, turn it off. */
2427 rctl
= E1000_READ_REG(hw
, RCTL
);
2428 rctl
&= ~E1000_RCTL_SBP
;
2429 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2430 hw
->tbi_compatibility_on
= FALSE
;
2433 /* If TBI compatibility is was previously off, turn it on. For
2434 * compatibility with a TBI link partner, we will store bad
2435 * packets. Some frames have an additional byte on the end and
2436 * will look like CRC errors to to the hardware.
2438 if(!hw
->tbi_compatibility_on
) {
2439 hw
->tbi_compatibility_on
= TRUE
;
2440 rctl
= E1000_READ_REG(hw
, RCTL
);
2441 rctl
|= E1000_RCTL_SBP
;
2442 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2447 /* If we don't have link (auto-negotiation failed or link partner cannot
2448 * auto-negotiate), the cable is plugged in (we have signal), and our
2449 * link partner is not trying to auto-negotiate with us (we are receiving
2450 * idles or data), we need to force link up. We also need to give
2451 * auto-negotiation time to complete, in case the cable was just plugged
2452 * in. The autoneg_failed flag does this.
2454 else if((((hw
->media_type
== e1000_media_type_fiber
) &&
2455 ((ctrl
& E1000_CTRL_SWDPIN1
) == signal
)) ||
2456 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2457 (!(status
& E1000_STATUS_LU
)) &&
2458 (!(rxcw
& E1000_RXCW_C
))) {
2459 if(hw
->autoneg_failed
== 0) {
2460 hw
->autoneg_failed
= 1;
2463 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2465 /* Disable auto-negotiation in the TXCW register */
2466 E1000_WRITE_REG(hw
, TXCW
, (hw
->txcw
& ~E1000_TXCW_ANE
));
2468 /* Force link-up and also force full-duplex. */
2469 ctrl
= E1000_READ_REG(hw
, CTRL
);
2470 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
2471 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2473 /* Configure Flow Control after forcing link up. */
2474 ret_val
= e1000_config_fc_after_link_up(hw
);
2476 DEBUGOUT("Error configuring flow control\n");
2480 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2481 * auto-negotiation in the TXCW register and disable forced link in the
2482 * Device Control register in an attempt to auto-negotiate with our link
2485 else if(((hw
->media_type
== e1000_media_type_fiber
) ||
2486 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2487 (ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
2488 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2489 E1000_WRITE_REG(hw
, TXCW
, hw
->txcw
);
2490 E1000_WRITE_REG(hw
, CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
2492 hw
->serdes_link_down
= FALSE
;
2494 /* If we force link for non-auto-negotiation switch, check link status
2495 * based on MAC synchronization for internal serdes media type.
2497 else if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2498 !(E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2499 /* SYNCH bit and IV bit are sticky. */
2501 if(E1000_RXCW_SYNCH
& E1000_READ_REG(hw
, RXCW
)) {
2502 if(!(rxcw
& E1000_RXCW_IV
)) {
2503 hw
->serdes_link_down
= FALSE
;
2504 DEBUGOUT("SERDES: Link is up.\n");
2507 hw
->serdes_link_down
= TRUE
;
2508 DEBUGOUT("SERDES: Link is down.\n");
2511 if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2512 (E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2513 hw
->serdes_link_down
= !(E1000_STATUS_LU
& E1000_READ_REG(hw
, STATUS
));
2515 return E1000_SUCCESS
;
2518 /******************************************************************************
2519 * Detects the current speed and duplex settings of the hardware.
2521 * hw - Struct containing variables accessed by shared code
2522 * speed - Speed of the connection
2523 * duplex - Duplex setting of the connection
2524 *****************************************************************************/
2526 e1000_get_speed_and_duplex(struct e1000_hw
*hw
,
2534 DEBUGFUNC("e1000_get_speed_and_duplex");
2536 if(hw
->mac_type
>= e1000_82543
) {
2537 status
= E1000_READ_REG(hw
, STATUS
);
2538 if(status
& E1000_STATUS_SPEED_1000
) {
2539 *speed
= SPEED_1000
;
2540 DEBUGOUT("1000 Mbs, ");
2541 } else if(status
& E1000_STATUS_SPEED_100
) {
2543 DEBUGOUT("100 Mbs, ");
2546 DEBUGOUT("10 Mbs, ");
2549 if(status
& E1000_STATUS_FD
) {
2550 *duplex
= FULL_DUPLEX
;
2551 DEBUGOUT("Full Duplex\r\n");
2553 *duplex
= HALF_DUPLEX
;
2554 DEBUGOUT(" Half Duplex\r\n");
2557 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2558 *speed
= SPEED_1000
;
2559 *duplex
= FULL_DUPLEX
;
2562 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2563 * if it is operating at half duplex. Here we set the duplex settings to
2564 * match the duplex in the link partner's capabilities.
2566 if(hw
->phy_type
== e1000_phy_igp
&& hw
->speed_downgraded
) {
2567 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_EXP
, &phy_data
);
2571 if(!(phy_data
& NWAY_ER_LP_NWAY_CAPS
))
2572 *duplex
= HALF_DUPLEX
;
2574 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
, &phy_data
);
2577 if((*speed
== SPEED_100
&& !(phy_data
& NWAY_LPAR_100TX_FD_CAPS
)) ||
2578 (*speed
== SPEED_10
&& !(phy_data
& NWAY_LPAR_10T_FD_CAPS
)))
2579 *duplex
= HALF_DUPLEX
;
2583 return E1000_SUCCESS
;
2586 /******************************************************************************
2587 * Blocks until autoneg completes or times out (~4.5 seconds)
2589 * hw - Struct containing variables accessed by shared code
2590 ******************************************************************************/
2592 e1000_wait_autoneg(struct e1000_hw
*hw
)
2598 DEBUGFUNC("e1000_wait_autoneg");
2599 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2601 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2602 for(i
= PHY_AUTO_NEG_TIME
; i
> 0; i
--) {
2603 /* Read the MII Status Register and wait for Auto-Neg
2604 * Complete bit to be set.
2606 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2609 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2612 if(phy_data
& MII_SR_AUTONEG_COMPLETE
) {
2613 return E1000_SUCCESS
;
2617 return E1000_SUCCESS
;
2620 /******************************************************************************
2621 * Raises the Management Data Clock
2623 * hw - Struct containing variables accessed by shared code
2624 * ctrl - Device control register's current value
2625 ******************************************************************************/
2627 e1000_raise_mdi_clk(struct e1000_hw
*hw
,
2630 /* Raise the clock input to the Management Data Clock (by setting the MDC
2631 * bit), and then delay 10 microseconds.
2633 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
| E1000_CTRL_MDC
));
2634 E1000_WRITE_FLUSH(hw
);
2638 /******************************************************************************
2639 * Lowers the Management Data Clock
2641 * hw - Struct containing variables accessed by shared code
2642 * ctrl - Device control register's current value
2643 ******************************************************************************/
2645 e1000_lower_mdi_clk(struct e1000_hw
*hw
,
2648 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2649 * bit), and then delay 10 microseconds.
2651 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
2652 E1000_WRITE_FLUSH(hw
);
2656 /******************************************************************************
2657 * Shifts data bits out to the PHY
2659 * hw - Struct containing variables accessed by shared code
2660 * data - Data to send out to the PHY
2661 * count - Number of bits to shift out
2663 * Bits are shifted out in MSB to LSB order.
2664 ******************************************************************************/
2666 e1000_shift_out_mdi_bits(struct e1000_hw
*hw
,
2673 /* We need to shift "count" number of bits out to the PHY. So, the value
2674 * in the "data" parameter will be shifted out to the PHY one bit at a
2675 * time. In order to do this, "data" must be broken down into bits.
2678 mask
<<= (count
- 1);
2680 ctrl
= E1000_READ_REG(hw
, CTRL
);
2682 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2683 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
2686 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2687 * then raising and lowering the Management Data Clock. A "0" is
2688 * shifted out to the PHY by setting the MDIO bit to "0" and then
2689 * raising and lowering the clock.
2691 if(data
& mask
) ctrl
|= E1000_CTRL_MDIO
;
2692 else ctrl
&= ~E1000_CTRL_MDIO
;
2694 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2695 E1000_WRITE_FLUSH(hw
);
2699 e1000_raise_mdi_clk(hw
, &ctrl
);
2700 e1000_lower_mdi_clk(hw
, &ctrl
);
2706 /******************************************************************************
2707 * Shifts data bits in from the PHY
2709 * hw - Struct containing variables accessed by shared code
2711 * Bits are shifted in in MSB to LSB order.
2712 ******************************************************************************/
2714 e1000_shift_in_mdi_bits(struct e1000_hw
*hw
)
2720 /* In order to read a register from the PHY, we need to shift in a total
2721 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2722 * to avoid contention on the MDIO pin when a read operation is performed.
2723 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2724 * by raising the input to the Management Data Clock (setting the MDC bit),
2725 * and then reading the value of the MDIO bit.
2727 ctrl
= E1000_READ_REG(hw
, CTRL
);
2729 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2730 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
2731 ctrl
&= ~E1000_CTRL_MDIO
;
2733 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2734 E1000_WRITE_FLUSH(hw
);
2736 /* Raise and Lower the clock before reading in the data. This accounts for
2737 * the turnaround bits. The first clock occurred when we clocked out the
2738 * last bit of the Register Address.
2740 e1000_raise_mdi_clk(hw
, &ctrl
);
2741 e1000_lower_mdi_clk(hw
, &ctrl
);
2743 for(data
= 0, i
= 0; i
< 16; i
++) {
2745 e1000_raise_mdi_clk(hw
, &ctrl
);
2746 ctrl
= E1000_READ_REG(hw
, CTRL
);
2747 /* Check to see if we shifted in a "1". */
2748 if(ctrl
& E1000_CTRL_MDIO
) data
|= 1;
2749 e1000_lower_mdi_clk(hw
, &ctrl
);
2752 e1000_raise_mdi_clk(hw
, &ctrl
);
2753 e1000_lower_mdi_clk(hw
, &ctrl
);
2758 /*****************************************************************************
2759 * Reads the value from a PHY register, if the value is on a specific non zero
2760 * page, sets the page first.
2761 * hw - Struct containing variables accessed by shared code
2762 * reg_addr - address of the PHY register to read
2763 ******************************************************************************/
2765 e1000_read_phy_reg(struct e1000_hw
*hw
,
2771 DEBUGFUNC("e1000_read_phy_reg");
2773 if((hw
->phy_type
== e1000_phy_igp
||
2774 hw
->phy_type
== e1000_phy_igp_2
) &&
2775 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2776 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2777 (uint16_t)reg_addr
);
2783 ret_val
= e1000_read_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2790 e1000_read_phy_reg_ex(struct e1000_hw
*hw
,
2796 const uint32_t phy_addr
= 1;
2798 DEBUGFUNC("e1000_read_phy_reg_ex");
2800 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2801 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2802 return -E1000_ERR_PARAM
;
2805 if(hw
->mac_type
> e1000_82543
) {
2806 /* Set up Op-code, Phy Address, and register address in the MDI
2807 * Control register. The MAC will take care of interfacing with the
2808 * PHY to retrieve the desired data.
2810 mdic
= ((reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2811 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2812 (E1000_MDIC_OP_READ
));
2814 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2816 /* Poll the ready bit to see if the MDI read completed */
2817 for(i
= 0; i
< 64; i
++) {
2819 mdic
= E1000_READ_REG(hw
, MDIC
);
2820 if(mdic
& E1000_MDIC_READY
) break;
2822 if(!(mdic
& E1000_MDIC_READY
)) {
2823 DEBUGOUT("MDI Read did not complete\n");
2824 return -E1000_ERR_PHY
;
2826 if(mdic
& E1000_MDIC_ERROR
) {
2827 DEBUGOUT("MDI Error\n");
2828 return -E1000_ERR_PHY
;
2830 *phy_data
= (uint16_t) mdic
;
2832 /* We must first send a preamble through the MDIO pin to signal the
2833 * beginning of an MII instruction. This is done by sending 32
2834 * consecutive "1" bits.
2836 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2838 /* Now combine the next few fields that are required for a read
2839 * operation. We use this method instead of calling the
2840 * e1000_shift_out_mdi_bits routine five different times. The format of
2841 * a MII read instruction consists of a shift out of 14 bits and is
2842 * defined as follows:
2843 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2844 * followed by a shift in of 18 bits. This first two bits shifted in
2845 * are TurnAround bits used to avoid contention on the MDIO pin when a
2846 * READ operation is performed. These two bits are thrown away
2847 * followed by a shift in of 16 bits which contains the desired data.
2849 mdic
= ((reg_addr
) | (phy_addr
<< 5) |
2850 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
2852 e1000_shift_out_mdi_bits(hw
, mdic
, 14);
2854 /* Now that we've shifted out the read command to the MII, we need to
2855 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2858 *phy_data
= e1000_shift_in_mdi_bits(hw
);
2860 return E1000_SUCCESS
;
2863 /******************************************************************************
2864 * Writes a value to a PHY register
2866 * hw - Struct containing variables accessed by shared code
2867 * reg_addr - address of the PHY register to write
2868 * data - data to write to the PHY
2869 ******************************************************************************/
2871 e1000_write_phy_reg(struct e1000_hw
*hw
,
2877 DEBUGFUNC("e1000_write_phy_reg");
2879 if((hw
->phy_type
== e1000_phy_igp
||
2880 hw
->phy_type
== e1000_phy_igp_2
) &&
2881 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2882 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2883 (uint16_t)reg_addr
);
2889 ret_val
= e1000_write_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2896 e1000_write_phy_reg_ex(struct e1000_hw
*hw
,
2902 const uint32_t phy_addr
= 1;
2904 DEBUGFUNC("e1000_write_phy_reg_ex");
2906 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2907 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2908 return -E1000_ERR_PARAM
;
2911 if(hw
->mac_type
> e1000_82543
) {
2912 /* Set up Op-code, Phy Address, register address, and data intended
2913 * for the PHY register in the MDI Control register. The MAC will take
2914 * care of interfacing with the PHY to send the desired data.
2916 mdic
= (((uint32_t) phy_data
) |
2917 (reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2918 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2919 (E1000_MDIC_OP_WRITE
));
2921 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2923 /* Poll the ready bit to see if the MDI read completed */
2924 for(i
= 0; i
< 640; i
++) {
2926 mdic
= E1000_READ_REG(hw
, MDIC
);
2927 if(mdic
& E1000_MDIC_READY
) break;
2929 if(!(mdic
& E1000_MDIC_READY
)) {
2930 DEBUGOUT("MDI Write did not complete\n");
2931 return -E1000_ERR_PHY
;
2934 /* We'll need to use the SW defined pins to shift the write command
2935 * out to the PHY. We first send a preamble to the PHY to signal the
2936 * beginning of the MII instruction. This is done by sending 32
2937 * consecutive "1" bits.
2939 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2941 /* Now combine the remaining required fields that will indicate a
2942 * write operation. We use this method instead of calling the
2943 * e1000_shift_out_mdi_bits routine for each field in the command. The
2944 * format of a MII write instruction is as follows:
2945 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2947 mdic
= ((PHY_TURNAROUND
) | (reg_addr
<< 2) | (phy_addr
<< 7) |
2948 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
2950 mdic
|= (uint32_t) phy_data
;
2952 e1000_shift_out_mdi_bits(hw
, mdic
, 32);
2955 return E1000_SUCCESS
;
2959 /******************************************************************************
2960 * Returns the PHY to the power-on reset state
2962 * hw - Struct containing variables accessed by shared code
2963 ******************************************************************************/
2965 e1000_phy_hw_reset(struct e1000_hw
*hw
)
2967 uint32_t ctrl
, ctrl_ext
;
2971 DEBUGFUNC("e1000_phy_hw_reset");
2973 /* In the case of the phy reset being blocked, it's not an error, we
2974 * simply return success without performing the reset. */
2975 ret_val
= e1000_check_phy_reset_block(hw
);
2977 return E1000_SUCCESS
;
2979 DEBUGOUT("Resetting Phy...\n");
2981 if(hw
->mac_type
> e1000_82543
) {
2982 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2983 * bit. Then, take it out of reset.
2984 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
2985 * and deassert. For e1000_82571 hardware and later, we instead delay
2986 * for 10ms after the deassertion.
2988 ctrl
= E1000_READ_REG(hw
, CTRL
);
2989 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2990 E1000_WRITE_FLUSH(hw
);
2992 if (hw
->mac_type
< e1000_82571
)
2997 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2998 E1000_WRITE_FLUSH(hw
);
3000 if (hw
->mac_type
>= e1000_82571
)
3003 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3004 * bit to put the PHY into reset. Then, take it out of reset.
3006 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
3007 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
3008 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
3009 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3010 E1000_WRITE_FLUSH(hw
);
3012 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
3013 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3014 E1000_WRITE_FLUSH(hw
);
3018 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
3019 /* Configure activity LED after PHY reset */
3020 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
3021 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
3022 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
3023 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
3026 /* Wait for FW to finish PHY configuration. */
3027 ret_val
= e1000_get_phy_cfg_done(hw
);
3032 /******************************************************************************
3035 * hw - Struct containing variables accessed by shared code
3037 * Sets bit 15 of the MII Control regiser
3038 ******************************************************************************/
3040 e1000_phy_reset(struct e1000_hw
*hw
)
3045 DEBUGFUNC("e1000_phy_reset");
3047 /* In the case of the phy reset being blocked, it's not an error, we
3048 * simply return success without performing the reset. */
3049 ret_val
= e1000_check_phy_reset_block(hw
);
3051 return E1000_SUCCESS
;
3053 switch (hw
->mac_type
) {
3054 case e1000_82541_rev_2
:
3057 ret_val
= e1000_phy_hw_reset(hw
);
3062 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
3066 phy_data
|= MII_CR_RESET
;
3067 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
3075 if(hw
->phy_type
== e1000_phy_igp
|| hw
->phy_type
== e1000_phy_igp_2
)
3076 e1000_phy_init_script(hw
);
3078 return E1000_SUCCESS
;
3081 /******************************************************************************
3082 * Probes the expected PHY address for known PHY IDs
3084 * hw - Struct containing variables accessed by shared code
3085 ******************************************************************************/
3087 e1000_detect_gig_phy(struct e1000_hw
*hw
)
3089 int32_t phy_init_status
, ret_val
;
3090 uint16_t phy_id_high
, phy_id_low
;
3091 boolean_t match
= FALSE
;
3093 DEBUGFUNC("e1000_detect_gig_phy");
3095 /* The 82571 firmware may still be configuring the PHY. In this
3096 * case, we cannot access the PHY until the configuration is done. So
3097 * we explicitly set the PHY values. */
3098 if(hw
->mac_type
== e1000_82571
||
3099 hw
->mac_type
== e1000_82572
) {
3100 hw
->phy_id
= IGP01E1000_I_PHY_ID
;
3101 hw
->phy_type
= e1000_phy_igp_2
;
3102 return E1000_SUCCESS
;
3105 /* Read the PHY ID Registers to identify which PHY is onboard. */
3106 ret_val
= e1000_read_phy_reg(hw
, PHY_ID1
, &phy_id_high
);
3110 hw
->phy_id
= (uint32_t) (phy_id_high
<< 16);
3112 ret_val
= e1000_read_phy_reg(hw
, PHY_ID2
, &phy_id_low
);
3116 hw
->phy_id
|= (uint32_t) (phy_id_low
& PHY_REVISION_MASK
);
3117 hw
->phy_revision
= (uint32_t) phy_id_low
& ~PHY_REVISION_MASK
;
3119 switch(hw
->mac_type
) {
3121 if(hw
->phy_id
== M88E1000_E_PHY_ID
) match
= TRUE
;
3124 if(hw
->phy_id
== M88E1000_I_PHY_ID
) match
= TRUE
;
3128 case e1000_82545_rev_3
:
3130 case e1000_82546_rev_3
:
3131 if(hw
->phy_id
== M88E1011_I_PHY_ID
) match
= TRUE
;
3134 case e1000_82541_rev_2
:
3136 case e1000_82547_rev_2
:
3137 if(hw
->phy_id
== IGP01E1000_I_PHY_ID
) match
= TRUE
;
3140 if(hw
->phy_id
== M88E1111_I_PHY_ID
) match
= TRUE
;
3143 DEBUGOUT1("Invalid MAC type %d\n", hw
->mac_type
);
3144 return -E1000_ERR_CONFIG
;
3146 phy_init_status
= e1000_set_phy_type(hw
);
3148 if ((match
) && (phy_init_status
== E1000_SUCCESS
)) {
3149 DEBUGOUT1("PHY ID 0x%X detected\n", hw
->phy_id
);
3150 return E1000_SUCCESS
;
3152 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw
->phy_id
);
3153 return -E1000_ERR_PHY
;
3156 /******************************************************************************
3157 * Resets the PHY's DSP
3159 * hw - Struct containing variables accessed by shared code
3160 ******************************************************************************/
3162 e1000_phy_reset_dsp(struct e1000_hw
*hw
)
3165 DEBUGFUNC("e1000_phy_reset_dsp");
3168 ret_val
= e1000_write_phy_reg(hw
, 29, 0x001d);
3170 ret_val
= e1000_write_phy_reg(hw
, 30, 0x00c1);
3172 ret_val
= e1000_write_phy_reg(hw
, 30, 0x0000);
3174 ret_val
= E1000_SUCCESS
;
3180 /******************************************************************************
3181 * Get PHY information from various PHY registers for igp PHY only.
3183 * hw - Struct containing variables accessed by shared code
3184 * phy_info - PHY information structure
3185 ******************************************************************************/
3187 e1000_phy_igp_get_info(struct e1000_hw
*hw
,
3188 struct e1000_phy_info
*phy_info
)
3191 uint16_t phy_data
, polarity
, min_length
, max_length
, average
;
3193 DEBUGFUNC("e1000_phy_igp_get_info");
3195 /* The downshift status is checked only once, after link is established,
3196 * and it stored in the hw->speed_downgraded parameter. */
3197 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3199 /* IGP01E1000 does not need to support it. */
3200 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_normal
;
3202 /* IGP01E1000 always correct polarity reversal */
3203 phy_info
->polarity_correction
= e1000_polarity_reversal_enabled
;
3205 /* Check polarity status */
3206 ret_val
= e1000_check_polarity(hw
, &polarity
);
3210 phy_info
->cable_polarity
= polarity
;
3212 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &phy_data
);
3216 phy_info
->mdix_mode
= (phy_data
& IGP01E1000_PSSR_MDIX
) >>
3217 IGP01E1000_PSSR_MDIX_SHIFT
;
3219 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
3220 IGP01E1000_PSSR_SPEED_1000MBPS
) {
3221 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3222 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3226 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3227 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3228 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3229 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3231 /* Get cable length */
3232 ret_val
= e1000_get_cable_length(hw
, &min_length
, &max_length
);
3236 /* Translate to old method */
3237 average
= (max_length
+ min_length
) / 2;
3239 if(average
<= e1000_igp_cable_length_50
)
3240 phy_info
->cable_length
= e1000_cable_length_50
;
3241 else if(average
<= e1000_igp_cable_length_80
)
3242 phy_info
->cable_length
= e1000_cable_length_50_80
;
3243 else if(average
<= e1000_igp_cable_length_110
)
3244 phy_info
->cable_length
= e1000_cable_length_80_110
;
3245 else if(average
<= e1000_igp_cable_length_140
)
3246 phy_info
->cable_length
= e1000_cable_length_110_140
;
3248 phy_info
->cable_length
= e1000_cable_length_140
;
3251 return E1000_SUCCESS
;
3254 /******************************************************************************
3255 * Get PHY information from various PHY registers fot m88 PHY only.
3257 * hw - Struct containing variables accessed by shared code
3258 * phy_info - PHY information structure
3259 ******************************************************************************/
3261 e1000_phy_m88_get_info(struct e1000_hw
*hw
,
3262 struct e1000_phy_info
*phy_info
)
3265 uint16_t phy_data
, polarity
;
3267 DEBUGFUNC("e1000_phy_m88_get_info");
3269 /* The downshift status is checked only once, after link is established,
3270 * and it stored in the hw->speed_downgraded parameter. */
3271 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3273 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
3277 phy_info
->extended_10bt_distance
=
3278 (phy_data
& M88E1000_PSCR_10BT_EXT_DIST_ENABLE
) >>
3279 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT
;
3280 phy_info
->polarity_correction
=
3281 (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
) >>
3282 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT
;
3284 /* Check polarity status */
3285 ret_val
= e1000_check_polarity(hw
, &polarity
);
3288 phy_info
->cable_polarity
= polarity
;
3290 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
3294 phy_info
->mdix_mode
= (phy_data
& M88E1000_PSSR_MDIX
) >>
3295 M88E1000_PSSR_MDIX_SHIFT
;
3297 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
3298 /* Cable Length Estimation and Local/Remote Receiver Information
3299 * are only valid at 1000 Mbps.
3301 phy_info
->cable_length
= ((phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
3302 M88E1000_PSSR_CABLE_LENGTH_SHIFT
);
3304 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3308 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3309 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3311 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3312 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3315 return E1000_SUCCESS
;
3318 /******************************************************************************
3319 * Get PHY information from various PHY registers
3321 * hw - Struct containing variables accessed by shared code
3322 * phy_info - PHY information structure
3323 ******************************************************************************/
3325 e1000_phy_get_info(struct e1000_hw
*hw
,
3326 struct e1000_phy_info
*phy_info
)
3331 DEBUGFUNC("e1000_phy_get_info");
3333 phy_info
->cable_length
= e1000_cable_length_undefined
;
3334 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_undefined
;
3335 phy_info
->cable_polarity
= e1000_rev_polarity_undefined
;
3336 phy_info
->downshift
= e1000_downshift_undefined
;
3337 phy_info
->polarity_correction
= e1000_polarity_reversal_undefined
;
3338 phy_info
->mdix_mode
= e1000_auto_x_mode_undefined
;
3339 phy_info
->local_rx
= e1000_1000t_rx_status_undefined
;
3340 phy_info
->remote_rx
= e1000_1000t_rx_status_undefined
;
3342 if(hw
->media_type
!= e1000_media_type_copper
) {
3343 DEBUGOUT("PHY info is only valid for copper media\n");
3344 return -E1000_ERR_CONFIG
;
3347 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3351 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3355 if((phy_data
& MII_SR_LINK_STATUS
) != MII_SR_LINK_STATUS
) {
3356 DEBUGOUT("PHY info is only valid if link is up\n");
3357 return -E1000_ERR_CONFIG
;
3360 if(hw
->phy_type
== e1000_phy_igp
||
3361 hw
->phy_type
== e1000_phy_igp_2
)
3362 return e1000_phy_igp_get_info(hw
, phy_info
);
3364 return e1000_phy_m88_get_info(hw
, phy_info
);
3368 e1000_validate_mdi_setting(struct e1000_hw
*hw
)
3370 DEBUGFUNC("e1000_validate_mdi_settings");
3372 if(!hw
->autoneg
&& (hw
->mdix
== 0 || hw
->mdix
== 3)) {
3373 DEBUGOUT("Invalid MDI setting detected\n");
3375 return -E1000_ERR_CONFIG
;
3377 return E1000_SUCCESS
;
3381 /******************************************************************************
3382 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3385 * hw - Struct containing variables accessed by shared code
3386 *****************************************************************************/
3388 e1000_init_eeprom_params(struct e1000_hw
*hw
)
3390 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3391 uint32_t eecd
= E1000_READ_REG(hw
, EECD
);
3392 int32_t ret_val
= E1000_SUCCESS
;
3393 uint16_t eeprom_size
;
3395 DEBUGFUNC("e1000_init_eeprom_params");
3397 switch (hw
->mac_type
) {
3398 case e1000_82542_rev2_0
:
3399 case e1000_82542_rev2_1
:
3402 eeprom
->type
= e1000_eeprom_microwire
;
3403 eeprom
->word_size
= 64;
3404 eeprom
->opcode_bits
= 3;
3405 eeprom
->address_bits
= 6;
3406 eeprom
->delay_usec
= 50;
3407 eeprom
->use_eerd
= FALSE
;
3408 eeprom
->use_eewr
= FALSE
;
3412 case e1000_82545_rev_3
:
3414 case e1000_82546_rev_3
:
3415 eeprom
->type
= e1000_eeprom_microwire
;
3416 eeprom
->opcode_bits
= 3;
3417 eeprom
->delay_usec
= 50;
3418 if(eecd
& E1000_EECD_SIZE
) {
3419 eeprom
->word_size
= 256;
3420 eeprom
->address_bits
= 8;
3422 eeprom
->word_size
= 64;
3423 eeprom
->address_bits
= 6;
3425 eeprom
->use_eerd
= FALSE
;
3426 eeprom
->use_eewr
= FALSE
;
3429 case e1000_82541_rev_2
:
3431 case e1000_82547_rev_2
:
3432 if (eecd
& E1000_EECD_TYPE
) {
3433 eeprom
->type
= e1000_eeprom_spi
;
3434 eeprom
->opcode_bits
= 8;
3435 eeprom
->delay_usec
= 1;
3436 if (eecd
& E1000_EECD_ADDR_BITS
) {
3437 eeprom
->page_size
= 32;
3438 eeprom
->address_bits
= 16;
3440 eeprom
->page_size
= 8;
3441 eeprom
->address_bits
= 8;
3444 eeprom
->type
= e1000_eeprom_microwire
;
3445 eeprom
->opcode_bits
= 3;
3446 eeprom
->delay_usec
= 50;
3447 if (eecd
& E1000_EECD_ADDR_BITS
) {
3448 eeprom
->word_size
= 256;
3449 eeprom
->address_bits
= 8;
3451 eeprom
->word_size
= 64;
3452 eeprom
->address_bits
= 6;
3455 eeprom
->use_eerd
= FALSE
;
3456 eeprom
->use_eewr
= FALSE
;
3460 eeprom
->type
= e1000_eeprom_spi
;
3461 eeprom
->opcode_bits
= 8;
3462 eeprom
->delay_usec
= 1;
3463 if (eecd
& E1000_EECD_ADDR_BITS
) {
3464 eeprom
->page_size
= 32;
3465 eeprom
->address_bits
= 16;
3467 eeprom
->page_size
= 8;
3468 eeprom
->address_bits
= 8;
3470 eeprom
->use_eerd
= FALSE
;
3471 eeprom
->use_eewr
= FALSE
;
3474 eeprom
->type
= e1000_eeprom_spi
;
3475 eeprom
->opcode_bits
= 8;
3476 eeprom
->delay_usec
= 1;
3477 if (eecd
& E1000_EECD_ADDR_BITS
) {
3478 eeprom
->page_size
= 32;
3479 eeprom
->address_bits
= 16;
3481 eeprom
->page_size
= 8;
3482 eeprom
->address_bits
= 8;
3484 eeprom
->use_eerd
= TRUE
;
3485 eeprom
->use_eewr
= TRUE
;
3486 if(e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
3487 eeprom
->type
= e1000_eeprom_flash
;
3488 eeprom
->word_size
= 2048;
3490 /* Ensure that the Autonomous FLASH update bit is cleared due to
3491 * Flash update issue on parts which use a FLASH for NVM. */
3492 eecd
&= ~E1000_EECD_AUPDEN
;
3493 E1000_WRITE_REG(hw
, EECD
, eecd
);
3500 if (eeprom
->type
== e1000_eeprom_spi
) {
3501 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3502 * 32KB (incremented by powers of 2).
3504 if(hw
->mac_type
<= e1000_82547_rev_2
) {
3505 /* Set to default value for initial eeprom read. */
3506 eeprom
->word_size
= 64;
3507 ret_val
= e1000_read_eeprom(hw
, EEPROM_CFG
, 1, &eeprom_size
);
3510 eeprom_size
= (eeprom_size
& EEPROM_SIZE_MASK
) >> EEPROM_SIZE_SHIFT
;
3511 /* 256B eeprom size was not supported in earlier hardware, so we
3512 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3513 * is never the result used in the shifting logic below. */
3517 eeprom_size
= (uint16_t)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
3518 E1000_EECD_SIZE_EX_SHIFT
);
3521 eeprom
->word_size
= 1 << (eeprom_size
+ EEPROM_WORD_SIZE_SHIFT
);
3526 /******************************************************************************
3527 * Raises the EEPROM's clock input.
3529 * hw - Struct containing variables accessed by shared code
3530 * eecd - EECD's current value
3531 *****************************************************************************/
3533 e1000_raise_ee_clk(struct e1000_hw
*hw
,
3536 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3537 * wait <delay> microseconds.
3539 *eecd
= *eecd
| E1000_EECD_SK
;
3540 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3541 E1000_WRITE_FLUSH(hw
);
3542 udelay(hw
->eeprom
.delay_usec
);
3545 /******************************************************************************
3546 * Lowers the EEPROM's clock input.
3548 * hw - Struct containing variables accessed by shared code
3549 * eecd - EECD's current value
3550 *****************************************************************************/
3552 e1000_lower_ee_clk(struct e1000_hw
*hw
,
3555 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3556 * wait 50 microseconds.
3558 *eecd
= *eecd
& ~E1000_EECD_SK
;
3559 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3560 E1000_WRITE_FLUSH(hw
);
3561 udelay(hw
->eeprom
.delay_usec
);
3564 /******************************************************************************
3565 * Shift data bits out to the EEPROM.
3567 * hw - Struct containing variables accessed by shared code
3568 * data - data to send to the EEPROM
3569 * count - number of bits to shift out
3570 *****************************************************************************/
3572 e1000_shift_out_ee_bits(struct e1000_hw
*hw
,
3576 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3580 /* We need to shift "count" bits out to the EEPROM. So, value in the
3581 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3582 * In order to do this, "data" must be broken down into bits.
3584 mask
= 0x01 << (count
- 1);
3585 eecd
= E1000_READ_REG(hw
, EECD
);
3586 if (eeprom
->type
== e1000_eeprom_microwire
) {
3587 eecd
&= ~E1000_EECD_DO
;
3588 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3589 eecd
|= E1000_EECD_DO
;
3592 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3593 * and then raising and then lowering the clock (the SK bit controls
3594 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3595 * by setting "DI" to "0" and then raising and then lowering the clock.
3597 eecd
&= ~E1000_EECD_DI
;
3600 eecd
|= E1000_EECD_DI
;
3602 E1000_WRITE_REG(hw
, EECD
, eecd
);
3603 E1000_WRITE_FLUSH(hw
);
3605 udelay(eeprom
->delay_usec
);
3607 e1000_raise_ee_clk(hw
, &eecd
);
3608 e1000_lower_ee_clk(hw
, &eecd
);
3614 /* We leave the "DI" bit set to "0" when we leave this routine. */
3615 eecd
&= ~E1000_EECD_DI
;
3616 E1000_WRITE_REG(hw
, EECD
, eecd
);
3619 /******************************************************************************
3620 * Shift data bits in from the EEPROM
3622 * hw - Struct containing variables accessed by shared code
3623 *****************************************************************************/
3625 e1000_shift_in_ee_bits(struct e1000_hw
*hw
,
3632 /* In order to read a register from the EEPROM, we need to shift 'count'
3633 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3634 * input to the EEPROM (setting the SK bit), and then reading the value of
3635 * the "DO" bit. During this "shifting in" process the "DI" bit should
3639 eecd
= E1000_READ_REG(hw
, EECD
);
3641 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
3644 for(i
= 0; i
< count
; i
++) {
3646 e1000_raise_ee_clk(hw
, &eecd
);
3648 eecd
= E1000_READ_REG(hw
, EECD
);
3650 eecd
&= ~(E1000_EECD_DI
);
3651 if(eecd
& E1000_EECD_DO
)
3654 e1000_lower_ee_clk(hw
, &eecd
);
3660 /******************************************************************************
3661 * Prepares EEPROM for access
3663 * hw - Struct containing variables accessed by shared code
3665 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3666 * function should be called before issuing a command to the EEPROM.
3667 *****************************************************************************/
3669 e1000_acquire_eeprom(struct e1000_hw
*hw
)
3671 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3674 DEBUGFUNC("e1000_acquire_eeprom");
3676 if(e1000_get_hw_eeprom_semaphore(hw
))
3677 return -E1000_ERR_EEPROM
;
3679 eecd
= E1000_READ_REG(hw
, EECD
);
3681 if (hw
->mac_type
!= e1000_82573
) {
3682 /* Request EEPROM Access */
3683 if(hw
->mac_type
> e1000_82544
) {
3684 eecd
|= E1000_EECD_REQ
;
3685 E1000_WRITE_REG(hw
, EECD
, eecd
);
3686 eecd
= E1000_READ_REG(hw
, EECD
);
3687 while((!(eecd
& E1000_EECD_GNT
)) &&
3688 (i
< E1000_EEPROM_GRANT_ATTEMPTS
)) {
3691 eecd
= E1000_READ_REG(hw
, EECD
);
3693 if(!(eecd
& E1000_EECD_GNT
)) {
3694 eecd
&= ~E1000_EECD_REQ
;
3695 E1000_WRITE_REG(hw
, EECD
, eecd
);
3696 DEBUGOUT("Could not acquire EEPROM grant\n");
3697 e1000_put_hw_eeprom_semaphore(hw
);
3698 return -E1000_ERR_EEPROM
;
3703 /* Setup EEPROM for Read/Write */
3705 if (eeprom
->type
== e1000_eeprom_microwire
) {
3706 /* Clear SK and DI */
3707 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
3708 E1000_WRITE_REG(hw
, EECD
, eecd
);
3711 eecd
|= E1000_EECD_CS
;
3712 E1000_WRITE_REG(hw
, EECD
, eecd
);
3713 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3714 /* Clear SK and CS */
3715 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3716 E1000_WRITE_REG(hw
, EECD
, eecd
);
3720 return E1000_SUCCESS
;
3723 /******************************************************************************
3724 * Returns EEPROM to a "standby" state
3726 * hw - Struct containing variables accessed by shared code
3727 *****************************************************************************/
3729 e1000_standby_eeprom(struct e1000_hw
*hw
)
3731 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3734 eecd
= E1000_READ_REG(hw
, EECD
);
3736 if(eeprom
->type
== e1000_eeprom_microwire
) {
3737 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3738 E1000_WRITE_REG(hw
, EECD
, eecd
);
3739 E1000_WRITE_FLUSH(hw
);
3740 udelay(eeprom
->delay_usec
);
3743 eecd
|= E1000_EECD_SK
;
3744 E1000_WRITE_REG(hw
, EECD
, eecd
);
3745 E1000_WRITE_FLUSH(hw
);
3746 udelay(eeprom
->delay_usec
);
3749 eecd
|= E1000_EECD_CS
;
3750 E1000_WRITE_REG(hw
, EECD
, eecd
);
3751 E1000_WRITE_FLUSH(hw
);
3752 udelay(eeprom
->delay_usec
);
3755 eecd
&= ~E1000_EECD_SK
;
3756 E1000_WRITE_REG(hw
, EECD
, eecd
);
3757 E1000_WRITE_FLUSH(hw
);
3758 udelay(eeprom
->delay_usec
);
3759 } else if(eeprom
->type
== e1000_eeprom_spi
) {
3760 /* Toggle CS to flush commands */
3761 eecd
|= E1000_EECD_CS
;
3762 E1000_WRITE_REG(hw
, EECD
, eecd
);
3763 E1000_WRITE_FLUSH(hw
);
3764 udelay(eeprom
->delay_usec
);
3765 eecd
&= ~E1000_EECD_CS
;
3766 E1000_WRITE_REG(hw
, EECD
, eecd
);
3767 E1000_WRITE_FLUSH(hw
);
3768 udelay(eeprom
->delay_usec
);
3772 /******************************************************************************
3773 * Terminates a command by inverting the EEPROM's chip select pin
3775 * hw - Struct containing variables accessed by shared code
3776 *****************************************************************************/
3778 e1000_release_eeprom(struct e1000_hw
*hw
)
3782 DEBUGFUNC("e1000_release_eeprom");
3784 eecd
= E1000_READ_REG(hw
, EECD
);
3786 if (hw
->eeprom
.type
== e1000_eeprom_spi
) {
3787 eecd
|= E1000_EECD_CS
; /* Pull CS high */
3788 eecd
&= ~E1000_EECD_SK
; /* Lower SCK */
3790 E1000_WRITE_REG(hw
, EECD
, eecd
);
3792 udelay(hw
->eeprom
.delay_usec
);
3793 } else if(hw
->eeprom
.type
== e1000_eeprom_microwire
) {
3794 /* cleanup eeprom */
3796 /* CS on Microwire is active-high */
3797 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
3799 E1000_WRITE_REG(hw
, EECD
, eecd
);
3801 /* Rising edge of clock */
3802 eecd
|= E1000_EECD_SK
;
3803 E1000_WRITE_REG(hw
, EECD
, eecd
);
3804 E1000_WRITE_FLUSH(hw
);
3805 udelay(hw
->eeprom
.delay_usec
);
3807 /* Falling edge of clock */
3808 eecd
&= ~E1000_EECD_SK
;
3809 E1000_WRITE_REG(hw
, EECD
, eecd
);
3810 E1000_WRITE_FLUSH(hw
);
3811 udelay(hw
->eeprom
.delay_usec
);
3814 /* Stop requesting EEPROM access */
3815 if(hw
->mac_type
> e1000_82544
) {
3816 eecd
&= ~E1000_EECD_REQ
;
3817 E1000_WRITE_REG(hw
, EECD
, eecd
);
3820 e1000_put_hw_eeprom_semaphore(hw
);
3823 /******************************************************************************
3824 * Reads a 16 bit word from the EEPROM.
3826 * hw - Struct containing variables accessed by shared code
3827 *****************************************************************************/
3829 e1000_spi_eeprom_ready(struct e1000_hw
*hw
)
3831 uint16_t retry_count
= 0;
3832 uint8_t spi_stat_reg
;
3834 DEBUGFUNC("e1000_spi_eeprom_ready");
3836 /* Read "Status Register" repeatedly until the LSB is cleared. The
3837 * EEPROM will signal that the command has been completed by clearing
3838 * bit 0 of the internal status register. If it's not cleared within
3839 * 5 milliseconds, then error out.
3843 e1000_shift_out_ee_bits(hw
, EEPROM_RDSR_OPCODE_SPI
,
3844 hw
->eeprom
.opcode_bits
);
3845 spi_stat_reg
= (uint8_t)e1000_shift_in_ee_bits(hw
, 8);
3846 if (!(spi_stat_reg
& EEPROM_STATUS_RDY_SPI
))
3852 e1000_standby_eeprom(hw
);
3853 } while(retry_count
< EEPROM_MAX_RETRY_SPI
);
3855 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3856 * only 0-5mSec on 5V devices)
3858 if(retry_count
>= EEPROM_MAX_RETRY_SPI
) {
3859 DEBUGOUT("SPI EEPROM Status error\n");
3860 return -E1000_ERR_EEPROM
;
3863 return E1000_SUCCESS
;
3866 /******************************************************************************
3867 * Reads a 16 bit word from the EEPROM.
3869 * hw - Struct containing variables accessed by shared code
3870 * offset - offset of word in the EEPROM to read
3871 * data - word read from the EEPROM
3872 * words - number of words to read
3873 *****************************************************************************/
3875 e1000_read_eeprom(struct e1000_hw
*hw
,
3880 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3884 DEBUGFUNC("e1000_read_eeprom");
3886 /* A check for invalid values: offset too large, too many words, and not
3889 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
3891 DEBUGOUT("\"words\" parameter out of bounds\n");
3892 return -E1000_ERR_EEPROM
;
3895 /* FLASH reads without acquiring the semaphore are safe */
3896 if (e1000_is_onboard_nvm_eeprom(hw
) == TRUE
&&
3897 hw
->eeprom
.use_eerd
== FALSE
) {
3898 switch (hw
->mac_type
) {
3900 /* Prepare the EEPROM for reading */
3901 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
3902 return -E1000_ERR_EEPROM
;
3907 if(eeprom
->use_eerd
== TRUE
) {
3908 ret_val
= e1000_read_eeprom_eerd(hw
, offset
, words
, data
);
3909 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3910 (hw
->mac_type
!= e1000_82573
))
3911 e1000_release_eeprom(hw
);
3915 if(eeprom
->type
== e1000_eeprom_spi
) {
3917 uint8_t read_opcode
= EEPROM_READ_OPCODE_SPI
;
3919 if(e1000_spi_eeprom_ready(hw
)) {
3920 e1000_release_eeprom(hw
);
3921 return -E1000_ERR_EEPROM
;
3924 e1000_standby_eeprom(hw
);
3926 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3927 if((eeprom
->address_bits
== 8) && (offset
>= 128))
3928 read_opcode
|= EEPROM_A8_OPCODE_SPI
;
3930 /* Send the READ command (opcode + addr) */
3931 e1000_shift_out_ee_bits(hw
, read_opcode
, eeprom
->opcode_bits
);
3932 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
*2), eeprom
->address_bits
);
3934 /* Read the data. The address of the eeprom internally increments with
3935 * each byte (spi) being read, saving on the overhead of eeprom setup
3936 * and tear-down. The address counter will roll over if reading beyond
3937 * the size of the eeprom, thus allowing the entire memory to be read
3938 * starting from any offset. */
3939 for (i
= 0; i
< words
; i
++) {
3940 word_in
= e1000_shift_in_ee_bits(hw
, 16);
3941 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
3943 } else if(eeprom
->type
== e1000_eeprom_microwire
) {
3944 for (i
= 0; i
< words
; i
++) {
3945 /* Send the READ command (opcode + addr) */
3946 e1000_shift_out_ee_bits(hw
, EEPROM_READ_OPCODE_MICROWIRE
,
3947 eeprom
->opcode_bits
);
3948 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ i
),
3949 eeprom
->address_bits
);
3951 /* Read the data. For microwire, each word requires the overhead
3952 * of eeprom setup and tear-down. */
3953 data
[i
] = e1000_shift_in_ee_bits(hw
, 16);
3954 e1000_standby_eeprom(hw
);
3958 /* End this read operation */
3959 e1000_release_eeprom(hw
);
3961 return E1000_SUCCESS
;
3964 /******************************************************************************
3965 * Reads a 16 bit word from the EEPROM using the EERD register.
3967 * hw - Struct containing variables accessed by shared code
3968 * offset - offset of word in the EEPROM to read
3969 * data - word read from the EEPROM
3970 * words - number of words to read
3971 *****************************************************************************/
3973 e1000_read_eeprom_eerd(struct e1000_hw
*hw
,
3978 uint32_t i
, eerd
= 0;
3981 for (i
= 0; i
< words
; i
++) {
3982 eerd
= ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) +
3983 E1000_EEPROM_RW_REG_START
;
3985 E1000_WRITE_REG(hw
, EERD
, eerd
);
3986 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_READ
);
3991 data
[i
] = (E1000_READ_REG(hw
, EERD
) >> E1000_EEPROM_RW_REG_DATA
);
3998 /******************************************************************************
3999 * Writes a 16 bit word from the EEPROM using the EEWR register.
4001 * hw - Struct containing variables accessed by shared code
4002 * offset - offset of word in the EEPROM to read
4003 * data - word read from the EEPROM
4004 * words - number of words to read
4005 *****************************************************************************/
4007 e1000_write_eeprom_eewr(struct e1000_hw
*hw
,
4012 uint32_t register_value
= 0;
4016 for (i
= 0; i
< words
; i
++) {
4017 register_value
= (data
[i
] << E1000_EEPROM_RW_REG_DATA
) |
4018 ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) |
4019 E1000_EEPROM_RW_REG_START
;
4021 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4026 E1000_WRITE_REG(hw
, EEWR
, register_value
);
4028 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4038 /******************************************************************************
4039 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4041 * hw - Struct containing variables accessed by shared code
4042 *****************************************************************************/
4044 e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
)
4046 uint32_t attempts
= 100000;
4047 uint32_t i
, reg
= 0;
4048 int32_t done
= E1000_ERR_EEPROM
;
4050 for(i
= 0; i
< attempts
; i
++) {
4051 if(eerd
== E1000_EEPROM_POLL_READ
)
4052 reg
= E1000_READ_REG(hw
, EERD
);
4054 reg
= E1000_READ_REG(hw
, EEWR
);
4056 if(reg
& E1000_EEPROM_RW_REG_DONE
) {
4057 done
= E1000_SUCCESS
;
4066 /***************************************************************************
4067 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4069 * hw - Struct containing variables accessed by shared code
4070 ****************************************************************************/
4072 e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
)
4076 if(hw
->mac_type
== e1000_82573
) {
4077 eecd
= E1000_READ_REG(hw
, EECD
);
4079 /* Isolate bits 15 & 16 */
4080 eecd
= ((eecd
>> 15) & 0x03);
4082 /* If both bits are set, device is Flash type */
4090 /******************************************************************************
4091 * Verifies that the EEPROM has a valid checksum
4093 * hw - Struct containing variables accessed by shared code
4095 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4096 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4098 *****************************************************************************/
4100 e1000_validate_eeprom_checksum(struct e1000_hw
*hw
)
4102 uint16_t checksum
= 0;
4103 uint16_t i
, eeprom_data
;
4105 DEBUGFUNC("e1000_validate_eeprom_checksum");
4107 if ((hw
->mac_type
== e1000_82573
) &&
4108 (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
)) {
4109 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4110 * 10h-12h. Checksum may need to be fixed. */
4111 e1000_read_eeprom(hw
, 0x10, 1, &eeprom_data
);
4112 if ((eeprom_data
& 0x10) == 0) {
4113 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4114 * has already been fixed. If the checksum is still wrong and this
4115 * bit is a 1, we need to return bad checksum. Otherwise, we need
4116 * to set this bit to a 1 and update the checksum. */
4117 e1000_read_eeprom(hw
, 0x23, 1, &eeprom_data
);
4118 if ((eeprom_data
& 0x8000) == 0) {
4119 eeprom_data
|= 0x8000;
4120 e1000_write_eeprom(hw
, 0x23, 1, &eeprom_data
);
4121 e1000_update_eeprom_checksum(hw
);
4126 for(i
= 0; i
< (EEPROM_CHECKSUM_REG
+ 1); i
++) {
4127 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4128 DEBUGOUT("EEPROM Read Error\n");
4129 return -E1000_ERR_EEPROM
;
4131 checksum
+= eeprom_data
;
4134 if(checksum
== (uint16_t) EEPROM_SUM
)
4135 return E1000_SUCCESS
;
4137 DEBUGOUT("EEPROM Checksum Invalid\n");
4138 return -E1000_ERR_EEPROM
;
4142 /******************************************************************************
4143 * Calculates the EEPROM checksum and writes it to the EEPROM
4145 * hw - Struct containing variables accessed by shared code
4147 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4148 * Writes the difference to word offset 63 of the EEPROM.
4149 *****************************************************************************/
4151 e1000_update_eeprom_checksum(struct e1000_hw
*hw
)
4153 uint16_t checksum
= 0;
4154 uint16_t i
, eeprom_data
;
4156 DEBUGFUNC("e1000_update_eeprom_checksum");
4158 for(i
= 0; i
< EEPROM_CHECKSUM_REG
; i
++) {
4159 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4160 DEBUGOUT("EEPROM Read Error\n");
4161 return -E1000_ERR_EEPROM
;
4163 checksum
+= eeprom_data
;
4165 checksum
= (uint16_t) EEPROM_SUM
- checksum
;
4166 if(e1000_write_eeprom(hw
, EEPROM_CHECKSUM_REG
, 1, &checksum
) < 0) {
4167 DEBUGOUT("EEPROM Write Error\n");
4168 return -E1000_ERR_EEPROM
;
4169 } else if (hw
->eeprom
.type
== e1000_eeprom_flash
) {
4170 e1000_commit_shadow_ram(hw
);
4172 return E1000_SUCCESS
;
4175 /******************************************************************************
4176 * Parent function for writing words to the different EEPROM types.
4178 * hw - Struct containing variables accessed by shared code
4179 * offset - offset within the EEPROM to be written to
4180 * words - number of words to write
4181 * data - 16 bit word to be written to the EEPROM
4183 * If e1000_update_eeprom_checksum is not called after this function, the
4184 * EEPROM will most likely contain an invalid checksum.
4185 *****************************************************************************/
4187 e1000_write_eeprom(struct e1000_hw
*hw
,
4192 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4195 DEBUGFUNC("e1000_write_eeprom");
4197 /* A check for invalid values: offset too large, too many words, and not
4200 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
4202 DEBUGOUT("\"words\" parameter out of bounds\n");
4203 return -E1000_ERR_EEPROM
;
4206 /* 82573 writes only through eewr */
4207 if(eeprom
->use_eewr
== TRUE
)
4208 return e1000_write_eeprom_eewr(hw
, offset
, words
, data
);
4210 /* Prepare the EEPROM for writing */
4211 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
4212 return -E1000_ERR_EEPROM
;
4214 if(eeprom
->type
== e1000_eeprom_microwire
) {
4215 status
= e1000_write_eeprom_microwire(hw
, offset
, words
, data
);
4217 status
= e1000_write_eeprom_spi(hw
, offset
, words
, data
);
4221 /* Done with writing */
4222 e1000_release_eeprom(hw
);
4227 /******************************************************************************
4228 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4230 * hw - Struct containing variables accessed by shared code
4231 * offset - offset within the EEPROM to be written to
4232 * words - number of words to write
4233 * data - pointer to array of 8 bit words to be written to the EEPROM
4235 *****************************************************************************/
4237 e1000_write_eeprom_spi(struct e1000_hw
*hw
,
4242 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4245 DEBUGFUNC("e1000_write_eeprom_spi");
4247 while (widx
< words
) {
4248 uint8_t write_opcode
= EEPROM_WRITE_OPCODE_SPI
;
4250 if(e1000_spi_eeprom_ready(hw
)) return -E1000_ERR_EEPROM
;
4252 e1000_standby_eeprom(hw
);
4254 /* Send the WRITE ENABLE command (8 bit opcode ) */
4255 e1000_shift_out_ee_bits(hw
, EEPROM_WREN_OPCODE_SPI
,
4256 eeprom
->opcode_bits
);
4258 e1000_standby_eeprom(hw
);
4260 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4261 if((eeprom
->address_bits
== 8) && (offset
>= 128))
4262 write_opcode
|= EEPROM_A8_OPCODE_SPI
;
4264 /* Send the Write command (8-bit opcode + addr) */
4265 e1000_shift_out_ee_bits(hw
, write_opcode
, eeprom
->opcode_bits
);
4267 e1000_shift_out_ee_bits(hw
, (uint16_t)((offset
+ widx
)*2),
4268 eeprom
->address_bits
);
4272 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4273 while (widx
< words
) {
4274 uint16_t word_out
= data
[widx
];
4275 word_out
= (word_out
>> 8) | (word_out
<< 8);
4276 e1000_shift_out_ee_bits(hw
, word_out
, 16);
4279 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4280 * operation, while the smaller eeproms are capable of an 8-byte
4281 * PAGE WRITE operation. Break the inner loop to pass new address
4283 if((((offset
+ widx
)*2) % eeprom
->page_size
) == 0) {
4284 e1000_standby_eeprom(hw
);
4290 return E1000_SUCCESS
;
4293 /******************************************************************************
4294 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4296 * hw - Struct containing variables accessed by shared code
4297 * offset - offset within the EEPROM to be written to
4298 * words - number of words to write
4299 * data - pointer to array of 16 bit words to be written to the EEPROM
4301 *****************************************************************************/
4303 e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
4308 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4310 uint16_t words_written
= 0;
4313 DEBUGFUNC("e1000_write_eeprom_microwire");
4315 /* Send the write enable command to the EEPROM (3-bit opcode plus
4316 * 6/8-bit dummy address beginning with 11). It's less work to include
4317 * the 11 of the dummy address as part of the opcode than it is to shift
4318 * it over the correct number of bits for the address. This puts the
4319 * EEPROM into write/erase mode.
4321 e1000_shift_out_ee_bits(hw
, EEPROM_EWEN_OPCODE_MICROWIRE
,
4322 (uint16_t)(eeprom
->opcode_bits
+ 2));
4324 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4326 /* Prepare the EEPROM */
4327 e1000_standby_eeprom(hw
);
4329 while (words_written
< words
) {
4330 /* Send the Write command (3-bit opcode + addr) */
4331 e1000_shift_out_ee_bits(hw
, EEPROM_WRITE_OPCODE_MICROWIRE
,
4332 eeprom
->opcode_bits
);
4334 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ words_written
),
4335 eeprom
->address_bits
);
4338 e1000_shift_out_ee_bits(hw
, data
[words_written
], 16);
4340 /* Toggle the CS line. This in effect tells the EEPROM to execute
4341 * the previous command.
4343 e1000_standby_eeprom(hw
);
4345 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4346 * signal that the command has been completed by raising the DO signal.
4347 * If DO does not go high in 10 milliseconds, then error out.
4349 for(i
= 0; i
< 200; i
++) {
4350 eecd
= E1000_READ_REG(hw
, EECD
);
4351 if(eecd
& E1000_EECD_DO
) break;
4355 DEBUGOUT("EEPROM Write did not complete\n");
4356 return -E1000_ERR_EEPROM
;
4359 /* Recover from write */
4360 e1000_standby_eeprom(hw
);
4365 /* Send the write disable command to the EEPROM (3-bit opcode plus
4366 * 6/8-bit dummy address beginning with 10). It's less work to include
4367 * the 10 of the dummy address as part of the opcode than it is to shift
4368 * it over the correct number of bits for the address. This takes the
4369 * EEPROM out of write/erase mode.
4371 e1000_shift_out_ee_bits(hw
, EEPROM_EWDS_OPCODE_MICROWIRE
,
4372 (uint16_t)(eeprom
->opcode_bits
+ 2));
4374 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4376 return E1000_SUCCESS
;
4379 /******************************************************************************
4380 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4381 * in the eeprom cache and the non modified values in the currently active bank
4384 * hw - Struct containing variables accessed by shared code
4385 * offset - offset of word in the EEPROM to read
4386 * data - word read from the EEPROM
4387 * words - number of words to read
4388 *****************************************************************************/
4390 e1000_commit_shadow_ram(struct e1000_hw
*hw
)
4392 uint32_t attempts
= 100000;
4396 int32_t error
= E1000_SUCCESS
;
4398 /* The flop register will be used to determine if flash type is STM */
4399 flop
= E1000_READ_REG(hw
, FLOP
);
4401 if (hw
->mac_type
== e1000_82573
) {
4402 for (i
=0; i
< attempts
; i
++) {
4403 eecd
= E1000_READ_REG(hw
, EECD
);
4404 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4410 if (i
== attempts
) {
4411 return -E1000_ERR_EEPROM
;
4414 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4415 if ((flop
& 0xFF00) == E1000_STM_OPCODE
) {
4416 E1000_WRITE_REG(hw
, HICR
, E1000_HICR_FW_RESET
);
4419 /* Perform the flash update */
4420 E1000_WRITE_REG(hw
, EECD
, eecd
| E1000_EECD_FLUPD
);
4422 for (i
=0; i
< attempts
; i
++) {
4423 eecd
= E1000_READ_REG(hw
, EECD
);
4424 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4430 if (i
== attempts
) {
4431 return -E1000_ERR_EEPROM
;
4438 /******************************************************************************
4439 * Reads the adapter's part number from the EEPROM
4441 * hw - Struct containing variables accessed by shared code
4442 * part_num - Adapter's part number
4443 *****************************************************************************/
4445 e1000_read_part_num(struct e1000_hw
*hw
,
4448 uint16_t offset
= EEPROM_PBA_BYTE_1
;
4449 uint16_t eeprom_data
;
4451 DEBUGFUNC("e1000_read_part_num");
4453 /* Get word 0 from EEPROM */
4454 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4455 DEBUGOUT("EEPROM Read Error\n");
4456 return -E1000_ERR_EEPROM
;
4458 /* Save word 0 in upper half of part_num */
4459 *part_num
= (uint32_t) (eeprom_data
<< 16);
4461 /* Get word 1 from EEPROM */
4462 if(e1000_read_eeprom(hw
, ++offset
, 1, &eeprom_data
) < 0) {
4463 DEBUGOUT("EEPROM Read Error\n");
4464 return -E1000_ERR_EEPROM
;
4466 /* Save word 1 in lower half of part_num */
4467 *part_num
|= eeprom_data
;
4469 return E1000_SUCCESS
;
4472 /******************************************************************************
4473 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4474 * second function of dual function devices
4476 * hw - Struct containing variables accessed by shared code
4477 *****************************************************************************/
4479 e1000_read_mac_addr(struct e1000_hw
* hw
)
4482 uint16_t eeprom_data
, i
;
4484 DEBUGFUNC("e1000_read_mac_addr");
4486 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
+= 2) {
4488 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4489 DEBUGOUT("EEPROM Read Error\n");
4490 return -E1000_ERR_EEPROM
;
4492 hw
->perm_mac_addr
[i
] = (uint8_t) (eeprom_data
& 0x00FF);
4493 hw
->perm_mac_addr
[i
+1] = (uint8_t) (eeprom_data
>> 8);
4495 switch (hw
->mac_type
) {
4499 case e1000_82546_rev_3
:
4501 if(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_FUNC_1
)
4502 hw
->perm_mac_addr
[5] ^= 0x01;
4506 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
++)
4507 hw
->mac_addr
[i
] = hw
->perm_mac_addr
[i
];
4508 return E1000_SUCCESS
;
4511 /******************************************************************************
4512 * Initializes receive address filters.
4514 * hw - Struct containing variables accessed by shared code
4516 * Places the MAC address in receive address register 0 and clears the rest
4517 * of the receive addresss registers. Clears the multicast table. Assumes
4518 * the receiver is in reset when the routine is called.
4519 *****************************************************************************/
4521 e1000_init_rx_addrs(struct e1000_hw
*hw
)
4526 DEBUGFUNC("e1000_init_rx_addrs");
4528 /* Setup the receive address. */
4529 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4531 e1000_rar_set(hw
, hw
->mac_addr
, 0);
4533 rar_num
= E1000_RAR_ENTRIES
;
4535 /* Reserve a spot for the Locally Administered Address to work around
4536 * an 82571 issue in which a reset on one port will reload the MAC on
4537 * the other port. */
4538 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4540 /* Zero out the other 15 receive addresses. */
4541 DEBUGOUT("Clearing RAR[1-15]\n");
4542 for(i
= 1; i
< rar_num
; i
++) {
4543 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4544 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4549 /******************************************************************************
4550 * Updates the MAC's list of multicast addresses.
4552 * hw - Struct containing variables accessed by shared code
4553 * mc_addr_list - the list of new multicast addresses
4554 * mc_addr_count - number of addresses
4555 * pad - number of bytes between addresses in the list
4556 * rar_used_count - offset where to start adding mc addresses into the RAR's
4558 * The given list replaces any existing list. Clears the last 15 receive
4559 * address registers and the multicast table. Uses receive address registers
4560 * for the first 15 multicast addresses, and hashes the rest into the
4562 *****************************************************************************/
4564 e1000_mc_addr_list_update(struct e1000_hw
*hw
,
4565 uint8_t *mc_addr_list
,
4566 uint32_t mc_addr_count
,
4568 uint32_t rar_used_count
)
4570 uint32_t hash_value
;
4572 uint32_t num_rar_entry
;
4573 uint32_t num_mta_entry
;
4575 DEBUGFUNC("e1000_mc_addr_list_update");
4577 /* Set the new number of MC addresses that we are being requested to use. */
4578 hw
->num_mc_addrs
= mc_addr_count
;
4580 /* Clear RAR[1-15] */
4581 DEBUGOUT(" Clearing RAR[1-15]\n");
4582 num_rar_entry
= E1000_RAR_ENTRIES
;
4583 /* Reserve a spot for the Locally Administered Address to work around
4584 * an 82571 issue in which a reset on one port will reload the MAC on
4585 * the other port. */
4586 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4589 for(i
= rar_used_count
; i
< num_rar_entry
; i
++) {
4590 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4591 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4595 DEBUGOUT(" Clearing MTA\n");
4596 num_mta_entry
= E1000_NUM_MTA_REGISTERS
;
4597 for(i
= 0; i
< num_mta_entry
; i
++) {
4598 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
4601 /* Add the new addresses */
4602 for(i
= 0; i
< mc_addr_count
; i
++) {
4603 DEBUGOUT(" Adding the multicast addresses:\n");
4604 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
4605 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)],
4606 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 1],
4607 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 2],
4608 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 3],
4609 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 4],
4610 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 5]);
4612 hash_value
= e1000_hash_mc_addr(hw
,
4614 (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)));
4616 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
4618 /* Place this multicast address in the RAR if there is room, *
4619 * else put it in the MTA
4621 if (rar_used_count
< num_rar_entry
) {
4623 mc_addr_list
+ (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)),
4627 e1000_mta_set(hw
, hash_value
);
4630 DEBUGOUT("MC Update Complete\n");
4634 /******************************************************************************
4635 * Hashes an address to determine its location in the multicast table
4637 * hw - Struct containing variables accessed by shared code
4638 * mc_addr - the multicast address to hash
4639 *****************************************************************************/
4641 e1000_hash_mc_addr(struct e1000_hw
*hw
,
4644 uint32_t hash_value
= 0;
4646 /* The portion of the address that is used for the hash table is
4647 * determined by the mc_filter_type setting.
4649 switch (hw
->mc_filter_type
) {
4650 /* [0] [1] [2] [3] [4] [5]
4655 /* [47:36] i.e. 0x563 for above example address */
4656 hash_value
= ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
4659 /* [46:35] i.e. 0xAC6 for above example address */
4660 hash_value
= ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
4663 /* [45:34] i.e. 0x5D8 for above example address */
4664 hash_value
= ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
4667 /* [43:32] i.e. 0x634 for above example address */
4668 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
4672 hash_value
&= 0xFFF;
4677 /******************************************************************************
4678 * Sets the bit in the multicast table corresponding to the hash value.
4680 * hw - Struct containing variables accessed by shared code
4681 * hash_value - Multicast address hash value
4682 *****************************************************************************/
4684 e1000_mta_set(struct e1000_hw
*hw
,
4685 uint32_t hash_value
)
4687 uint32_t hash_bit
, hash_reg
;
4691 /* The MTA is a register array of 128 32-bit registers.
4692 * It is treated like an array of 4096 bits. We want to set
4693 * bit BitArray[hash_value]. So we figure out what register
4694 * the bit is in, read it, OR in the new bit, then write
4695 * back the new value. The register is determined by the
4696 * upper 7 bits of the hash value and the bit within that
4697 * register are determined by the lower 5 bits of the value.
4699 hash_reg
= (hash_value
>> 5) & 0x7F;
4700 hash_bit
= hash_value
& 0x1F;
4702 mta
= E1000_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
4704 mta
|= (1 << hash_bit
);
4706 /* If we are on an 82544 and we are trying to write an odd offset
4707 * in the MTA, save off the previous entry before writing and
4708 * restore the old value after writing.
4710 if((hw
->mac_type
== e1000_82544
) && ((hash_reg
& 0x1) == 1)) {
4711 temp
= E1000_READ_REG_ARRAY(hw
, MTA
, (hash_reg
- 1));
4712 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4713 E1000_WRITE_REG_ARRAY(hw
, MTA
, (hash_reg
- 1), temp
);
4715 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4719 /******************************************************************************
4720 * Puts an ethernet address into a receive address register.
4722 * hw - Struct containing variables accessed by shared code
4723 * addr - Address to put into receive address register
4724 * index - Receive address register to write
4725 *****************************************************************************/
4727 e1000_rar_set(struct e1000_hw
*hw
,
4731 uint32_t rar_low
, rar_high
;
4733 /* HW expects these in little endian so we reverse the byte order
4734 * from network order (big endian) to little endian
4736 rar_low
= ((uint32_t) addr
[0] |
4737 ((uint32_t) addr
[1] << 8) |
4738 ((uint32_t) addr
[2] << 16) | ((uint32_t) addr
[3] << 24));
4740 rar_high
= ((uint32_t) addr
[4] | ((uint32_t) addr
[5] << 8) | E1000_RAH_AV
);
4742 E1000_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
4743 E1000_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
4746 /******************************************************************************
4747 * Writes a value to the specified offset in the VLAN filter table.
4749 * hw - Struct containing variables accessed by shared code
4750 * offset - Offset in VLAN filer table to write
4751 * value - Value to write into VLAN filter table
4752 *****************************************************************************/
4754 e1000_write_vfta(struct e1000_hw
*hw
,
4760 if((hw
->mac_type
== e1000_82544
) && ((offset
& 0x1) == 1)) {
4761 temp
= E1000_READ_REG_ARRAY(hw
, VFTA
, (offset
- 1));
4762 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4763 E1000_WRITE_REG_ARRAY(hw
, VFTA
, (offset
- 1), temp
);
4765 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4769 /******************************************************************************
4770 * Clears the VLAN filer table
4772 * hw - Struct containing variables accessed by shared code
4773 *****************************************************************************/
4775 e1000_clear_vfta(struct e1000_hw
*hw
)
4778 uint32_t vfta_value
= 0;
4779 uint32_t vfta_offset
= 0;
4780 uint32_t vfta_bit_in_reg
= 0;
4782 if (hw
->mac_type
== e1000_82573
) {
4783 if (hw
->mng_cookie
.vlan_id
!= 0) {
4784 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4785 * ID. The following operations determine which 32b entry
4786 * (i.e. offset) into the array we want to set the VLAN ID
4787 * (i.e. bit) of the manageability unit. */
4788 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
4789 E1000_VFTA_ENTRY_SHIFT
) &
4790 E1000_VFTA_ENTRY_MASK
;
4791 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
4792 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
4795 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
4796 /* If the offset we want to clear is the same offset of the
4797 * manageability VLAN ID, then clear all bits except that of the
4798 * manageability unit */
4799 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
4800 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, vfta_value
);
4805 e1000_id_led_init(struct e1000_hw
* hw
)
4808 const uint32_t ledctl_mask
= 0x000000FF;
4809 const uint32_t ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
4810 const uint32_t ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
4811 uint16_t eeprom_data
, i
, temp
;
4812 const uint16_t led_mask
= 0x0F;
4814 DEBUGFUNC("e1000_id_led_init");
4816 if(hw
->mac_type
< e1000_82540
) {
4818 return E1000_SUCCESS
;
4821 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4822 hw
->ledctl_default
= ledctl
;
4823 hw
->ledctl_mode1
= hw
->ledctl_default
;
4824 hw
->ledctl_mode2
= hw
->ledctl_default
;
4826 if(e1000_read_eeprom(hw
, EEPROM_ID_LED_SETTINGS
, 1, &eeprom_data
) < 0) {
4827 DEBUGOUT("EEPROM Read Error\n");
4828 return -E1000_ERR_EEPROM
;
4830 if((eeprom_data
== ID_LED_RESERVED_0000
) ||
4831 (eeprom_data
== ID_LED_RESERVED_FFFF
)) eeprom_data
= ID_LED_DEFAULT
;
4832 for(i
= 0; i
< 4; i
++) {
4833 temp
= (eeprom_data
>> (i
<< 2)) & led_mask
;
4835 case ID_LED_ON1_DEF2
:
4836 case ID_LED_ON1_ON2
:
4837 case ID_LED_ON1_OFF2
:
4838 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4839 hw
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
4841 case ID_LED_OFF1_DEF2
:
4842 case ID_LED_OFF1_ON2
:
4843 case ID_LED_OFF1_OFF2
:
4844 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4845 hw
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
4852 case ID_LED_DEF1_ON2
:
4853 case ID_LED_ON1_ON2
:
4854 case ID_LED_OFF1_ON2
:
4855 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4856 hw
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
4858 case ID_LED_DEF1_OFF2
:
4859 case ID_LED_ON1_OFF2
:
4860 case ID_LED_OFF1_OFF2
:
4861 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4862 hw
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
4869 return E1000_SUCCESS
;
4872 /******************************************************************************
4873 * Prepares SW controlable LED for use and saves the current state of the LED.
4875 * hw - Struct containing variables accessed by shared code
4876 *****************************************************************************/
4878 e1000_setup_led(struct e1000_hw
*hw
)
4881 int32_t ret_val
= E1000_SUCCESS
;
4883 DEBUGFUNC("e1000_setup_led");
4885 switch(hw
->mac_type
) {
4886 case e1000_82542_rev2_0
:
4887 case e1000_82542_rev2_1
:
4890 /* No setup necessary */
4894 case e1000_82541_rev_2
:
4895 case e1000_82547_rev_2
:
4896 /* Turn off PHY Smart Power Down (if enabled) */
4897 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4898 &hw
->phy_spd_default
);
4901 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4902 (uint16_t)(hw
->phy_spd_default
&
4903 ~IGP01E1000_GMII_SPD
));
4908 if(hw
->media_type
== e1000_media_type_fiber
) {
4909 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4910 /* Save current LEDCTL settings */
4911 hw
->ledctl_default
= ledctl
;
4913 ledctl
&= ~(E1000_LEDCTL_LED0_IVRT
|
4914 E1000_LEDCTL_LED0_BLINK
|
4915 E1000_LEDCTL_LED0_MODE_MASK
);
4916 ledctl
|= (E1000_LEDCTL_MODE_LED_OFF
<<
4917 E1000_LEDCTL_LED0_MODE_SHIFT
);
4918 E1000_WRITE_REG(hw
, LEDCTL
, ledctl
);
4919 } else if(hw
->media_type
== e1000_media_type_copper
)
4920 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
4924 return E1000_SUCCESS
;
4927 /******************************************************************************
4928 * Restores the saved state of the SW controlable LED.
4930 * hw - Struct containing variables accessed by shared code
4931 *****************************************************************************/
4933 e1000_cleanup_led(struct e1000_hw
*hw
)
4935 int32_t ret_val
= E1000_SUCCESS
;
4937 DEBUGFUNC("e1000_cleanup_led");
4939 switch(hw
->mac_type
) {
4940 case e1000_82542_rev2_0
:
4941 case e1000_82542_rev2_1
:
4944 /* No cleanup necessary */
4948 case e1000_82541_rev_2
:
4949 case e1000_82547_rev_2
:
4950 /* Turn on PHY Smart Power Down (if previously enabled) */
4951 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4952 hw
->phy_spd_default
);
4957 /* Restore LEDCTL settings */
4958 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_default
);
4962 return E1000_SUCCESS
;
4965 /******************************************************************************
4966 * Turns on the software controllable LED
4968 * hw - Struct containing variables accessed by shared code
4969 *****************************************************************************/
4971 e1000_led_on(struct e1000_hw
*hw
)
4973 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
4975 DEBUGFUNC("e1000_led_on");
4977 switch(hw
->mac_type
) {
4978 case e1000_82542_rev2_0
:
4979 case e1000_82542_rev2_1
:
4981 /* Set SW Defineable Pin 0 to turn on the LED */
4982 ctrl
|= E1000_CTRL_SWDPIN0
;
4983 ctrl
|= E1000_CTRL_SWDPIO0
;
4986 if(hw
->media_type
== e1000_media_type_fiber
) {
4987 /* Set SW Defineable Pin 0 to turn on the LED */
4988 ctrl
|= E1000_CTRL_SWDPIN0
;
4989 ctrl
|= E1000_CTRL_SWDPIO0
;
4991 /* Clear SW Defineable Pin 0 to turn on the LED */
4992 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4993 ctrl
|= E1000_CTRL_SWDPIO0
;
4997 if(hw
->media_type
== e1000_media_type_fiber
) {
4998 /* Clear SW Defineable Pin 0 to turn on the LED */
4999 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5000 ctrl
|= E1000_CTRL_SWDPIO0
;
5001 } else if(hw
->media_type
== e1000_media_type_copper
) {
5002 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode2
);
5003 return E1000_SUCCESS
;
5008 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
5010 return E1000_SUCCESS
;
5013 /******************************************************************************
5014 * Turns off the software controllable LED
5016 * hw - Struct containing variables accessed by shared code
5017 *****************************************************************************/
5019 e1000_led_off(struct e1000_hw
*hw
)
5021 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
5023 DEBUGFUNC("e1000_led_off");
5025 switch(hw
->mac_type
) {
5026 case e1000_82542_rev2_0
:
5027 case e1000_82542_rev2_1
:
5029 /* Clear SW Defineable Pin 0 to turn off the LED */
5030 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5031 ctrl
|= E1000_CTRL_SWDPIO0
;
5034 if(hw
->media_type
== e1000_media_type_fiber
) {
5035 /* Clear SW Defineable Pin 0 to turn off the LED */
5036 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5037 ctrl
|= E1000_CTRL_SWDPIO0
;
5039 /* Set SW Defineable Pin 0 to turn off the LED */
5040 ctrl
|= E1000_CTRL_SWDPIN0
;
5041 ctrl
|= E1000_CTRL_SWDPIO0
;
5045 if(hw
->media_type
== e1000_media_type_fiber
) {
5046 /* Set SW Defineable Pin 0 to turn off the LED */
5047 ctrl
|= E1000_CTRL_SWDPIN0
;
5048 ctrl
|= E1000_CTRL_SWDPIO0
;
5049 } else if(hw
->media_type
== e1000_media_type_copper
) {
5050 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
5051 return E1000_SUCCESS
;
5056 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
5058 return E1000_SUCCESS
;
5061 /******************************************************************************
5062 * Clears all hardware statistics counters.
5064 * hw - Struct containing variables accessed by shared code
5065 *****************************************************************************/
5067 e1000_clear_hw_cntrs(struct e1000_hw
*hw
)
5069 volatile uint32_t temp
;
5071 temp
= E1000_READ_REG(hw
, CRCERRS
);
5072 temp
= E1000_READ_REG(hw
, SYMERRS
);
5073 temp
= E1000_READ_REG(hw
, MPC
);
5074 temp
= E1000_READ_REG(hw
, SCC
);
5075 temp
= E1000_READ_REG(hw
, ECOL
);
5076 temp
= E1000_READ_REG(hw
, MCC
);
5077 temp
= E1000_READ_REG(hw
, LATECOL
);
5078 temp
= E1000_READ_REG(hw
, COLC
);
5079 temp
= E1000_READ_REG(hw
, DC
);
5080 temp
= E1000_READ_REG(hw
, SEC
);
5081 temp
= E1000_READ_REG(hw
, RLEC
);
5082 temp
= E1000_READ_REG(hw
, XONRXC
);
5083 temp
= E1000_READ_REG(hw
, XONTXC
);
5084 temp
= E1000_READ_REG(hw
, XOFFRXC
);
5085 temp
= E1000_READ_REG(hw
, XOFFTXC
);
5086 temp
= E1000_READ_REG(hw
, FCRUC
);
5087 temp
= E1000_READ_REG(hw
, PRC64
);
5088 temp
= E1000_READ_REG(hw
, PRC127
);
5089 temp
= E1000_READ_REG(hw
, PRC255
);
5090 temp
= E1000_READ_REG(hw
, PRC511
);
5091 temp
= E1000_READ_REG(hw
, PRC1023
);
5092 temp
= E1000_READ_REG(hw
, PRC1522
);
5093 temp
= E1000_READ_REG(hw
, GPRC
);
5094 temp
= E1000_READ_REG(hw
, BPRC
);
5095 temp
= E1000_READ_REG(hw
, MPRC
);
5096 temp
= E1000_READ_REG(hw
, GPTC
);
5097 temp
= E1000_READ_REG(hw
, GORCL
);
5098 temp
= E1000_READ_REG(hw
, GORCH
);
5099 temp
= E1000_READ_REG(hw
, GOTCL
);
5100 temp
= E1000_READ_REG(hw
, GOTCH
);
5101 temp
= E1000_READ_REG(hw
, RNBC
);
5102 temp
= E1000_READ_REG(hw
, RUC
);
5103 temp
= E1000_READ_REG(hw
, RFC
);
5104 temp
= E1000_READ_REG(hw
, ROC
);
5105 temp
= E1000_READ_REG(hw
, RJC
);
5106 temp
= E1000_READ_REG(hw
, TORL
);
5107 temp
= E1000_READ_REG(hw
, TORH
);
5108 temp
= E1000_READ_REG(hw
, TOTL
);
5109 temp
= E1000_READ_REG(hw
, TOTH
);
5110 temp
= E1000_READ_REG(hw
, TPR
);
5111 temp
= E1000_READ_REG(hw
, TPT
);
5112 temp
= E1000_READ_REG(hw
, PTC64
);
5113 temp
= E1000_READ_REG(hw
, PTC127
);
5114 temp
= E1000_READ_REG(hw
, PTC255
);
5115 temp
= E1000_READ_REG(hw
, PTC511
);
5116 temp
= E1000_READ_REG(hw
, PTC1023
);
5117 temp
= E1000_READ_REG(hw
, PTC1522
);
5118 temp
= E1000_READ_REG(hw
, MPTC
);
5119 temp
= E1000_READ_REG(hw
, BPTC
);
5121 if(hw
->mac_type
< e1000_82543
) return;
5123 temp
= E1000_READ_REG(hw
, ALGNERRC
);
5124 temp
= E1000_READ_REG(hw
, RXERRC
);
5125 temp
= E1000_READ_REG(hw
, TNCRS
);
5126 temp
= E1000_READ_REG(hw
, CEXTERR
);
5127 temp
= E1000_READ_REG(hw
, TSCTC
);
5128 temp
= E1000_READ_REG(hw
, TSCTFC
);
5130 if(hw
->mac_type
<= e1000_82544
) return;
5132 temp
= E1000_READ_REG(hw
, MGTPRC
);
5133 temp
= E1000_READ_REG(hw
, MGTPDC
);
5134 temp
= E1000_READ_REG(hw
, MGTPTC
);
5136 if(hw
->mac_type
<= e1000_82547_rev_2
) return;
5138 temp
= E1000_READ_REG(hw
, IAC
);
5139 temp
= E1000_READ_REG(hw
, ICRXOC
);
5140 temp
= E1000_READ_REG(hw
, ICRXPTC
);
5141 temp
= E1000_READ_REG(hw
, ICRXATC
);
5142 temp
= E1000_READ_REG(hw
, ICTXPTC
);
5143 temp
= E1000_READ_REG(hw
, ICTXATC
);
5144 temp
= E1000_READ_REG(hw
, ICTXQEC
);
5145 temp
= E1000_READ_REG(hw
, ICTXQMTC
);
5146 temp
= E1000_READ_REG(hw
, ICRXDMTC
);
5149 /******************************************************************************
5150 * Resets Adaptive IFS to its default state.
5152 * hw - Struct containing variables accessed by shared code
5154 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5155 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5156 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5157 * before calling this function.
5158 *****************************************************************************/
5160 e1000_reset_adaptive(struct e1000_hw
*hw
)
5162 DEBUGFUNC("e1000_reset_adaptive");
5164 if(hw
->adaptive_ifs
) {
5165 if(!hw
->ifs_params_forced
) {
5166 hw
->current_ifs_val
= 0;
5167 hw
->ifs_min_val
= IFS_MIN
;
5168 hw
->ifs_max_val
= IFS_MAX
;
5169 hw
->ifs_step_size
= IFS_STEP
;
5170 hw
->ifs_ratio
= IFS_RATIO
;
5172 hw
->in_ifs_mode
= FALSE
;
5173 E1000_WRITE_REG(hw
, AIT
, 0);
5175 DEBUGOUT("Not in Adaptive IFS mode!\n");
5179 /******************************************************************************
5180 * Called during the callback/watchdog routine to update IFS value based on
5181 * the ratio of transmits to collisions.
5183 * hw - Struct containing variables accessed by shared code
5184 * tx_packets - Number of transmits since last callback
5185 * total_collisions - Number of collisions since last callback
5186 *****************************************************************************/
5188 e1000_update_adaptive(struct e1000_hw
*hw
)
5190 DEBUGFUNC("e1000_update_adaptive");
5192 if(hw
->adaptive_ifs
) {
5193 if((hw
->collision_delta
* hw
->ifs_ratio
) > hw
->tx_packet_delta
) {
5194 if(hw
->tx_packet_delta
> MIN_NUM_XMITS
) {
5195 hw
->in_ifs_mode
= TRUE
;
5196 if(hw
->current_ifs_val
< hw
->ifs_max_val
) {
5197 if(hw
->current_ifs_val
== 0)
5198 hw
->current_ifs_val
= hw
->ifs_min_val
;
5200 hw
->current_ifs_val
+= hw
->ifs_step_size
;
5201 E1000_WRITE_REG(hw
, AIT
, hw
->current_ifs_val
);
5205 if(hw
->in_ifs_mode
&& (hw
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
5206 hw
->current_ifs_val
= 0;
5207 hw
->in_ifs_mode
= FALSE
;
5208 E1000_WRITE_REG(hw
, AIT
, 0);
5212 DEBUGOUT("Not in Adaptive IFS mode!\n");
5216 /******************************************************************************
5217 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5219 * hw - Struct containing variables accessed by shared code
5220 * frame_len - The length of the frame in question
5221 * mac_addr - The Ethernet destination address of the frame in question
5222 *****************************************************************************/
5224 e1000_tbi_adjust_stats(struct e1000_hw
*hw
,
5225 struct e1000_hw_stats
*stats
,
5231 /* First adjust the frame length. */
5233 /* We need to adjust the statistics counters, since the hardware
5234 * counters overcount this packet as a CRC error and undercount
5235 * the packet as a good packet
5237 /* This packet should not be counted as a CRC error. */
5239 /* This packet does count as a Good Packet Received. */
5242 /* Adjust the Good Octets received counters */
5243 carry_bit
= 0x80000000 & stats
->gorcl
;
5244 stats
->gorcl
+= frame_len
;
5245 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5246 * Received Count) was one before the addition,
5247 * AND it is zero after, then we lost the carry out,
5248 * need to add one to Gorch (Good Octets Received Count High).
5249 * This could be simplified if all environments supported
5252 if(carry_bit
&& ((stats
->gorcl
& 0x80000000) == 0))
5254 /* Is this a broadcast or multicast? Check broadcast first,
5255 * since the test for a multicast frame will test positive on
5256 * a broadcast frame.
5258 if((mac_addr
[0] == (uint8_t) 0xff) && (mac_addr
[1] == (uint8_t) 0xff))
5259 /* Broadcast packet */
5261 else if(*mac_addr
& 0x01)
5262 /* Multicast packet */
5265 if(frame_len
== hw
->max_frame_size
) {
5266 /* In this case, the hardware has overcounted the number of
5273 /* Adjust the bin counters when the extra byte put the frame in the
5274 * wrong bin. Remember that the frame_len was adjusted above.
5276 if(frame_len
== 64) {
5279 } else if(frame_len
== 127) {
5282 } else if(frame_len
== 255) {
5285 } else if(frame_len
== 511) {
5288 } else if(frame_len
== 1023) {
5291 } else if(frame_len
== 1522) {
5296 /******************************************************************************
5297 * Gets the current PCI bus type, speed, and width of the hardware
5299 * hw - Struct containing variables accessed by shared code
5300 *****************************************************************************/
5302 e1000_get_bus_info(struct e1000_hw
*hw
)
5306 switch (hw
->mac_type
) {
5307 case e1000_82542_rev2_0
:
5308 case e1000_82542_rev2_1
:
5309 hw
->bus_type
= e1000_bus_type_unknown
;
5310 hw
->bus_speed
= e1000_bus_speed_unknown
;
5311 hw
->bus_width
= e1000_bus_width_unknown
;
5315 hw
->bus_type
= e1000_bus_type_pci_express
;
5316 hw
->bus_speed
= e1000_bus_speed_2500
;
5317 hw
->bus_width
= e1000_bus_width_pciex_1
;
5320 hw
->bus_type
= e1000_bus_type_pci_express
;
5321 hw
->bus_speed
= e1000_bus_speed_2500
;
5322 hw
->bus_width
= e1000_bus_width_pciex_4
;
5325 status
= E1000_READ_REG(hw
, STATUS
);
5326 hw
->bus_type
= (status
& E1000_STATUS_PCIX_MODE
) ?
5327 e1000_bus_type_pcix
: e1000_bus_type_pci
;
5329 if(hw
->device_id
== E1000_DEV_ID_82546EB_QUAD_COPPER
) {
5330 hw
->bus_speed
= (hw
->bus_type
== e1000_bus_type_pci
) ?
5331 e1000_bus_speed_66
: e1000_bus_speed_120
;
5332 } else if(hw
->bus_type
== e1000_bus_type_pci
) {
5333 hw
->bus_speed
= (status
& E1000_STATUS_PCI66
) ?
5334 e1000_bus_speed_66
: e1000_bus_speed_33
;
5336 switch (status
& E1000_STATUS_PCIX_SPEED
) {
5337 case E1000_STATUS_PCIX_SPEED_66
:
5338 hw
->bus_speed
= e1000_bus_speed_66
;
5340 case E1000_STATUS_PCIX_SPEED_100
:
5341 hw
->bus_speed
= e1000_bus_speed_100
;
5343 case E1000_STATUS_PCIX_SPEED_133
:
5344 hw
->bus_speed
= e1000_bus_speed_133
;
5347 hw
->bus_speed
= e1000_bus_speed_reserved
;
5351 hw
->bus_width
= (status
& E1000_STATUS_BUS64
) ?
5352 e1000_bus_width_64
: e1000_bus_width_32
;
5358 /******************************************************************************
5359 * Reads a value from one of the devices registers using port I/O (as opposed
5360 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5362 * hw - Struct containing variables accessed by shared code
5363 * offset - offset to read from
5364 *****************************************************************************/
5366 e1000_read_reg_io(struct e1000_hw
*hw
,
5369 unsigned long io_addr
= hw
->io_base
;
5370 unsigned long io_data
= hw
->io_base
+ 4;
5372 e1000_io_write(hw
, io_addr
, offset
);
5373 return e1000_io_read(hw
, io_data
);
5377 /******************************************************************************
5378 * Writes a value to one of the devices registers using port I/O (as opposed to
5379 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5381 * hw - Struct containing variables accessed by shared code
5382 * offset - offset to write to
5383 * value - value to write
5384 *****************************************************************************/
5386 e1000_write_reg_io(struct e1000_hw
*hw
,
5390 unsigned long io_addr
= hw
->io_base
;
5391 unsigned long io_data
= hw
->io_base
+ 4;
5393 e1000_io_write(hw
, io_addr
, offset
);
5394 e1000_io_write(hw
, io_data
, value
);
5398 /******************************************************************************
5399 * Estimates the cable length.
5401 * hw - Struct containing variables accessed by shared code
5402 * min_length - The estimated minimum length
5403 * max_length - The estimated maximum length
5405 * returns: - E1000_ERR_XXX
5408 * This function always returns a ranged length (minimum & maximum).
5409 * So for M88 phy's, this function interprets the one value returned from the
5410 * register to the minimum and maximum range.
5411 * For IGP phy's, the function calculates the range by the AGC registers.
5412 *****************************************************************************/
5414 e1000_get_cable_length(struct e1000_hw
*hw
,
5415 uint16_t *min_length
,
5416 uint16_t *max_length
)
5419 uint16_t agc_value
= 0;
5420 uint16_t cur_agc
, min_agc
= IGP01E1000_AGC_LENGTH_TABLE_SIZE
;
5421 uint16_t max_agc
= 0;
5422 uint16_t i
, phy_data
;
5423 uint16_t cable_length
;
5425 DEBUGFUNC("e1000_get_cable_length");
5427 *min_length
= *max_length
= 0;
5429 /* Use old method for Phy older than IGP */
5430 if(hw
->phy_type
== e1000_phy_m88
) {
5432 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5436 cable_length
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
5437 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
5439 /* Convert the enum value to ranged values */
5440 switch (cable_length
) {
5441 case e1000_cable_length_50
:
5443 *max_length
= e1000_igp_cable_length_50
;
5445 case e1000_cable_length_50_80
:
5446 *min_length
= e1000_igp_cable_length_50
;
5447 *max_length
= e1000_igp_cable_length_80
;
5449 case e1000_cable_length_80_110
:
5450 *min_length
= e1000_igp_cable_length_80
;
5451 *max_length
= e1000_igp_cable_length_110
;
5453 case e1000_cable_length_110_140
:
5454 *min_length
= e1000_igp_cable_length_110
;
5455 *max_length
= e1000_igp_cable_length_140
;
5457 case e1000_cable_length_140
:
5458 *min_length
= e1000_igp_cable_length_140
;
5459 *max_length
= e1000_igp_cable_length_170
;
5462 return -E1000_ERR_PHY
;
5465 } else if(hw
->phy_type
== e1000_phy_igp
) { /* For IGP PHY */
5466 uint16_t agc_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5467 {IGP01E1000_PHY_AGC_A
,
5468 IGP01E1000_PHY_AGC_B
,
5469 IGP01E1000_PHY_AGC_C
,
5470 IGP01E1000_PHY_AGC_D
};
5471 /* Read the AGC registers for all channels */
5472 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5474 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5478 cur_agc
= phy_data
>> IGP01E1000_AGC_LENGTH_SHIFT
;
5480 /* Array bound check. */
5481 if((cur_agc
>= IGP01E1000_AGC_LENGTH_TABLE_SIZE
- 1) ||
5483 return -E1000_ERR_PHY
;
5485 agc_value
+= cur_agc
;
5487 /* Update minimal AGC value. */
5488 if(min_agc
> cur_agc
)
5492 /* Remove the minimal AGC result for length < 50m */
5493 if(agc_value
< IGP01E1000_PHY_CHANNEL_NUM
* e1000_igp_cable_length_50
) {
5494 agc_value
-= min_agc
;
5496 /* Get the average length of the remaining 3 channels */
5497 agc_value
/= (IGP01E1000_PHY_CHANNEL_NUM
- 1);
5499 /* Get the average length of all the 4 channels. */
5500 agc_value
/= IGP01E1000_PHY_CHANNEL_NUM
;
5503 /* Set the range of the calculated length. */
5504 *min_length
= ((e1000_igp_cable_length_table
[agc_value
] -
5505 IGP01E1000_AGC_RANGE
) > 0) ?
5506 (e1000_igp_cable_length_table
[agc_value
] -
5507 IGP01E1000_AGC_RANGE
) : 0;
5508 *max_length
= e1000_igp_cable_length_table
[agc_value
] +
5509 IGP01E1000_AGC_RANGE
;
5510 } else if (hw
->phy_type
== e1000_phy_igp_2
) {
5511 uint16_t agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
5512 {IGP02E1000_PHY_AGC_A
,
5513 IGP02E1000_PHY_AGC_B
,
5514 IGP02E1000_PHY_AGC_C
,
5515 IGP02E1000_PHY_AGC_D
};
5516 /* Read the AGC registers for all channels */
5517 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
5518 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5522 /* Getting bits 15:9, which represent the combination of course and
5523 * fine gain values. The result is a number that can be put into
5524 * the lookup table to obtain the approximate cable length. */
5525 cur_agc
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
5526 IGP02E1000_AGC_LENGTH_MASK
;
5528 /* Remove min & max AGC values from calculation. */
5529 if (e1000_igp_2_cable_length_table
[min_agc
] > e1000_igp_2_cable_length_table
[cur_agc
])
5531 if (e1000_igp_2_cable_length_table
[max_agc
] < e1000_igp_2_cable_length_table
[cur_agc
])
5534 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc
];
5537 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc
] + e1000_igp_2_cable_length_table
[max_agc
]);
5538 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
5540 /* Calculate cable length with the error range of +/- 10 meters. */
5541 *min_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
5542 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
5543 *max_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
5546 return E1000_SUCCESS
;
5549 /******************************************************************************
5550 * Check the cable polarity
5552 * hw - Struct containing variables accessed by shared code
5553 * polarity - output parameter : 0 - Polarity is not reversed
5554 * 1 - Polarity is reversed.
5556 * returns: - E1000_ERR_XXX
5559 * For phy's older then IGP, this function simply reads the polarity bit in the
5560 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5561 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5562 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5563 * IGP01E1000_PHY_PCS_INIT_REG.
5564 *****************************************************************************/
5566 e1000_check_polarity(struct e1000_hw
*hw
,
5572 DEBUGFUNC("e1000_check_polarity");
5574 if(hw
->phy_type
== e1000_phy_m88
) {
5575 /* return the Polarity bit in the Status register. */
5576 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5580 *polarity
= (phy_data
& M88E1000_PSSR_REV_POLARITY
) >>
5581 M88E1000_PSSR_REV_POLARITY_SHIFT
;
5582 } else if(hw
->phy_type
== e1000_phy_igp
||
5583 hw
->phy_type
== e1000_phy_igp_2
) {
5584 /* Read the Status register to check the speed */
5585 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
5590 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5591 * find the polarity status */
5592 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
5593 IGP01E1000_PSSR_SPEED_1000MBPS
) {
5595 /* Read the GIG initialization PCS register (0x00B4) */
5596 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PCS_INIT_REG
,
5601 /* Check the polarity bits */
5602 *polarity
= (phy_data
& IGP01E1000_PHY_POLARITY_MASK
) ? 1 : 0;
5604 /* For 10 Mbps, read the polarity bit in the status register. (for
5605 * 100 Mbps this bit is always 0) */
5606 *polarity
= phy_data
& IGP01E1000_PSSR_POLARITY_REVERSED
;
5609 return E1000_SUCCESS
;
5612 /******************************************************************************
5613 * Check if Downshift occured
5615 * hw - Struct containing variables accessed by shared code
5616 * downshift - output parameter : 0 - No Downshift ocured.
5617 * 1 - Downshift ocured.
5619 * returns: - E1000_ERR_XXX
5622 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5623 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5624 * Link Health register. In IGP this bit is latched high, so the driver must
5625 * read it immediately after link is established.
5626 *****************************************************************************/
5628 e1000_check_downshift(struct e1000_hw
*hw
)
5633 DEBUGFUNC("e1000_check_downshift");
5635 if(hw
->phy_type
== e1000_phy_igp
||
5636 hw
->phy_type
== e1000_phy_igp_2
) {
5637 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_LINK_HEALTH
,
5642 hw
->speed_downgraded
= (phy_data
& IGP01E1000_PLHR_SS_DOWNGRADE
) ? 1 : 0;
5643 } else if(hw
->phy_type
== e1000_phy_m88
) {
5644 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5649 hw
->speed_downgraded
= (phy_data
& M88E1000_PSSR_DOWNSHIFT
) >>
5650 M88E1000_PSSR_DOWNSHIFT_SHIFT
;
5653 return E1000_SUCCESS
;
5656 /*****************************************************************************
5658 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5659 * gigabit link is achieved to improve link quality.
5661 * hw: Struct containing variables accessed by shared code
5663 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5664 * E1000_SUCCESS at any other case.
5666 ****************************************************************************/
5669 e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
5673 uint16_t phy_data
, phy_saved_data
, speed
, duplex
, i
;
5674 uint16_t dsp_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5675 {IGP01E1000_PHY_AGC_PARAM_A
,
5676 IGP01E1000_PHY_AGC_PARAM_B
,
5677 IGP01E1000_PHY_AGC_PARAM_C
,
5678 IGP01E1000_PHY_AGC_PARAM_D
};
5679 uint16_t min_length
, max_length
;
5681 DEBUGFUNC("e1000_config_dsp_after_link_change");
5683 if(hw
->phy_type
!= e1000_phy_igp
)
5684 return E1000_SUCCESS
;
5687 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
5689 DEBUGOUT("Error getting link speed and duplex\n");
5693 if(speed
== SPEED_1000
) {
5695 e1000_get_cable_length(hw
, &min_length
, &max_length
);
5697 if((hw
->dsp_config_state
== e1000_dsp_config_enabled
) &&
5698 min_length
>= e1000_igp_cable_length_50
) {
5700 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5701 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
],
5706 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5708 ret_val
= e1000_write_phy_reg(hw
, dsp_reg_array
[i
],
5713 hw
->dsp_config_state
= e1000_dsp_config_activated
;
5716 if((hw
->ffe_config_state
== e1000_ffe_config_enabled
) &&
5717 (min_length
< e1000_igp_cable_length_50
)) {
5719 uint16_t ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_20
;
5720 uint32_t idle_errs
= 0;
5722 /* clear previous idle error counts */
5723 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5728 for(i
= 0; i
< ffe_idle_err_timeout
; i
++) {
5730 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5735 idle_errs
+= (phy_data
& SR_1000T_IDLE_ERROR_CNT
);
5736 if(idle_errs
> SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT
) {
5737 hw
->ffe_config_state
= e1000_ffe_config_active
;
5739 ret_val
= e1000_write_phy_reg(hw
,
5740 IGP01E1000_PHY_DSP_FFE
,
5741 IGP01E1000_PHY_DSP_FFE_CM_CP
);
5748 ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_100
;
5753 if(hw
->dsp_config_state
== e1000_dsp_config_activated
) {
5754 /* Save off the current value of register 0x2F5B to be restored at
5755 * the end of the routines. */
5756 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5761 /* Disable the PHY transmitter */
5762 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5769 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5770 IGP01E1000_IEEE_FORCE_GIGA
);
5773 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5774 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
], &phy_data
);
5778 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5779 phy_data
|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS
;
5781 ret_val
= e1000_write_phy_reg(hw
,dsp_reg_array
[i
], phy_data
);
5786 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5787 IGP01E1000_IEEE_RESTART_AUTONEG
);
5793 /* Now enable the transmitter */
5794 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5799 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
5802 if(hw
->ffe_config_state
== e1000_ffe_config_active
) {
5803 /* Save off the current value of register 0x2F5B to be restored at
5804 * the end of the routines. */
5805 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5810 /* Disable the PHY transmitter */
5811 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5818 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5819 IGP01E1000_IEEE_FORCE_GIGA
);
5822 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_DSP_FFE
,
5823 IGP01E1000_PHY_DSP_FFE_DEFAULT
);
5827 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5828 IGP01E1000_IEEE_RESTART_AUTONEG
);
5834 /* Now enable the transmitter */
5835 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5840 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
5843 return E1000_SUCCESS
;
5846 /*****************************************************************************
5847 * Set PHY to class A mode
5848 * Assumes the following operations will follow to enable the new class mode.
5849 * 1. Do a PHY soft reset
5850 * 2. Restart auto-negotiation or force link.
5852 * hw - Struct containing variables accessed by shared code
5853 ****************************************************************************/
5855 e1000_set_phy_mode(struct e1000_hw
*hw
)
5858 uint16_t eeprom_data
;
5860 DEBUGFUNC("e1000_set_phy_mode");
5862 if((hw
->mac_type
== e1000_82545_rev_3
) &&
5863 (hw
->media_type
== e1000_media_type_copper
)) {
5864 ret_val
= e1000_read_eeprom(hw
, EEPROM_PHY_CLASS_WORD
, 1, &eeprom_data
);
5869 if((eeprom_data
!= EEPROM_RESERVED_WORD
) &&
5870 (eeprom_data
& EEPROM_PHY_CLASS_A
)) {
5871 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x000B);
5874 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x8104);
5878 hw
->phy_reset_disable
= FALSE
;
5882 return E1000_SUCCESS
;
5885 /*****************************************************************************
5887 * This function sets the lplu state according to the active flag. When
5888 * activating lplu this function also disables smart speed and vise versa.
5889 * lplu will not be activated unless the device autonegotiation advertisment
5890 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5891 * hw: Struct containing variables accessed by shared code
5892 * active - true to enable lplu false to disable lplu.
5894 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5895 * E1000_SUCCESS at any other case.
5897 ****************************************************************************/
5900 e1000_set_d3_lplu_state(struct e1000_hw
*hw
,
5905 DEBUGFUNC("e1000_set_d3_lplu_state");
5907 if(hw
->phy_type
!= e1000_phy_igp
&& hw
->phy_type
!= e1000_phy_igp_2
)
5908 return E1000_SUCCESS
;
5910 /* During driver activity LPLU should not be used or it will attain link
5911 * from the lowest speeds starting from 10Mbps. The capability is used for
5912 * Dx transitions and states */
5913 if(hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
) {
5914 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
, &phy_data
);
5918 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
5924 if(hw
->mac_type
== e1000_82541_rev_2
||
5925 hw
->mac_type
== e1000_82547_rev_2
) {
5926 phy_data
&= ~IGP01E1000_GMII_FLEX_SPD
;
5927 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5931 phy_data
&= ~IGP02E1000_PM_D3_LPLU
;
5932 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5938 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5939 * Dx states where the power conservation is most important. During
5940 * driver activity we should enable SmartSpeed, so performance is
5942 if (hw
->smart_speed
== e1000_smart_speed_on
) {
5943 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5948 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
5949 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5953 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
5954 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5959 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5960 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5966 } else if((hw
->autoneg_advertised
== AUTONEG_ADVERTISE_SPEED_DEFAULT
) ||
5967 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_ALL
) ||
5968 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_100_ALL
)) {
5970 if(hw
->mac_type
== e1000_82541_rev_2
||
5971 hw
->mac_type
== e1000_82547_rev_2
) {
5972 phy_data
|= IGP01E1000_GMII_FLEX_SPD
;
5973 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5977 phy_data
|= IGP02E1000_PM_D3_LPLU
;
5978 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5984 /* When LPLU is enabled we should disable SmartSpeed */
5985 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
5989 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5990 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
5995 return E1000_SUCCESS
;
5998 /*****************************************************************************
6000 * This function sets the lplu d0 state according to the active flag. When
6001 * activating lplu this function also disables smart speed and vise versa.
6002 * lplu will not be activated unless the device autonegotiation advertisment
6003 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6004 * hw: Struct containing variables accessed by shared code
6005 * active - true to enable lplu false to disable lplu.
6007 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6008 * E1000_SUCCESS at any other case.
6010 ****************************************************************************/
6013 e1000_set_d0_lplu_state(struct e1000_hw
*hw
,
6018 DEBUGFUNC("e1000_set_d0_lplu_state");
6020 if(hw
->mac_type
<= e1000_82547_rev_2
)
6021 return E1000_SUCCESS
;
6023 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
6028 phy_data
&= ~IGP02E1000_PM_D0_LPLU
;
6029 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6033 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6034 * Dx states where the power conservation is most important. During
6035 * driver activity we should enable SmartSpeed, so performance is
6037 if (hw
->smart_speed
== e1000_smart_speed_on
) {
6038 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6043 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
6044 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6048 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
6049 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6054 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6055 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6064 phy_data
|= IGP02E1000_PM_D0_LPLU
;
6065 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6069 /* When LPLU is enabled we should disable SmartSpeed */
6070 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
6074 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6075 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
6080 return E1000_SUCCESS
;
6083 /******************************************************************************
6084 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6086 * hw - Struct containing variables accessed by shared code
6087 *****************************************************************************/
6089 e1000_set_vco_speed(struct e1000_hw
*hw
)
6092 uint16_t default_page
= 0;
6095 DEBUGFUNC("e1000_set_vco_speed");
6097 switch(hw
->mac_type
) {
6098 case e1000_82545_rev_3
:
6099 case e1000_82546_rev_3
:
6102 return E1000_SUCCESS
;
6105 /* Set PHY register 30, page 5, bit 8 to 0 */
6107 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, &default_page
);
6111 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0005);
6115 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6119 phy_data
&= ~M88E1000_PHY_VCO_REG_BIT8
;
6120 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6124 /* Set PHY register 30, page 4, bit 11 to 1 */
6126 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0004);
6130 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6134 phy_data
|= M88E1000_PHY_VCO_REG_BIT11
;
6135 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6139 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, default_page
);
6143 return E1000_SUCCESS
;
6147 /*****************************************************************************
6148 * This function reads the cookie from ARC ram.
6150 * returns: - E1000_SUCCESS .
6151 ****************************************************************************/
6153 e1000_host_if_read_cookie(struct e1000_hw
* hw
, uint8_t *buffer
)
6156 uint32_t offset
= E1000_MNG_DHCP_COOKIE_OFFSET
;
6157 uint8_t length
= E1000_MNG_DHCP_COOKIE_LENGTH
;
6159 length
= (length
>> 2);
6160 offset
= (offset
>> 2);
6162 for (i
= 0; i
< length
; i
++) {
6163 *((uint32_t *) buffer
+ i
) =
6164 E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
);
6166 return E1000_SUCCESS
;
6170 /*****************************************************************************
6171 * This function checks whether the HOST IF is enabled for command operaton
6172 * and also checks whether the previous command is completed.
6173 * It busy waits in case of previous command is not completed.
6175 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6177 * - E1000_SUCCESS for success.
6178 ****************************************************************************/
6180 e1000_mng_enable_host_if(struct e1000_hw
* hw
)
6185 /* Check that the host interface is enabled. */
6186 hicr
= E1000_READ_REG(hw
, HICR
);
6187 if ((hicr
& E1000_HICR_EN
) == 0) {
6188 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6189 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6191 /* check the previous command is completed */
6192 for (i
= 0; i
< E1000_MNG_DHCP_COMMAND_TIMEOUT
; i
++) {
6193 hicr
= E1000_READ_REG(hw
, HICR
);
6194 if (!(hicr
& E1000_HICR_C
))
6199 if (i
== E1000_MNG_DHCP_COMMAND_TIMEOUT
) {
6200 DEBUGOUT("Previous command timeout failed .\n");
6201 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6203 return E1000_SUCCESS
;
6206 /*****************************************************************************
6207 * This function writes the buffer content at the offset given on the host if.
6208 * It also does alignment considerations to do the writes in most efficient way.
6209 * Also fills up the sum of the buffer in *buffer parameter.
6211 * returns - E1000_SUCCESS for success.
6212 ****************************************************************************/
6214 e1000_mng_host_if_write(struct e1000_hw
* hw
, uint8_t *buffer
,
6215 uint16_t length
, uint16_t offset
, uint8_t *sum
)
6218 uint8_t *bufptr
= buffer
;
6220 uint16_t remaining
, i
, j
, prev_bytes
;
6222 /* sum = only sum of the data and it is not checksum */
6224 if (length
== 0 || offset
+ length
> E1000_HI_MAX_MNG_DATA_LENGTH
) {
6225 return -E1000_ERR_PARAM
;
6228 tmp
= (uint8_t *)&data
;
6229 prev_bytes
= offset
& 0x3;
6234 data
= E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
);
6235 for (j
= prev_bytes
; j
< sizeof(uint32_t); j
++) {
6236 *(tmp
+ j
) = *bufptr
++;
6239 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
, data
);
6240 length
-= j
- prev_bytes
;
6244 remaining
= length
& 0x3;
6245 length
-= remaining
;
6247 /* Calculate length in DWORDs */
6250 /* The device driver writes the relevant command block into the
6252 for (i
= 0; i
< length
; i
++) {
6253 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6254 *(tmp
+ j
) = *bufptr
++;
6258 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6261 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6263 *(tmp
+ j
) = *bufptr
++;
6269 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6272 return E1000_SUCCESS
;
6276 /*****************************************************************************
6277 * This function writes the command header after does the checksum calculation.
6279 * returns - E1000_SUCCESS for success.
6280 ****************************************************************************/
6282 e1000_mng_write_cmd_header(struct e1000_hw
* hw
,
6283 struct e1000_host_mng_command_header
* hdr
)
6289 /* Write the whole command header structure which includes sum of
6292 uint16_t length
= sizeof(struct e1000_host_mng_command_header
);
6294 sum
= hdr
->checksum
;
6297 buffer
= (uint8_t *) hdr
;
6302 hdr
->checksum
= 0 - sum
;
6305 /* The device driver writes the relevant command block into the ram area. */
6306 for (i
= 0; i
< length
; i
++)
6307 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, i
, *((uint32_t *) hdr
+ i
));
6309 return E1000_SUCCESS
;
6313 /*****************************************************************************
6314 * This function indicates to ARC that a new command is pending which completes
6315 * one write operation by the driver.
6317 * returns - E1000_SUCCESS for success.
6318 ****************************************************************************/
6320 e1000_mng_write_commit(
6321 struct e1000_hw
* hw
)
6325 hicr
= E1000_READ_REG(hw
, HICR
);
6326 /* Setting this bit tells the ARC that a new command is pending. */
6327 E1000_WRITE_REG(hw
, HICR
, hicr
| E1000_HICR_C
);
6329 return E1000_SUCCESS
;
6333 /*****************************************************************************
6334 * This function checks the mode of the firmware.
6336 * returns - TRUE when the mode is IAMT or FALSE.
6337 ****************************************************************************/
6339 e1000_check_mng_mode(
6340 struct e1000_hw
*hw
)
6344 fwsm
= E1000_READ_REG(hw
, FWSM
);
6346 if((fwsm
& E1000_FWSM_MODE_MASK
) ==
6347 (E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
6354 /*****************************************************************************
6355 * This function writes the dhcp info .
6356 ****************************************************************************/
6358 e1000_mng_write_dhcp_info(struct e1000_hw
* hw
, uint8_t *buffer
,
6362 struct e1000_host_mng_command_header hdr
;
6364 hdr
.command_id
= E1000_MNG_DHCP_TX_PAYLOAD_CMD
;
6365 hdr
.command_length
= length
;
6370 ret_val
= e1000_mng_enable_host_if(hw
);
6371 if (ret_val
== E1000_SUCCESS
) {
6372 ret_val
= e1000_mng_host_if_write(hw
, buffer
, length
, sizeof(hdr
),
6374 if (ret_val
== E1000_SUCCESS
) {
6375 ret_val
= e1000_mng_write_cmd_header(hw
, &hdr
);
6376 if (ret_val
== E1000_SUCCESS
)
6377 ret_val
= e1000_mng_write_commit(hw
);
6384 /*****************************************************************************
6385 * This function calculates the checksum.
6387 * returns - checksum of buffer contents.
6388 ****************************************************************************/
6390 e1000_calculate_mng_checksum(char *buffer
, uint32_t length
)
6398 for (i
=0; i
< length
; i
++)
6401 return (uint8_t) (0 - sum
);
6404 /*****************************************************************************
6405 * This function checks whether tx pkt filtering needs to be enabled or not.
6407 * returns - TRUE for packet filtering or FALSE.
6408 ****************************************************************************/
6410 e1000_enable_tx_pkt_filtering(struct e1000_hw
*hw
)
6412 /* called in init as well as watchdog timer functions */
6414 int32_t ret_val
, checksum
;
6415 boolean_t tx_filter
= FALSE
;
6416 struct e1000_host_mng_dhcp_cookie
*hdr
= &(hw
->mng_cookie
);
6417 uint8_t *buffer
= (uint8_t *) &(hw
->mng_cookie
);
6419 if (e1000_check_mng_mode(hw
)) {
6420 ret_val
= e1000_mng_enable_host_if(hw
);
6421 if (ret_val
== E1000_SUCCESS
) {
6422 ret_val
= e1000_host_if_read_cookie(hw
, buffer
);
6423 if (ret_val
== E1000_SUCCESS
) {
6424 checksum
= hdr
->checksum
;
6426 if ((hdr
->signature
== E1000_IAMT_SIGNATURE
) &&
6427 checksum
== e1000_calculate_mng_checksum((char *)buffer
,
6428 E1000_MNG_DHCP_COOKIE_LENGTH
)) {
6430 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT
)
6439 hw
->tx_pkt_filtering
= tx_filter
;
6443 /******************************************************************************
6444 * Verifies the hardware needs to allow ARPs to be processed by the host
6446 * hw - Struct containing variables accessed by shared code
6448 * returns: - TRUE/FALSE
6450 *****************************************************************************/
6452 e1000_enable_mng_pass_thru(struct e1000_hw
*hw
)
6455 uint32_t fwsm
, factps
;
6457 if (hw
->asf_firmware_present
) {
6458 manc
= E1000_READ_REG(hw
, MANC
);
6460 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
6461 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
6463 if (e1000_arc_subsystem_valid(hw
) == TRUE
) {
6464 fwsm
= E1000_READ_REG(hw
, FWSM
);
6465 factps
= E1000_READ_REG(hw
, FACTPS
);
6467 if (((fwsm
& E1000_FWSM_MODE_MASK
) ==
6468 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
)) &&
6469 (factps
& E1000_FACTPS_MNGCG
))
6472 if ((manc
& E1000_MANC_SMBUS_EN
) && !(manc
& E1000_MANC_ASF_EN
))
6479 e1000_polarity_reversal_workaround(struct e1000_hw
*hw
)
6482 uint16_t mii_status_reg
;
6485 /* Polarity reversal workaround for forced 10F/10H links. */
6487 /* Disable the transmitter on the PHY */
6489 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6492 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFFF);
6496 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6500 /* This loop will early-out if the NO link condition has been met. */
6501 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6502 /* Read the MII Status Register and wait for Link Status bit
6506 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6510 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6514 if((mii_status_reg
& ~MII_SR_LINK_STATUS
) == 0) break;
6515 msec_delay_irq(100);
6518 /* Recommended delay time after link has been lost */
6519 msec_delay_irq(1000);
6521 /* Now we will re-enable th transmitter on the PHY */
6523 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6527 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFF0);
6531 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFF00);
6535 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x0000);
6539 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6543 /* This loop will early-out if the link condition has been met. */
6544 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6545 /* Read the MII Status Register and wait for Link Status bit
6549 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6553 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6557 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
6558 msec_delay_irq(100);
6560 return E1000_SUCCESS
;
6563 /***************************************************************************
6565 * Disables PCI-Express master access.
6567 * hw: Struct containing variables accessed by shared code
6571 ***************************************************************************/
6573 e1000_set_pci_express_master_disable(struct e1000_hw
*hw
)
6577 DEBUGFUNC("e1000_set_pci_express_master_disable");
6579 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6582 ctrl
= E1000_READ_REG(hw
, CTRL
);
6583 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
6584 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6588 /***************************************************************************
6590 * Enables PCI-Express master access.
6592 * hw: Struct containing variables accessed by shared code
6596 ***************************************************************************/
6598 e1000_enable_pciex_master(struct e1000_hw
*hw
)
6602 DEBUGFUNC("e1000_enable_pciex_master");
6604 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6607 ctrl
= E1000_READ_REG(hw
, CTRL
);
6608 ctrl
&= ~E1000_CTRL_GIO_MASTER_DISABLE
;
6609 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6613 /*******************************************************************************
6615 * Disables PCI-Express master access and verifies there are no pending requests
6617 * hw: Struct containing variables accessed by shared code
6619 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6620 * caused the master requests to be disabled.
6621 * E1000_SUCCESS master requests disabled.
6623 ******************************************************************************/
6625 e1000_disable_pciex_master(struct e1000_hw
*hw
)
6627 int32_t timeout
= MASTER_DISABLE_TIMEOUT
; /* 80ms */
6629 DEBUGFUNC("e1000_disable_pciex_master");
6631 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6632 return E1000_SUCCESS
;
6634 e1000_set_pci_express_master_disable(hw
);
6637 if(!(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_GIO_MASTER_ENABLE
))
6645 DEBUGOUT("Master requests are pending.\n");
6646 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
6649 return E1000_SUCCESS
;
6652 /*******************************************************************************
6654 * Check for EEPROM Auto Read bit done.
6656 * hw: Struct containing variables accessed by shared code
6658 * returns: - E1000_ERR_RESET if fail to reset MAC
6659 * E1000_SUCCESS at any other case.
6661 ******************************************************************************/
6663 e1000_get_auto_rd_done(struct e1000_hw
*hw
)
6665 int32_t timeout
= AUTO_READ_DONE_TIMEOUT
;
6667 DEBUGFUNC("e1000_get_auto_rd_done");
6669 switch (hw
->mac_type
) {
6677 if (E1000_READ_REG(hw
, EECD
) & E1000_EECD_AUTO_RD
) break;
6683 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6684 return -E1000_ERR_RESET
;
6689 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6690 * Need to wait for PHY configuration completion before accessing NVM
6692 if (hw
->mac_type
== e1000_82573
)
6695 return E1000_SUCCESS
;
6698 /***************************************************************************
6699 * Checks if the PHY configuration is done
6701 * hw: Struct containing variables accessed by shared code
6703 * returns: - E1000_ERR_RESET if fail to reset MAC
6704 * E1000_SUCCESS at any other case.
6706 ***************************************************************************/
6708 e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
6710 int32_t timeout
= PHY_CFG_TIMEOUT
;
6711 uint32_t cfg_mask
= E1000_EEPROM_CFG_DONE
;
6713 DEBUGFUNC("e1000_get_phy_cfg_done");
6715 switch (hw
->mac_type
) {
6722 if (E1000_READ_REG(hw
, EEMNGCTL
) & cfg_mask
)
6730 DEBUGOUT("MNG configuration cycle has not completed.\n");
6731 return -E1000_ERR_RESET
;
6736 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6737 * Need to wait for PHY configuration completion before accessing NVM
6739 if (hw
->mac_type
== e1000_82573
)
6742 return E1000_SUCCESS
;
6745 /***************************************************************************
6747 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6748 * adapter or Eeprom access.
6750 * hw: Struct containing variables accessed by shared code
6752 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6753 * E1000_SUCCESS at any other case.
6755 ***************************************************************************/
6757 e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6762 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6764 if(!hw
->eeprom_semaphore_present
)
6765 return E1000_SUCCESS
;
6768 /* Get the FW semaphore. */
6769 timeout
= hw
->eeprom
.word_size
+ 1;
6771 swsm
= E1000_READ_REG(hw
, SWSM
);
6772 swsm
|= E1000_SWSM_SWESMBI
;
6773 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6774 /* if we managed to set the bit we got the semaphore. */
6775 swsm
= E1000_READ_REG(hw
, SWSM
);
6776 if(swsm
& E1000_SWSM_SWESMBI
)
6784 /* Release semaphores */
6785 e1000_put_hw_eeprom_semaphore(hw
);
6786 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6787 return -E1000_ERR_EEPROM
;
6790 return E1000_SUCCESS
;
6793 /***************************************************************************
6794 * This function clears HW semaphore bits.
6796 * hw: Struct containing variables accessed by shared code
6800 ***************************************************************************/
6802 e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6806 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6808 if(!hw
->eeprom_semaphore_present
)
6811 swsm
= E1000_READ_REG(hw
, SWSM
);
6812 swsm
&= ~(E1000_SWSM_SWESMBI
);
6813 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6816 /******************************************************************************
6817 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6818 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6819 * the caller to figure out how to deal with it.
6821 * hw - Struct containing variables accessed by shared code
6823 * returns: - E1000_BLK_PHY_RESET
6826 *****************************************************************************/
6828 e1000_check_phy_reset_block(struct e1000_hw
*hw
)
6831 if(hw
->mac_type
> e1000_82547_rev_2
)
6832 manc
= E1000_READ_REG(hw
, MANC
);
6833 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
6834 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
6838 e1000_arc_subsystem_valid(struct e1000_hw
*hw
)
6842 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6843 * may not be provided a DMA clock when no manageability features are
6844 * enabled. We do not want to perform any reads/writes to these registers
6845 * if this is the case. We read FWSM to determine the manageability mode.
6847 switch (hw
->mac_type
) {
6851 fwsm
= E1000_READ_REG(hw
, FWSM
);
6852 if((fwsm
& E1000_FWSM_MODE_MASK
) != 0)