1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
58 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
);
59 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
);
60 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
);
61 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
);
62 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
63 u16 words
, u16
*data
);
64 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
);
66 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
);
68 static void e1000_clear_vfta_82571(struct e1000_hw
*hw
);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
);
70 static s32
e1000_led_on_82574(struct e1000_hw
*hw
);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
);
72 static void e1000_power_down_phy_copper_82571(struct e1000_hw
*hw
);
75 * e1000_init_phy_params_82571 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
78 static s32
e1000_init_phy_params_82571(struct e1000_hw
*hw
)
80 struct e1000_phy_info
*phy
= &hw
->phy
;
83 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
84 phy
->type
= e1000_phy_none
;
89 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
90 phy
->reset_delay_us
= 100;
92 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
93 phy
->ops
.power_down
= e1000_power_down_phy_copper_82571
;
95 switch (hw
->mac
.type
) {
98 phy
->type
= e1000_phy_igp_2
;
101 phy
->type
= e1000_phy_m88
;
105 phy
->type
= e1000_phy_bm
;
108 return -E1000_ERR_PHY
;
112 /* This can only be done after all function pointers are setup. */
113 ret_val
= e1000_get_phy_id_82571(hw
);
116 switch (hw
->mac
.type
) {
119 if (phy
->id
!= IGP01E1000_I_PHY_ID
)
120 return -E1000_ERR_PHY
;
123 if (phy
->id
!= M88E1111_I_PHY_ID
)
124 return -E1000_ERR_PHY
;
128 if (phy
->id
!= BME1000_E_PHY_ID_R2
)
129 return -E1000_ERR_PHY
;
132 return -E1000_ERR_PHY
;
140 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
141 * @hw: pointer to the HW structure
143 static s32
e1000_init_nvm_params_82571(struct e1000_hw
*hw
)
145 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
146 u32 eecd
= er32(EECD
);
149 nvm
->opcode_bits
= 8;
151 switch (nvm
->override
) {
152 case e1000_nvm_override_spi_large
:
154 nvm
->address_bits
= 16;
156 case e1000_nvm_override_spi_small
:
158 nvm
->address_bits
= 8;
161 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
162 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
166 switch (hw
->mac
.type
) {
170 if (((eecd
>> 15) & 0x3) == 0x3) {
171 nvm
->type
= e1000_nvm_flash_hw
;
172 nvm
->word_size
= 2048;
174 * Autonomous Flash update bit must be cleared due
175 * to Flash update issue.
177 eecd
&= ~E1000_EECD_AUPDEN
;
183 nvm
->type
= e1000_nvm_eeprom_spi
;
184 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
185 E1000_EECD_SIZE_EX_SHIFT
);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
192 /* EEPROM access above 16k is unsupported */
195 nvm
->word_size
= 1 << size
;
203 * e1000_init_mac_params_82571 - Init MAC func ptrs.
204 * @hw: pointer to the HW structure
206 static s32
e1000_init_mac_params_82571(struct e1000_adapter
*adapter
)
208 struct e1000_hw
*hw
= &adapter
->hw
;
209 struct e1000_mac_info
*mac
= &hw
->mac
;
210 struct e1000_mac_operations
*func
= &mac
->ops
;
213 bool force_clear_smbi
= false;
216 switch (adapter
->pdev
->device
) {
217 case E1000_DEV_ID_82571EB_FIBER
:
218 case E1000_DEV_ID_82572EI_FIBER
:
219 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
220 hw
->phy
.media_type
= e1000_media_type_fiber
;
222 case E1000_DEV_ID_82571EB_SERDES
:
223 case E1000_DEV_ID_82572EI_SERDES
:
224 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
225 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
226 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
229 hw
->phy
.media_type
= e1000_media_type_copper
;
233 /* Set mta register count */
234 mac
->mta_reg_count
= 128;
235 /* Set rar entry count */
236 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
237 /* Set if manageability features are enabled. */
238 mac
->arc_subsystem_valid
= (er32(FWSM
) & E1000_FWSM_MODE_MASK
)
242 switch (hw
->phy
.media_type
) {
243 case e1000_media_type_copper
:
244 func
->setup_physical_interface
= e1000_setup_copper_link_82571
;
245 func
->check_for_link
= e1000e_check_for_copper_link
;
246 func
->get_link_up_info
= e1000e_get_speed_and_duplex_copper
;
248 case e1000_media_type_fiber
:
249 func
->setup_physical_interface
=
250 e1000_setup_fiber_serdes_link_82571
;
251 func
->check_for_link
= e1000e_check_for_fiber_link
;
252 func
->get_link_up_info
=
253 e1000e_get_speed_and_duplex_fiber_serdes
;
255 case e1000_media_type_internal_serdes
:
256 func
->setup_physical_interface
=
257 e1000_setup_fiber_serdes_link_82571
;
258 func
->check_for_link
= e1000_check_for_serdes_link_82571
;
259 func
->get_link_up_info
=
260 e1000e_get_speed_and_duplex_fiber_serdes
;
263 return -E1000_ERR_CONFIG
;
267 switch (hw
->mac
.type
) {
270 func
->check_mng_mode
= e1000_check_mng_mode_82574
;
271 func
->led_on
= e1000_led_on_82574
;
274 func
->check_mng_mode
= e1000e_check_mng_mode_generic
;
275 func
->led_on
= e1000e_led_on_generic
;
280 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
281 * first NVM or PHY acess. This should be done for single-port
282 * devices, and for one port only on dual-port devices so that
283 * for those devices we can still use the SMBI lock to synchronize
284 * inter-port accesses to the PHY & NVM.
286 switch (hw
->mac
.type
) {
291 if (!(swsm2
& E1000_SWSM2_LOCK
)) {
292 /* Only do this for the first interface on this card */
294 swsm2
| E1000_SWSM2_LOCK
);
295 force_clear_smbi
= true;
297 force_clear_smbi
= false;
300 force_clear_smbi
= true;
304 if (force_clear_smbi
) {
305 /* Make sure SWSM.SMBI is clear */
307 if (swsm
& E1000_SWSM_SMBI
) {
308 /* This bit should not be set on a first interface, and
309 * indicates that the bootagent or EFI code has
310 * improperly left this bit enabled
312 e_dbg("Please update your 82571 Bootagent\n");
314 ew32(SWSM
, swsm
& ~E1000_SWSM_SMBI
);
318 * Initialze device specific counter of SMBI acquisition
321 hw
->dev_spec
.e82571
.smb_counter
= 0;
326 static s32
e1000_get_variants_82571(struct e1000_adapter
*adapter
)
328 struct e1000_hw
*hw
= &adapter
->hw
;
329 static int global_quad_port_a
; /* global port a indication */
330 struct pci_dev
*pdev
= adapter
->pdev
;
332 int is_port_b
= er32(STATUS
) & E1000_STATUS_FUNC_1
;
335 rc
= e1000_init_mac_params_82571(adapter
);
339 rc
= e1000_init_nvm_params_82571(hw
);
343 rc
= e1000_init_phy_params_82571(hw
);
347 /* tag quad port adapters first, it's used below */
348 switch (pdev
->device
) {
349 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
350 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
351 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP
:
352 case E1000_DEV_ID_82571PT_QUAD_COPPER
:
353 adapter
->flags
|= FLAG_IS_QUAD_PORT
;
354 /* mark the first port */
355 if (global_quad_port_a
== 0)
356 adapter
->flags
|= FLAG_IS_QUAD_PORT_A
;
357 /* Reset for multiple quad port adapters */
358 global_quad_port_a
++;
359 if (global_quad_port_a
== 4)
360 global_quad_port_a
= 0;
366 switch (adapter
->hw
.mac
.type
) {
368 /* these dual ports don't have WoL on port B at all */
369 if (((pdev
->device
== E1000_DEV_ID_82571EB_FIBER
) ||
370 (pdev
->device
== E1000_DEV_ID_82571EB_SERDES
) ||
371 (pdev
->device
== E1000_DEV_ID_82571EB_COPPER
)) &&
373 adapter
->flags
&= ~FLAG_HAS_WOL
;
374 /* quad ports only support WoL on port A */
375 if (adapter
->flags
& FLAG_IS_QUAD_PORT
&&
376 (!(adapter
->flags
& FLAG_IS_QUAD_PORT_A
)))
377 adapter
->flags
&= ~FLAG_HAS_WOL
;
378 /* Does not support WoL on any port */
379 if (pdev
->device
== E1000_DEV_ID_82571EB_SERDES_QUAD
)
380 adapter
->flags
&= ~FLAG_HAS_WOL
;
384 if (pdev
->device
== E1000_DEV_ID_82573L
) {
385 if (e1000_read_nvm(&adapter
->hw
, NVM_INIT_3GIO_3
, 1,
388 if (!(eeprom_data
& NVM_WORD1A_ASPM_MASK
)) {
389 adapter
->flags
|= FLAG_HAS_JUMBO_FRAMES
;
390 adapter
->max_hw_frame_size
= DEFAULT_JUMBO
;
402 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
403 * @hw: pointer to the HW structure
405 * Reads the PHY registers and stores the PHY ID and possibly the PHY
406 * revision in the hardware structure.
408 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
)
410 struct e1000_phy_info
*phy
= &hw
->phy
;
414 switch (hw
->mac
.type
) {
418 * The 82571 firmware may still be configuring the PHY.
419 * In this case, we cannot access the PHY until the
420 * configuration is done. So we explicitly set the
423 phy
->id
= IGP01E1000_I_PHY_ID
;
426 return e1000e_get_phy_id(hw
);
430 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
434 phy
->id
= (u32
)(phy_id
<< 16);
436 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
440 phy
->id
|= (u32
)(phy_id
);
441 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
444 return -E1000_ERR_PHY
;
452 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
453 * @hw: pointer to the HW structure
455 * Acquire the HW semaphore to access the PHY or NVM
457 static s32
e1000_get_hw_semaphore_82571(struct e1000_hw
*hw
)
460 s32 sw_timeout
= hw
->nvm
.word_size
+ 1;
461 s32 fw_timeout
= hw
->nvm
.word_size
+ 1;
465 * If we have timedout 3 times on trying to acquire
466 * the inter-port SMBI semaphore, there is old code
467 * operating on the other port, and it is not
468 * releasing SMBI. Modify the number of times that
469 * we try for the semaphore to interwork with this
472 if (hw
->dev_spec
.e82571
.smb_counter
> 2)
475 /* Get the SW semaphore */
476 while (i
< sw_timeout
) {
478 if (!(swsm
& E1000_SWSM_SMBI
))
485 if (i
== sw_timeout
) {
486 e_dbg("Driver can't access device - SMBI bit is set.\n");
487 hw
->dev_spec
.e82571
.smb_counter
++;
489 /* Get the FW semaphore. */
490 for (i
= 0; i
< fw_timeout
; i
++) {
492 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
494 /* Semaphore acquired if bit latched */
495 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
501 if (i
== fw_timeout
) {
502 /* Release semaphores */
503 e1000_put_hw_semaphore_82571(hw
);
504 e_dbg("Driver can't access the NVM\n");
505 return -E1000_ERR_NVM
;
512 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
513 * @hw: pointer to the HW structure
515 * Release hardware semaphore used to access the PHY or NVM
517 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
)
522 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
527 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
528 * @hw: pointer to the HW structure
530 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
531 * Then for non-82573 hardware, set the EEPROM access request bit and wait
532 * for EEPROM access grant bit. If the access grant bit is not set, release
533 * hardware semaphore.
535 static s32
e1000_acquire_nvm_82571(struct e1000_hw
*hw
)
539 ret_val
= e1000_get_hw_semaphore_82571(hw
);
543 switch (hw
->mac
.type
) {
549 ret_val
= e1000e_acquire_nvm(hw
);
554 e1000_put_hw_semaphore_82571(hw
);
560 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
561 * @hw: pointer to the HW structure
563 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
565 static void e1000_release_nvm_82571(struct e1000_hw
*hw
)
567 e1000e_release_nvm(hw
);
568 e1000_put_hw_semaphore_82571(hw
);
572 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
573 * @hw: pointer to the HW structure
574 * @offset: offset within the EEPROM to be written to
575 * @words: number of words to write
576 * @data: 16 bit word(s) to be written to the EEPROM
578 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
580 * If e1000e_update_nvm_checksum is not called after this function, the
581 * EEPROM will most likely contain an invalid checksum.
583 static s32
e1000_write_nvm_82571(struct e1000_hw
*hw
, u16 offset
, u16 words
,
588 switch (hw
->mac
.type
) {
592 ret_val
= e1000_write_nvm_eewr_82571(hw
, offset
, words
, data
);
596 ret_val
= e1000e_write_nvm_spi(hw
, offset
, words
, data
);
599 ret_val
= -E1000_ERR_NVM
;
607 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
608 * @hw: pointer to the HW structure
610 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
611 * up to the checksum. Then calculates the EEPROM checksum and writes the
612 * value to the EEPROM.
614 static s32
e1000_update_nvm_checksum_82571(struct e1000_hw
*hw
)
620 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
625 * If our nvm is an EEPROM, then we're done
626 * otherwise, commit the checksum to the flash NVM.
628 if (hw
->nvm
.type
!= e1000_nvm_flash_hw
)
631 /* Check for pending operations. */
632 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
634 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
638 if (i
== E1000_FLASH_UPDATES
)
639 return -E1000_ERR_NVM
;
641 /* Reset the firmware if using STM opcode. */
642 if ((er32(FLOP
) & 0xFF00) == E1000_STM_OPCODE
) {
644 * The enabling of and the actual reset must be done
645 * in two write cycles.
647 ew32(HICR
, E1000_HICR_FW_RESET_ENABLE
);
649 ew32(HICR
, E1000_HICR_FW_RESET
);
652 /* Commit the write to flash */
653 eecd
= er32(EECD
) | E1000_EECD_FLUPD
;
656 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
658 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
662 if (i
== E1000_FLASH_UPDATES
)
663 return -E1000_ERR_NVM
;
669 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
670 * @hw: pointer to the HW structure
672 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
673 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
675 static s32
e1000_validate_nvm_checksum_82571(struct e1000_hw
*hw
)
677 if (hw
->nvm
.type
== e1000_nvm_flash_hw
)
678 e1000_fix_nvm_checksum_82571(hw
);
680 return e1000e_validate_nvm_checksum_generic(hw
);
684 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
685 * @hw: pointer to the HW structure
686 * @offset: offset within the EEPROM to be written to
687 * @words: number of words to write
688 * @data: 16 bit word(s) to be written to the EEPROM
690 * After checking for invalid values, poll the EEPROM to ensure the previous
691 * command has completed before trying to write the next word. After write
692 * poll for completion.
694 * If e1000e_update_nvm_checksum is not called after this function, the
695 * EEPROM will most likely contain an invalid checksum.
697 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
698 u16 words
, u16
*data
)
700 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
705 * A check for invalid values: offset too large, too many words,
706 * and not enough words.
708 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
710 e_dbg("nvm parameter(s) out of bounds\n");
711 return -E1000_ERR_NVM
;
714 for (i
= 0; i
< words
; i
++) {
715 eewr
= (data
[i
] << E1000_NVM_RW_REG_DATA
) |
716 ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
717 E1000_NVM_RW_REG_START
;
719 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
725 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
734 * e1000_get_cfg_done_82571 - Poll for configuration done
735 * @hw: pointer to the HW structure
737 * Reads the management control register for the config done bit to be set.
739 static s32
e1000_get_cfg_done_82571(struct e1000_hw
*hw
)
741 s32 timeout
= PHY_CFG_TIMEOUT
;
745 E1000_NVM_CFG_DONE_PORT_0
)
751 e_dbg("MNG configuration cycle has not completed.\n");
752 return -E1000_ERR_RESET
;
759 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
760 * @hw: pointer to the HW structure
761 * @active: true to enable LPLU, false to disable
763 * Sets the LPLU D0 state according to the active flag. When activating LPLU
764 * this function also disables smart speed and vice versa. LPLU will not be
765 * activated unless the device autonegotiation advertisement meets standards
766 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
767 * pointer entry point only called by PHY setup routines.
769 static s32
e1000_set_d0_lplu_state_82571(struct e1000_hw
*hw
, bool active
)
771 struct e1000_phy_info
*phy
= &hw
->phy
;
775 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
780 data
|= IGP02E1000_PM_D0_LPLU
;
781 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
785 /* When LPLU is enabled, we should disable SmartSpeed */
786 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
787 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
788 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
792 data
&= ~IGP02E1000_PM_D0_LPLU
;
793 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
795 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
796 * during Dx states where the power conservation is most
797 * important. During driver activity we should enable
798 * SmartSpeed, so performance is maintained.
800 if (phy
->smart_speed
== e1000_smart_speed_on
) {
801 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
806 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
807 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
811 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
812 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
817 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
818 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
829 * e1000_reset_hw_82571 - Reset hardware
830 * @hw: pointer to the HW structure
832 * This resets the hardware into a known state.
834 static s32
e1000_reset_hw_82571(struct e1000_hw
*hw
)
836 u32 ctrl
, extcnf_ctrl
, ctrl_ext
, icr
;
841 * Prevent the PCI-E bus from sticking if there is no TLP connection
842 * on the last TLP read/write transaction when MAC is reset.
844 ret_val
= e1000e_disable_pcie_master(hw
);
846 e_dbg("PCI-E Master disable polling has failed.\n");
848 e_dbg("Masking off all interrupts\n");
849 ew32(IMC
, 0xffffffff);
852 ew32(TCTL
, E1000_TCTL_PSP
);
858 * Must acquire the MDIO ownership before MAC reset.
859 * Ownership defaults to firmware after a reset.
861 switch (hw
->mac
.type
) {
865 extcnf_ctrl
= er32(EXTCNF_CTRL
);
866 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
869 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
870 extcnf_ctrl
= er32(EXTCNF_CTRL
);
872 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
875 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
879 } while (i
< MDIO_OWNERSHIP_TIMEOUT
);
887 e_dbg("Issuing a global reset to MAC\n");
888 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
890 if (hw
->nvm
.type
== e1000_nvm_flash_hw
) {
892 ctrl_ext
= er32(CTRL_EXT
);
893 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
894 ew32(CTRL_EXT
, ctrl_ext
);
898 ret_val
= e1000e_get_auto_rd_done(hw
);
900 /* We don't want to continue accessing MAC registers. */
904 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
905 * Need to wait for Phy configuration completion before accessing
909 switch (hw
->mac
.type
) {
919 /* Clear any pending interrupt events. */
920 ew32(IMC
, 0xffffffff);
923 if (hw
->mac
.type
== e1000_82571
&&
924 hw
->dev_spec
.e82571
.alt_mac_addr_is_present
)
925 e1000e_set_laa_state_82571(hw
, true);
927 /* Reinitialize the 82571 serdes link state machine */
928 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
929 hw
->mac
.serdes_link_state
= e1000_serdes_link_down
;
935 * e1000_init_hw_82571 - Initialize hardware
936 * @hw: pointer to the HW structure
938 * This inits the hardware readying it for operation.
940 static s32
e1000_init_hw_82571(struct e1000_hw
*hw
)
942 struct e1000_mac_info
*mac
= &hw
->mac
;
945 u16 i
, rar_count
= mac
->rar_entry_count
;
947 e1000_initialize_hw_bits_82571(hw
);
949 /* Initialize identification LED */
950 ret_val
= e1000e_id_led_init(hw
);
952 e_dbg("Error initializing identification LED\n");
953 /* This is not fatal and we should not stop init due to this */
955 /* Disabling VLAN filtering */
956 e_dbg("Initializing the IEEE VLAN\n");
957 mac
->ops
.clear_vfta(hw
);
959 /* Setup the receive address. */
961 * If, however, a locally administered address was assigned to the
962 * 82571, we must reserve a RAR for it to work around an issue where
963 * resetting one port will reload the MAC on the other port.
965 if (e1000e_get_laa_state_82571(hw
))
967 e1000e_init_rx_addrs(hw
, rar_count
);
969 /* Zero out the Multicast HASH table */
970 e_dbg("Zeroing the MTA\n");
971 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
972 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
974 /* Setup link and flow control */
975 ret_val
= e1000_setup_link_82571(hw
);
977 /* Set the transmit descriptor write-back policy */
978 reg_data
= er32(TXDCTL(0));
979 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
980 E1000_TXDCTL_FULL_TX_DESC_WB
|
981 E1000_TXDCTL_COUNT_DESC
;
982 ew32(TXDCTL(0), reg_data
);
984 /* ...for both queues. */
989 e1000e_enable_tx_pkt_filtering(hw
);
990 reg_data
= er32(GCR
);
991 reg_data
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
995 reg_data
= er32(TXDCTL(1));
996 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
997 E1000_TXDCTL_FULL_TX_DESC_WB
|
998 E1000_TXDCTL_COUNT_DESC
;
999 ew32(TXDCTL(1), reg_data
);
1004 * Clear all of the statistics registers (clear on read). It is
1005 * important that we do this after we have tried to establish link
1006 * because the symbol error count will increment wildly if there
1009 e1000_clear_hw_cntrs_82571(hw
);
1015 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1016 * @hw: pointer to the HW structure
1018 * Initializes required hardware-dependent bits needed for normal operation.
1020 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
)
1024 /* Transmit Descriptor Control 0 */
1025 reg
= er32(TXDCTL(0));
1027 ew32(TXDCTL(0), reg
);
1029 /* Transmit Descriptor Control 1 */
1030 reg
= er32(TXDCTL(1));
1032 ew32(TXDCTL(1), reg
);
1034 /* Transmit Arbitration Control 0 */
1035 reg
= er32(TARC(0));
1036 reg
&= ~(0xF << 27); /* 30:27 */
1037 switch (hw
->mac
.type
) {
1040 reg
|= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1047 /* Transmit Arbitration Control 1 */
1048 reg
= er32(TARC(1));
1049 switch (hw
->mac
.type
) {
1052 reg
&= ~((1 << 29) | (1 << 30));
1053 reg
|= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1054 if (er32(TCTL
) & E1000_TCTL_MULR
)
1064 /* Device Control */
1065 switch (hw
->mac
.type
) {
1077 /* Extended Device Control */
1078 switch (hw
->mac
.type
) {
1082 reg
= er32(CTRL_EXT
);
1085 ew32(CTRL_EXT
, reg
);
1091 if (hw
->mac
.type
== e1000_82571
) {
1092 reg
= er32(PBA_ECC
);
1093 reg
|= E1000_PBA_ECC_CORR_EN
;
1097 * Workaround for hardware errata.
1098 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1101 if ((hw
->mac
.type
== e1000_82571
) ||
1102 (hw
->mac
.type
== e1000_82572
)) {
1103 reg
= er32(CTRL_EXT
);
1104 reg
&= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN
;
1105 ew32(CTRL_EXT
, reg
);
1109 /* PCI-Ex Control Registers */
1110 switch (hw
->mac
.type
) {
1118 * Workaround for hardware errata.
1119 * apply workaround for hardware errata documented in errata
1120 * docs Fixes issue where some error prone or unreliable PCIe
1121 * completions are occurring, particularly with ASPM enabled.
1122 * Without fix, issue can cause tx timeouts.
1136 * e1000_clear_vfta_82571 - Clear VLAN filter table
1137 * @hw: pointer to the HW structure
1139 * Clears the register array which contains the VLAN filter table by
1140 * setting all the values to 0.
1142 static void e1000_clear_vfta_82571(struct e1000_hw
*hw
)
1146 u32 vfta_offset
= 0;
1147 u32 vfta_bit_in_reg
= 0;
1149 switch (hw
->mac
.type
) {
1153 if (hw
->mng_cookie
.vlan_id
!= 0) {
1155 * The VFTA is a 4096b bit-field, each identifying
1156 * a single VLAN ID. The following operations
1157 * determine which 32b entry (i.e. offset) into the
1158 * array we want to set the VLAN ID (i.e. bit) of
1159 * the manageability unit.
1161 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
1162 E1000_VFTA_ENTRY_SHIFT
) &
1163 E1000_VFTA_ENTRY_MASK
;
1164 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
1165 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
1171 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
1173 * If the offset we want to clear is the same offset of the
1174 * manageability VLAN ID, then clear all bits except that of
1175 * the manageability unit.
1177 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
1178 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, vfta_value
);
1184 * e1000_check_mng_mode_82574 - Check manageability is enabled
1185 * @hw: pointer to the HW structure
1187 * Reads the NVM Initialization Control Word 2 and returns true
1188 * (>0) if any manageability is enabled, else false (0).
1190 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
)
1194 e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &data
);
1195 return (data
& E1000_NVM_INIT_CTRL2_MNGM
) != 0;
1199 * e1000_led_on_82574 - Turn LED on
1200 * @hw: pointer to the HW structure
1204 static s32
e1000_led_on_82574(struct e1000_hw
*hw
)
1209 ctrl
= hw
->mac
.ledctl_mode2
;
1210 if (!(E1000_STATUS_LU
& er32(STATUS
))) {
1212 * If no link, then turn LED on by setting the invert bit
1213 * for each LED that's "on" (0x0E) in ledctl_mode2.
1215 for (i
= 0; i
< 4; i
++)
1216 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1217 E1000_LEDCTL_MODE_LED_ON
)
1218 ctrl
|= (E1000_LEDCTL_LED0_IVRT
<< (i
* 8));
1226 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1227 * @hw: pointer to the HW structure
1228 * @mc_addr_list: array of multicast addresses to program
1229 * @mc_addr_count: number of multicast addresses to program
1230 * @rar_used_count: the first RAR register free to program
1231 * @rar_count: total number of supported Receive Address Registers
1233 * Updates the Receive Address Registers and Multicast Table Array.
1234 * The caller must have a packed mc_addr_list of multicast addresses.
1235 * The parameter rar_count will usually be hw->mac.rar_entry_count
1236 * unless there are workarounds that change this.
1238 static void e1000_update_mc_addr_list_82571(struct e1000_hw
*hw
,
1244 if (e1000e_get_laa_state_82571(hw
))
1247 e1000e_update_mc_addr_list_generic(hw
, mc_addr_list
, mc_addr_count
,
1248 rar_used_count
, rar_count
);
1252 * e1000_setup_link_82571 - Setup flow control and link settings
1253 * @hw: pointer to the HW structure
1255 * Determines which flow control settings to use, then configures flow
1256 * control. Calls the appropriate media-specific link configuration
1257 * function. Assuming the adapter has a valid link partner, a valid link
1258 * should be established. Assumes the hardware has previously been reset
1259 * and the transmitter and receiver are not enabled.
1261 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
)
1264 * 82573 does not have a word in the NVM to determine
1265 * the default flow control setting, so we explicitly
1268 switch (hw
->mac
.type
) {
1272 if (hw
->fc
.requested_mode
== e1000_fc_default
)
1273 hw
->fc
.requested_mode
= e1000_fc_full
;
1279 return e1000e_setup_link(hw
);
1283 * e1000_setup_copper_link_82571 - Configure copper link settings
1284 * @hw: pointer to the HW structure
1286 * Configures the link for auto-neg or forced speed and duplex. Then we check
1287 * for link, once link is established calls to configure collision distance
1288 * and flow control are called.
1290 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
)
1296 ctrl
|= E1000_CTRL_SLU
;
1297 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1300 switch (hw
->phy
.type
) {
1303 ret_val
= e1000e_copper_link_setup_m88(hw
);
1305 case e1000_phy_igp_2
:
1306 ret_val
= e1000e_copper_link_setup_igp(hw
);
1309 return -E1000_ERR_PHY
;
1316 ret_val
= e1000e_setup_copper_link(hw
);
1322 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1323 * @hw: pointer to the HW structure
1325 * Configures collision distance and flow control for fiber and serdes links.
1326 * Upon successful setup, poll for link.
1328 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
)
1330 switch (hw
->mac
.type
) {
1334 * If SerDes loopback mode is entered, there is no form
1335 * of reset to take the adapter out of that mode. So we
1336 * have to explicitly take the adapter out of loopback
1337 * mode. This prevents drivers from twiddling their thumbs
1338 * if another tool failed to take it out of loopback mode.
1340 ew32(SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1346 return e1000e_setup_fiber_serdes_link(hw
);
1350 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1351 * @hw: pointer to the HW structure
1353 * Reports the link state as up or down.
1355 * If autonegotiation is supported by the link partner, the link state is
1356 * determined by the result of autonegotiation. This is the most likely case.
1357 * If autonegotiation is not supported by the link partner, and the link
1358 * has a valid signal, force the link up.
1360 * The link state is represented internally here by 4 states:
1363 * 2) autoneg_progress
1364 * 3) autoneg_complete (the link sucessfully autonegotiated)
1365 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1368 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
)
1370 struct e1000_mac_info
*mac
= &hw
->mac
;
1377 status
= er32(STATUS
);
1380 if ((rxcw
& E1000_RXCW_SYNCH
) && !(rxcw
& E1000_RXCW_IV
)) {
1382 /* Receiver is synchronized with no invalid bits. */
1383 switch (mac
->serdes_link_state
) {
1384 case e1000_serdes_link_autoneg_complete
:
1385 if (!(status
& E1000_STATUS_LU
)) {
1387 * We have lost link, retry autoneg before
1388 * reporting link failure
1390 mac
->serdes_link_state
=
1391 e1000_serdes_link_autoneg_progress
;
1392 mac
->serdes_has_link
= false;
1393 e_dbg("AN_UP -> AN_PROG\n");
1397 case e1000_serdes_link_forced_up
:
1399 * If we are receiving /C/ ordered sets, re-enable
1400 * auto-negotiation in the TXCW register and disable
1401 * forced link in the Device Control register in an
1402 * attempt to auto-negotiate with our link partner.
1404 if (rxcw
& E1000_RXCW_C
) {
1405 /* Enable autoneg, and unforce link up */
1406 ew32(TXCW
, mac
->txcw
);
1407 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
1408 mac
->serdes_link_state
=
1409 e1000_serdes_link_autoneg_progress
;
1410 mac
->serdes_has_link
= false;
1411 e_dbg("FORCED_UP -> AN_PROG\n");
1415 case e1000_serdes_link_autoneg_progress
:
1416 if (rxcw
& E1000_RXCW_C
) {
1418 * We received /C/ ordered sets, meaning the
1419 * link partner has autonegotiated, and we can
1420 * trust the Link Up (LU) status bit.
1422 if (status
& E1000_STATUS_LU
) {
1423 mac
->serdes_link_state
=
1424 e1000_serdes_link_autoneg_complete
;
1425 e_dbg("AN_PROG -> AN_UP\n");
1426 mac
->serdes_has_link
= true;
1428 /* Autoneg completed, but failed. */
1429 mac
->serdes_link_state
=
1430 e1000_serdes_link_down
;
1431 e_dbg("AN_PROG -> DOWN\n");
1435 * The link partner did not autoneg.
1436 * Force link up and full duplex, and change
1439 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
1440 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
1443 /* Configure Flow Control after link up. */
1444 ret_val
= e1000e_config_fc_after_link_up(hw
);
1446 e_dbg("Error config flow control\n");
1449 mac
->serdes_link_state
=
1450 e1000_serdes_link_forced_up
;
1451 mac
->serdes_has_link
= true;
1452 e_dbg("AN_PROG -> FORCED_UP\n");
1456 case e1000_serdes_link_down
:
1459 * The link was down but the receiver has now gained
1460 * valid sync, so lets see if we can bring the link
1463 ew32(TXCW
, mac
->txcw
);
1464 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
1465 mac
->serdes_link_state
=
1466 e1000_serdes_link_autoneg_progress
;
1467 e_dbg("DOWN -> AN_PROG\n");
1471 if (!(rxcw
& E1000_RXCW_SYNCH
)) {
1472 mac
->serdes_has_link
= false;
1473 mac
->serdes_link_state
= e1000_serdes_link_down
;
1474 e_dbg("ANYSTATE -> DOWN\n");
1477 * We have sync, and can tolerate one invalid (IV)
1478 * codeword before declaring link down, so reread
1483 if (rxcw
& E1000_RXCW_IV
) {
1484 mac
->serdes_link_state
= e1000_serdes_link_down
;
1485 mac
->serdes_has_link
= false;
1486 e_dbg("ANYSTATE -> DOWN\n");
1495 * e1000_valid_led_default_82571 - Verify a valid default LED config
1496 * @hw: pointer to the HW structure
1497 * @data: pointer to the NVM (EEPROM)
1499 * Read the EEPROM for the current default LED configuration. If the
1500 * LED configuration is not valid, set to a valid LED configuration.
1502 static s32
e1000_valid_led_default_82571(struct e1000_hw
*hw
, u16
*data
)
1506 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1508 e_dbg("NVM Read Error\n");
1512 switch (hw
->mac
.type
) {
1516 if (*data
== ID_LED_RESERVED_F746
)
1517 *data
= ID_LED_DEFAULT_82573
;
1520 if (*data
== ID_LED_RESERVED_0000
||
1521 *data
== ID_LED_RESERVED_FFFF
)
1522 *data
= ID_LED_DEFAULT
;
1530 * e1000e_get_laa_state_82571 - Get locally administered address state
1531 * @hw: pointer to the HW structure
1533 * Retrieve and return the current locally administered address state.
1535 bool e1000e_get_laa_state_82571(struct e1000_hw
*hw
)
1537 if (hw
->mac
.type
!= e1000_82571
)
1540 return hw
->dev_spec
.e82571
.laa_is_present
;
1544 * e1000e_set_laa_state_82571 - Set locally administered address state
1545 * @hw: pointer to the HW structure
1546 * @state: enable/disable locally administered address
1548 * Enable/Disable the current locally administered address state.
1550 void e1000e_set_laa_state_82571(struct e1000_hw
*hw
, bool state
)
1552 if (hw
->mac
.type
!= e1000_82571
)
1555 hw
->dev_spec
.e82571
.laa_is_present
= state
;
1557 /* If workaround is activated... */
1560 * Hold a copy of the LAA in RAR[14] This is done so that
1561 * between the time RAR[0] gets clobbered and the time it
1562 * gets fixed, the actual LAA is in one of the RARs and no
1563 * incoming packets directed to this port are dropped.
1564 * Eventually the LAA will be in RAR[0] and RAR[14].
1566 e1000e_rar_set(hw
, hw
->mac
.addr
, hw
->mac
.rar_entry_count
- 1);
1570 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1571 * @hw: pointer to the HW structure
1573 * Verifies that the EEPROM has completed the update. After updating the
1574 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1575 * the checksum fix is not implemented, we need to set the bit and update
1576 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1577 * we need to return bad checksum.
1579 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
)
1581 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1585 if (nvm
->type
!= e1000_nvm_flash_hw
)
1589 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1590 * 10h-12h. Checksum may need to be fixed.
1592 ret_val
= e1000_read_nvm(hw
, 0x10, 1, &data
);
1596 if (!(data
& 0x10)) {
1598 * Read 0x23 and check bit 15. This bit is a 1
1599 * when the checksum has already been fixed. If
1600 * the checksum is still wrong and this bit is a
1601 * 1, we need to return bad checksum. Otherwise,
1602 * we need to set this bit to a 1 and update the
1605 ret_val
= e1000_read_nvm(hw
, 0x23, 1, &data
);
1609 if (!(data
& 0x8000)) {
1611 ret_val
= e1000_write_nvm(hw
, 0x23, 1, &data
);
1614 ret_val
= e1000e_update_nvm_checksum(hw
);
1622 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1623 * @hw: pointer to the HW structure
1625 * In the case of a PHY power down to save power, or to turn off link during a
1626 * driver unload, or wake on lan is not enabled, remove the link.
1628 static void e1000_power_down_phy_copper_82571(struct e1000_hw
*hw
)
1630 struct e1000_phy_info
*phy
= &hw
->phy
;
1631 struct e1000_mac_info
*mac
= &hw
->mac
;
1633 if (!(phy
->ops
.check_reset_block
))
1636 /* If the management interface is not enabled, then power down */
1637 if (!(mac
->ops
.check_mng_mode(hw
) || phy
->ops
.check_reset_block(hw
)))
1638 e1000_power_down_phy_copper(hw
);
1644 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1645 * @hw: pointer to the HW structure
1647 * Clears the hardware counters by reading the counter registers.
1649 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
)
1651 e1000e_clear_hw_cntrs_base(hw
);
1689 static struct e1000_mac_operations e82571_mac_ops
= {
1690 /* .check_mng_mode: mac type dependent */
1691 /* .check_for_link: media type dependent */
1692 .id_led_init
= e1000e_id_led_init
,
1693 .cleanup_led
= e1000e_cleanup_led_generic
,
1694 .clear_hw_cntrs
= e1000_clear_hw_cntrs_82571
,
1695 .get_bus_info
= e1000e_get_bus_info_pcie
,
1696 /* .get_link_up_info: media type dependent */
1697 /* .led_on: mac type dependent */
1698 .led_off
= e1000e_led_off_generic
,
1699 .update_mc_addr_list
= e1000_update_mc_addr_list_82571
,
1700 .write_vfta
= e1000_write_vfta_generic
,
1701 .clear_vfta
= e1000_clear_vfta_82571
,
1702 .reset_hw
= e1000_reset_hw_82571
,
1703 .init_hw
= e1000_init_hw_82571
,
1704 .setup_link
= e1000_setup_link_82571
,
1705 /* .setup_physical_interface: media type dependent */
1706 .setup_led
= e1000e_setup_led_generic
,
1709 static struct e1000_phy_operations e82_phy_ops_igp
= {
1710 .acquire
= e1000_get_hw_semaphore_82571
,
1711 .check_polarity
= e1000_check_polarity_igp
,
1712 .check_reset_block
= e1000e_check_reset_block_generic
,
1714 .force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
,
1715 .get_cfg_done
= e1000_get_cfg_done_82571
,
1716 .get_cable_length
= e1000e_get_cable_length_igp_2
,
1717 .get_info
= e1000e_get_phy_info_igp
,
1718 .read_reg
= e1000e_read_phy_reg_igp
,
1719 .release
= e1000_put_hw_semaphore_82571
,
1720 .reset
= e1000e_phy_hw_reset_generic
,
1721 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1722 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1723 .write_reg
= e1000e_write_phy_reg_igp
,
1724 .cfg_on_link_up
= NULL
,
1727 static struct e1000_phy_operations e82_phy_ops_m88
= {
1728 .acquire
= e1000_get_hw_semaphore_82571
,
1729 .check_polarity
= e1000_check_polarity_m88
,
1730 .check_reset_block
= e1000e_check_reset_block_generic
,
1731 .commit
= e1000e_phy_sw_reset
,
1732 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1733 .get_cfg_done
= e1000e_get_cfg_done
,
1734 .get_cable_length
= e1000e_get_cable_length_m88
,
1735 .get_info
= e1000e_get_phy_info_m88
,
1736 .read_reg
= e1000e_read_phy_reg_m88
,
1737 .release
= e1000_put_hw_semaphore_82571
,
1738 .reset
= e1000e_phy_hw_reset_generic
,
1739 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1740 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1741 .write_reg
= e1000e_write_phy_reg_m88
,
1742 .cfg_on_link_up
= NULL
,
1745 static struct e1000_phy_operations e82_phy_ops_bm
= {
1746 .acquire
= e1000_get_hw_semaphore_82571
,
1747 .check_polarity
= e1000_check_polarity_m88
,
1748 .check_reset_block
= e1000e_check_reset_block_generic
,
1749 .commit
= e1000e_phy_sw_reset
,
1750 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1751 .get_cfg_done
= e1000e_get_cfg_done
,
1752 .get_cable_length
= e1000e_get_cable_length_m88
,
1753 .get_info
= e1000e_get_phy_info_m88
,
1754 .read_reg
= e1000e_read_phy_reg_bm2
,
1755 .release
= e1000_put_hw_semaphore_82571
,
1756 .reset
= e1000e_phy_hw_reset_generic
,
1757 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1758 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1759 .write_reg
= e1000e_write_phy_reg_bm2
,
1760 .cfg_on_link_up
= NULL
,
1763 static struct e1000_nvm_operations e82571_nvm_ops
= {
1764 .acquire
= e1000_acquire_nvm_82571
,
1765 .read
= e1000e_read_nvm_eerd
,
1766 .release
= e1000_release_nvm_82571
,
1767 .update
= e1000_update_nvm_checksum_82571
,
1768 .valid_led_default
= e1000_valid_led_default_82571
,
1769 .validate
= e1000_validate_nvm_checksum_82571
,
1770 .write
= e1000_write_nvm_82571
,
1773 struct e1000_info e1000_82571_info
= {
1775 .flags
= FLAG_HAS_HW_VLAN_FILTER
1776 | FLAG_HAS_JUMBO_FRAMES
1778 | FLAG_APME_IN_CTRL3
1779 | FLAG_RX_CSUM_ENABLED
1780 | FLAG_HAS_CTRLEXT_ON_LOAD
1781 | FLAG_HAS_SMART_POWER_DOWN
1782 | FLAG_RESET_OVERWRITES_LAA
/* errata */
1783 | FLAG_TARC_SPEED_MODE_BIT
/* errata */
1784 | FLAG_APME_CHECK_PORT_B
,
1786 .max_hw_frame_size
= DEFAULT_JUMBO
,
1787 .get_variants
= e1000_get_variants_82571
,
1788 .mac_ops
= &e82571_mac_ops
,
1789 .phy_ops
= &e82_phy_ops_igp
,
1790 .nvm_ops
= &e82571_nvm_ops
,
1793 struct e1000_info e1000_82572_info
= {
1795 .flags
= FLAG_HAS_HW_VLAN_FILTER
1796 | FLAG_HAS_JUMBO_FRAMES
1798 | FLAG_APME_IN_CTRL3
1799 | FLAG_RX_CSUM_ENABLED
1800 | FLAG_HAS_CTRLEXT_ON_LOAD
1801 | FLAG_TARC_SPEED_MODE_BIT
, /* errata */
1803 .max_hw_frame_size
= DEFAULT_JUMBO
,
1804 .get_variants
= e1000_get_variants_82571
,
1805 .mac_ops
= &e82571_mac_ops
,
1806 .phy_ops
= &e82_phy_ops_igp
,
1807 .nvm_ops
= &e82571_nvm_ops
,
1810 struct e1000_info e1000_82573_info
= {
1812 .flags
= FLAG_HAS_HW_VLAN_FILTER
1813 | FLAG_HAS_JUMBO_FRAMES
1815 | FLAG_APME_IN_CTRL3
1816 | FLAG_RX_CSUM_ENABLED
1817 | FLAG_HAS_SMART_POWER_DOWN
1820 | FLAG_HAS_SWSM_ON_LOAD
,
1822 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1823 .get_variants
= e1000_get_variants_82571
,
1824 .mac_ops
= &e82571_mac_ops
,
1825 .phy_ops
= &e82_phy_ops_m88
,
1826 .nvm_ops
= &e82571_nvm_ops
,
1829 struct e1000_info e1000_82574_info
= {
1831 .flags
= FLAG_HAS_HW_VLAN_FILTER
1833 | FLAG_HAS_JUMBO_FRAMES
1835 | FLAG_APME_IN_CTRL3
1836 | FLAG_RX_CSUM_ENABLED
1837 | FLAG_HAS_SMART_POWER_DOWN
1839 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1841 .max_hw_frame_size
= DEFAULT_JUMBO
,
1842 .get_variants
= e1000_get_variants_82571
,
1843 .mac_ops
= &e82571_mac_ops
,
1844 .phy_ops
= &e82_phy_ops_bm
,
1845 .nvm_ops
= &e82571_nvm_ops
,
1848 struct e1000_info e1000_82583_info
= {
1850 .flags
= FLAG_HAS_HW_VLAN_FILTER
1852 | FLAG_APME_IN_CTRL3
1853 | FLAG_RX_CSUM_ENABLED
1854 | FLAG_HAS_SMART_POWER_DOWN
1856 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1858 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1859 .get_variants
= e1000_get_variants_82571
,
1860 .mac_ops
= &e82571_mac_ops
,
1861 .phy_ops
= &e82_phy_ops_bm
,
1862 .nvm_ops
= &e82571_nvm_ops
,