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1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include <linux/netdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/delay.h>
60 #include <linux/pci.h>
61
62 #include "e1000.h"
63
64 #define ICH_FLASH_GFPREG 0x0000
65 #define ICH_FLASH_HSFSTS 0x0004
66 #define ICH_FLASH_HSFCTL 0x0006
67 #define ICH_FLASH_FADDR 0x0008
68 #define ICH_FLASH_FDATA0 0x0010
69 #define ICH_FLASH_PR0 0x0074
70
71 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
76
77 #define ICH_CYCLE_READ 0
78 #define ICH_CYCLE_WRITE 2
79 #define ICH_CYCLE_ERASE 3
80
81 #define FLASH_GFPREG_BASE_MASK 0x1FFF
82 #define FLASH_SECTOR_ADDR_SHIFT 12
83
84 #define ICH_FLASH_SEG_SIZE_256 256
85 #define ICH_FLASH_SEG_SIZE_4K 4096
86 #define ICH_FLASH_SEG_SIZE_8K 8192
87 #define ICH_FLASH_SEG_SIZE_64K 65536
88
89
90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
91
92 #define E1000_ICH_MNG_IAMT_MODE 0x2
93
94 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
97 (ID_LED_DEF1_DEF2))
98
99 #define E1000_ICH_NVM_SIG_WORD 0x13
100 #define E1000_ICH_NVM_SIG_MASK 0xC000
101 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102 #define E1000_ICH_NVM_SIG_VALUE 0x80
103
104 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105
106 #define E1000_FEXTNVM_SW_CONFIG 1
107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110
111 #define E1000_ICH_RAR_ENTRIES 7
112
113 #define PHY_PAGE_SHIFT 5
114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
117 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
118
119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
122
123 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
124
125 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
126
127 /* SMBus Address Phy Register */
128 #define HV_SMB_ADDR PHY_REG(768, 26)
129 #define HV_SMB_ADDR_PEC_EN 0x0200
130 #define HV_SMB_ADDR_VALID 0x0080
131
132 /* Strapping Option Register - RO */
133 #define E1000_STRAP 0x0000C
134 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
135 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
136
137 /* OEM Bits Phy Register */
138 #define HV_OEM_BITS PHY_REG(768, 25)
139 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
140 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
141 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
142
143 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
144 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
145
146 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
147 /* Offset 04h HSFSTS */
148 union ich8_hws_flash_status {
149 struct ich8_hsfsts {
150 u16 flcdone :1; /* bit 0 Flash Cycle Done */
151 u16 flcerr :1; /* bit 1 Flash Cycle Error */
152 u16 dael :1; /* bit 2 Direct Access error Log */
153 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
154 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
155 u16 reserved1 :2; /* bit 13:6 Reserved */
156 u16 reserved2 :6; /* bit 13:6 Reserved */
157 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
158 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
159 } hsf_status;
160 u16 regval;
161 };
162
163 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
164 /* Offset 06h FLCTL */
165 union ich8_hws_flash_ctrl {
166 struct ich8_hsflctl {
167 u16 flcgo :1; /* 0 Flash Cycle Go */
168 u16 flcycle :2; /* 2:1 Flash Cycle */
169 u16 reserved :5; /* 7:3 Reserved */
170 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
171 u16 flockdn :6; /* 15:10 Reserved */
172 } hsf_ctrl;
173 u16 regval;
174 };
175
176 /* ICH Flash Region Access Permissions */
177 union ich8_hws_flash_regacc {
178 struct ich8_flracc {
179 u32 grra :8; /* 0:7 GbE region Read Access */
180 u32 grwa :8; /* 8:15 GbE region Write Access */
181 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
182 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
183 } hsf_flregacc;
184 u16 regval;
185 };
186
187 /* ICH Flash Protected Region */
188 union ich8_flash_protected_range {
189 struct ich8_pr {
190 u32 base:13; /* 0:12 Protected Range Base */
191 u32 reserved1:2; /* 13:14 Reserved */
192 u32 rpe:1; /* 15 Read Protection Enable */
193 u32 limit:13; /* 16:28 Protected Range Limit */
194 u32 reserved2:2; /* 29:30 Reserved */
195 u32 wpe:1; /* 31 Write Protection Enable */
196 } range;
197 u32 regval;
198 };
199
200 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
201 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
202 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
203 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
226 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
227 static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
228
229 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
230 {
231 return readw(hw->flash_address + reg);
232 }
233
234 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
235 {
236 return readl(hw->flash_address + reg);
237 }
238
239 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
240 {
241 writew(val, hw->flash_address + reg);
242 }
243
244 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
245 {
246 writel(val, hw->flash_address + reg);
247 }
248
249 #define er16flash(reg) __er16flash(hw, (reg))
250 #define er32flash(reg) __er32flash(hw, (reg))
251 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
252 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
253
254 /**
255 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
256 * @hw: pointer to the HW structure
257 *
258 * Initialize family-specific PHY parameters and function pointers.
259 **/
260 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
261 {
262 struct e1000_phy_info *phy = &hw->phy;
263 s32 ret_val = 0;
264
265 phy->addr = 1;
266 phy->reset_delay_us = 100;
267
268 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
269 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
270 phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
271 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
272 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
274 phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
276
277 phy->id = e1000_phy_unknown;
278 e1000e_get_phy_id(hw);
279 phy->type = e1000e_get_phy_type_from_id(phy->id);
280
281 if (phy->type == e1000_phy_82577) {
282 phy->ops.check_polarity = e1000_check_polarity_82577;
283 phy->ops.force_speed_duplex =
284 e1000_phy_force_speed_duplex_82577;
285 phy->ops.get_cable_length = e1000_get_cable_length_82577;
286 phy->ops.get_phy_info = e1000_get_phy_info_82577;
287 phy->ops.commit_phy = e1000e_phy_sw_reset;
288 }
289
290 return ret_val;
291 }
292
293 /**
294 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
295 * @hw: pointer to the HW structure
296 *
297 * Initialize family-specific PHY parameters and function pointers.
298 **/
299 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
300 {
301 struct e1000_phy_info *phy = &hw->phy;
302 s32 ret_val;
303 u16 i = 0;
304
305 phy->addr = 1;
306 phy->reset_delay_us = 100;
307
308 /*
309 * We may need to do this twice - once for IGP and if that fails,
310 * we'll set BM func pointers and try again
311 */
312 ret_val = e1000e_determine_phy_address(hw);
313 if (ret_val) {
314 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
315 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
316 ret_val = e1000e_determine_phy_address(hw);
317 if (ret_val)
318 return ret_val;
319 }
320
321 phy->id = 0;
322 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
323 (i++ < 100)) {
324 msleep(1);
325 ret_val = e1000e_get_phy_id(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330 /* Verify phy id */
331 switch (phy->id) {
332 case IGP03E1000_E_PHY_ID:
333 phy->type = e1000_phy_igp_3;
334 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
335 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
336 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
337 break;
338 case IFE_E_PHY_ID:
339 case IFE_PLUS_E_PHY_ID:
340 case IFE_C_E_PHY_ID:
341 phy->type = e1000_phy_ife;
342 phy->autoneg_mask = E1000_ALL_NOT_GIG;
343 break;
344 case BME1000_E_PHY_ID:
345 phy->type = e1000_phy_bm;
346 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
347 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
348 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
349 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
350 break;
351 default:
352 return -E1000_ERR_PHY;
353 break;
354 }
355
356 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
357
358 return 0;
359 }
360
361 /**
362 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
363 * @hw: pointer to the HW structure
364 *
365 * Initialize family-specific NVM parameters and function
366 * pointers.
367 **/
368 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
369 {
370 struct e1000_nvm_info *nvm = &hw->nvm;
371 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
372 u32 gfpreg, sector_base_addr, sector_end_addr;
373 u16 i;
374
375 /* Can't read flash registers if the register set isn't mapped. */
376 if (!hw->flash_address) {
377 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
378 return -E1000_ERR_CONFIG;
379 }
380
381 nvm->type = e1000_nvm_flash_sw;
382
383 gfpreg = er32flash(ICH_FLASH_GFPREG);
384
385 /*
386 * sector_X_addr is a "sector"-aligned address (4096 bytes)
387 * Add 1 to sector_end_addr since this sector is included in
388 * the overall size.
389 */
390 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
391 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
392
393 /* flash_base_addr is byte-aligned */
394 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
395
396 /*
397 * find total size of the NVM, then cut in half since the total
398 * size represents two separate NVM banks.
399 */
400 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
401 << FLASH_SECTOR_ADDR_SHIFT;
402 nvm->flash_bank_size /= 2;
403 /* Adjust to word count */
404 nvm->flash_bank_size /= sizeof(u16);
405
406 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
407
408 /* Clear shadow ram */
409 for (i = 0; i < nvm->word_size; i++) {
410 dev_spec->shadow_ram[i].modified = 0;
411 dev_spec->shadow_ram[i].value = 0xFFFF;
412 }
413
414 return 0;
415 }
416
417 /**
418 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
419 * @hw: pointer to the HW structure
420 *
421 * Initialize family-specific MAC parameters and function
422 * pointers.
423 **/
424 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
425 {
426 struct e1000_hw *hw = &adapter->hw;
427 struct e1000_mac_info *mac = &hw->mac;
428
429 /* Set media type function pointer */
430 hw->phy.media_type = e1000_media_type_copper;
431
432 /* Set mta register count */
433 mac->mta_reg_count = 32;
434 /* Set rar entry count */
435 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
436 if (mac->type == e1000_ich8lan)
437 mac->rar_entry_count--;
438 /* Set if manageability features are enabled. */
439 mac->arc_subsystem_valid = 1;
440
441 /* LED operations */
442 switch (mac->type) {
443 case e1000_ich8lan:
444 case e1000_ich9lan:
445 case e1000_ich10lan:
446 /* ID LED init */
447 mac->ops.id_led_init = e1000e_id_led_init;
448 /* setup LED */
449 mac->ops.setup_led = e1000e_setup_led_generic;
450 /* cleanup LED */
451 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
452 /* turn on/off LED */
453 mac->ops.led_on = e1000_led_on_ich8lan;
454 mac->ops.led_off = e1000_led_off_ich8lan;
455 break;
456 case e1000_pchlan:
457 /* ID LED init */
458 mac->ops.id_led_init = e1000_id_led_init_pchlan;
459 /* setup LED */
460 mac->ops.setup_led = e1000_setup_led_pchlan;
461 /* cleanup LED */
462 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
463 /* turn on/off LED */
464 mac->ops.led_on = e1000_led_on_pchlan;
465 mac->ops.led_off = e1000_led_off_pchlan;
466 break;
467 default:
468 break;
469 }
470
471 /* Enable PCS Lock-loss workaround for ICH8 */
472 if (mac->type == e1000_ich8lan)
473 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
474
475 return 0;
476 }
477
478 /**
479 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
480 * @hw: pointer to the HW structure
481 *
482 * Checks to see of the link status of the hardware has changed. If a
483 * change in link status has been detected, then we read the PHY registers
484 * to get the current speed/duplex if link exists.
485 **/
486 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
487 {
488 struct e1000_mac_info *mac = &hw->mac;
489 s32 ret_val;
490 bool link;
491
492 /*
493 * We only want to go out to the PHY registers to see if Auto-Neg
494 * has completed and/or if our link status has changed. The
495 * get_link_status flag is set upon receiving a Link Status
496 * Change or Rx Sequence Error interrupt.
497 */
498 if (!mac->get_link_status) {
499 ret_val = 0;
500 goto out;
501 }
502
503 /*
504 * First we want to see if the MII Status Register reports
505 * link. If so, then we want to get the current speed/duplex
506 * of the PHY.
507 */
508 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
509 if (ret_val)
510 goto out;
511
512 if (hw->mac.type == e1000_pchlan) {
513 ret_val = e1000_k1_gig_workaround_hv(hw, link);
514 if (ret_val)
515 goto out;
516 }
517
518 if (!link)
519 goto out; /* No link detected */
520
521 mac->get_link_status = false;
522
523 if (hw->phy.type == e1000_phy_82578) {
524 ret_val = e1000_link_stall_workaround_hv(hw);
525 if (ret_val)
526 goto out;
527 }
528
529 /*
530 * Check if there was DownShift, must be checked
531 * immediately after link-up
532 */
533 e1000e_check_downshift(hw);
534
535 /*
536 * If we are forcing speed/duplex, then we simply return since
537 * we have already determined whether we have link or not.
538 */
539 if (!mac->autoneg) {
540 ret_val = -E1000_ERR_CONFIG;
541 goto out;
542 }
543
544 /*
545 * Auto-Neg is enabled. Auto Speed Detection takes care
546 * of MAC speed/duplex configuration. So we only need to
547 * configure Collision Distance in the MAC.
548 */
549 e1000e_config_collision_dist(hw);
550
551 /*
552 * Configure Flow Control now that Auto-Neg has completed.
553 * First, we need to restore the desired flow control
554 * settings because we may have had to re-autoneg with a
555 * different link partner.
556 */
557 ret_val = e1000e_config_fc_after_link_up(hw);
558 if (ret_val)
559 hw_dbg(hw, "Error configuring flow control\n");
560
561 out:
562 return ret_val;
563 }
564
565 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
566 {
567 struct e1000_hw *hw = &adapter->hw;
568 s32 rc;
569
570 rc = e1000_init_mac_params_ich8lan(adapter);
571 if (rc)
572 return rc;
573
574 rc = e1000_init_nvm_params_ich8lan(hw);
575 if (rc)
576 return rc;
577
578 if (hw->mac.type == e1000_pchlan)
579 rc = e1000_init_phy_params_pchlan(hw);
580 else
581 rc = e1000_init_phy_params_ich8lan(hw);
582 if (rc)
583 return rc;
584
585 if (adapter->hw.phy.type == e1000_phy_ife) {
586 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
587 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
588 }
589
590 if ((adapter->hw.mac.type == e1000_ich8lan) &&
591 (adapter->hw.phy.type == e1000_phy_igp_3))
592 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
593
594 return 0;
595 }
596
597 static DEFINE_MUTEX(nvm_mutex);
598
599 /**
600 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
601 * @hw: pointer to the HW structure
602 *
603 * Acquires the mutex for performing NVM operations.
604 **/
605 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
606 {
607 mutex_lock(&nvm_mutex);
608
609 return 0;
610 }
611
612 /**
613 * e1000_release_nvm_ich8lan - Release NVM mutex
614 * @hw: pointer to the HW structure
615 *
616 * Releases the mutex used while performing NVM operations.
617 **/
618 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
619 {
620 mutex_unlock(&nvm_mutex);
621
622 return;
623 }
624
625 static DEFINE_MUTEX(swflag_mutex);
626
627 /**
628 * e1000_acquire_swflag_ich8lan - Acquire software control flag
629 * @hw: pointer to the HW structure
630 *
631 * Acquires the software control flag for performing PHY and select
632 * MAC CSR accesses.
633 **/
634 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
635 {
636 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
637 s32 ret_val = 0;
638
639 might_sleep();
640
641 mutex_lock(&swflag_mutex);
642
643 while (timeout) {
644 extcnf_ctrl = er32(EXTCNF_CTRL);
645 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
646 break;
647
648 mdelay(1);
649 timeout--;
650 }
651
652 if (!timeout) {
653 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
654 ret_val = -E1000_ERR_CONFIG;
655 goto out;
656 }
657
658 timeout = SW_FLAG_TIMEOUT;
659
660 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
661 ew32(EXTCNF_CTRL, extcnf_ctrl);
662
663 while (timeout) {
664 extcnf_ctrl = er32(EXTCNF_CTRL);
665 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
666 break;
667
668 mdelay(1);
669 timeout--;
670 }
671
672 if (!timeout) {
673 hw_dbg(hw, "Failed to acquire the semaphore.\n");
674 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
675 ew32(EXTCNF_CTRL, extcnf_ctrl);
676 ret_val = -E1000_ERR_CONFIG;
677 goto out;
678 }
679
680 out:
681 if (ret_val)
682 mutex_unlock(&swflag_mutex);
683
684 return ret_val;
685 }
686
687 /**
688 * e1000_release_swflag_ich8lan - Release software control flag
689 * @hw: pointer to the HW structure
690 *
691 * Releases the software control flag for performing PHY and select
692 * MAC CSR accesses.
693 **/
694 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
695 {
696 u32 extcnf_ctrl;
697
698 extcnf_ctrl = er32(EXTCNF_CTRL);
699 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
700 ew32(EXTCNF_CTRL, extcnf_ctrl);
701
702 mutex_unlock(&swflag_mutex);
703
704 return;
705 }
706
707 /**
708 * e1000_check_mng_mode_ich8lan - Checks management mode
709 * @hw: pointer to the HW structure
710 *
711 * This checks if the adapter has manageability enabled.
712 * This is a function pointer entry point only called by read/write
713 * routines for the PHY and NVM parts.
714 **/
715 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
716 {
717 u32 fwsm = er32(FWSM);
718
719 return (fwsm & E1000_FWSM_MODE_MASK) ==
720 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
721 }
722
723 /**
724 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
725 * @hw: pointer to the HW structure
726 *
727 * Checks if firmware is blocking the reset of the PHY.
728 * This is a function pointer entry point only called by
729 * reset routines.
730 **/
731 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
732 {
733 u32 fwsm;
734
735 fwsm = er32(FWSM);
736
737 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
738 }
739
740 /**
741 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
742 * @hw: pointer to the HW structure
743 *
744 * Forces the speed and duplex settings of the PHY.
745 * This is a function pointer entry point only called by
746 * PHY setup routines.
747 **/
748 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
749 {
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val;
752 u16 data;
753 bool link;
754
755 if (phy->type != e1000_phy_ife) {
756 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
757 return ret_val;
758 }
759
760 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
761 if (ret_val)
762 return ret_val;
763
764 e1000e_phy_force_speed_duplex_setup(hw, &data);
765
766 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
767 if (ret_val)
768 return ret_val;
769
770 /* Disable MDI-X support for 10/100 */
771 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
772 if (ret_val)
773 return ret_val;
774
775 data &= ~IFE_PMC_AUTO_MDIX;
776 data &= ~IFE_PMC_FORCE_MDIX;
777
778 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
779 if (ret_val)
780 return ret_val;
781
782 hw_dbg(hw, "IFE PMC: %X\n", data);
783
784 udelay(1);
785
786 if (phy->autoneg_wait_to_complete) {
787 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
788
789 ret_val = e1000e_phy_has_link_generic(hw,
790 PHY_FORCE_LIMIT,
791 100000,
792 &link);
793 if (ret_val)
794 return ret_val;
795
796 if (!link)
797 hw_dbg(hw, "Link taking longer than expected.\n");
798
799 /* Try once more */
800 ret_val = e1000e_phy_has_link_generic(hw,
801 PHY_FORCE_LIMIT,
802 100000,
803 &link);
804 if (ret_val)
805 return ret_val;
806 }
807
808 return 0;
809 }
810
811 /**
812 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
813 * @hw: pointer to the HW structure
814 *
815 * SW should configure the LCD from the NVM extended configuration region
816 * as a workaround for certain parts.
817 **/
818 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
819 {
820 struct e1000_phy_info *phy = &hw->phy;
821 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
822 s32 ret_val;
823 u16 word_addr, reg_data, reg_addr, phy_page = 0;
824
825 ret_val = hw->phy.ops.acquire_phy(hw);
826 if (ret_val)
827 return ret_val;
828
829 /*
830 * Initialize the PHY from the NVM on ICH platforms. This
831 * is needed due to an issue where the NVM configuration is
832 * not properly autoloaded after power transitions.
833 * Therefore, after each PHY reset, we will load the
834 * configuration data out of the NVM manually.
835 */
836 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
837 (hw->mac.type == e1000_pchlan)) {
838 struct e1000_adapter *adapter = hw->adapter;
839
840 /* Check if SW needs to configure the PHY */
841 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
842 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
843 (hw->mac.type == e1000_pchlan))
844 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
845 else
846 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
847
848 data = er32(FEXTNVM);
849 if (!(data & sw_cfg_mask))
850 goto out;
851
852 /* Wait for basic configuration completes before proceeding */
853 e1000_lan_init_done_ich8lan(hw);
854
855 /*
856 * Make sure HW does not configure LCD from PHY
857 * extended configuration before SW configuration
858 */
859 data = er32(EXTCNF_CTRL);
860 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
861 goto out;
862
863 cnf_size = er32(EXTCNF_SIZE);
864 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
865 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
866 if (!cnf_size)
867 goto out;
868
869 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
870 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
871
872 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
873 (hw->mac.type == e1000_pchlan)) {
874 /*
875 * HW configures the SMBus address and LEDs when the
876 * OEM and LCD Write Enable bits are set in the NVM.
877 * When both NVM bits are cleared, SW will configure
878 * them instead.
879 */
880 data = er32(STRAP);
881 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
882 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
883 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
884 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
885 reg_data);
886 if (ret_val)
887 goto out;
888
889 data = er32(LEDCTL);
890 ret_val = e1000_write_phy_reg_hv_locked(hw,
891 HV_LED_CONFIG,
892 (u16)data);
893 if (ret_val)
894 goto out;
895 }
896 /* Configure LCD from extended configuration region. */
897
898 /* cnf_base_addr is in DWORD */
899 word_addr = (u16)(cnf_base_addr << 1);
900
901 for (i = 0; i < cnf_size; i++) {
902 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
903 &reg_data);
904 if (ret_val)
905 goto out;
906
907 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
908 1, &reg_addr);
909 if (ret_val)
910 goto out;
911
912 /* Save off the PHY page for future writes. */
913 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
914 phy_page = reg_data;
915 continue;
916 }
917
918 reg_addr &= PHY_REG_MASK;
919 reg_addr |= phy_page;
920
921 ret_val = phy->ops.write_phy_reg_locked(hw,
922 (u32)reg_addr,
923 reg_data);
924 if (ret_val)
925 goto out;
926 }
927 }
928
929 out:
930 hw->phy.ops.release_phy(hw);
931 return ret_val;
932 }
933
934 /**
935 * e1000_k1_gig_workaround_hv - K1 Si workaround
936 * @hw: pointer to the HW structure
937 * @link: link up bool flag
938 *
939 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
940 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
941 * If link is down, the function will restore the default K1 setting located
942 * in the NVM.
943 **/
944 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
945 {
946 s32 ret_val = 0;
947 u16 status_reg = 0;
948 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
949
950 if (hw->mac.type != e1000_pchlan)
951 goto out;
952
953 /* Wrap the whole flow with the sw flag */
954 ret_val = hw->phy.ops.acquire_phy(hw);
955 if (ret_val)
956 goto out;
957
958 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
959 if (link) {
960 if (hw->phy.type == e1000_phy_82578) {
961 ret_val = hw->phy.ops.read_phy_reg_locked(hw,
962 BM_CS_STATUS,
963 &status_reg);
964 if (ret_val)
965 goto release;
966
967 status_reg &= BM_CS_STATUS_LINK_UP |
968 BM_CS_STATUS_RESOLVED |
969 BM_CS_STATUS_SPEED_MASK;
970
971 if (status_reg == (BM_CS_STATUS_LINK_UP |
972 BM_CS_STATUS_RESOLVED |
973 BM_CS_STATUS_SPEED_1000))
974 k1_enable = false;
975 }
976
977 if (hw->phy.type == e1000_phy_82577) {
978 ret_val = hw->phy.ops.read_phy_reg_locked(hw,
979 HV_M_STATUS,
980 &status_reg);
981 if (ret_val)
982 goto release;
983
984 status_reg &= HV_M_STATUS_LINK_UP |
985 HV_M_STATUS_AUTONEG_COMPLETE |
986 HV_M_STATUS_SPEED_MASK;
987
988 if (status_reg == (HV_M_STATUS_LINK_UP |
989 HV_M_STATUS_AUTONEG_COMPLETE |
990 HV_M_STATUS_SPEED_1000))
991 k1_enable = false;
992 }
993
994 /* Link stall fix for link up */
995 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
996 0x0100);
997 if (ret_val)
998 goto release;
999
1000 } else {
1001 /* Link stall fix for link down */
1002 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
1003 0x4100);
1004 if (ret_val)
1005 goto release;
1006 }
1007
1008 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1009
1010 release:
1011 hw->phy.ops.release_phy(hw);
1012 out:
1013 return ret_val;
1014 }
1015
1016 /**
1017 * e1000_configure_k1_ich8lan - Configure K1 power state
1018 * @hw: pointer to the HW structure
1019 * @enable: K1 state to configure
1020 *
1021 * Configure the K1 power state based on the provided parameter.
1022 * Assumes semaphore already acquired.
1023 *
1024 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1025 **/
1026 static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1027 {
1028 s32 ret_val = 0;
1029 u32 ctrl_reg = 0;
1030 u32 ctrl_ext = 0;
1031 u32 reg = 0;
1032 u16 kmrn_reg = 0;
1033
1034 ret_val = e1000e_read_kmrn_reg_locked(hw,
1035 E1000_KMRNCTRLSTA_K1_CONFIG,
1036 &kmrn_reg);
1037 if (ret_val)
1038 goto out;
1039
1040 if (k1_enable)
1041 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1042 else
1043 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1044
1045 ret_val = e1000e_write_kmrn_reg_locked(hw,
1046 E1000_KMRNCTRLSTA_K1_CONFIG,
1047 kmrn_reg);
1048 if (ret_val)
1049 goto out;
1050
1051 udelay(20);
1052 ctrl_ext = er32(CTRL_EXT);
1053 ctrl_reg = er32(CTRL);
1054
1055 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1056 reg |= E1000_CTRL_FRCSPD;
1057 ew32(CTRL, reg);
1058
1059 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1060 udelay(20);
1061 ew32(CTRL, ctrl_reg);
1062 ew32(CTRL_EXT, ctrl_ext);
1063 udelay(20);
1064
1065 out:
1066 return ret_val;
1067 }
1068
1069 /**
1070 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1071 * @hw: pointer to the HW structure
1072 * @d0_state: boolean if entering d0 or d3 device state
1073 *
1074 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1075 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1076 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1077 **/
1078 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1079 {
1080 s32 ret_val = 0;
1081 u32 mac_reg;
1082 u16 oem_reg;
1083
1084 if (hw->mac.type != e1000_pchlan)
1085 return ret_val;
1086
1087 ret_val = hw->phy.ops.acquire_phy(hw);
1088 if (ret_val)
1089 return ret_val;
1090
1091 mac_reg = er32(EXTCNF_CTRL);
1092 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1093 goto out;
1094
1095 mac_reg = er32(FEXTNVM);
1096 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1097 goto out;
1098
1099 mac_reg = er32(PHY_CTRL);
1100
1101 ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1102 if (ret_val)
1103 goto out;
1104
1105 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1106
1107 if (d0_state) {
1108 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1109 oem_reg |= HV_OEM_BITS_GBE_DIS;
1110
1111 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1112 oem_reg |= HV_OEM_BITS_LPLU;
1113 } else {
1114 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1115 oem_reg |= HV_OEM_BITS_GBE_DIS;
1116
1117 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1118 oem_reg |= HV_OEM_BITS_LPLU;
1119 }
1120 /* Restart auto-neg to activate the bits */
1121 if (!e1000_check_reset_block(hw))
1122 oem_reg |= HV_OEM_BITS_RESTART_AN;
1123 ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
1124
1125 out:
1126 hw->phy.ops.release_phy(hw);
1127
1128 return ret_val;
1129 }
1130
1131
1132 /**
1133 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1134 * done after every PHY reset.
1135 **/
1136 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1137 {
1138 s32 ret_val = 0;
1139
1140 if (hw->mac.type != e1000_pchlan)
1141 return ret_val;
1142
1143 if (((hw->phy.type == e1000_phy_82577) &&
1144 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1145 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1146 /* Disable generation of early preamble */
1147 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1148 if (ret_val)
1149 return ret_val;
1150
1151 /* Preamble tuning for SSC */
1152 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1153 if (ret_val)
1154 return ret_val;
1155 }
1156
1157 if (hw->phy.type == e1000_phy_82578) {
1158 /*
1159 * Return registers to default by doing a soft reset then
1160 * writing 0x3140 to the control register.
1161 */
1162 if (hw->phy.revision < 2) {
1163 e1000e_phy_sw_reset(hw);
1164 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1165 }
1166 }
1167
1168 /* Select page 0 */
1169 ret_val = hw->phy.ops.acquire_phy(hw);
1170 if (ret_val)
1171 return ret_val;
1172
1173 hw->phy.addr = 1;
1174 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1175 if (ret_val)
1176 goto out;
1177 hw->phy.ops.release_phy(hw);
1178
1179 /*
1180 * Configure the K1 Si workaround during phy reset assuming there is
1181 * link so that it disables K1 if link is in 1Gbps.
1182 */
1183 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1184
1185 out:
1186 return ret_val;
1187 }
1188
1189 /**
1190 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1191 * @hw: pointer to the HW structure
1192 *
1193 * Check the appropriate indication the MAC has finished configuring the
1194 * PHY after a software reset.
1195 **/
1196 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1197 {
1198 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1199
1200 /* Wait for basic configuration completes before proceeding */
1201 do {
1202 data = er32(STATUS);
1203 data &= E1000_STATUS_LAN_INIT_DONE;
1204 udelay(100);
1205 } while ((!data) && --loop);
1206
1207 /*
1208 * If basic configuration is incomplete before the above loop
1209 * count reaches 0, loading the configuration from NVM will
1210 * leave the PHY in a bad state possibly resulting in no link.
1211 */
1212 if (loop == 0)
1213 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
1214
1215 /* Clear the Init Done bit for the next init event */
1216 data = er32(STATUS);
1217 data &= ~E1000_STATUS_LAN_INIT_DONE;
1218 ew32(STATUS, data);
1219 }
1220
1221 /**
1222 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1223 * @hw: pointer to the HW structure
1224 *
1225 * Resets the PHY
1226 * This is a function pointer entry point called by drivers
1227 * or other shared routines.
1228 **/
1229 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1230 {
1231 s32 ret_val = 0;
1232 u16 reg;
1233
1234 ret_val = e1000e_phy_hw_reset_generic(hw);
1235 if (ret_val)
1236 return ret_val;
1237
1238 /* Allow time for h/w to get to a quiescent state after reset */
1239 mdelay(10);
1240
1241 if (hw->mac.type == e1000_pchlan) {
1242 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1243 if (ret_val)
1244 return ret_val;
1245 }
1246
1247 /* Dummy read to clear the phy wakeup bit after lcd reset */
1248 if (hw->mac.type == e1000_pchlan)
1249 e1e_rphy(hw, BM_WUC, &reg);
1250
1251 /* Configure the LCD with the extended configuration region in NVM */
1252 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1253 if (ret_val)
1254 goto out;
1255
1256 /* Configure the LCD with the OEM bits in NVM */
1257 if (hw->mac.type == e1000_pchlan)
1258 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1259
1260 out:
1261 return 0;
1262 }
1263
1264 /**
1265 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1266 * @hw: pointer to the HW structure
1267 *
1268 * Populates "phy" structure with various feature states.
1269 * This function is only called by other family-specific
1270 * routines.
1271 **/
1272 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1273 {
1274 struct e1000_phy_info *phy = &hw->phy;
1275 s32 ret_val;
1276 u16 data;
1277 bool link;
1278
1279 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1280 if (ret_val)
1281 return ret_val;
1282
1283 if (!link) {
1284 hw_dbg(hw, "Phy info is only valid if link is up\n");
1285 return -E1000_ERR_CONFIG;
1286 }
1287
1288 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1289 if (ret_val)
1290 return ret_val;
1291 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1292
1293 if (phy->polarity_correction) {
1294 ret_val = phy->ops.check_polarity(hw);
1295 if (ret_val)
1296 return ret_val;
1297 } else {
1298 /* Polarity is forced */
1299 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1300 ? e1000_rev_polarity_reversed
1301 : e1000_rev_polarity_normal;
1302 }
1303
1304 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1305 if (ret_val)
1306 return ret_val;
1307
1308 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1309
1310 /* The following parameters are undefined for 10/100 operation. */
1311 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1312 phy->local_rx = e1000_1000t_rx_status_undefined;
1313 phy->remote_rx = e1000_1000t_rx_status_undefined;
1314
1315 return 0;
1316 }
1317
1318 /**
1319 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1320 * @hw: pointer to the HW structure
1321 *
1322 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1323 * This is a function pointer entry point called by drivers
1324 * or other shared routines.
1325 **/
1326 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1327 {
1328 switch (hw->phy.type) {
1329 case e1000_phy_ife:
1330 return e1000_get_phy_info_ife_ich8lan(hw);
1331 break;
1332 case e1000_phy_igp_3:
1333 case e1000_phy_bm:
1334 case e1000_phy_82578:
1335 case e1000_phy_82577:
1336 return e1000e_get_phy_info_igp(hw);
1337 break;
1338 default:
1339 break;
1340 }
1341
1342 return -E1000_ERR_PHY_TYPE;
1343 }
1344
1345 /**
1346 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1347 * @hw: pointer to the HW structure
1348 *
1349 * Polarity is determined on the polarity reversal feature being enabled.
1350 * This function is only called by other family-specific
1351 * routines.
1352 **/
1353 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1354 {
1355 struct e1000_phy_info *phy = &hw->phy;
1356 s32 ret_val;
1357 u16 phy_data, offset, mask;
1358
1359 /*
1360 * Polarity is determined based on the reversal feature being enabled.
1361 */
1362 if (phy->polarity_correction) {
1363 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1364 mask = IFE_PESC_POLARITY_REVERSED;
1365 } else {
1366 offset = IFE_PHY_SPECIAL_CONTROL;
1367 mask = IFE_PSC_FORCE_POLARITY;
1368 }
1369
1370 ret_val = e1e_rphy(hw, offset, &phy_data);
1371
1372 if (!ret_val)
1373 phy->cable_polarity = (phy_data & mask)
1374 ? e1000_rev_polarity_reversed
1375 : e1000_rev_polarity_normal;
1376
1377 return ret_val;
1378 }
1379
1380 /**
1381 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1382 * @hw: pointer to the HW structure
1383 * @active: true to enable LPLU, false to disable
1384 *
1385 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1386 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1387 * the phy speed. This function will manually set the LPLU bit and restart
1388 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1389 * since it configures the same bit.
1390 **/
1391 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1392 {
1393 s32 ret_val = 0;
1394 u16 oem_reg;
1395
1396 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1397 if (ret_val)
1398 goto out;
1399
1400 if (active)
1401 oem_reg |= HV_OEM_BITS_LPLU;
1402 else
1403 oem_reg &= ~HV_OEM_BITS_LPLU;
1404
1405 oem_reg |= HV_OEM_BITS_RESTART_AN;
1406 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1407
1408 out:
1409 return ret_val;
1410 }
1411
1412 /**
1413 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1414 * @hw: pointer to the HW structure
1415 * @active: TRUE to enable LPLU, FALSE to disable
1416 *
1417 * Sets the LPLU D0 state according to the active flag. When
1418 * activating LPLU this function also disables smart speed
1419 * and vice versa. LPLU will not be activated unless the
1420 * device autonegotiation advertisement meets standards of
1421 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1422 * This is a function pointer entry point only called by
1423 * PHY setup routines.
1424 **/
1425 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1426 {
1427 struct e1000_phy_info *phy = &hw->phy;
1428 u32 phy_ctrl;
1429 s32 ret_val = 0;
1430 u16 data;
1431
1432 if (phy->type == e1000_phy_ife)
1433 return ret_val;
1434
1435 phy_ctrl = er32(PHY_CTRL);
1436
1437 if (active) {
1438 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1439 ew32(PHY_CTRL, phy_ctrl);
1440
1441 if (phy->type != e1000_phy_igp_3)
1442 return 0;
1443
1444 /*
1445 * Call gig speed drop workaround on LPLU before accessing
1446 * any PHY registers
1447 */
1448 if (hw->mac.type == e1000_ich8lan)
1449 e1000e_gig_downshift_workaround_ich8lan(hw);
1450
1451 /* When LPLU is enabled, we should disable SmartSpeed */
1452 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1453 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1454 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1455 if (ret_val)
1456 return ret_val;
1457 } else {
1458 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1459 ew32(PHY_CTRL, phy_ctrl);
1460
1461 if (phy->type != e1000_phy_igp_3)
1462 return 0;
1463
1464 /*
1465 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1466 * during Dx states where the power conservation is most
1467 * important. During driver activity we should enable
1468 * SmartSpeed, so performance is maintained.
1469 */
1470 if (phy->smart_speed == e1000_smart_speed_on) {
1471 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1472 &data);
1473 if (ret_val)
1474 return ret_val;
1475
1476 data |= IGP01E1000_PSCFR_SMART_SPEED;
1477 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1478 data);
1479 if (ret_val)
1480 return ret_val;
1481 } else if (phy->smart_speed == e1000_smart_speed_off) {
1482 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1483 &data);
1484 if (ret_val)
1485 return ret_val;
1486
1487 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1488 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1489 data);
1490 if (ret_val)
1491 return ret_val;
1492 }
1493 }
1494
1495 return 0;
1496 }
1497
1498 /**
1499 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1500 * @hw: pointer to the HW structure
1501 * @active: TRUE to enable LPLU, FALSE to disable
1502 *
1503 * Sets the LPLU D3 state according to the active flag. When
1504 * activating LPLU this function also disables smart speed
1505 * and vice versa. LPLU will not be activated unless the
1506 * device autonegotiation advertisement meets standards of
1507 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1508 * This is a function pointer entry point only called by
1509 * PHY setup routines.
1510 **/
1511 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1512 {
1513 struct e1000_phy_info *phy = &hw->phy;
1514 u32 phy_ctrl;
1515 s32 ret_val;
1516 u16 data;
1517
1518 phy_ctrl = er32(PHY_CTRL);
1519
1520 if (!active) {
1521 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1522 ew32(PHY_CTRL, phy_ctrl);
1523
1524 if (phy->type != e1000_phy_igp_3)
1525 return 0;
1526
1527 /*
1528 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1529 * during Dx states where the power conservation is most
1530 * important. During driver activity we should enable
1531 * SmartSpeed, so performance is maintained.
1532 */
1533 if (phy->smart_speed == e1000_smart_speed_on) {
1534 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1535 &data);
1536 if (ret_val)
1537 return ret_val;
1538
1539 data |= IGP01E1000_PSCFR_SMART_SPEED;
1540 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1541 data);
1542 if (ret_val)
1543 return ret_val;
1544 } else if (phy->smart_speed == e1000_smart_speed_off) {
1545 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1546 &data);
1547 if (ret_val)
1548 return ret_val;
1549
1550 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1551 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1552 data);
1553 if (ret_val)
1554 return ret_val;
1555 }
1556 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1557 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1558 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1559 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1560 ew32(PHY_CTRL, phy_ctrl);
1561
1562 if (phy->type != e1000_phy_igp_3)
1563 return 0;
1564
1565 /*
1566 * Call gig speed drop workaround on LPLU before accessing
1567 * any PHY registers
1568 */
1569 if (hw->mac.type == e1000_ich8lan)
1570 e1000e_gig_downshift_workaround_ich8lan(hw);
1571
1572 /* When LPLU is enabled, we should disable SmartSpeed */
1573 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1574 if (ret_val)
1575 return ret_val;
1576
1577 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1578 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1579 }
1580
1581 return 0;
1582 }
1583
1584 /**
1585 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1586 * @hw: pointer to the HW structure
1587 * @bank: pointer to the variable that returns the active bank
1588 *
1589 * Reads signature byte from the NVM using the flash access registers.
1590 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1591 **/
1592 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1593 {
1594 u32 eecd;
1595 struct e1000_nvm_info *nvm = &hw->nvm;
1596 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1597 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1598 u8 sig_byte = 0;
1599 s32 ret_val = 0;
1600
1601 switch (hw->mac.type) {
1602 case e1000_ich8lan:
1603 case e1000_ich9lan:
1604 eecd = er32(EECD);
1605 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1606 E1000_EECD_SEC1VAL_VALID_MASK) {
1607 if (eecd & E1000_EECD_SEC1VAL)
1608 *bank = 1;
1609 else
1610 *bank = 0;
1611
1612 return 0;
1613 }
1614 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1615 "reading flash signature\n");
1616 /* fall-thru */
1617 default:
1618 /* set bank to 0 in case flash read fails */
1619 *bank = 0;
1620
1621 /* Check bank 0 */
1622 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1623 &sig_byte);
1624 if (ret_val)
1625 return ret_val;
1626 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1627 E1000_ICH_NVM_SIG_VALUE) {
1628 *bank = 0;
1629 return 0;
1630 }
1631
1632 /* Check bank 1 */
1633 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1634 bank1_offset,
1635 &sig_byte);
1636 if (ret_val)
1637 return ret_val;
1638 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1639 E1000_ICH_NVM_SIG_VALUE) {
1640 *bank = 1;
1641 return 0;
1642 }
1643
1644 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1645 return -E1000_ERR_NVM;
1646 }
1647
1648 return 0;
1649 }
1650
1651 /**
1652 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1653 * @hw: pointer to the HW structure
1654 * @offset: The offset (in bytes) of the word(s) to read.
1655 * @words: Size of data to read in words
1656 * @data: Pointer to the word(s) to read at offset.
1657 *
1658 * Reads a word(s) from the NVM using the flash access registers.
1659 **/
1660 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1661 u16 *data)
1662 {
1663 struct e1000_nvm_info *nvm = &hw->nvm;
1664 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1665 u32 act_offset;
1666 s32 ret_val = 0;
1667 u32 bank = 0;
1668 u16 i, word;
1669
1670 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1671 (words == 0)) {
1672 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1673 ret_val = -E1000_ERR_NVM;
1674 goto out;
1675 }
1676
1677 nvm->ops.acquire_nvm(hw);
1678
1679 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1680 if (ret_val) {
1681 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1682 bank = 0;
1683 }
1684
1685 act_offset = (bank) ? nvm->flash_bank_size : 0;
1686 act_offset += offset;
1687
1688 ret_val = 0;
1689 for (i = 0; i < words; i++) {
1690 if ((dev_spec->shadow_ram) &&
1691 (dev_spec->shadow_ram[offset+i].modified)) {
1692 data[i] = dev_spec->shadow_ram[offset+i].value;
1693 } else {
1694 ret_val = e1000_read_flash_word_ich8lan(hw,
1695 act_offset + i,
1696 &word);
1697 if (ret_val)
1698 break;
1699 data[i] = word;
1700 }
1701 }
1702
1703 nvm->ops.release_nvm(hw);
1704
1705 out:
1706 if (ret_val)
1707 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1708
1709 return ret_val;
1710 }
1711
1712 /**
1713 * e1000_flash_cycle_init_ich8lan - Initialize flash
1714 * @hw: pointer to the HW structure
1715 *
1716 * This function does initial flash setup so that a new read/write/erase cycle
1717 * can be started.
1718 **/
1719 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1720 {
1721 union ich8_hws_flash_status hsfsts;
1722 s32 ret_val = -E1000_ERR_NVM;
1723 s32 i = 0;
1724
1725 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1726
1727 /* Check if the flash descriptor is valid */
1728 if (hsfsts.hsf_status.fldesvalid == 0) {
1729 hw_dbg(hw, "Flash descriptor invalid. "
1730 "SW Sequencing must be used.");
1731 return -E1000_ERR_NVM;
1732 }
1733
1734 /* Clear FCERR and DAEL in hw status by writing 1 */
1735 hsfsts.hsf_status.flcerr = 1;
1736 hsfsts.hsf_status.dael = 1;
1737
1738 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1739
1740 /*
1741 * Either we should have a hardware SPI cycle in progress
1742 * bit to check against, in order to start a new cycle or
1743 * FDONE bit should be changed in the hardware so that it
1744 * is 1 after hardware reset, which can then be used as an
1745 * indication whether a cycle is in progress or has been
1746 * completed.
1747 */
1748
1749 if (hsfsts.hsf_status.flcinprog == 0) {
1750 /*
1751 * There is no cycle running at present,
1752 * so we can start a cycle
1753 * Begin by setting Flash Cycle Done.
1754 */
1755 hsfsts.hsf_status.flcdone = 1;
1756 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1757 ret_val = 0;
1758 } else {
1759 /*
1760 * otherwise poll for sometime so the current
1761 * cycle has a chance to end before giving up.
1762 */
1763 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1764 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1765 if (hsfsts.hsf_status.flcinprog == 0) {
1766 ret_val = 0;
1767 break;
1768 }
1769 udelay(1);
1770 }
1771 if (ret_val == 0) {
1772 /*
1773 * Successful in waiting for previous cycle to timeout,
1774 * now set the Flash Cycle Done.
1775 */
1776 hsfsts.hsf_status.flcdone = 1;
1777 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1778 } else {
1779 hw_dbg(hw, "Flash controller busy, cannot get access");
1780 }
1781 }
1782
1783 return ret_val;
1784 }
1785
1786 /**
1787 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1788 * @hw: pointer to the HW structure
1789 * @timeout: maximum time to wait for completion
1790 *
1791 * This function starts a flash cycle and waits for its completion.
1792 **/
1793 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1794 {
1795 union ich8_hws_flash_ctrl hsflctl;
1796 union ich8_hws_flash_status hsfsts;
1797 s32 ret_val = -E1000_ERR_NVM;
1798 u32 i = 0;
1799
1800 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1801 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1802 hsflctl.hsf_ctrl.flcgo = 1;
1803 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1804
1805 /* wait till FDONE bit is set to 1 */
1806 do {
1807 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1808 if (hsfsts.hsf_status.flcdone == 1)
1809 break;
1810 udelay(1);
1811 } while (i++ < timeout);
1812
1813 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1814 return 0;
1815
1816 return ret_val;
1817 }
1818
1819 /**
1820 * e1000_read_flash_word_ich8lan - Read word from flash
1821 * @hw: pointer to the HW structure
1822 * @offset: offset to data location
1823 * @data: pointer to the location for storing the data
1824 *
1825 * Reads the flash word at offset into data. Offset is converted
1826 * to bytes before read.
1827 **/
1828 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1829 u16 *data)
1830 {
1831 /* Must convert offset into bytes. */
1832 offset <<= 1;
1833
1834 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1835 }
1836
1837 /**
1838 * e1000_read_flash_byte_ich8lan - Read byte from flash
1839 * @hw: pointer to the HW structure
1840 * @offset: The offset of the byte to read.
1841 * @data: Pointer to a byte to store the value read.
1842 *
1843 * Reads a single byte from the NVM using the flash access registers.
1844 **/
1845 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1846 u8 *data)
1847 {
1848 s32 ret_val;
1849 u16 word = 0;
1850
1851 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1852 if (ret_val)
1853 return ret_val;
1854
1855 *data = (u8)word;
1856
1857 return 0;
1858 }
1859
1860 /**
1861 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1862 * @hw: pointer to the HW structure
1863 * @offset: The offset (in bytes) of the byte or word to read.
1864 * @size: Size of data to read, 1=byte 2=word
1865 * @data: Pointer to the word to store the value read.
1866 *
1867 * Reads a byte or word from the NVM using the flash access registers.
1868 **/
1869 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1870 u8 size, u16 *data)
1871 {
1872 union ich8_hws_flash_status hsfsts;
1873 union ich8_hws_flash_ctrl hsflctl;
1874 u32 flash_linear_addr;
1875 u32 flash_data = 0;
1876 s32 ret_val = -E1000_ERR_NVM;
1877 u8 count = 0;
1878
1879 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1880 return -E1000_ERR_NVM;
1881
1882 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1883 hw->nvm.flash_base_addr;
1884
1885 do {
1886 udelay(1);
1887 /* Steps */
1888 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1889 if (ret_val != 0)
1890 break;
1891
1892 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1893 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1894 hsflctl.hsf_ctrl.fldbcount = size - 1;
1895 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1896 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1897
1898 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1899
1900 ret_val = e1000_flash_cycle_ich8lan(hw,
1901 ICH_FLASH_READ_COMMAND_TIMEOUT);
1902
1903 /*
1904 * Check if FCERR is set to 1, if set to 1, clear it
1905 * and try the whole sequence a few more times, else
1906 * read in (shift in) the Flash Data0, the order is
1907 * least significant byte first msb to lsb
1908 */
1909 if (ret_val == 0) {
1910 flash_data = er32flash(ICH_FLASH_FDATA0);
1911 if (size == 1) {
1912 *data = (u8)(flash_data & 0x000000FF);
1913 } else if (size == 2) {
1914 *data = (u16)(flash_data & 0x0000FFFF);
1915 }
1916 break;
1917 } else {
1918 /*
1919 * If we've gotten here, then things are probably
1920 * completely hosed, but if the error condition is
1921 * detected, it won't hurt to give it another try...
1922 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1923 */
1924 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1925 if (hsfsts.hsf_status.flcerr == 1) {
1926 /* Repeat for some time before giving up. */
1927 continue;
1928 } else if (hsfsts.hsf_status.flcdone == 0) {
1929 hw_dbg(hw, "Timeout error - flash cycle "
1930 "did not complete.");
1931 break;
1932 }
1933 }
1934 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1935
1936 return ret_val;
1937 }
1938
1939 /**
1940 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1941 * @hw: pointer to the HW structure
1942 * @offset: The offset (in bytes) of the word(s) to write.
1943 * @words: Size of data to write in words
1944 * @data: Pointer to the word(s) to write at offset.
1945 *
1946 * Writes a byte or word to the NVM using the flash access registers.
1947 **/
1948 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1949 u16 *data)
1950 {
1951 struct e1000_nvm_info *nvm = &hw->nvm;
1952 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1953 u16 i;
1954
1955 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1956 (words == 0)) {
1957 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1958 return -E1000_ERR_NVM;
1959 }
1960
1961 nvm->ops.acquire_nvm(hw);
1962
1963 for (i = 0; i < words; i++) {
1964 dev_spec->shadow_ram[offset+i].modified = 1;
1965 dev_spec->shadow_ram[offset+i].value = data[i];
1966 }
1967
1968 nvm->ops.release_nvm(hw);
1969
1970 return 0;
1971 }
1972
1973 /**
1974 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1975 * @hw: pointer to the HW structure
1976 *
1977 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1978 * which writes the checksum to the shadow ram. The changes in the shadow
1979 * ram are then committed to the EEPROM by processing each bank at a time
1980 * checking for the modified bit and writing only the pending changes.
1981 * After a successful commit, the shadow ram is cleared and is ready for
1982 * future writes.
1983 **/
1984 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1985 {
1986 struct e1000_nvm_info *nvm = &hw->nvm;
1987 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1988 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1989 s32 ret_val;
1990 u16 data;
1991
1992 ret_val = e1000e_update_nvm_checksum_generic(hw);
1993 if (ret_val)
1994 goto out;
1995
1996 if (nvm->type != e1000_nvm_flash_sw)
1997 goto out;
1998
1999 nvm->ops.acquire_nvm(hw);
2000
2001 /*
2002 * We're writing to the opposite bank so if we're on bank 1,
2003 * write to bank 0 etc. We also need to erase the segment that
2004 * is going to be written
2005 */
2006 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2007 if (ret_val) {
2008 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
2009 bank = 0;
2010 }
2011
2012 if (bank == 0) {
2013 new_bank_offset = nvm->flash_bank_size;
2014 old_bank_offset = 0;
2015 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2016 if (ret_val) {
2017 nvm->ops.release_nvm(hw);
2018 goto out;
2019 }
2020 } else {
2021 old_bank_offset = nvm->flash_bank_size;
2022 new_bank_offset = 0;
2023 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2024 if (ret_val) {
2025 nvm->ops.release_nvm(hw);
2026 goto out;
2027 }
2028 }
2029
2030 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2031 /*
2032 * Determine whether to write the value stored
2033 * in the other NVM bank or a modified value stored
2034 * in the shadow RAM
2035 */
2036 if (dev_spec->shadow_ram[i].modified) {
2037 data = dev_spec->shadow_ram[i].value;
2038 } else {
2039 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2040 old_bank_offset,
2041 &data);
2042 if (ret_val)
2043 break;
2044 }
2045
2046 /*
2047 * If the word is 0x13, then make sure the signature bits
2048 * (15:14) are 11b until the commit has completed.
2049 * This will allow us to write 10b which indicates the
2050 * signature is valid. We want to do this after the write
2051 * has completed so that we don't mark the segment valid
2052 * while the write is still in progress
2053 */
2054 if (i == E1000_ICH_NVM_SIG_WORD)
2055 data |= E1000_ICH_NVM_SIG_MASK;
2056
2057 /* Convert offset to bytes. */
2058 act_offset = (i + new_bank_offset) << 1;
2059
2060 udelay(100);
2061 /* Write the bytes to the new bank. */
2062 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2063 act_offset,
2064 (u8)data);
2065 if (ret_val)
2066 break;
2067
2068 udelay(100);
2069 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2070 act_offset + 1,
2071 (u8)(data >> 8));
2072 if (ret_val)
2073 break;
2074 }
2075
2076 /*
2077 * Don't bother writing the segment valid bits if sector
2078 * programming failed.
2079 */
2080 if (ret_val) {
2081 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2082 hw_dbg(hw, "Flash commit failed.\n");
2083 nvm->ops.release_nvm(hw);
2084 goto out;
2085 }
2086
2087 /*
2088 * Finally validate the new segment by setting bit 15:14
2089 * to 10b in word 0x13 , this can be done without an
2090 * erase as well since these bits are 11 to start with
2091 * and we need to change bit 14 to 0b
2092 */
2093 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2094 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2095 if (ret_val) {
2096 nvm->ops.release_nvm(hw);
2097 goto out;
2098 }
2099 data &= 0xBFFF;
2100 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2101 act_offset * 2 + 1,
2102 (u8)(data >> 8));
2103 if (ret_val) {
2104 nvm->ops.release_nvm(hw);
2105 goto out;
2106 }
2107
2108 /*
2109 * And invalidate the previously valid segment by setting
2110 * its signature word (0x13) high_byte to 0b. This can be
2111 * done without an erase because flash erase sets all bits
2112 * to 1's. We can write 1's to 0's without an erase
2113 */
2114 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2115 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2116 if (ret_val) {
2117 nvm->ops.release_nvm(hw);
2118 goto out;
2119 }
2120
2121 /* Great! Everything worked, we can now clear the cached entries. */
2122 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2123 dev_spec->shadow_ram[i].modified = 0;
2124 dev_spec->shadow_ram[i].value = 0xFFFF;
2125 }
2126
2127 nvm->ops.release_nvm(hw);
2128
2129 /*
2130 * Reload the EEPROM, or else modifications will not appear
2131 * until after the next adapter reset.
2132 */
2133 e1000e_reload_nvm(hw);
2134 msleep(10);
2135
2136 out:
2137 if (ret_val)
2138 hw_dbg(hw, "NVM update error: %d\n", ret_val);
2139
2140 return ret_val;
2141 }
2142
2143 /**
2144 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2145 * @hw: pointer to the HW structure
2146 *
2147 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2148 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2149 * calculated, in which case we need to calculate the checksum and set bit 6.
2150 **/
2151 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2152 {
2153 s32 ret_val;
2154 u16 data;
2155
2156 /*
2157 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2158 * needs to be fixed. This bit is an indication that the NVM
2159 * was prepared by OEM software and did not calculate the
2160 * checksum...a likely scenario.
2161 */
2162 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2163 if (ret_val)
2164 return ret_val;
2165
2166 if ((data & 0x40) == 0) {
2167 data |= 0x40;
2168 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2169 if (ret_val)
2170 return ret_val;
2171 ret_val = e1000e_update_nvm_checksum(hw);
2172 if (ret_val)
2173 return ret_val;
2174 }
2175
2176 return e1000e_validate_nvm_checksum_generic(hw);
2177 }
2178
2179 /**
2180 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2181 * @hw: pointer to the HW structure
2182 *
2183 * To prevent malicious write/erase of the NVM, set it to be read-only
2184 * so that the hardware ignores all write/erase cycles of the NVM via
2185 * the flash control registers. The shadow-ram copy of the NVM will
2186 * still be updated, however any updates to this copy will not stick
2187 * across driver reloads.
2188 **/
2189 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2190 {
2191 struct e1000_nvm_info *nvm = &hw->nvm;
2192 union ich8_flash_protected_range pr0;
2193 union ich8_hws_flash_status hsfsts;
2194 u32 gfpreg;
2195
2196 nvm->ops.acquire_nvm(hw);
2197
2198 gfpreg = er32flash(ICH_FLASH_GFPREG);
2199
2200 /* Write-protect GbE Sector of NVM */
2201 pr0.regval = er32flash(ICH_FLASH_PR0);
2202 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2203 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2204 pr0.range.wpe = true;
2205 ew32flash(ICH_FLASH_PR0, pr0.regval);
2206
2207 /*
2208 * Lock down a subset of GbE Flash Control Registers, e.g.
2209 * PR0 to prevent the write-protection from being lifted.
2210 * Once FLOCKDN is set, the registers protected by it cannot
2211 * be written until FLOCKDN is cleared by a hardware reset.
2212 */
2213 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2214 hsfsts.hsf_status.flockdn = true;
2215 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2216
2217 nvm->ops.release_nvm(hw);
2218 }
2219
2220 /**
2221 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2222 * @hw: pointer to the HW structure
2223 * @offset: The offset (in bytes) of the byte/word to read.
2224 * @size: Size of data to read, 1=byte 2=word
2225 * @data: The byte(s) to write to the NVM.
2226 *
2227 * Writes one/two bytes to the NVM using the flash access registers.
2228 **/
2229 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2230 u8 size, u16 data)
2231 {
2232 union ich8_hws_flash_status hsfsts;
2233 union ich8_hws_flash_ctrl hsflctl;
2234 u32 flash_linear_addr;
2235 u32 flash_data = 0;
2236 s32 ret_val;
2237 u8 count = 0;
2238
2239 if (size < 1 || size > 2 || data > size * 0xff ||
2240 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2241 return -E1000_ERR_NVM;
2242
2243 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2244 hw->nvm.flash_base_addr;
2245
2246 do {
2247 udelay(1);
2248 /* Steps */
2249 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2250 if (ret_val)
2251 break;
2252
2253 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2254 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2255 hsflctl.hsf_ctrl.fldbcount = size -1;
2256 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2257 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2258
2259 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2260
2261 if (size == 1)
2262 flash_data = (u32)data & 0x00FF;
2263 else
2264 flash_data = (u32)data;
2265
2266 ew32flash(ICH_FLASH_FDATA0, flash_data);
2267
2268 /*
2269 * check if FCERR is set to 1 , if set to 1, clear it
2270 * and try the whole sequence a few more times else done
2271 */
2272 ret_val = e1000_flash_cycle_ich8lan(hw,
2273 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2274 if (!ret_val)
2275 break;
2276
2277 /*
2278 * If we're here, then things are most likely
2279 * completely hosed, but if the error condition
2280 * is detected, it won't hurt to give it another
2281 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2282 */
2283 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2284 if (hsfsts.hsf_status.flcerr == 1)
2285 /* Repeat for some time before giving up. */
2286 continue;
2287 if (hsfsts.hsf_status.flcdone == 0) {
2288 hw_dbg(hw, "Timeout error - flash cycle "
2289 "did not complete.");
2290 break;
2291 }
2292 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2293
2294 return ret_val;
2295 }
2296
2297 /**
2298 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2299 * @hw: pointer to the HW structure
2300 * @offset: The index of the byte to read.
2301 * @data: The byte to write to the NVM.
2302 *
2303 * Writes a single byte to the NVM using the flash access registers.
2304 **/
2305 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2306 u8 data)
2307 {
2308 u16 word = (u16)data;
2309
2310 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2311 }
2312
2313 /**
2314 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2315 * @hw: pointer to the HW structure
2316 * @offset: The offset of the byte to write.
2317 * @byte: The byte to write to the NVM.
2318 *
2319 * Writes a single byte to the NVM using the flash access registers.
2320 * Goes through a retry algorithm before giving up.
2321 **/
2322 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2323 u32 offset, u8 byte)
2324 {
2325 s32 ret_val;
2326 u16 program_retries;
2327
2328 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2329 if (!ret_val)
2330 return ret_val;
2331
2332 for (program_retries = 0; program_retries < 100; program_retries++) {
2333 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2334 udelay(100);
2335 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2336 if (!ret_val)
2337 break;
2338 }
2339 if (program_retries == 100)
2340 return -E1000_ERR_NVM;
2341
2342 return 0;
2343 }
2344
2345 /**
2346 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2347 * @hw: pointer to the HW structure
2348 * @bank: 0 for first bank, 1 for second bank, etc.
2349 *
2350 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2351 * bank N is 4096 * N + flash_reg_addr.
2352 **/
2353 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2354 {
2355 struct e1000_nvm_info *nvm = &hw->nvm;
2356 union ich8_hws_flash_status hsfsts;
2357 union ich8_hws_flash_ctrl hsflctl;
2358 u32 flash_linear_addr;
2359 /* bank size is in 16bit words - adjust to bytes */
2360 u32 flash_bank_size = nvm->flash_bank_size * 2;
2361 s32 ret_val;
2362 s32 count = 0;
2363 s32 iteration;
2364 s32 sector_size;
2365 s32 j;
2366
2367 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2368
2369 /*
2370 * Determine HW Sector size: Read BERASE bits of hw flash status
2371 * register
2372 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2373 * consecutive sectors. The start index for the nth Hw sector
2374 * can be calculated as = bank * 4096 + n * 256
2375 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2376 * The start index for the nth Hw sector can be calculated
2377 * as = bank * 4096
2378 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2379 * (ich9 only, otherwise error condition)
2380 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2381 */
2382 switch (hsfsts.hsf_status.berasesz) {
2383 case 0:
2384 /* Hw sector size 256 */
2385 sector_size = ICH_FLASH_SEG_SIZE_256;
2386 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2387 break;
2388 case 1:
2389 sector_size = ICH_FLASH_SEG_SIZE_4K;
2390 iteration = 1;
2391 break;
2392 case 2:
2393 sector_size = ICH_FLASH_SEG_SIZE_8K;
2394 iteration = 1;
2395 break;
2396 case 3:
2397 sector_size = ICH_FLASH_SEG_SIZE_64K;
2398 iteration = 1;
2399 break;
2400 default:
2401 return -E1000_ERR_NVM;
2402 }
2403
2404 /* Start with the base address, then add the sector offset. */
2405 flash_linear_addr = hw->nvm.flash_base_addr;
2406 flash_linear_addr += (bank) ? flash_bank_size : 0;
2407
2408 for (j = 0; j < iteration ; j++) {
2409 do {
2410 /* Steps */
2411 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2412 if (ret_val)
2413 return ret_val;
2414
2415 /*
2416 * Write a value 11 (block Erase) in Flash
2417 * Cycle field in hw flash control
2418 */
2419 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2420 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2421 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2422
2423 /*
2424 * Write the last 24 bits of an index within the
2425 * block into Flash Linear address field in Flash
2426 * Address.
2427 */
2428 flash_linear_addr += (j * sector_size);
2429 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2430
2431 ret_val = e1000_flash_cycle_ich8lan(hw,
2432 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2433 if (ret_val == 0)
2434 break;
2435
2436 /*
2437 * Check if FCERR is set to 1. If 1,
2438 * clear it and try the whole sequence
2439 * a few more times else Done
2440 */
2441 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2442 if (hsfsts.hsf_status.flcerr == 1)
2443 /* repeat for some time before giving up */
2444 continue;
2445 else if (hsfsts.hsf_status.flcdone == 0)
2446 return ret_val;
2447 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2448 }
2449
2450 return 0;
2451 }
2452
2453 /**
2454 * e1000_valid_led_default_ich8lan - Set the default LED settings
2455 * @hw: pointer to the HW structure
2456 * @data: Pointer to the LED settings
2457 *
2458 * Reads the LED default settings from the NVM to data. If the NVM LED
2459 * settings is all 0's or F's, set the LED default to a valid LED default
2460 * setting.
2461 **/
2462 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2463 {
2464 s32 ret_val;
2465
2466 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2467 if (ret_val) {
2468 hw_dbg(hw, "NVM Read Error\n");
2469 return ret_val;
2470 }
2471
2472 if (*data == ID_LED_RESERVED_0000 ||
2473 *data == ID_LED_RESERVED_FFFF)
2474 *data = ID_LED_DEFAULT_ICH8LAN;
2475
2476 return 0;
2477 }
2478
2479 /**
2480 * e1000_id_led_init_pchlan - store LED configurations
2481 * @hw: pointer to the HW structure
2482 *
2483 * PCH does not control LEDs via the LEDCTL register, rather it uses
2484 * the PHY LED configuration register.
2485 *
2486 * PCH also does not have an "always on" or "always off" mode which
2487 * complicates the ID feature. Instead of using the "on" mode to indicate
2488 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2489 * use "link_up" mode. The LEDs will still ID on request if there is no
2490 * link based on logic in e1000_led_[on|off]_pchlan().
2491 **/
2492 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2493 {
2494 struct e1000_mac_info *mac = &hw->mac;
2495 s32 ret_val;
2496 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2497 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2498 u16 data, i, temp, shift;
2499
2500 /* Get default ID LED modes */
2501 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2502 if (ret_val)
2503 goto out;
2504
2505 mac->ledctl_default = er32(LEDCTL);
2506 mac->ledctl_mode1 = mac->ledctl_default;
2507 mac->ledctl_mode2 = mac->ledctl_default;
2508
2509 for (i = 0; i < 4; i++) {
2510 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2511 shift = (i * 5);
2512 switch (temp) {
2513 case ID_LED_ON1_DEF2:
2514 case ID_LED_ON1_ON2:
2515 case ID_LED_ON1_OFF2:
2516 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2517 mac->ledctl_mode1 |= (ledctl_on << shift);
2518 break;
2519 case ID_LED_OFF1_DEF2:
2520 case ID_LED_OFF1_ON2:
2521 case ID_LED_OFF1_OFF2:
2522 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2523 mac->ledctl_mode1 |= (ledctl_off << shift);
2524 break;
2525 default:
2526 /* Do nothing */
2527 break;
2528 }
2529 switch (temp) {
2530 case ID_LED_DEF1_ON2:
2531 case ID_LED_ON1_ON2:
2532 case ID_LED_OFF1_ON2:
2533 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2534 mac->ledctl_mode2 |= (ledctl_on << shift);
2535 break;
2536 case ID_LED_DEF1_OFF2:
2537 case ID_LED_ON1_OFF2:
2538 case ID_LED_OFF1_OFF2:
2539 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2540 mac->ledctl_mode2 |= (ledctl_off << shift);
2541 break;
2542 default:
2543 /* Do nothing */
2544 break;
2545 }
2546 }
2547
2548 out:
2549 return ret_val;
2550 }
2551
2552 /**
2553 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2554 * @hw: pointer to the HW structure
2555 *
2556 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2557 * register, so the the bus width is hard coded.
2558 **/
2559 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2560 {
2561 struct e1000_bus_info *bus = &hw->bus;
2562 s32 ret_val;
2563
2564 ret_val = e1000e_get_bus_info_pcie(hw);
2565
2566 /*
2567 * ICH devices are "PCI Express"-ish. They have
2568 * a configuration space, but do not contain
2569 * PCI Express Capability registers, so bus width
2570 * must be hardcoded.
2571 */
2572 if (bus->width == e1000_bus_width_unknown)
2573 bus->width = e1000_bus_width_pcie_x1;
2574
2575 return ret_val;
2576 }
2577
2578 /**
2579 * e1000_reset_hw_ich8lan - Reset the hardware
2580 * @hw: pointer to the HW structure
2581 *
2582 * Does a full reset of the hardware which includes a reset of the PHY and
2583 * MAC.
2584 **/
2585 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2586 {
2587 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2588 u16 reg;
2589 u32 ctrl, icr, kab;
2590 s32 ret_val;
2591
2592 /*
2593 * Prevent the PCI-E bus from sticking if there is no TLP connection
2594 * on the last TLP read/write transaction when MAC is reset.
2595 */
2596 ret_val = e1000e_disable_pcie_master(hw);
2597 if (ret_val) {
2598 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2599 }
2600
2601 hw_dbg(hw, "Masking off all interrupts\n");
2602 ew32(IMC, 0xffffffff);
2603
2604 /*
2605 * Disable the Transmit and Receive units. Then delay to allow
2606 * any pending transactions to complete before we hit the MAC
2607 * with the global reset.
2608 */
2609 ew32(RCTL, 0);
2610 ew32(TCTL, E1000_TCTL_PSP);
2611 e1e_flush();
2612
2613 msleep(10);
2614
2615 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2616 if (hw->mac.type == e1000_ich8lan) {
2617 /* Set Tx and Rx buffer allocation to 8k apiece. */
2618 ew32(PBA, E1000_PBA_8K);
2619 /* Set Packet Buffer Size to 16k. */
2620 ew32(PBS, E1000_PBS_16K);
2621 }
2622
2623 if (hw->mac.type == e1000_pchlan) {
2624 /* Save the NVM K1 bit setting*/
2625 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2626 if (ret_val)
2627 return ret_val;
2628
2629 if (reg & E1000_NVM_K1_ENABLE)
2630 dev_spec->nvm_k1_enabled = true;
2631 else
2632 dev_spec->nvm_k1_enabled = false;
2633 }
2634
2635 ctrl = er32(CTRL);
2636
2637 if (!e1000_check_reset_block(hw)) {
2638 /* Clear PHY Reset Asserted bit */
2639 if (hw->mac.type >= e1000_pchlan) {
2640 u32 status = er32(STATUS);
2641 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2642 }
2643
2644 /*
2645 * PHY HW reset requires MAC CORE reset at the same
2646 * time to make sure the interface between MAC and the
2647 * external PHY is reset.
2648 */
2649 ctrl |= E1000_CTRL_PHY_RST;
2650 }
2651 ret_val = e1000_acquire_swflag_ich8lan(hw);
2652 /* Whether or not the swflag was acquired, we need to reset the part */
2653 hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2654 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2655 msleep(20);
2656
2657 if (!ret_val)
2658 e1000_release_swflag_ich8lan(hw);
2659
2660 if (ctrl & E1000_CTRL_PHY_RST)
2661 ret_val = hw->phy.ops.get_cfg_done(hw);
2662
2663 if (hw->mac.type >= e1000_ich10lan) {
2664 e1000_lan_init_done_ich8lan(hw);
2665 } else {
2666 ret_val = e1000e_get_auto_rd_done(hw);
2667 if (ret_val) {
2668 /*
2669 * When auto config read does not complete, do not
2670 * return with an error. This can happen in situations
2671 * where there is no eeprom and prevents getting link.
2672 */
2673 hw_dbg(hw, "Auto Read Done did not complete\n");
2674 }
2675 }
2676 /* Dummy read to clear the phy wakeup bit after lcd reset */
2677 if (hw->mac.type == e1000_pchlan)
2678 e1e_rphy(hw, BM_WUC, &reg);
2679
2680 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2681 if (ret_val)
2682 goto out;
2683
2684 if (hw->mac.type == e1000_pchlan) {
2685 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2686 if (ret_val)
2687 goto out;
2688 }
2689 /*
2690 * For PCH, this write will make sure that any noise
2691 * will be detected as a CRC error and be dropped rather than show up
2692 * as a bad packet to the DMA engine.
2693 */
2694 if (hw->mac.type == e1000_pchlan)
2695 ew32(CRC_OFFSET, 0x65656565);
2696
2697 ew32(IMC, 0xffffffff);
2698 icr = er32(ICR);
2699
2700 kab = er32(KABGTXD);
2701 kab |= E1000_KABGTXD_BGSQLBIAS;
2702 ew32(KABGTXD, kab);
2703
2704 if (hw->mac.type == e1000_pchlan)
2705 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2706
2707 out:
2708 return ret_val;
2709 }
2710
2711 /**
2712 * e1000_init_hw_ich8lan - Initialize the hardware
2713 * @hw: pointer to the HW structure
2714 *
2715 * Prepares the hardware for transmit and receive by doing the following:
2716 * - initialize hardware bits
2717 * - initialize LED identification
2718 * - setup receive address registers
2719 * - setup flow control
2720 * - setup transmit descriptors
2721 * - clear statistics
2722 **/
2723 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2724 {
2725 struct e1000_mac_info *mac = &hw->mac;
2726 u32 ctrl_ext, txdctl, snoop;
2727 s32 ret_val;
2728 u16 i;
2729
2730 e1000_initialize_hw_bits_ich8lan(hw);
2731
2732 /* Initialize identification LED */
2733 ret_val = mac->ops.id_led_init(hw);
2734 if (ret_val) {
2735 hw_dbg(hw, "Error initializing identification LED\n");
2736 return ret_val;
2737 }
2738
2739 /* Setup the receive address. */
2740 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2741
2742 /* Zero out the Multicast HASH table */
2743 hw_dbg(hw, "Zeroing the MTA\n");
2744 for (i = 0; i < mac->mta_reg_count; i++)
2745 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2746
2747 /*
2748 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2749 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2750 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2751 */
2752 if (hw->phy.type == e1000_phy_82578) {
2753 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2754 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2755 if (ret_val)
2756 return ret_val;
2757 }
2758
2759 /* Setup link and flow control */
2760 ret_val = e1000_setup_link_ich8lan(hw);
2761
2762 /* Set the transmit descriptor write-back policy for both queues */
2763 txdctl = er32(TXDCTL(0));
2764 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2765 E1000_TXDCTL_FULL_TX_DESC_WB;
2766 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2767 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2768 ew32(TXDCTL(0), txdctl);
2769 txdctl = er32(TXDCTL(1));
2770 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2771 E1000_TXDCTL_FULL_TX_DESC_WB;
2772 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2773 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2774 ew32(TXDCTL(1), txdctl);
2775
2776 /*
2777 * ICH8 has opposite polarity of no_snoop bits.
2778 * By default, we should use snoop behavior.
2779 */
2780 if (mac->type == e1000_ich8lan)
2781 snoop = PCIE_ICH8_SNOOP_ALL;
2782 else
2783 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2784 e1000e_set_pcie_no_snoop(hw, snoop);
2785
2786 ctrl_ext = er32(CTRL_EXT);
2787 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2788 ew32(CTRL_EXT, ctrl_ext);
2789
2790 /*
2791 * Clear all of the statistics registers (clear on read). It is
2792 * important that we do this after we have tried to establish link
2793 * because the symbol error count will increment wildly if there
2794 * is no link.
2795 */
2796 e1000_clear_hw_cntrs_ich8lan(hw);
2797
2798 return 0;
2799 }
2800 /**
2801 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2802 * @hw: pointer to the HW structure
2803 *
2804 * Sets/Clears required hardware bits necessary for correctly setting up the
2805 * hardware for transmit and receive.
2806 **/
2807 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2808 {
2809 u32 reg;
2810
2811 /* Extended Device Control */
2812 reg = er32(CTRL_EXT);
2813 reg |= (1 << 22);
2814 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2815 if (hw->mac.type >= e1000_pchlan)
2816 reg |= E1000_CTRL_EXT_PHYPDEN;
2817 ew32(CTRL_EXT, reg);
2818
2819 /* Transmit Descriptor Control 0 */
2820 reg = er32(TXDCTL(0));
2821 reg |= (1 << 22);
2822 ew32(TXDCTL(0), reg);
2823
2824 /* Transmit Descriptor Control 1 */
2825 reg = er32(TXDCTL(1));
2826 reg |= (1 << 22);
2827 ew32(TXDCTL(1), reg);
2828
2829 /* Transmit Arbitration Control 0 */
2830 reg = er32(TARC(0));
2831 if (hw->mac.type == e1000_ich8lan)
2832 reg |= (1 << 28) | (1 << 29);
2833 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2834 ew32(TARC(0), reg);
2835
2836 /* Transmit Arbitration Control 1 */
2837 reg = er32(TARC(1));
2838 if (er32(TCTL) & E1000_TCTL_MULR)
2839 reg &= ~(1 << 28);
2840 else
2841 reg |= (1 << 28);
2842 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2843 ew32(TARC(1), reg);
2844
2845 /* Device Status */
2846 if (hw->mac.type == e1000_ich8lan) {
2847 reg = er32(STATUS);
2848 reg &= ~(1 << 31);
2849 ew32(STATUS, reg);
2850 }
2851 }
2852
2853 /**
2854 * e1000_setup_link_ich8lan - Setup flow control and link settings
2855 * @hw: pointer to the HW structure
2856 *
2857 * Determines which flow control settings to use, then configures flow
2858 * control. Calls the appropriate media-specific link configuration
2859 * function. Assuming the adapter has a valid link partner, a valid link
2860 * should be established. Assumes the hardware has previously been reset
2861 * and the transmitter and receiver are not enabled.
2862 **/
2863 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2864 {
2865 s32 ret_val;
2866
2867 if (e1000_check_reset_block(hw))
2868 return 0;
2869
2870 /*
2871 * ICH parts do not have a word in the NVM to determine
2872 * the default flow control setting, so we explicitly
2873 * set it to full.
2874 */
2875 if (hw->fc.requested_mode == e1000_fc_default) {
2876 /* Workaround h/w hang when Tx flow control enabled */
2877 if (hw->mac.type == e1000_pchlan)
2878 hw->fc.requested_mode = e1000_fc_rx_pause;
2879 else
2880 hw->fc.requested_mode = e1000_fc_full;
2881 }
2882
2883 /*
2884 * Save off the requested flow control mode for use later. Depending
2885 * on the link partner's capabilities, we may or may not use this mode.
2886 */
2887 hw->fc.current_mode = hw->fc.requested_mode;
2888
2889 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2890 hw->fc.current_mode);
2891
2892 /* Continue to configure the copper link. */
2893 ret_val = e1000_setup_copper_link_ich8lan(hw);
2894 if (ret_val)
2895 return ret_val;
2896
2897 ew32(FCTTV, hw->fc.pause_time);
2898 if ((hw->phy.type == e1000_phy_82578) ||
2899 (hw->phy.type == e1000_phy_82577)) {
2900 ret_val = hw->phy.ops.write_phy_reg(hw,
2901 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2902 hw->fc.pause_time);
2903 if (ret_val)
2904 return ret_val;
2905 }
2906
2907 return e1000e_set_fc_watermarks(hw);
2908 }
2909
2910 /**
2911 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2912 * @hw: pointer to the HW structure
2913 *
2914 * Configures the kumeran interface to the PHY to wait the appropriate time
2915 * when polling the PHY, then call the generic setup_copper_link to finish
2916 * configuring the copper link.
2917 **/
2918 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2919 {
2920 u32 ctrl;
2921 s32 ret_val;
2922 u16 reg_data;
2923
2924 ctrl = er32(CTRL);
2925 ctrl |= E1000_CTRL_SLU;
2926 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2927 ew32(CTRL, ctrl);
2928
2929 /*
2930 * Set the mac to wait the maximum time between each iteration
2931 * and increase the max iterations when polling the phy;
2932 * this fixes erroneous timeouts at 10Mbps.
2933 */
2934 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2935 if (ret_val)
2936 return ret_val;
2937 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2938 if (ret_val)
2939 return ret_val;
2940 reg_data |= 0x3F;
2941 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2942 if (ret_val)
2943 return ret_val;
2944
2945 switch (hw->phy.type) {
2946 case e1000_phy_igp_3:
2947 ret_val = e1000e_copper_link_setup_igp(hw);
2948 if (ret_val)
2949 return ret_val;
2950 break;
2951 case e1000_phy_bm:
2952 case e1000_phy_82578:
2953 ret_val = e1000e_copper_link_setup_m88(hw);
2954 if (ret_val)
2955 return ret_val;
2956 break;
2957 case e1000_phy_82577:
2958 ret_val = e1000_copper_link_setup_82577(hw);
2959 if (ret_val)
2960 return ret_val;
2961 break;
2962 case e1000_phy_ife:
2963 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2964 &reg_data);
2965 if (ret_val)
2966 return ret_val;
2967
2968 reg_data &= ~IFE_PMC_AUTO_MDIX;
2969
2970 switch (hw->phy.mdix) {
2971 case 1:
2972 reg_data &= ~IFE_PMC_FORCE_MDIX;
2973 break;
2974 case 2:
2975 reg_data |= IFE_PMC_FORCE_MDIX;
2976 break;
2977 case 0:
2978 default:
2979 reg_data |= IFE_PMC_AUTO_MDIX;
2980 break;
2981 }
2982 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2983 reg_data);
2984 if (ret_val)
2985 return ret_val;
2986 break;
2987 default:
2988 break;
2989 }
2990 return e1000e_setup_copper_link(hw);
2991 }
2992
2993 /**
2994 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2995 * @hw: pointer to the HW structure
2996 * @speed: pointer to store current link speed
2997 * @duplex: pointer to store the current link duplex
2998 *
2999 * Calls the generic get_speed_and_duplex to retrieve the current link
3000 * information and then calls the Kumeran lock loss workaround for links at
3001 * gigabit speeds.
3002 **/
3003 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3004 u16 *duplex)
3005 {
3006 s32 ret_val;
3007
3008 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3009 if (ret_val)
3010 return ret_val;
3011
3012 if ((hw->mac.type == e1000_ich8lan) &&
3013 (hw->phy.type == e1000_phy_igp_3) &&
3014 (*speed == SPEED_1000)) {
3015 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3016 }
3017
3018 return ret_val;
3019 }
3020
3021 /**
3022 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3023 * @hw: pointer to the HW structure
3024 *
3025 * Work-around for 82566 Kumeran PCS lock loss:
3026 * On link status change (i.e. PCI reset, speed change) and link is up and
3027 * speed is gigabit-
3028 * 0) if workaround is optionally disabled do nothing
3029 * 1) wait 1ms for Kumeran link to come up
3030 * 2) check Kumeran Diagnostic register PCS lock loss bit
3031 * 3) if not set the link is locked (all is good), otherwise...
3032 * 4) reset the PHY
3033 * 5) repeat up to 10 times
3034 * Note: this is only called for IGP3 copper when speed is 1gb.
3035 **/
3036 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3037 {
3038 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3039 u32 phy_ctrl;
3040 s32 ret_val;
3041 u16 i, data;
3042 bool link;
3043
3044 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3045 return 0;
3046
3047 /*
3048 * Make sure link is up before proceeding. If not just return.
3049 * Attempting this while link is negotiating fouled up link
3050 * stability
3051 */
3052 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3053 if (!link)
3054 return 0;
3055
3056 for (i = 0; i < 10; i++) {
3057 /* read once to clear */
3058 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3059 if (ret_val)
3060 return ret_val;
3061 /* and again to get new status */
3062 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3063 if (ret_val)
3064 return ret_val;
3065
3066 /* check for PCS lock */
3067 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3068 return 0;
3069
3070 /* Issue PHY reset */
3071 e1000_phy_hw_reset(hw);
3072 mdelay(5);
3073 }
3074 /* Disable GigE link negotiation */
3075 phy_ctrl = er32(PHY_CTRL);
3076 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3077 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3078 ew32(PHY_CTRL, phy_ctrl);
3079
3080 /*
3081 * Call gig speed drop workaround on Gig disable before accessing
3082 * any PHY registers
3083 */
3084 e1000e_gig_downshift_workaround_ich8lan(hw);
3085
3086 /* unable to acquire PCS lock */
3087 return -E1000_ERR_PHY;
3088 }
3089
3090 /**
3091 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3092 * @hw: pointer to the HW structure
3093 * @state: boolean value used to set the current Kumeran workaround state
3094 *
3095 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
3096 * /disabled - FALSE).
3097 **/
3098 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3099 bool state)
3100 {
3101 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3102
3103 if (hw->mac.type != e1000_ich8lan) {
3104 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
3105 return;
3106 }
3107
3108 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3109 }
3110
3111 /**
3112 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3113 * @hw: pointer to the HW structure
3114 *
3115 * Workaround for 82566 power-down on D3 entry:
3116 * 1) disable gigabit link
3117 * 2) write VR power-down enable
3118 * 3) read it back
3119 * Continue if successful, else issue LCD reset and repeat
3120 **/
3121 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3122 {
3123 u32 reg;
3124 u16 data;
3125 u8 retry = 0;
3126
3127 if (hw->phy.type != e1000_phy_igp_3)
3128 return;
3129
3130 /* Try the workaround twice (if needed) */
3131 do {
3132 /* Disable link */
3133 reg = er32(PHY_CTRL);
3134 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3135 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3136 ew32(PHY_CTRL, reg);
3137
3138 /*
3139 * Call gig speed drop workaround on Gig disable before
3140 * accessing any PHY registers
3141 */
3142 if (hw->mac.type == e1000_ich8lan)
3143 e1000e_gig_downshift_workaround_ich8lan(hw);
3144
3145 /* Write VR power-down enable */
3146 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3147 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3148 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3149
3150 /* Read it back and test */
3151 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3152 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3153 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3154 break;
3155
3156 /* Issue PHY reset and repeat at most one more time */
3157 reg = er32(CTRL);
3158 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3159 retry++;
3160 } while (retry);
3161 }
3162
3163 /**
3164 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3165 * @hw: pointer to the HW structure
3166 *
3167 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3168 * LPLU, Gig disable, MDIC PHY reset):
3169 * 1) Set Kumeran Near-end loopback
3170 * 2) Clear Kumeran Near-end loopback
3171 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3172 **/
3173 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3174 {
3175 s32 ret_val;
3176 u16 reg_data;
3177
3178 if ((hw->mac.type != e1000_ich8lan) ||
3179 (hw->phy.type != e1000_phy_igp_3))
3180 return;
3181
3182 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3183 &reg_data);
3184 if (ret_val)
3185 return;
3186 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3187 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3188 reg_data);
3189 if (ret_val)
3190 return;
3191 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3192 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3193 reg_data);
3194 }
3195
3196 /**
3197 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3198 * @hw: pointer to the HW structure
3199 *
3200 * During S0 to Sx transition, it is possible the link remains at gig
3201 * instead of negotiating to a lower speed. Before going to Sx, set
3202 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3203 * to a lower speed.
3204 *
3205 * Should only be called for applicable parts.
3206 **/
3207 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3208 {
3209 u32 phy_ctrl;
3210
3211 switch (hw->mac.type) {
3212 case e1000_ich9lan:
3213 case e1000_ich10lan:
3214 case e1000_pchlan:
3215 phy_ctrl = er32(PHY_CTRL);
3216 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3217 E1000_PHY_CTRL_GBE_DISABLE;
3218 ew32(PHY_CTRL, phy_ctrl);
3219
3220 if (hw->mac.type == e1000_pchlan)
3221 e1000_phy_hw_reset_ich8lan(hw);
3222 default:
3223 break;
3224 }
3225
3226 return;
3227 }
3228
3229 /**
3230 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3231 * @hw: pointer to the HW structure
3232 *
3233 * Return the LED back to the default configuration.
3234 **/
3235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3236 {
3237 if (hw->phy.type == e1000_phy_ife)
3238 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3239
3240 ew32(LEDCTL, hw->mac.ledctl_default);
3241 return 0;
3242 }
3243
3244 /**
3245 * e1000_led_on_ich8lan - Turn LEDs on
3246 * @hw: pointer to the HW structure
3247 *
3248 * Turn on the LEDs.
3249 **/
3250 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3251 {
3252 if (hw->phy.type == e1000_phy_ife)
3253 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3254 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3255
3256 ew32(LEDCTL, hw->mac.ledctl_mode2);
3257 return 0;
3258 }
3259
3260 /**
3261 * e1000_led_off_ich8lan - Turn LEDs off
3262 * @hw: pointer to the HW structure
3263 *
3264 * Turn off the LEDs.
3265 **/
3266 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3267 {
3268 if (hw->phy.type == e1000_phy_ife)
3269 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3270 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3271
3272 ew32(LEDCTL, hw->mac.ledctl_mode1);
3273 return 0;
3274 }
3275
3276 /**
3277 * e1000_setup_led_pchlan - Configures SW controllable LED
3278 * @hw: pointer to the HW structure
3279 *
3280 * This prepares the SW controllable LED for use.
3281 **/
3282 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3283 {
3284 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3285 (u16)hw->mac.ledctl_mode1);
3286 }
3287
3288 /**
3289 * e1000_cleanup_led_pchlan - Restore the default LED operation
3290 * @hw: pointer to the HW structure
3291 *
3292 * Return the LED back to the default configuration.
3293 **/
3294 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3295 {
3296 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3297 (u16)hw->mac.ledctl_default);
3298 }
3299
3300 /**
3301 * e1000_led_on_pchlan - Turn LEDs on
3302 * @hw: pointer to the HW structure
3303 *
3304 * Turn on the LEDs.
3305 **/
3306 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3307 {
3308 u16 data = (u16)hw->mac.ledctl_mode2;
3309 u32 i, led;
3310
3311 /*
3312 * If no link, then turn LED on by setting the invert bit
3313 * for each LED that's mode is "link_up" in ledctl_mode2.
3314 */
3315 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3316 for (i = 0; i < 3; i++) {
3317 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3318 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3319 E1000_LEDCTL_MODE_LINK_UP)
3320 continue;
3321 if (led & E1000_PHY_LED0_IVRT)
3322 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3323 else
3324 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3325 }
3326 }
3327
3328 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3329 }
3330
3331 /**
3332 * e1000_led_off_pchlan - Turn LEDs off
3333 * @hw: pointer to the HW structure
3334 *
3335 * Turn off the LEDs.
3336 **/
3337 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3338 {
3339 u16 data = (u16)hw->mac.ledctl_mode1;
3340 u32 i, led;
3341
3342 /*
3343 * If no link, then turn LED off by clearing the invert bit
3344 * for each LED that's mode is "link_up" in ledctl_mode1.
3345 */
3346 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3347 for (i = 0; i < 3; i++) {
3348 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3349 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3350 E1000_LEDCTL_MODE_LINK_UP)
3351 continue;
3352 if (led & E1000_PHY_LED0_IVRT)
3353 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3354 else
3355 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3356 }
3357 }
3358
3359 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3360 }
3361
3362 /**
3363 * e1000_get_cfg_done_ich8lan - Read config done bit
3364 * @hw: pointer to the HW structure
3365 *
3366 * Read the management control register for the config done bit for
3367 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3368 * to read the config done bit, so an error is *ONLY* logged and returns
3369 * 0. If we were to return with error, EEPROM-less silicon
3370 * would not be able to be reset or change link.
3371 **/
3372 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3373 {
3374 u32 bank = 0;
3375
3376 if (hw->mac.type >= e1000_pchlan) {
3377 u32 status = er32(STATUS);
3378
3379 if (status & E1000_STATUS_PHYRA)
3380 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3381 else
3382 hw_dbg(hw,
3383 "PHY Reset Asserted not set - needs delay\n");
3384 }
3385
3386 e1000e_get_cfg_done(hw);
3387
3388 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3389 if ((hw->mac.type != e1000_ich10lan) &&
3390 (hw->mac.type != e1000_pchlan)) {
3391 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3392 (hw->phy.type == e1000_phy_igp_3)) {
3393 e1000e_phy_init_script_igp3(hw);
3394 }
3395 } else {
3396 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3397 /* Maybe we should do a basic PHY config */
3398 hw_dbg(hw, "EEPROM not present\n");
3399 return -E1000_ERR_CONFIG;
3400 }
3401 }
3402
3403 return 0;
3404 }
3405
3406 /**
3407 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3408 * @hw: pointer to the HW structure
3409 *
3410 * Clears hardware counters specific to the silicon family and calls
3411 * clear_hw_cntrs_generic to clear all general purpose counters.
3412 **/
3413 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3414 {
3415 u32 temp;
3416 u16 phy_data;
3417
3418 e1000e_clear_hw_cntrs_base(hw);
3419
3420 temp = er32(ALGNERRC);
3421 temp = er32(RXERRC);
3422 temp = er32(TNCRS);
3423 temp = er32(CEXTERR);
3424 temp = er32(TSCTC);
3425 temp = er32(TSCTFC);
3426
3427 temp = er32(MGTPRC);
3428 temp = er32(MGTPDC);
3429 temp = er32(MGTPTC);
3430
3431 temp = er32(IAC);
3432 temp = er32(ICRXOC);
3433
3434 /* Clear PHY statistics registers */
3435 if ((hw->phy.type == e1000_phy_82578) ||
3436 (hw->phy.type == e1000_phy_82577)) {
3437 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3438 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3439 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3440 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3441 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3442 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3443 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3444 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3445 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3446 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3447 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3448 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3449 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3450 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3451 }
3452 }
3453
3454 static struct e1000_mac_operations ich8_mac_ops = {
3455 .id_led_init = e1000e_id_led_init,
3456 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3457 .check_for_link = e1000_check_for_copper_link_ich8lan,
3458 /* cleanup_led dependent on mac type */
3459 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3460 .get_bus_info = e1000_get_bus_info_ich8lan,
3461 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3462 /* led_on dependent on mac type */
3463 /* led_off dependent on mac type */
3464 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3465 .reset_hw = e1000_reset_hw_ich8lan,
3466 .init_hw = e1000_init_hw_ich8lan,
3467 .setup_link = e1000_setup_link_ich8lan,
3468 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3469 /* id_led_init dependent on mac type */
3470 };
3471
3472 static struct e1000_phy_operations ich8_phy_ops = {
3473 .acquire_phy = e1000_acquire_swflag_ich8lan,
3474 .check_reset_block = e1000_check_reset_block_ich8lan,
3475 .commit_phy = NULL,
3476 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3477 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3478 .get_cable_length = e1000e_get_cable_length_igp_2,
3479 .get_phy_info = e1000_get_phy_info_ich8lan,
3480 .read_phy_reg = e1000e_read_phy_reg_igp,
3481 .release_phy = e1000_release_swflag_ich8lan,
3482 .reset_phy = e1000_phy_hw_reset_ich8lan,
3483 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3484 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3485 .write_phy_reg = e1000e_write_phy_reg_igp,
3486 };
3487
3488 static struct e1000_nvm_operations ich8_nvm_ops = {
3489 .acquire_nvm = e1000_acquire_nvm_ich8lan,
3490 .read_nvm = e1000_read_nvm_ich8lan,
3491 .release_nvm = e1000_release_nvm_ich8lan,
3492 .update_nvm = e1000_update_nvm_checksum_ich8lan,
3493 .valid_led_default = e1000_valid_led_default_ich8lan,
3494 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
3495 .write_nvm = e1000_write_nvm_ich8lan,
3496 };
3497
3498 struct e1000_info e1000_ich8_info = {
3499 .mac = e1000_ich8lan,
3500 .flags = FLAG_HAS_WOL
3501 | FLAG_IS_ICH
3502 | FLAG_RX_CSUM_ENABLED
3503 | FLAG_HAS_CTRLEXT_ON_LOAD
3504 | FLAG_HAS_AMT
3505 | FLAG_HAS_FLASH
3506 | FLAG_APME_IN_WUC,
3507 .pba = 8,
3508 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3509 .get_variants = e1000_get_variants_ich8lan,
3510 .mac_ops = &ich8_mac_ops,
3511 .phy_ops = &ich8_phy_ops,
3512 .nvm_ops = &ich8_nvm_ops,
3513 };
3514
3515 struct e1000_info e1000_ich9_info = {
3516 .mac = e1000_ich9lan,
3517 .flags = FLAG_HAS_JUMBO_FRAMES
3518 | FLAG_IS_ICH
3519 | FLAG_HAS_WOL
3520 | FLAG_RX_CSUM_ENABLED
3521 | FLAG_HAS_CTRLEXT_ON_LOAD
3522 | FLAG_HAS_AMT
3523 | FLAG_HAS_ERT
3524 | FLAG_HAS_FLASH
3525 | FLAG_APME_IN_WUC,
3526 .pba = 10,
3527 .max_hw_frame_size = DEFAULT_JUMBO,
3528 .get_variants = e1000_get_variants_ich8lan,
3529 .mac_ops = &ich8_mac_ops,
3530 .phy_ops = &ich8_phy_ops,
3531 .nvm_ops = &ich8_nvm_ops,
3532 };
3533
3534 struct e1000_info e1000_ich10_info = {
3535 .mac = e1000_ich10lan,
3536 .flags = FLAG_HAS_JUMBO_FRAMES
3537 | FLAG_IS_ICH
3538 | FLAG_HAS_WOL
3539 | FLAG_RX_CSUM_ENABLED
3540 | FLAG_HAS_CTRLEXT_ON_LOAD
3541 | FLAG_HAS_AMT
3542 | FLAG_HAS_ERT
3543 | FLAG_HAS_FLASH
3544 | FLAG_APME_IN_WUC,
3545 .pba = 10,
3546 .max_hw_frame_size = DEFAULT_JUMBO,
3547 .get_variants = e1000_get_variants_ich8lan,
3548 .mac_ops = &ich8_mac_ops,
3549 .phy_ops = &ich8_phy_ops,
3550 .nvm_ops = &ich8_nvm_ops,
3551 };
3552
3553 struct e1000_info e1000_pch_info = {
3554 .mac = e1000_pchlan,
3555 .flags = FLAG_IS_ICH
3556 | FLAG_HAS_WOL
3557 | FLAG_RX_CSUM_ENABLED
3558 | FLAG_HAS_CTRLEXT_ON_LOAD
3559 | FLAG_HAS_AMT
3560 | FLAG_HAS_FLASH
3561 | FLAG_HAS_JUMBO_FRAMES
3562 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3563 | FLAG_APME_IN_WUC,
3564 .pba = 26,
3565 .max_hw_frame_size = 4096,
3566 .get_variants = e1000_get_variants_ich8lan,
3567 .mac_ops = &ich8_mac_ops,
3568 .phy_ops = &ich8_phy_ops,
3569 .nvm_ops = &ich8_nvm_ops,
3570 };
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