1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
3 Written/copyright 1997-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
24 ---------------------------------------------------------------------
28 #define DRV_NAME "epic100"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sept 11, 2006"
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
35 static int debug
= 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37 /* Used to pass the full-duplex flag, etc. */
38 #define MAX_UNITS 8 /* More are supported, limit only on options */
39 static int options
[MAX_UNITS
] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex
[MAX_UNITS
] = {-1, -1, -1, -1, -1, -1, -1, -1};
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44 static int rx_copybreak
;
46 /* Operational parameters that are set at compile time. */
48 /* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53 #define TX_RING_SIZE 256
54 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55 #define RX_RING_SIZE 256
56 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
59 /* Operational parameters that usually are not changed. */
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (2*HZ)
63 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
65 /* Bytes transferred to chip before transmission starts. */
66 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67 #define TX_FIFO_THRESH 256
68 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/interrupt.h>
77 #include <linux/pci.h>
78 #include <linux/delay.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/init.h>
83 #include <linux/spinlock.h>
84 #include <linux/ethtool.h>
85 #include <linux/mii.h>
86 #include <linux/crc32.h>
87 #include <linux/bitops.h>
89 #include <asm/uaccess.h>
91 /* These identify the driver base version and may not be removed. */
92 static char version
[] __devinitdata
=
93 DRV_NAME
".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
94 static char version2
[] __devinitdata
=
95 " (unofficial 2.4.x kernel port, version " DRV_VERSION
", " DRV_RELDATE
")\n";
97 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
98 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
99 MODULE_LICENSE("GPL");
101 module_param(debug
, int, 0);
102 module_param(rx_copybreak
, int, 0);
103 module_param_array(options
, int, NULL
, 0);
104 module_param_array(full_duplex
, int, NULL
, 0);
105 MODULE_PARM_DESC(debug
, "EPIC/100 debug level (0-5)");
106 MODULE_PARM_DESC(options
, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
107 MODULE_PARM_DESC(rx_copybreak
, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
108 MODULE_PARM_DESC(full_duplex
, "EPIC/100 full duplex setting(s) (1)");
113 I. Board Compatibility
115 This device driver is designed for the SMC "EPIC/100", the SMC
116 single-chip Ethernet controllers for PCI. This chip is used on
117 the SMC EtherPower II boards.
119 II. Board-specific settings
121 PCI bus devices are configured by the system at boot time, so no jumpers
122 need to be set on the board. The system BIOS will assign the
123 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
124 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
127 III. Driver operation
133 http://www.smsc.com/main/tools/discontinued/83c171.pdf
134 http://www.smsc.com/main/tools/discontinued/83c175.pdf
135 http://scyld.com/expert/NWay.html
136 http://www.national.com/pf/DP/DP83840A.html
143 enum chip_capability_flags
{ MII_PWRDWN
=1, TYPE2_INTR
=2, NO_MII
=4 };
145 #define EPIC_TOTAL_SIZE 0x100
155 struct epic_chip_info
{
157 int drv_flags
; /* Driver use, intended as capability flags. */
161 /* indexed by chip_t */
162 static const struct epic_chip_info pci_id_tbl
[] = {
163 { "SMSC EPIC/100 83c170", TYPE2_INTR
| NO_MII
| MII_PWRDWN
},
164 { "SMSC EPIC/100 83c170", TYPE2_INTR
},
165 { "SMSC EPIC/C 83c175", TYPE2_INTR
| MII_PWRDWN
},
169 static DEFINE_PCI_DEVICE_TABLE(epic_pci_tbl
) = {
170 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0
},
171 { 0x10B8, 0x0005, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, SMSC_83C170
},
172 { 0x10B8, 0x0006, PCI_ANY_ID
, PCI_ANY_ID
,
173 PCI_CLASS_NETWORK_ETHERNET
<< 8, 0xffff00, SMSC_83C175
},
176 MODULE_DEVICE_TABLE (pci
, epic_pci_tbl
);
194 /* Offsets to registers, using the (ugh) SMC names. */
195 enum epic_registers
{
196 COMMAND
=0, INTSTAT
=4, INTMASK
=8, GENCTL
=0x0C, NVCTL
=0x10, EECTL
=0x14,
198 TEST1
=0x1C, CRCCNT
=0x20, ALICNT
=0x24, MPCNT
=0x28, /* Rx error counters. */
199 MIICtrl
=0x30, MIIData
=0x34, MIICfg
=0x38,
200 LAN0
=64, /* MAC address. */
201 MC0
=80, /* Multicast filter table. */
202 RxCtrl
=96, TxCtrl
=112, TxSTAT
=0x74,
203 PRxCDAR
=0x84, RxSTAT
=0xA4, EarlyRx
=0xB0, PTxCDAR
=0xC4, TxThresh
=0xDC,
206 /* Interrupt register bits, using my own meaningful names. */
208 TxIdle
=0x40000, RxIdle
=0x20000, IntrSummary
=0x010000,
209 PCIBusErr170
=0x7000, PCIBusErr175
=0x1000, PhyEvent175
=0x8000,
210 RxStarted
=0x0800, RxEarlyWarn
=0x0400, CntFull
=0x0200, TxUnderrun
=0x0100,
211 TxEmpty
=0x0080, TxDone
=0x0020, RxError
=0x0010,
212 RxOverflow
=0x0008, RxFull
=0x0004, RxHeader
=0x0002, RxDone
=0x0001,
215 StopRx
=1, StartRx
=2, TxQueued
=4, RxQueued
=8,
216 StopTxDMA
=0x20, StopRxDMA
=0x40, RestartTx
=0x80,
219 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221 #define EpicNapiEvent (TxEmpty | TxDone | \
222 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
223 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225 static const u16 media2miictl
[16] = {
226 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
227 0, 0, 0, 0, 0, 0, 0, 0 };
230 * The EPIC100 Rx and Tx buffer descriptors. Note that these
231 * really ARE host-endian; it's not a misannotation. We tell
232 * the card to byteswap them internally on big-endian hosts -
233 * look for #ifdef CONFIG_BIG_ENDIAN in epic_open().
236 struct epic_tx_desc
{
243 struct epic_rx_desc
{
250 enum desc_status_bits
{
254 #define PRIV_ALIGN 15 /* Required alignment mask */
255 struct epic_private
{
256 struct epic_rx_desc
*rx_ring
;
257 struct epic_tx_desc
*tx_ring
;
258 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
259 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
260 /* The addresses of receive-in-place skbuffs. */
261 struct sk_buff
* rx_skbuff
[RX_RING_SIZE
];
263 dma_addr_t tx_ring_dma
;
264 dma_addr_t rx_ring_dma
;
267 spinlock_t lock
; /* Group with Tx control cache line. */
268 spinlock_t napi_lock
;
269 struct napi_struct napi
;
270 unsigned int reschedule_in_poll
;
271 unsigned int cur_tx
, dirty_tx
;
273 unsigned int cur_rx
, dirty_rx
;
275 unsigned int rx_buf_sz
; /* Based on MTU+slack. */
277 struct pci_dev
*pci_dev
; /* PCI bus location. */
278 int chip_id
, chip_flags
;
280 struct net_device_stats stats
;
281 struct timer_list timer
; /* Media selection timer. */
283 unsigned char mc_filter
[8];
284 signed char phys
[4]; /* MII device addresses. */
285 u16 advertising
; /* NWay media advertisement */
287 struct mii_if_info mii
;
288 unsigned int tx_full
:1; /* The Tx queue is full. */
289 unsigned int default_port
:4; /* Last dev->if_port value. */
292 static int epic_open(struct net_device
*dev
);
293 static int read_eeprom(long ioaddr
, int location
);
294 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
);
295 static void mdio_write(struct net_device
*dev
, int phy_id
, int loc
, int val
);
296 static void epic_restart(struct net_device
*dev
);
297 static void epic_timer(unsigned long data
);
298 static void epic_tx_timeout(struct net_device
*dev
);
299 static void epic_init_ring(struct net_device
*dev
);
300 static netdev_tx_t
epic_start_xmit(struct sk_buff
*skb
,
301 struct net_device
*dev
);
302 static int epic_rx(struct net_device
*dev
, int budget
);
303 static int epic_poll(struct napi_struct
*napi
, int budget
);
304 static irqreturn_t
epic_interrupt(int irq
, void *dev_instance
);
305 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
306 static const struct ethtool_ops netdev_ethtool_ops
;
307 static int epic_close(struct net_device
*dev
);
308 static struct net_device_stats
*epic_get_stats(struct net_device
*dev
);
309 static void set_rx_mode(struct net_device
*dev
);
311 static const struct net_device_ops epic_netdev_ops
= {
312 .ndo_open
= epic_open
,
313 .ndo_stop
= epic_close
,
314 .ndo_start_xmit
= epic_start_xmit
,
315 .ndo_tx_timeout
= epic_tx_timeout
,
316 .ndo_get_stats
= epic_get_stats
,
317 .ndo_set_multicast_list
= set_rx_mode
,
318 .ndo_do_ioctl
= netdev_ioctl
,
319 .ndo_change_mtu
= eth_change_mtu
,
320 .ndo_set_mac_address
= eth_mac_addr
,
321 .ndo_validate_addr
= eth_validate_addr
,
324 static int __devinit
epic_init_one (struct pci_dev
*pdev
,
325 const struct pci_device_id
*ent
)
327 static int card_idx
= -1;
329 int chip_idx
= (int) ent
->driver_data
;
331 struct net_device
*dev
;
332 struct epic_private
*ep
;
333 int i
, ret
, option
= 0, duplex
= 0;
337 /* when built into the kernel, we only print version if device is found */
339 static int printed_version
;
340 if (!printed_version
++)
341 printk(KERN_INFO
"%s%s", version
, version2
);
346 ret
= pci_enable_device(pdev
);
351 if (pci_resource_len(pdev
, 0) < EPIC_TOTAL_SIZE
) {
352 dev_err(&pdev
->dev
, "no PCI region space\n");
354 goto err_out_disable
;
357 pci_set_master(pdev
);
359 ret
= pci_request_regions(pdev
, DRV_NAME
);
361 goto err_out_disable
;
365 dev
= alloc_etherdev(sizeof (*ep
));
367 dev_err(&pdev
->dev
, "no memory for eth device\n");
368 goto err_out_free_res
;
370 SET_NETDEV_DEV(dev
, &pdev
->dev
);
373 ioaddr
= pci_resource_start (pdev
, 0);
375 ioaddr
= pci_resource_start (pdev
, 1);
376 ioaddr
= (long) pci_ioremap_bar(pdev
, 1);
378 dev_err(&pdev
->dev
, "ioremap failed\n");
379 goto err_out_free_netdev
;
383 pci_set_drvdata(pdev
, dev
);
384 ep
= netdev_priv(dev
);
386 ep
->mii
.mdio_read
= mdio_read
;
387 ep
->mii
.mdio_write
= mdio_write
;
388 ep
->mii
.phy_id_mask
= 0x1f;
389 ep
->mii
.reg_num_mask
= 0x1f;
391 ring_space
= pci_alloc_consistent(pdev
, TX_TOTAL_SIZE
, &ring_dma
);
393 goto err_out_iounmap
;
394 ep
->tx_ring
= (struct epic_tx_desc
*)ring_space
;
395 ep
->tx_ring_dma
= ring_dma
;
397 ring_space
= pci_alloc_consistent(pdev
, RX_TOTAL_SIZE
, &ring_dma
);
399 goto err_out_unmap_tx
;
400 ep
->rx_ring
= (struct epic_rx_desc
*)ring_space
;
401 ep
->rx_ring_dma
= ring_dma
;
403 if (dev
->mem_start
) {
404 option
= dev
->mem_start
;
405 duplex
= (dev
->mem_start
& 16) ? 1 : 0;
406 } else if (card_idx
>= 0 && card_idx
< MAX_UNITS
) {
407 if (options
[card_idx
] >= 0)
408 option
= options
[card_idx
];
409 if (full_duplex
[card_idx
] >= 0)
410 duplex
= full_duplex
[card_idx
];
413 dev
->base_addr
= ioaddr
;
416 spin_lock_init(&ep
->lock
);
417 spin_lock_init(&ep
->napi_lock
);
418 ep
->reschedule_in_poll
= 0;
420 /* Bring the chip out of low-power mode. */
421 outl(0x4200, ioaddr
+ GENCTL
);
422 /* Magic?! If we don't set this bit the MII interface won't work. */
423 /* This magic is documented in SMSC app note 7.15 */
424 for (i
= 16; i
> 0; i
--)
425 outl(0x0008, ioaddr
+ TEST1
);
427 /* Turn on the MII transceiver. */
428 outl(0x12, ioaddr
+ MIICfg
);
430 outl((inl(ioaddr
+ NVCTL
) & ~0x003C) | 0x4800, ioaddr
+ NVCTL
);
431 outl(0x0200, ioaddr
+ GENCTL
);
433 /* Note: the '175 does not have a serial EEPROM. */
434 for (i
= 0; i
< 3; i
++)
435 ((__le16
*)dev
->dev_addr
)[i
] = cpu_to_le16(inw(ioaddr
+ LAN0
+ i
*4));
438 dev_printk(KERN_DEBUG
, &pdev
->dev
, "EEPROM contents:\n");
439 for (i
= 0; i
< 64; i
++)
440 printk(" %4.4x%s", read_eeprom(ioaddr
, i
),
441 i
% 16 == 15 ? "\n" : "");
445 ep
->chip_id
= chip_idx
;
446 ep
->chip_flags
= pci_id_tbl
[chip_idx
].drv_flags
;
448 (ep
->chip_flags
& TYPE2_INTR
? PCIBusErr175
: PCIBusErr170
)
449 | CntFull
| TxUnderrun
| EpicNapiEvent
;
451 /* Find the connected MII xcvrs.
452 Doing this in open() would allow detecting external xcvrs later, but
453 takes much time and no cards have external MII. */
455 int phy
, phy_idx
= 0;
456 for (phy
= 1; phy
< 32 && phy_idx
< sizeof(ep
->phys
); phy
++) {
457 int mii_status
= mdio_read(dev
, phy
, MII_BMSR
);
458 if (mii_status
!= 0xffff && mii_status
!= 0x0000) {
459 ep
->phys
[phy_idx
++] = phy
;
461 "MII transceiver #%d control "
462 "%4.4x status %4.4x.\n",
463 phy
, mdio_read(dev
, phy
, 0), mii_status
);
466 ep
->mii_phy_cnt
= phy_idx
;
469 ep
->mii
.advertising
= mdio_read(dev
, phy
, MII_ADVERTISE
);
471 "Autonegotiation advertising %4.4x link "
473 ep
->mii
.advertising
, mdio_read(dev
, phy
, 5));
474 } else if ( ! (ep
->chip_flags
& NO_MII
)) {
476 "***WARNING***: No MII transceiver found!\n");
477 /* Use the known PHY address of the EPII. */
480 ep
->mii
.phy_id
= ep
->phys
[0];
483 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
484 if (ep
->chip_flags
& MII_PWRDWN
)
485 outl(inl(ioaddr
+ NVCTL
) & ~0x483C, ioaddr
+ NVCTL
);
486 outl(0x0008, ioaddr
+ GENCTL
);
488 /* The lower four bits are the media type. */
490 ep
->mii
.force_media
= ep
->mii
.full_duplex
= 1;
491 dev_info(&pdev
->dev
, "Forced full duplex requested.\n");
493 dev
->if_port
= ep
->default_port
= option
;
495 /* The Epic-specific entries in the device structure. */
496 dev
->netdev_ops
= &epic_netdev_ops
;
497 dev
->ethtool_ops
= &netdev_ethtool_ops
;
498 dev
->watchdog_timeo
= TX_TIMEOUT
;
499 netif_napi_add(dev
, &ep
->napi
, epic_poll
, 64);
501 ret
= register_netdev(dev
);
503 goto err_out_unmap_rx
;
505 printk(KERN_INFO
"%s: %s at %#lx, IRQ %d, %pM\n",
506 dev
->name
, pci_id_tbl
[chip_idx
].name
, ioaddr
, dev
->irq
,
513 pci_free_consistent(pdev
, RX_TOTAL_SIZE
, ep
->rx_ring
, ep
->rx_ring_dma
);
515 pci_free_consistent(pdev
, TX_TOTAL_SIZE
, ep
->tx_ring
, ep
->tx_ring_dma
);
523 pci_release_regions(pdev
);
525 pci_disable_device(pdev
);
529 /* Serial EEPROM section. */
531 /* EEPROM_Ctrl bits. */
532 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
533 #define EE_CS 0x02 /* EEPROM chip select. */
534 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
535 #define EE_WRITE_0 0x01
536 #define EE_WRITE_1 0x09
537 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
538 #define EE_ENB (0x0001 | EE_CS)
540 /* Delay between EEPROM clock transitions.
541 This serves to flush the operation to the PCI bus.
544 #define eeprom_delay() inl(ee_addr)
546 /* The EEPROM commands include the alway-set leading bit. */
547 #define EE_WRITE_CMD (5 << 6)
548 #define EE_READ64_CMD (6 << 6)
549 #define EE_READ256_CMD (6 << 8)
550 #define EE_ERASE_CMD (7 << 6)
552 static void epic_disable_int(struct net_device
*dev
, struct epic_private
*ep
)
554 long ioaddr
= dev
->base_addr
;
556 outl(0x00000000, ioaddr
+ INTMASK
);
559 static inline void __epic_pci_commit(long ioaddr
)
562 inl(ioaddr
+ INTMASK
);
566 static inline void epic_napi_irq_off(struct net_device
*dev
,
567 struct epic_private
*ep
)
569 long ioaddr
= dev
->base_addr
;
571 outl(ep
->irq_mask
& ~EpicNapiEvent
, ioaddr
+ INTMASK
);
572 __epic_pci_commit(ioaddr
);
575 static inline void epic_napi_irq_on(struct net_device
*dev
,
576 struct epic_private
*ep
)
578 long ioaddr
= dev
->base_addr
;
580 /* No need to commit possible posted write */
581 outl(ep
->irq_mask
| EpicNapiEvent
, ioaddr
+ INTMASK
);
584 static int __devinit
read_eeprom(long ioaddr
, int location
)
588 long ee_addr
= ioaddr
+ EECTL
;
589 int read_cmd
= location
|
590 (inl(ee_addr
) & 0x40 ? EE_READ64_CMD
: EE_READ256_CMD
);
592 outl(EE_ENB
& ~EE_CS
, ee_addr
);
593 outl(EE_ENB
, ee_addr
);
595 /* Shift the read command bits out. */
596 for (i
= 12; i
>= 0; i
--) {
597 short dataval
= (read_cmd
& (1 << i
)) ? EE_WRITE_1
: EE_WRITE_0
;
598 outl(EE_ENB
| dataval
, ee_addr
);
600 outl(EE_ENB
| dataval
| EE_SHIFT_CLK
, ee_addr
);
603 outl(EE_ENB
, ee_addr
);
605 for (i
= 16; i
> 0; i
--) {
606 outl(EE_ENB
| EE_SHIFT_CLK
, ee_addr
);
608 retval
= (retval
<< 1) | ((inl(ee_addr
) & EE_DATA_READ
) ? 1 : 0);
609 outl(EE_ENB
, ee_addr
);
613 /* Terminate the EEPROM access. */
614 outl(EE_ENB
& ~EE_CS
, ee_addr
);
619 #define MII_WRITEOP 2
620 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
622 long ioaddr
= dev
->base_addr
;
623 int read_cmd
= (phy_id
<< 9) | (location
<< 4) | MII_READOP
;
626 outl(read_cmd
, ioaddr
+ MIICtrl
);
627 /* Typical operation takes 25 loops. */
628 for (i
= 400; i
> 0; i
--) {
630 if ((inl(ioaddr
+ MIICtrl
) & MII_READOP
) == 0) {
631 /* Work around read failure bug. */
632 if (phy_id
== 1 && location
< 6 &&
633 inw(ioaddr
+ MIIData
) == 0xffff) {
634 outl(read_cmd
, ioaddr
+ MIICtrl
);
637 return inw(ioaddr
+ MIIData
);
643 static void mdio_write(struct net_device
*dev
, int phy_id
, int loc
, int value
)
645 long ioaddr
= dev
->base_addr
;
648 outw(value
, ioaddr
+ MIIData
);
649 outl((phy_id
<< 9) | (loc
<< 4) | MII_WRITEOP
, ioaddr
+ MIICtrl
);
650 for (i
= 10000; i
> 0; i
--) {
652 if ((inl(ioaddr
+ MIICtrl
) & MII_WRITEOP
) == 0)
659 static int epic_open(struct net_device
*dev
)
661 struct epic_private
*ep
= netdev_priv(dev
);
662 long ioaddr
= dev
->base_addr
;
666 /* Soft reset the chip. */
667 outl(0x4001, ioaddr
+ GENCTL
);
669 napi_enable(&ep
->napi
);
670 if ((retval
= request_irq(dev
->irq
, epic_interrupt
, IRQF_SHARED
, dev
->name
, dev
))) {
671 napi_disable(&ep
->napi
);
677 outl(0x4000, ioaddr
+ GENCTL
);
678 /* This magic is documented in SMSC app note 7.15 */
679 for (i
= 16; i
> 0; i
--)
680 outl(0x0008, ioaddr
+ TEST1
);
682 /* Pull the chip out of low-power mode, enable interrupts, and set for
683 PCI read multiple. The MIIcfg setting and strange write order are
684 required by the details of which bits are reset and the transceiver
685 wiring on the Ositech CardBus card.
688 outl(dev
->if_port
== 1 ? 0x13 : 0x12, ioaddr
+ MIICfg
);
690 if (ep
->chip_flags
& MII_PWRDWN
)
691 outl((inl(ioaddr
+ NVCTL
) & ~0x003C) | 0x4800, ioaddr
+ NVCTL
);
693 /* Tell the chip to byteswap descriptors on big-endian hosts */
694 #ifdef CONFIG_BIG_ENDIAN
695 outl(0x4432 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
696 inl(ioaddr
+ GENCTL
);
697 outl(0x0432 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
699 outl(0x4412 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
700 inl(ioaddr
+ GENCTL
);
701 outl(0x0412 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
704 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
706 for (i
= 0; i
< 3; i
++)
707 outl(le16_to_cpu(((__le16
*)dev
->dev_addr
)[i
]), ioaddr
+ LAN0
+ i
*4);
709 ep
->tx_threshold
= TX_FIFO_THRESH
;
710 outl(ep
->tx_threshold
, ioaddr
+ TxThresh
);
712 if (media2miictl
[dev
->if_port
& 15]) {
714 mdio_write(dev
, ep
->phys
[0], MII_BMCR
, media2miictl
[dev
->if_port
&15]);
715 if (dev
->if_port
== 1) {
717 printk(KERN_INFO
"%s: Using the 10base2 transceiver, MII "
719 dev
->name
, mdio_read(dev
, ep
->phys
[0], MII_BMSR
));
722 int mii_lpa
= mdio_read(dev
, ep
->phys
[0], MII_LPA
);
723 if (mii_lpa
!= 0xffff) {
724 if ((mii_lpa
& LPA_100FULL
) || (mii_lpa
& 0x01C0) == LPA_10FULL
)
725 ep
->mii
.full_duplex
= 1;
726 else if (! (mii_lpa
& LPA_LPACK
))
727 mdio_write(dev
, ep
->phys
[0], MII_BMCR
, BMCR_ANENABLE
|BMCR_ANRESTART
);
729 printk(KERN_INFO
"%s: Setting %s-duplex based on MII xcvr %d"
730 " register read of %4.4x.\n", dev
->name
,
731 ep
->mii
.full_duplex
? "full" : "half",
732 ep
->phys
[0], mii_lpa
);
736 outl(ep
->mii
.full_duplex
? 0x7F : 0x79, ioaddr
+ TxCtrl
);
737 outl(ep
->rx_ring_dma
, ioaddr
+ PRxCDAR
);
738 outl(ep
->tx_ring_dma
, ioaddr
+ PTxCDAR
);
740 /* Start the chip's Rx process. */
742 outl(StartRx
| RxQueued
, ioaddr
+ COMMAND
);
744 netif_start_queue(dev
);
746 /* Enable interrupts by setting the interrupt mask. */
747 outl((ep
->chip_flags
& TYPE2_INTR
? PCIBusErr175
: PCIBusErr170
)
748 | CntFull
| TxUnderrun
749 | RxError
| RxHeader
| EpicNapiEvent
, ioaddr
+ INTMASK
);
752 printk(KERN_DEBUG
"%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
754 dev
->name
, ioaddr
, dev
->irq
, (int)inl(ioaddr
+ GENCTL
),
755 ep
->mii
.full_duplex
? "full" : "half");
757 /* Set the timer to switch to check for link beat and perhaps switch
758 to an alternate media type. */
759 init_timer(&ep
->timer
);
760 ep
->timer
.expires
= jiffies
+ 3*HZ
;
761 ep
->timer
.data
= (unsigned long)dev
;
762 ep
->timer
.function
= &epic_timer
; /* timer handler */
763 add_timer(&ep
->timer
);
768 /* Reset the chip to recover from a PCI transaction error.
769 This may occur at interrupt time. */
770 static void epic_pause(struct net_device
*dev
)
772 long ioaddr
= dev
->base_addr
;
773 struct epic_private
*ep
= netdev_priv(dev
);
775 netif_stop_queue (dev
);
777 /* Disable interrupts by clearing the interrupt mask. */
778 outl(0x00000000, ioaddr
+ INTMASK
);
779 /* Stop the chip's Tx and Rx DMA processes. */
780 outw(StopRx
| StopTxDMA
| StopRxDMA
, ioaddr
+ COMMAND
);
782 /* Update the error counts. */
783 if (inw(ioaddr
+ COMMAND
) != 0xffff) {
784 ep
->stats
.rx_missed_errors
+= inb(ioaddr
+ MPCNT
);
785 ep
->stats
.rx_frame_errors
+= inb(ioaddr
+ ALICNT
);
786 ep
->stats
.rx_crc_errors
+= inb(ioaddr
+ CRCCNT
);
789 /* Remove the packets on the Rx queue. */
790 epic_rx(dev
, RX_RING_SIZE
);
793 static void epic_restart(struct net_device
*dev
)
795 long ioaddr
= dev
->base_addr
;
796 struct epic_private
*ep
= netdev_priv(dev
);
799 /* Soft reset the chip. */
800 outl(0x4001, ioaddr
+ GENCTL
);
802 printk(KERN_DEBUG
"%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
803 dev
->name
, ep
->cur_rx
, ep
->dirty_rx
, ep
->dirty_tx
, ep
->cur_tx
);
806 /* This magic is documented in SMSC app note 7.15 */
807 for (i
= 16; i
> 0; i
--)
808 outl(0x0008, ioaddr
+ TEST1
);
810 #ifdef CONFIG_BIG_ENDIAN
811 outl(0x0432 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
813 outl(0x0412 | (RX_FIFO_THRESH
<<8), ioaddr
+ GENCTL
);
815 outl(dev
->if_port
== 1 ? 0x13 : 0x12, ioaddr
+ MIICfg
);
816 if (ep
->chip_flags
& MII_PWRDWN
)
817 outl((inl(ioaddr
+ NVCTL
) & ~0x003C) | 0x4800, ioaddr
+ NVCTL
);
819 for (i
= 0; i
< 3; i
++)
820 outl(le16_to_cpu(((__le16
*)dev
->dev_addr
)[i
]), ioaddr
+ LAN0
+ i
*4);
822 ep
->tx_threshold
= TX_FIFO_THRESH
;
823 outl(ep
->tx_threshold
, ioaddr
+ TxThresh
);
824 outl(ep
->mii
.full_duplex
? 0x7F : 0x79, ioaddr
+ TxCtrl
);
825 outl(ep
->rx_ring_dma
+ (ep
->cur_rx
%RX_RING_SIZE
)*
826 sizeof(struct epic_rx_desc
), ioaddr
+ PRxCDAR
);
827 outl(ep
->tx_ring_dma
+ (ep
->dirty_tx
%TX_RING_SIZE
)*
828 sizeof(struct epic_tx_desc
), ioaddr
+ PTxCDAR
);
830 /* Start the chip's Rx process. */
832 outl(StartRx
| RxQueued
, ioaddr
+ COMMAND
);
834 /* Enable interrupts by setting the interrupt mask. */
835 outl((ep
->chip_flags
& TYPE2_INTR
? PCIBusErr175
: PCIBusErr170
)
836 | CntFull
| TxUnderrun
837 | RxError
| RxHeader
| EpicNapiEvent
, ioaddr
+ INTMASK
);
839 printk(KERN_DEBUG
"%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
840 " interrupt %4.4x.\n",
841 dev
->name
, (int)inl(ioaddr
+ COMMAND
), (int)inl(ioaddr
+ GENCTL
),
842 (int)inl(ioaddr
+ INTSTAT
));
846 static void check_media(struct net_device
*dev
)
848 struct epic_private
*ep
= netdev_priv(dev
);
849 long ioaddr
= dev
->base_addr
;
850 int mii_lpa
= ep
->mii_phy_cnt
? mdio_read(dev
, ep
->phys
[0], MII_LPA
) : 0;
851 int negotiated
= mii_lpa
& ep
->mii
.advertising
;
852 int duplex
= (negotiated
& 0x0100) || (negotiated
& 0x01C0) == 0x0040;
854 if (ep
->mii
.force_media
)
856 if (mii_lpa
== 0xffff) /* Bogus read */
858 if (ep
->mii
.full_duplex
!= duplex
) {
859 ep
->mii
.full_duplex
= duplex
;
860 printk(KERN_INFO
"%s: Setting %s-duplex based on MII #%d link"
861 " partner capability of %4.4x.\n", dev
->name
,
862 ep
->mii
.full_duplex
? "full" : "half", ep
->phys
[0], mii_lpa
);
863 outl(ep
->mii
.full_duplex
? 0x7F : 0x79, ioaddr
+ TxCtrl
);
867 static void epic_timer(unsigned long data
)
869 struct net_device
*dev
= (struct net_device
*)data
;
870 struct epic_private
*ep
= netdev_priv(dev
);
871 long ioaddr
= dev
->base_addr
;
872 int next_tick
= 5*HZ
;
875 printk(KERN_DEBUG
"%s: Media monitor tick, Tx status %8.8x.\n",
876 dev
->name
, (int)inl(ioaddr
+ TxSTAT
));
877 printk(KERN_DEBUG
"%s: Other registers are IntMask %4.4x "
878 "IntStatus %4.4x RxStatus %4.4x.\n",
879 dev
->name
, (int)inl(ioaddr
+ INTMASK
),
880 (int)inl(ioaddr
+ INTSTAT
), (int)inl(ioaddr
+ RxSTAT
));
885 ep
->timer
.expires
= jiffies
+ next_tick
;
886 add_timer(&ep
->timer
);
889 static void epic_tx_timeout(struct net_device
*dev
)
891 struct epic_private
*ep
= netdev_priv(dev
);
892 long ioaddr
= dev
->base_addr
;
895 printk(KERN_WARNING
"%s: Transmit timeout using MII device, "
896 "Tx status %4.4x.\n",
897 dev
->name
, (int)inw(ioaddr
+ TxSTAT
));
899 printk(KERN_DEBUG
"%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
900 dev
->name
, ep
->dirty_tx
, ep
->cur_tx
);
903 if (inw(ioaddr
+ TxSTAT
) & 0x10) { /* Tx FIFO underflow. */
904 ep
->stats
.tx_fifo_errors
++;
905 outl(RestartTx
, ioaddr
+ COMMAND
);
908 outl(TxQueued
, dev
->base_addr
+ COMMAND
);
911 dev
->trans_start
= jiffies
; /* prevent tx timeout */
912 ep
->stats
.tx_errors
++;
914 netif_wake_queue(dev
);
917 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
918 static void epic_init_ring(struct net_device
*dev
)
920 struct epic_private
*ep
= netdev_priv(dev
);
924 ep
->dirty_tx
= ep
->cur_tx
= 0;
925 ep
->cur_rx
= ep
->dirty_rx
= 0;
926 ep
->rx_buf_sz
= (dev
->mtu
<= 1500 ? PKT_BUF_SZ
: dev
->mtu
+ 32);
928 /* Initialize all Rx descriptors. */
929 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
930 ep
->rx_ring
[i
].rxstatus
= 0;
931 ep
->rx_ring
[i
].buflength
= ep
->rx_buf_sz
;
932 ep
->rx_ring
[i
].next
= ep
->rx_ring_dma
+
933 (i
+1)*sizeof(struct epic_rx_desc
);
934 ep
->rx_skbuff
[i
] = NULL
;
936 /* Mark the last entry as wrapping the ring. */
937 ep
->rx_ring
[i
-1].next
= ep
->rx_ring_dma
;
939 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
940 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
941 struct sk_buff
*skb
= dev_alloc_skb(ep
->rx_buf_sz
);
942 ep
->rx_skbuff
[i
] = skb
;
945 skb_reserve(skb
, 2); /* 16 byte align the IP header. */
946 ep
->rx_ring
[i
].bufaddr
= pci_map_single(ep
->pci_dev
,
947 skb
->data
, ep
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
948 ep
->rx_ring
[i
].rxstatus
= DescOwn
;
950 ep
->dirty_rx
= (unsigned int)(i
- RX_RING_SIZE
);
952 /* The Tx buffer descriptor is filled in as needed, but we
953 do need to clear the ownership bit. */
954 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
955 ep
->tx_skbuff
[i
] = NULL
;
956 ep
->tx_ring
[i
].txstatus
= 0x0000;
957 ep
->tx_ring
[i
].next
= ep
->tx_ring_dma
+
958 (i
+1)*sizeof(struct epic_tx_desc
);
960 ep
->tx_ring
[i
-1].next
= ep
->tx_ring_dma
;
964 static netdev_tx_t
epic_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
966 struct epic_private
*ep
= netdev_priv(dev
);
967 int entry
, free_count
;
971 if (skb_padto(skb
, ETH_ZLEN
))
974 /* Caution: the write order is important here, set the field with the
975 "ownership" bit last. */
977 /* Calculate the next Tx descriptor entry. */
978 spin_lock_irqsave(&ep
->lock
, flags
);
979 free_count
= ep
->cur_tx
- ep
->dirty_tx
;
980 entry
= ep
->cur_tx
% TX_RING_SIZE
;
982 ep
->tx_skbuff
[entry
] = skb
;
983 ep
->tx_ring
[entry
].bufaddr
= pci_map_single(ep
->pci_dev
, skb
->data
,
984 skb
->len
, PCI_DMA_TODEVICE
);
985 if (free_count
< TX_QUEUE_LEN
/2) {/* Typical path */
986 ctrl_word
= 0x100000; /* No interrupt */
987 } else if (free_count
== TX_QUEUE_LEN
/2) {
988 ctrl_word
= 0x140000; /* Tx-done intr. */
989 } else if (free_count
< TX_QUEUE_LEN
- 1) {
990 ctrl_word
= 0x100000; /* No Tx-done intr. */
992 /* Leave room for an additional entry. */
993 ctrl_word
= 0x140000; /* Tx-done intr. */
996 ep
->tx_ring
[entry
].buflength
= ctrl_word
| skb
->len
;
997 ep
->tx_ring
[entry
].txstatus
=
998 ((skb
->len
>= ETH_ZLEN
? skb
->len
: ETH_ZLEN
) << 16)
1003 netif_stop_queue(dev
);
1005 spin_unlock_irqrestore(&ep
->lock
, flags
);
1006 /* Trigger an immediate transmit demand. */
1007 outl(TxQueued
, dev
->base_addr
+ COMMAND
);
1010 printk(KERN_DEBUG
"%s: Queued Tx packet size %d to slot %d, "
1011 "flag %2.2x Tx status %8.8x.\n",
1012 dev
->name
, (int)skb
->len
, entry
, ctrl_word
,
1013 (int)inl(dev
->base_addr
+ TxSTAT
));
1015 return NETDEV_TX_OK
;
1018 static void epic_tx_error(struct net_device
*dev
, struct epic_private
*ep
,
1021 struct net_device_stats
*stats
= &ep
->stats
;
1023 #ifndef final_version
1024 /* There was an major error, log it. */
1026 printk(KERN_DEBUG
"%s: Transmit error, Tx status %8.8x.\n",
1030 if (status
& 0x1050)
1031 stats
->tx_aborted_errors
++;
1032 if (status
& 0x0008)
1033 stats
->tx_carrier_errors
++;
1034 if (status
& 0x0040)
1035 stats
->tx_window_errors
++;
1036 if (status
& 0x0010)
1037 stats
->tx_fifo_errors
++;
1040 static void epic_tx(struct net_device
*dev
, struct epic_private
*ep
)
1042 unsigned int dirty_tx
, cur_tx
;
1045 * Note: if this lock becomes a problem we can narrow the locked
1046 * region at the cost of occasionally grabbing the lock more times.
1048 cur_tx
= ep
->cur_tx
;
1049 for (dirty_tx
= ep
->dirty_tx
; cur_tx
- dirty_tx
> 0; dirty_tx
++) {
1050 struct sk_buff
*skb
;
1051 int entry
= dirty_tx
% TX_RING_SIZE
;
1052 int txstatus
= ep
->tx_ring
[entry
].txstatus
;
1054 if (txstatus
& DescOwn
)
1055 break; /* It still hasn't been Txed */
1057 if (likely(txstatus
& 0x0001)) {
1058 ep
->stats
.collisions
+= (txstatus
>> 8) & 15;
1059 ep
->stats
.tx_packets
++;
1060 ep
->stats
.tx_bytes
+= ep
->tx_skbuff
[entry
]->len
;
1062 epic_tx_error(dev
, ep
, txstatus
);
1064 /* Free the original skb. */
1065 skb
= ep
->tx_skbuff
[entry
];
1066 pci_unmap_single(ep
->pci_dev
, ep
->tx_ring
[entry
].bufaddr
,
1067 skb
->len
, PCI_DMA_TODEVICE
);
1068 dev_kfree_skb_irq(skb
);
1069 ep
->tx_skbuff
[entry
] = NULL
;
1072 #ifndef final_version
1073 if (cur_tx
- dirty_tx
> TX_RING_SIZE
) {
1075 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1076 dev
->name
, dirty_tx
, cur_tx
, ep
->tx_full
);
1077 dirty_tx
+= TX_RING_SIZE
;
1080 ep
->dirty_tx
= dirty_tx
;
1081 if (ep
->tx_full
&& cur_tx
- dirty_tx
< TX_QUEUE_LEN
- 4) {
1082 /* The ring is no longer full, allow new TX entries. */
1084 netif_wake_queue(dev
);
1088 /* The interrupt handler does all of the Rx thread work and cleans up
1089 after the Tx thread. */
1090 static irqreturn_t
epic_interrupt(int irq
, void *dev_instance
)
1092 struct net_device
*dev
= dev_instance
;
1093 struct epic_private
*ep
= netdev_priv(dev
);
1094 long ioaddr
= dev
->base_addr
;
1095 unsigned int handled
= 0;
1098 status
= inl(ioaddr
+ INTSTAT
);
1099 /* Acknowledge all of the current interrupt sources ASAP. */
1100 outl(status
& EpicNormalEvent
, ioaddr
+ INTSTAT
);
1103 printk(KERN_DEBUG
"%s: Interrupt, status=%#8.8x new "
1104 "intstat=%#8.8x.\n", dev
->name
, status
,
1105 (int)inl(ioaddr
+ INTSTAT
));
1108 if ((status
& IntrSummary
) == 0)
1113 if ((status
& EpicNapiEvent
) && !ep
->reschedule_in_poll
) {
1114 spin_lock(&ep
->napi_lock
);
1115 if (napi_schedule_prep(&ep
->napi
)) {
1116 epic_napi_irq_off(dev
, ep
);
1117 __napi_schedule(&ep
->napi
);
1119 ep
->reschedule_in_poll
++;
1120 spin_unlock(&ep
->napi_lock
);
1122 status
&= ~EpicNapiEvent
;
1124 /* Check uncommon events all at once. */
1125 if (status
& (CntFull
| TxUnderrun
| PCIBusErr170
| PCIBusErr175
)) {
1126 if (status
== EpicRemoved
)
1129 /* Always update the error counts to avoid overhead later. */
1130 ep
->stats
.rx_missed_errors
+= inb(ioaddr
+ MPCNT
);
1131 ep
->stats
.rx_frame_errors
+= inb(ioaddr
+ ALICNT
);
1132 ep
->stats
.rx_crc_errors
+= inb(ioaddr
+ CRCCNT
);
1134 if (status
& TxUnderrun
) { /* Tx FIFO underflow. */
1135 ep
->stats
.tx_fifo_errors
++;
1136 outl(ep
->tx_threshold
+= 128, ioaddr
+ TxThresh
);
1137 /* Restart the transmit process. */
1138 outl(RestartTx
, ioaddr
+ COMMAND
);
1140 if (status
& PCIBusErr170
) {
1141 printk(KERN_ERR
"%s: PCI Bus Error! status %4.4x.\n",
1146 /* Clear all error sources. */
1147 outl(status
& 0x7f18, ioaddr
+ INTSTAT
);
1152 printk(KERN_DEBUG
"%s: exit interrupt, intr_status=%#4.4x.\n",
1156 return IRQ_RETVAL(handled
);
1159 static int epic_rx(struct net_device
*dev
, int budget
)
1161 struct epic_private
*ep
= netdev_priv(dev
);
1162 int entry
= ep
->cur_rx
% RX_RING_SIZE
;
1163 int rx_work_limit
= ep
->dirty_rx
+ RX_RING_SIZE
- ep
->cur_rx
;
1167 printk(KERN_DEBUG
" In epic_rx(), entry %d %8.8x.\n", entry
,
1168 ep
->rx_ring
[entry
].rxstatus
);
1170 if (rx_work_limit
> budget
)
1171 rx_work_limit
= budget
;
1173 /* If we own the next entry, it's a new packet. Send it up. */
1174 while ((ep
->rx_ring
[entry
].rxstatus
& DescOwn
) == 0) {
1175 int status
= ep
->rx_ring
[entry
].rxstatus
;
1178 printk(KERN_DEBUG
" epic_rx() status was %8.8x.\n", status
);
1179 if (--rx_work_limit
< 0)
1181 if (status
& 0x2006) {
1183 printk(KERN_DEBUG
"%s: epic_rx() error status was %8.8x.\n",
1185 if (status
& 0x2000) {
1186 printk(KERN_WARNING
"%s: Oversized Ethernet frame spanned "
1187 "multiple buffers, status %4.4x!\n", dev
->name
, status
);
1188 ep
->stats
.rx_length_errors
++;
1189 } else if (status
& 0x0006)
1190 /* Rx Frame errors are counted in hardware. */
1191 ep
->stats
.rx_errors
++;
1193 /* Malloc up new buffer, compatible with net-2e. */
1194 /* Omit the four octet CRC from the length. */
1195 short pkt_len
= (status
>> 16) - 4;
1196 struct sk_buff
*skb
;
1198 if (pkt_len
> PKT_BUF_SZ
- 4) {
1199 printk(KERN_ERR
"%s: Oversized Ethernet frame, status %x "
1201 dev
->name
, status
, pkt_len
);
1204 /* Check if the packet is long enough to accept without copying
1205 to a minimally-sized skbuff. */
1206 if (pkt_len
< rx_copybreak
&&
1207 (skb
= dev_alloc_skb(pkt_len
+ 2)) != NULL
) {
1208 skb_reserve(skb
, 2); /* 16 byte align the IP header */
1209 pci_dma_sync_single_for_cpu(ep
->pci_dev
,
1210 ep
->rx_ring
[entry
].bufaddr
,
1212 PCI_DMA_FROMDEVICE
);
1213 skb_copy_to_linear_data(skb
, ep
->rx_skbuff
[entry
]->data
, pkt_len
);
1214 skb_put(skb
, pkt_len
);
1215 pci_dma_sync_single_for_device(ep
->pci_dev
,
1216 ep
->rx_ring
[entry
].bufaddr
,
1218 PCI_DMA_FROMDEVICE
);
1220 pci_unmap_single(ep
->pci_dev
,
1221 ep
->rx_ring
[entry
].bufaddr
,
1222 ep
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1223 skb_put(skb
= ep
->rx_skbuff
[entry
], pkt_len
);
1224 ep
->rx_skbuff
[entry
] = NULL
;
1226 skb
->protocol
= eth_type_trans(skb
, dev
);
1227 netif_receive_skb(skb
);
1228 ep
->stats
.rx_packets
++;
1229 ep
->stats
.rx_bytes
+= pkt_len
;
1232 entry
= (++ep
->cur_rx
) % RX_RING_SIZE
;
1235 /* Refill the Rx ring buffers. */
1236 for (; ep
->cur_rx
- ep
->dirty_rx
> 0; ep
->dirty_rx
++) {
1237 entry
= ep
->dirty_rx
% RX_RING_SIZE
;
1238 if (ep
->rx_skbuff
[entry
] == NULL
) {
1239 struct sk_buff
*skb
;
1240 skb
= ep
->rx_skbuff
[entry
] = dev_alloc_skb(ep
->rx_buf_sz
);
1243 skb_reserve(skb
, 2); /* Align IP on 16 byte boundaries */
1244 ep
->rx_ring
[entry
].bufaddr
= pci_map_single(ep
->pci_dev
,
1245 skb
->data
, ep
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1248 /* AV: shouldn't we add a barrier here? */
1249 ep
->rx_ring
[entry
].rxstatus
= DescOwn
;
1254 static void epic_rx_err(struct net_device
*dev
, struct epic_private
*ep
)
1256 long ioaddr
= dev
->base_addr
;
1259 status
= inl(ioaddr
+ INTSTAT
);
1261 if (status
== EpicRemoved
)
1263 if (status
& RxOverflow
) /* Missed a Rx frame. */
1264 ep
->stats
.rx_errors
++;
1265 if (status
& (RxOverflow
| RxFull
))
1266 outw(RxQueued
, ioaddr
+ COMMAND
);
1269 static int epic_poll(struct napi_struct
*napi
, int budget
)
1271 struct epic_private
*ep
= container_of(napi
, struct epic_private
, napi
);
1272 struct net_device
*dev
= ep
->mii
.dev
;
1274 long ioaddr
= dev
->base_addr
;
1280 work_done
+= epic_rx(dev
, budget
);
1282 epic_rx_err(dev
, ep
);
1284 if (work_done
< budget
) {
1285 unsigned long flags
;
1288 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1290 spin_lock_irqsave(&ep
->napi_lock
, flags
);
1292 more
= ep
->reschedule_in_poll
;
1294 __napi_complete(napi
);
1295 outl(EpicNapiEvent
, ioaddr
+ INTSTAT
);
1296 epic_napi_irq_on(dev
, ep
);
1298 ep
->reschedule_in_poll
--;
1300 spin_unlock_irqrestore(&ep
->napi_lock
, flags
);
1309 static int epic_close(struct net_device
*dev
)
1311 long ioaddr
= dev
->base_addr
;
1312 struct epic_private
*ep
= netdev_priv(dev
);
1313 struct sk_buff
*skb
;
1316 netif_stop_queue(dev
);
1317 napi_disable(&ep
->napi
);
1320 printk(KERN_DEBUG
"%s: Shutting down ethercard, status was %2.2x.\n",
1321 dev
->name
, (int)inl(ioaddr
+ INTSTAT
));
1323 del_timer_sync(&ep
->timer
);
1325 epic_disable_int(dev
, ep
);
1327 free_irq(dev
->irq
, dev
);
1331 /* Free all the skbuffs in the Rx queue. */
1332 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1333 skb
= ep
->rx_skbuff
[i
];
1334 ep
->rx_skbuff
[i
] = NULL
;
1335 ep
->rx_ring
[i
].rxstatus
= 0; /* Not owned by Epic chip. */
1336 ep
->rx_ring
[i
].buflength
= 0;
1338 pci_unmap_single(ep
->pci_dev
, ep
->rx_ring
[i
].bufaddr
,
1339 ep
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1342 ep
->rx_ring
[i
].bufaddr
= 0xBADF00D0; /* An invalid address. */
1344 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1345 skb
= ep
->tx_skbuff
[i
];
1346 ep
->tx_skbuff
[i
] = NULL
;
1349 pci_unmap_single(ep
->pci_dev
, ep
->tx_ring
[i
].bufaddr
,
1350 skb
->len
, PCI_DMA_TODEVICE
);
1354 /* Green! Leave the chip in low-power mode. */
1355 outl(0x0008, ioaddr
+ GENCTL
);
1360 static struct net_device_stats
*epic_get_stats(struct net_device
*dev
)
1362 struct epic_private
*ep
= netdev_priv(dev
);
1363 long ioaddr
= dev
->base_addr
;
1365 if (netif_running(dev
)) {
1366 /* Update the error counts. */
1367 ep
->stats
.rx_missed_errors
+= inb(ioaddr
+ MPCNT
);
1368 ep
->stats
.rx_frame_errors
+= inb(ioaddr
+ ALICNT
);
1369 ep
->stats
.rx_crc_errors
+= inb(ioaddr
+ CRCCNT
);
1375 /* Set or clear the multicast filter for this adaptor.
1376 Note that we only use exclusion around actually queueing the
1377 new frame, not around filling ep->setup_frame. This is non-deterministic
1378 when re-entered but still correct. */
1380 static void set_rx_mode(struct net_device
*dev
)
1382 long ioaddr
= dev
->base_addr
;
1383 struct epic_private
*ep
= netdev_priv(dev
);
1384 unsigned char mc_filter
[8]; /* Multicast hash filter */
1387 if (dev
->flags
& IFF_PROMISC
) { /* Set promiscuous. */
1388 outl(0x002C, ioaddr
+ RxCtrl
);
1389 /* Unconditionally log net taps. */
1390 memset(mc_filter
, 0xff, sizeof(mc_filter
));
1391 } else if ((!netdev_mc_empty(dev
)) || (dev
->flags
& IFF_ALLMULTI
)) {
1392 /* There is apparently a chip bug, so the multicast filter
1393 is never enabled. */
1394 /* Too many to filter perfectly -- accept all multicasts. */
1395 memset(mc_filter
, 0xff, sizeof(mc_filter
));
1396 outl(0x000C, ioaddr
+ RxCtrl
);
1397 } else if (netdev_mc_empty(dev
)) {
1398 outl(0x0004, ioaddr
+ RxCtrl
);
1400 } else { /* Never executed, for now. */
1401 struct netdev_hw_addr
*ha
;
1403 memset(mc_filter
, 0, sizeof(mc_filter
));
1404 netdev_for_each_mc_addr(ha
, dev
) {
1405 unsigned int bit_nr
=
1406 ether_crc_le(ETH_ALEN
, ha
->addr
) & 0x3f;
1407 mc_filter
[bit_nr
>> 3] |= (1 << bit_nr
);
1410 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1411 if (memcmp(mc_filter
, ep
->mc_filter
, sizeof(mc_filter
))) {
1412 for (i
= 0; i
< 4; i
++)
1413 outw(((u16
*)mc_filter
)[i
], ioaddr
+ MC0
+ i
*4);
1414 memcpy(ep
->mc_filter
, mc_filter
, sizeof(mc_filter
));
1419 static void netdev_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1421 struct epic_private
*np
= netdev_priv(dev
);
1423 strcpy (info
->driver
, DRV_NAME
);
1424 strcpy (info
->version
, DRV_VERSION
);
1425 strcpy (info
->bus_info
, pci_name(np
->pci_dev
));
1428 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1430 struct epic_private
*np
= netdev_priv(dev
);
1433 spin_lock_irq(&np
->lock
);
1434 rc
= mii_ethtool_gset(&np
->mii
, cmd
);
1435 spin_unlock_irq(&np
->lock
);
1440 static int netdev_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1442 struct epic_private
*np
= netdev_priv(dev
);
1445 spin_lock_irq(&np
->lock
);
1446 rc
= mii_ethtool_sset(&np
->mii
, cmd
);
1447 spin_unlock_irq(&np
->lock
);
1452 static int netdev_nway_reset(struct net_device
*dev
)
1454 struct epic_private
*np
= netdev_priv(dev
);
1455 return mii_nway_restart(&np
->mii
);
1458 static u32
netdev_get_link(struct net_device
*dev
)
1460 struct epic_private
*np
= netdev_priv(dev
);
1461 return mii_link_ok(&np
->mii
);
1464 static u32
netdev_get_msglevel(struct net_device
*dev
)
1469 static void netdev_set_msglevel(struct net_device
*dev
, u32 value
)
1474 static int ethtool_begin(struct net_device
*dev
)
1476 unsigned long ioaddr
= dev
->base_addr
;
1477 /* power-up, if interface is down */
1478 if (! netif_running(dev
)) {
1479 outl(0x0200, ioaddr
+ GENCTL
);
1480 outl((inl(ioaddr
+ NVCTL
) & ~0x003C) | 0x4800, ioaddr
+ NVCTL
);
1485 static void ethtool_complete(struct net_device
*dev
)
1487 unsigned long ioaddr
= dev
->base_addr
;
1488 /* power-down, if interface is down */
1489 if (! netif_running(dev
)) {
1490 outl(0x0008, ioaddr
+ GENCTL
);
1491 outl((inl(ioaddr
+ NVCTL
) & ~0x483C) | 0x0000, ioaddr
+ NVCTL
);
1495 static const struct ethtool_ops netdev_ethtool_ops
= {
1496 .get_drvinfo
= netdev_get_drvinfo
,
1497 .get_settings
= netdev_get_settings
,
1498 .set_settings
= netdev_set_settings
,
1499 .nway_reset
= netdev_nway_reset
,
1500 .get_link
= netdev_get_link
,
1501 .get_msglevel
= netdev_get_msglevel
,
1502 .set_msglevel
= netdev_set_msglevel
,
1503 .begin
= ethtool_begin
,
1504 .complete
= ethtool_complete
1507 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1509 struct epic_private
*np
= netdev_priv(dev
);
1510 long ioaddr
= dev
->base_addr
;
1511 struct mii_ioctl_data
*data
= if_mii(rq
);
1514 /* power-up, if interface is down */
1515 if (! netif_running(dev
)) {
1516 outl(0x0200, ioaddr
+ GENCTL
);
1517 outl((inl(ioaddr
+ NVCTL
) & ~0x003C) | 0x4800, ioaddr
+ NVCTL
);
1520 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1521 spin_lock_irq(&np
->lock
);
1522 rc
= generic_mii_ioctl(&np
->mii
, data
, cmd
, NULL
);
1523 spin_unlock_irq(&np
->lock
);
1525 /* power-down, if interface is down */
1526 if (! netif_running(dev
)) {
1527 outl(0x0008, ioaddr
+ GENCTL
);
1528 outl((inl(ioaddr
+ NVCTL
) & ~0x483C) | 0x0000, ioaddr
+ NVCTL
);
1534 static void __devexit
epic_remove_one (struct pci_dev
*pdev
)
1536 struct net_device
*dev
= pci_get_drvdata(pdev
);
1537 struct epic_private
*ep
= netdev_priv(dev
);
1539 pci_free_consistent(pdev
, TX_TOTAL_SIZE
, ep
->tx_ring
, ep
->tx_ring_dma
);
1540 pci_free_consistent(pdev
, RX_TOTAL_SIZE
, ep
->rx_ring
, ep
->rx_ring_dma
);
1541 unregister_netdev(dev
);
1543 iounmap((void*) dev
->base_addr
);
1545 pci_release_regions(pdev
);
1547 pci_disable_device(pdev
);
1548 pci_set_drvdata(pdev
, NULL
);
1549 /* pci_power_off(pdev, -1); */
1555 static int epic_suspend (struct pci_dev
*pdev
, pm_message_t state
)
1557 struct net_device
*dev
= pci_get_drvdata(pdev
);
1558 long ioaddr
= dev
->base_addr
;
1560 if (!netif_running(dev
))
1563 /* Put the chip into low-power mode. */
1564 outl(0x0008, ioaddr
+ GENCTL
);
1565 /* pci_power_off(pdev, -1); */
1570 static int epic_resume (struct pci_dev
*pdev
)
1572 struct net_device
*dev
= pci_get_drvdata(pdev
);
1574 if (!netif_running(dev
))
1577 /* pci_power_on(pdev); */
1581 #endif /* CONFIG_PM */
1584 static struct pci_driver epic_driver
= {
1586 .id_table
= epic_pci_tbl
,
1587 .probe
= epic_init_one
,
1588 .remove
= __devexit_p(epic_remove_one
),
1590 .suspend
= epic_suspend
,
1591 .resume
= epic_resume
,
1592 #endif /* CONFIG_PM */
1596 static int __init
epic_init (void)
1598 /* when a module, this is printed whether or not devices are found in probe */
1600 printk (KERN_INFO
"%s%s",
1604 return pci_register_driver(&epic_driver
);
1608 static void __exit
epic_cleanup (void)
1610 pci_unregister_driver (&epic_driver
);
1614 module_init(epic_init
);
1615 module_exit(epic_cleanup
);