2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 * Copyright © 2005 Agere Systems Inc.
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
10 *------------------------------------------------------------------------------
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/pci.h>
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/kernel.h>
61 #include <linux/sched.h>
62 #include <linux/ptrace.h>
63 #include <linux/slab.h>
64 #include <linux/ctype.h>
65 #include <linux/string.h>
66 #include <linux/timer.h>
67 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/bitops.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_arp.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/phy.h>
84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
86 MODULE_LICENSE("Dual BSD/GPL");
87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
90 #define MAX_NUM_REGISTER_POLLS 1000
91 #define MAX_NUM_WRITE_RETRIES 2
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
98 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
99 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
102 /* For interrupts, normal running is:
103 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104 * watchdog_interrupt & txdma_xfer_done
106 * In both cases, when flow control is enabled for either Tx or bi-direction,
107 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108 * buffer rings are running low.
110 #define INT_MASK_DISABLE 0xffffffff
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113 * #define INT_MASK_ENABLE 0xfff6bf17
114 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
116 #define INT_MASK_ENABLE 0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE 60
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST 128
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
134 #define ET131X_TX_TIMEOUT (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
137 /* MP_ADAPTER flags */
138 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
140 /* MP_SHARED flags */
141 #define FMP_ADAPTER_LOWER_POWER 0x00200000
143 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
144 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
146 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
148 /* Some offsets in PCI config space that are actually used. */
149 #define ET1310_PCI_MAC_ADDRESS 0xA4
150 #define ET1310_PCI_EEPROM_STATUS 0xB2
151 #define ET1310_PCI_ACK_NACK 0xC0
152 #define ET1310_PCI_REPLAY 0xC2
153 #define ET1310_PCI_L0L1LATENCY 0xCF
155 /* PCI Product IDs */
156 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
157 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
159 /* Define order of magnitude converter */
160 #define NANO_IN_A_MICRO 1000
162 #define PARM_RX_NUM_BUFS_DEF 4
163 #define PARM_RX_TIME_INT_DEF 10
164 #define PARM_RX_MEM_END_DEF 0x2bc
165 #define PARM_TX_TIME_INT_DEF 40
166 #define PARM_TX_NUM_BUFS_DEF 4
167 #define PARM_DMA_CACHE_DEF 0
170 #define FBR_CHUNKS 32
171 #define MAX_DESC_PER_RING_RX 1024
173 /* number of RFDs - default and min */
174 #define RFD_LOW_WATER_MARK 40
175 #define NIC_DEFAULT_NUM_RFD 1024
178 #define MAX_PACKETS_HANDLED 256
179 #define ET131X_MIN_MTU 64
180 #define ET131X_MAX_MTU 9216
182 #define ALCATEL_MULTICAST_PKT 0x01000000
183 #define ALCATEL_BROADCAST_PKT 0x02000000
185 /* typedefs for Free Buffer Descriptors */
189 u32 word2
; /* Bits 10-31 reserved, 0-9 descriptor */
192 /* Packet Status Ring Descriptors
196 * top 16 bits are from the Alcatel Status Word as enumerated in
197 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
200 * 1: ipa IP checksum assist
201 * 2: ipp IP checksum pass
202 * 3: tcpa TCP checksum assist
203 * 4: tcpp TCP checksum pass
205 * 6: rxmac_error RXMAC Error Indicator
206 * 7: drop Drop packet
207 * 8: ft Frame Truncated
211 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
212 * 17: asw_RX_DV_event short receive event detected
213 * 18: asw_false_carrier_event bad carrier since last good packet
214 * 19: asw_code_err one or more nibbles signalled as errors
215 * 20: asw_CRC_err CRC error
216 * 21: asw_len_chk_err frame length field incorrect
217 * 22: asw_too_long frame length > 1518 bytes
218 * 23: asw_OK valid CRC + no code error
219 * 24: asw_multicast has a multicast address
220 * 25: asw_broadcast has a broadcast address
221 * 26: asw_dribble_nibble spurious bits after EOP
222 * 27: asw_control_frame is a control frame
223 * 28: asw_pause_frame is a pause frame
224 * 29: asw_unsupported_op unsupported OP code
225 * 30: asw_VLAN_tag VLAN tag detected
226 * 31: asw_long_evt Rx long event
229 * 0-15: length length in bytes
230 * 16-25: bi Buffer Index
231 * 26-27: ri Ring Index
234 struct pkt_stat_desc
{
239 /* Typedefs for the RX DMA status word */
241 /* rx status word 0 holds part of the status bits of the Rx DMA engine
242 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
243 * which contains the Free Buffer ring 0 and 1 available offset.
245 * bit 0-9 FBR1 offset
246 * bit 10 Wrap flag for FBR1
247 * bit 16-25 FBR0 offset
248 * bit 26 Wrap flag for FBR0
251 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
252 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
253 * which contains the Packet Status Ring available offset.
256 * bit 16-27 PSRoffset
261 /* struct rx_status_block is a structure representing the status of the Rx
262 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
264 struct rx_status_block
{
269 /* Structure for look-up table holding free buffer ring pointers, addresses
273 void *virt
[MAX_DESC_PER_RING_RX
];
274 u32 bus_high
[MAX_DESC_PER_RING_RX
];
275 u32 bus_low
[MAX_DESC_PER_RING_RX
];
277 dma_addr_t ring_physaddr
;
278 void *mem_virtaddrs
[MAX_DESC_PER_RING_RX
/ FBR_CHUNKS
];
279 dma_addr_t mem_physaddrs
[MAX_DESC_PER_RING_RX
/ FBR_CHUNKS
];
285 /* struct rx_ring is the structure representing the adaptor's local
286 * reference(s) to the rings
289 struct fbr_lookup
*fbr
[NUM_FBRS
];
290 void *ps_ring_virtaddr
;
291 dma_addr_t ps_ring_physaddr
;
295 struct rx_status_block
*rx_status_block
;
296 dma_addr_t rx_status_bus
;
298 struct list_head recv_list
;
303 bool unfinished_receives
;
307 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
309 * 0-15: length of packet
312 * 29-31: VLAN priority
314 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
316 * 0: last packet in the sequence
317 * 1: first packet in the sequence
318 * 2: interrupt the processor when this pkt sent
319 * 3: Control word - no packet data
320 * 4: Issue half-duplex backpressure : XON/XOFF
321 * 5: send pause frame
322 * 6: Tx frame has error
326 * 10: Packet is a Huge packet
327 * 11: append VLAN tag
328 * 12: IP checksum assist
329 * 13: TCP checksum assist
330 * 14: UDP checksum assist
332 #define TXDESC_FLAG_LASTPKT 0x0001
333 #define TXDESC_FLAG_FIRSTPKT 0x0002
334 #define TXDESC_FLAG_INTPROC 0x0004
336 /* struct tx_desc represents each descriptor on the ring */
340 u32 len_vlan
; /* control words how to xmit the */
341 u32 flags
; /* data (detailed above) */
344 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
345 * by 0x101c / 0x1020. This is a DMA10 type
348 /* TCB (Transmit Control Block: Host Side) */
350 struct tcb
*next
; /* Next entry in ring */
351 u32 count
; /* Used to spot stuck/lost packets */
352 u32 stale
; /* Used to spot stuck/lost packets */
353 struct sk_buff
*skb
; /* Network skb we are tied to */
354 u32 index
; /* Ring indexes */
358 /* Structure representing our local reference(s) to the ring */
360 /* TCB (Transmit Control Block) memory and lists */
361 struct tcb
*tcb_ring
;
363 /* List of TCBs that are ready to be used */
364 struct tcb
*tcb_qhead
;
365 struct tcb
*tcb_qtail
;
367 /* list of TCBs that are currently being sent. */
368 struct tcb
*send_head
;
369 struct tcb
*send_tail
;
372 /* The actual descriptor ring */
373 struct tx_desc
*tx_desc_ring
;
374 dma_addr_t tx_desc_ring_pa
;
376 /* send_idx indicates where we last wrote to in the descriptor ring. */
379 /* The location of the write-back status block */
381 dma_addr_t tx_status_pa
;
383 /* Packets since the last IRQ: used for interrupt coalescing */
387 /* Do not change these values: if changed, then change also in respective
388 * TXdma and Rxdma engines
390 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
393 /* These values are all superseded by registry entries to facilitate tuning.
394 * Once the desired performance has been achieved, the optimal registry values
395 * should be re-populated to these #defines:
397 #define TX_ERROR_PERIOD 1000
399 #define LO_MARK_PERCENT_FOR_PSR 15
400 #define LO_MARK_PERCENT_FOR_RX 15
402 /* RFD (Receive Frame Descriptor) */
404 struct list_head list_node
;
406 u32 len
; /* total size of receive frame */
413 #define FLOW_TXONLY 1
414 #define FLOW_RXONLY 2
417 /* Struct to define some device statistics */
419 u32 multicast_pkts_rcvd
;
420 u32 rcvd_pkts_dropped
;
424 u32 tx_excessive_collisions
;
425 u32 tx_first_collisions
;
426 u32 tx_late_collisions
;
434 u32 rx_code_violations
;
437 u32 interrupt_status
;
440 /* The private adapter structure */
441 struct et131x_adapter
{
442 struct net_device
*netdev
;
443 struct pci_dev
*pdev
;
444 struct mii_bus
*mii_bus
;
445 struct napi_struct napi
;
447 /* Flags that indicate current state of the adapter */
450 /* local link state, to determine if a state change has occurred */
454 u8 rom_addr
[ETH_ALEN
];
459 spinlock_t tcb_send_qlock
; /* protects the tx_ring send tcb list */
460 spinlock_t tcb_ready_qlock
; /* protects the tx_ring ready tcb list */
461 spinlock_t rcv_lock
; /* protects the rx_ring receive list */
463 /* Packet Filter and look ahead size */
467 u32 multicast_addr_count
;
468 u8 multicast_list
[NIC_MAX_MCAST_LIST
][ETH_ALEN
];
470 /* Pointer to the device's PCI register space */
471 struct address_map __iomem
*regs
;
473 /* Registry parameters */
474 u8 wanted_flow
; /* Flow we want for 802.3x flow control */
475 u32 registry_jumbo_packet
; /* Max supported ethernet packet size */
477 /* Derived from the registry: */
478 u8 flow
; /* flow control validated by the far-end */
480 /* Minimize init-time */
481 struct timer_list error_timer
;
483 /* variable putting the phy into coma mode when boot up with no cable
484 * plugged in after 5 seconds
488 /* Tx Memory Variables */
489 struct tx_ring tx_ring
;
491 /* Rx Memory Variables */
492 struct rx_ring rx_ring
;
494 struct ce_stats stats
;
497 static int eeprom_wait_ready(struct pci_dev
*pdev
, u32
*status
)
502 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
503 * bits 7,1:0 both equal to 1, at least once after reset.
504 * Subsequent operations need only to check that bits 1:0 are equal
505 * to 1 prior to starting a single byte read/write
507 for (i
= 0; i
< MAX_NUM_REGISTER_POLLS
; i
++) {
508 if (pci_read_config_dword(pdev
, LBCIF_DWORD1_GROUP
, ®
))
511 /* I2C idle and Phy Queue Avail both true */
512 if ((reg
& 0x3000) == 0x3000) {
521 static int eeprom_write(struct et131x_adapter
*adapter
, u32 addr
, u8 data
)
523 struct pci_dev
*pdev
= adapter
->pdev
;
531 /* For an EEPROM, an I2C single byte write is defined as a START
532 * condition followed by the device address, EEPROM address, one byte
533 * of data and a STOP condition. The STOP condition will trigger the
534 * EEPROM's internally timed write cycle to the nonvolatile memory.
535 * All inputs are disabled during this write cycle and the EEPROM will
536 * not respond to any access until the internal write is complete.
538 err
= eeprom_wait_ready(pdev
, NULL
);
542 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
543 * and bits 1:0 both =0. Bit 5 should be set according to the
544 * type of EEPROM being accessed (1=two byte addressing, 0=one
547 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
548 LBCIF_CONTROL_LBCIF_ENABLE
|
549 LBCIF_CONTROL_I2C_WRITE
))
552 /* Prepare EEPROM address for Step 3 */
553 for (retries
= 0; retries
< MAX_NUM_WRITE_RETRIES
; retries
++) {
554 if (pci_write_config_dword(pdev
, LBCIF_ADDRESS_REGISTER
, addr
))
556 /* Write the data to the LBCIF Data Register (the I2C write
559 if (pci_write_config_byte(pdev
, LBCIF_DATA_REGISTER
, data
))
561 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
562 * 1:0 are both equal to 1, the I2C write has completed and the
563 * internal write cycle of the EEPROM is about to start.
564 * (bits 1:0 = 01 is a legal state while waiting from both
565 * equal to 1, but bits 1:0 = 10 is invalid and implies that
566 * something is broken).
568 err
= eeprom_wait_ready(pdev
, &status
);
572 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
573 * an error has occurred.Don't break here if we are revision
574 * 1, this is so we do a blind write for load bug.
576 if ((status
& LBCIF_STATUS_GENERAL_ERROR
) &&
577 adapter
->pdev
->revision
== 0)
580 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
581 * ACK error has occurred on the address phase of the write.
582 * This could be due to an actual hardware failure or the
583 * EEPROM may still be in its internal write cycle from a
584 * previous write. This write operation was ignored and must be
587 if (status
& LBCIF_STATUS_ACK_ERROR
) {
588 /* This could be due to an actual hardware failure
589 * or the EEPROM may still be in its internal write
590 * cycle from a previous write. This write operation
591 * was ignored and must be repeated later.
604 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
605 LBCIF_CONTROL_LBCIF_ENABLE
))
608 /* Do read until internal ACK_ERROR goes away meaning write
612 pci_write_config_dword(pdev
,
613 LBCIF_ADDRESS_REGISTER
,
616 pci_read_config_dword(pdev
,
619 } while ((val
& 0x00010000) == 0);
620 } while (val
& 0x00040000);
622 if ((val
& 0xFF00) != 0xC000 || index
== 10000)
626 return writeok
? 0 : -EIO
;
629 static int eeprom_read(struct et131x_adapter
*adapter
, u32 addr
, u8
*pdata
)
631 struct pci_dev
*pdev
= adapter
->pdev
;
635 /* A single byte read is similar to the single byte write, with the
636 * exception of the data flow:
638 err
= eeprom_wait_ready(pdev
, NULL
);
641 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
642 * and bits 1:0 both =0. Bit 5 should be set according to the type
643 * of EEPROM being accessed (1=two byte addressing, 0=one byte
646 if (pci_write_config_byte(pdev
, LBCIF_CONTROL_REGISTER
,
647 LBCIF_CONTROL_LBCIF_ENABLE
))
649 /* Write the address to the LBCIF Address Register (I2C read will
652 if (pci_write_config_dword(pdev
, LBCIF_ADDRESS_REGISTER
, addr
))
654 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
655 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
658 err
= eeprom_wait_ready(pdev
, &status
);
661 /* Regardless of error status, read data byte from LBCIF Data
666 return (status
& LBCIF_STATUS_ACK_ERROR
) ? -EIO
: 0;
669 static int et131x_init_eeprom(struct et131x_adapter
*adapter
)
671 struct pci_dev
*pdev
= adapter
->pdev
;
674 pci_read_config_byte(pdev
, ET1310_PCI_EEPROM_STATUS
, &eestatus
);
676 /* THIS IS A WORKAROUND:
677 * I need to call this function twice to get my card in a
678 * LG M1 Express Dual running. I tried also a msleep before this
679 * function, because I thought there could be some time conditions
680 * but it didn't work. Call the whole function twice also work.
682 if (pci_read_config_byte(pdev
, ET1310_PCI_EEPROM_STATUS
, &eestatus
)) {
684 "Could not read PCI config space for EEPROM Status\n");
688 /* Determine if the error(s) we care about are present. If they are
689 * present we need to fail.
691 if (eestatus
& 0x4C) {
692 int write_failed
= 0;
694 if (pdev
->revision
== 0x01) {
696 static const u8 eedata
[4] = { 0xFE, 0x13, 0x10, 0xFF };
698 /* Re-write the first 4 bytes if we have an eeprom
699 * present and the revision id is 1, this fixes the
700 * corruption seen with 1310 B Silicon
702 for (i
= 0; i
< 3; i
++)
703 if (eeprom_write(adapter
, i
, eedata
[i
]) < 0)
706 if (pdev
->revision
!= 0x01 || write_failed
) {
708 "Fatal EEPROM Status Error - 0x%04x\n",
711 /* This error could mean that there was an error
712 * reading the eeprom or that the eeprom doesn't exist.
713 * We will treat each case the same and not try to
714 * gather additional information that normally would
715 * come from the eeprom, like MAC Address
717 adapter
->has_eeprom
= 0;
721 adapter
->has_eeprom
= 1;
723 /* Read the EEPROM for information regarding LED behavior. Refer to
724 * et131x_xcvr_init() for its use.
726 eeprom_read(adapter
, 0x70, &adapter
->eeprom_data
[0]);
727 eeprom_read(adapter
, 0x71, &adapter
->eeprom_data
[1]);
729 if (adapter
->eeprom_data
[0] != 0xcd)
730 /* Disable all optional features */
731 adapter
->eeprom_data
[1] = 0x00;
736 static void et131x_rx_dma_enable(struct et131x_adapter
*adapter
)
738 /* Setup the receive dma configuration register for normal operation */
739 u32 csr
= ET_RXDMA_CSR_FBR1_ENABLE
;
740 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
742 if (rx_ring
->fbr
[1]->buffsize
== 4096)
743 csr
|= ET_RXDMA_CSR_FBR1_SIZE_LO
;
744 else if (rx_ring
->fbr
[1]->buffsize
== 8192)
745 csr
|= ET_RXDMA_CSR_FBR1_SIZE_HI
;
746 else if (rx_ring
->fbr
[1]->buffsize
== 16384)
747 csr
|= ET_RXDMA_CSR_FBR1_SIZE_LO
| ET_RXDMA_CSR_FBR1_SIZE_HI
;
749 csr
|= ET_RXDMA_CSR_FBR0_ENABLE
;
750 if (rx_ring
->fbr
[0]->buffsize
== 256)
751 csr
|= ET_RXDMA_CSR_FBR0_SIZE_LO
;
752 else if (rx_ring
->fbr
[0]->buffsize
== 512)
753 csr
|= ET_RXDMA_CSR_FBR0_SIZE_HI
;
754 else if (rx_ring
->fbr
[0]->buffsize
== 1024)
755 csr
|= ET_RXDMA_CSR_FBR0_SIZE_LO
| ET_RXDMA_CSR_FBR0_SIZE_HI
;
756 writel(csr
, &adapter
->regs
->rxdma
.csr
);
758 csr
= readl(&adapter
->regs
->rxdma
.csr
);
759 if (csr
& ET_RXDMA_CSR_HALT_STATUS
) {
761 csr
= readl(&adapter
->regs
->rxdma
.csr
);
762 if (csr
& ET_RXDMA_CSR_HALT_STATUS
) {
763 dev_err(&adapter
->pdev
->dev
,
764 "RX Dma failed to exit halt state. CSR 0x%08x\n",
770 static void et131x_rx_dma_disable(struct et131x_adapter
*adapter
)
773 /* Setup the receive dma configuration register */
774 writel(ET_RXDMA_CSR_HALT
| ET_RXDMA_CSR_FBR1_ENABLE
,
775 &adapter
->regs
->rxdma
.csr
);
776 csr
= readl(&adapter
->regs
->rxdma
.csr
);
777 if (!(csr
& ET_RXDMA_CSR_HALT_STATUS
)) {
779 csr
= readl(&adapter
->regs
->rxdma
.csr
);
780 if (!(csr
& ET_RXDMA_CSR_HALT_STATUS
))
781 dev_err(&adapter
->pdev
->dev
,
782 "RX Dma failed to enter halt state. CSR 0x%08x\n",
787 static void et131x_tx_dma_enable(struct et131x_adapter
*adapter
)
789 /* Setup the transmit dma configuration register for normal
792 writel(ET_TXDMA_SNGL_EPKT
| (PARM_DMA_CACHE_DEF
<< ET_TXDMA_CACHE_SHIFT
),
793 &adapter
->regs
->txdma
.csr
);
796 static inline void add_10bit(u32
*v
, int n
)
798 *v
= INDEX10(*v
+ n
) | (*v
& ET_DMA10_WRAP
);
801 static inline void add_12bit(u32
*v
, int n
)
803 *v
= INDEX12(*v
+ n
) | (*v
& ET_DMA12_WRAP
);
806 static void et1310_config_mac_regs1(struct et131x_adapter
*adapter
)
808 struct mac_regs __iomem
*macregs
= &adapter
->regs
->mac
;
813 /* First we need to reset everything. Write to MAC configuration
814 * register 1 to perform reset.
816 writel(ET_MAC_CFG1_SOFT_RESET
| ET_MAC_CFG1_SIM_RESET
|
817 ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
818 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
,
821 /* Next lets configure the MAC Inter-packet gap register */
822 ipg
= 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
823 ipg
|= 0x50 << 8; /* ifg enforce 0x50 */
824 writel(ipg
, ¯egs
->ipg
);
826 /* Next lets configure the MAC Half Duplex register */
827 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
828 writel(0x00A1F037, ¯egs
->hfdp
);
830 /* Next lets configure the MAC Interface Control register */
831 writel(0, ¯egs
->if_ctrl
);
833 writel(ET_MAC_MIIMGMT_CLK_RST
, ¯egs
->mii_mgmt_cfg
);
835 /* Next lets configure the MAC Station Address register. These
836 * values are read from the EEPROM during initialization and stored
837 * in the adapter structure. We write what is stored in the adapter
838 * structure to the MAC Station Address registers high and low. This
839 * station address is used for generating and checking pause control
842 station2
= (adapter
->addr
[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT
) |
843 (adapter
->addr
[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT
);
844 station1
= (adapter
->addr
[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT
) |
845 (adapter
->addr
[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT
) |
846 (adapter
->addr
[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT
) |
848 writel(station1
, ¯egs
->station_addr_1
);
849 writel(station2
, ¯egs
->station_addr_2
);
851 /* Max ethernet packet in bytes that will be passed by the mac without
852 * being truncated. Allow the MAC to pass 4 more than our max packet
853 * size. This is 4 for the Ethernet CRC.
855 * Packets larger than (registry_jumbo_packet) that do not contain a
856 * VLAN ID will be dropped by the Rx function.
858 writel(adapter
->registry_jumbo_packet
+ 4, ¯egs
->max_fm_len
);
860 /* clear out MAC config reset */
861 writel(0, ¯egs
->cfg1
);
864 static void et1310_config_mac_regs2(struct et131x_adapter
*adapter
)
867 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
868 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
874 ctl
= readl(&adapter
->regs
->txmac
.ctl
);
875 cfg1
= readl(&mac
->cfg1
);
876 cfg2
= readl(&mac
->cfg2
);
877 ifctrl
= readl(&mac
->if_ctrl
);
879 /* Set up the if mode bits */
880 cfg2
&= ~ET_MAC_CFG2_IFMODE_MASK
;
881 if (phydev
->speed
== SPEED_1000
) {
882 cfg2
|= ET_MAC_CFG2_IFMODE_1000
;
883 ifctrl
&= ~ET_MAC_IFCTRL_PHYMODE
;
885 cfg2
|= ET_MAC_CFG2_IFMODE_100
;
886 ifctrl
|= ET_MAC_IFCTRL_PHYMODE
;
889 cfg1
|= ET_MAC_CFG1_RX_ENABLE
| ET_MAC_CFG1_TX_ENABLE
|
892 cfg1
&= ~(ET_MAC_CFG1_LOOPBACK
| ET_MAC_CFG1_RX_FLOW
);
893 if (adapter
->flow
== FLOW_RXONLY
|| adapter
->flow
== FLOW_BOTH
)
894 cfg1
|= ET_MAC_CFG1_RX_FLOW
;
895 writel(cfg1
, &mac
->cfg1
);
897 /* Now we need to initialize the MAC Configuration 2 register */
898 /* preamble 7, check length, huge frame off, pad crc, crc enable
901 cfg2
|= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT
;
902 cfg2
|= ET_MAC_CFG2_IFMODE_LEN_CHECK
;
903 cfg2
|= ET_MAC_CFG2_IFMODE_PAD_CRC
;
904 cfg2
|= ET_MAC_CFG2_IFMODE_CRC_ENABLE
;
905 cfg2
&= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME
;
906 cfg2
&= ~ET_MAC_CFG2_IFMODE_FULL_DPLX
;
908 if (phydev
->duplex
== DUPLEX_FULL
)
909 cfg2
|= ET_MAC_CFG2_IFMODE_FULL_DPLX
;
911 ifctrl
&= ~ET_MAC_IFCTRL_GHDMODE
;
912 if (phydev
->duplex
== DUPLEX_HALF
)
913 ifctrl
|= ET_MAC_IFCTRL_GHDMODE
;
915 writel(ifctrl
, &mac
->if_ctrl
);
916 writel(cfg2
, &mac
->cfg2
);
921 cfg1
= readl(&mac
->cfg1
);
922 } while ((cfg1
& ET_MAC_CFG1_WAIT
) != ET_MAC_CFG1_WAIT
&& delay
< 100);
925 dev_warn(&adapter
->pdev
->dev
,
926 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
930 ctl
|= ET_TX_CTRL_TXMAC_ENABLE
| ET_TX_CTRL_FC_DISABLE
;
931 writel(ctl
, &adapter
->regs
->txmac
.ctl
);
933 if (adapter
->flags
& FMP_ADAPTER_LOWER_POWER
) {
934 et131x_rx_dma_enable(adapter
);
935 et131x_tx_dma_enable(adapter
);
939 static int et1310_in_phy_coma(struct et131x_adapter
*adapter
)
941 u32 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
943 return ET_PM_PHY_SW_COMA
& pmcsr
? 1 : 0;
946 static void et1310_setup_device_for_multicast(struct et131x_adapter
*adapter
)
948 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
955 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
956 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
957 * specified) then we should pass NO multi-cast addresses to the
960 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_MULTICAST
) {
963 /* Loop through our multicast array and set up the device */
964 for (i
= 0; i
< adapter
->multicast_addr_count
; i
++) {
967 result
= ether_crc(6, adapter
->multicast_list
[i
]);
969 result
= (result
& 0x3F800000) >> 23;
972 hash1
|= (1 << result
);
973 } else if ((31 < result
) && (result
< 64)) {
975 hash2
|= (1 << result
);
976 } else if ((63 < result
) && (result
< 96)) {
978 hash3
|= (1 << result
);
981 hash4
|= (1 << result
);
986 /* Write out the new hash to the device */
987 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
988 if (!et1310_in_phy_coma(adapter
)) {
989 writel(hash1
, &rxmac
->multi_hash1
);
990 writel(hash2
, &rxmac
->multi_hash2
);
991 writel(hash3
, &rxmac
->multi_hash3
);
992 writel(hash4
, &rxmac
->multi_hash4
);
996 static void et1310_setup_device_for_unicast(struct et131x_adapter
*adapter
)
998 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
1004 /* Set up unicast packet filter reg 3 to be the first two octets of
1005 * the MAC address for both address
1007 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1008 * MAC address for second address
1010 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1011 * MAC address for first address
1013 uni_pf3
= (adapter
->addr
[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT
) |
1014 (adapter
->addr
[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT
) |
1015 (adapter
->addr
[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT
) |
1018 uni_pf2
= (adapter
->addr
[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT
) |
1019 (adapter
->addr
[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT
) |
1020 (adapter
->addr
[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT
) |
1023 uni_pf1
= (adapter
->addr
[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT
) |
1024 (adapter
->addr
[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT
) |
1025 (adapter
->addr
[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT
) |
1028 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
1029 if (!et1310_in_phy_coma(adapter
)) {
1030 writel(uni_pf1
, &rxmac
->uni_pf_addr1
);
1031 writel(uni_pf2
, &rxmac
->uni_pf_addr2
);
1032 writel(uni_pf3
, &rxmac
->uni_pf_addr3
);
1036 static void et1310_config_rxmac_regs(struct et131x_adapter
*adapter
)
1038 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
1039 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
1045 /* Disable the MAC while it is being configured (also disable WOL) */
1046 writel(0x8, &rxmac
->ctrl
);
1048 /* Initialize WOL to disabled. */
1049 writel(0, &rxmac
->crc0
);
1050 writel(0, &rxmac
->crc12
);
1051 writel(0, &rxmac
->crc34
);
1053 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1054 * its default Values of 0x00000000 because there are not WOL masks
1057 for (wolw
= &rxmac
->mask0_word0
; wolw
<= &rxmac
->mask4_word3
; wolw
++)
1060 /* Lets setup the WOL Source Address */
1061 sa_lo
= (adapter
->addr
[2] << ET_RX_WOL_LO_SA3_SHIFT
) |
1062 (adapter
->addr
[3] << ET_RX_WOL_LO_SA4_SHIFT
) |
1063 (adapter
->addr
[4] << ET_RX_WOL_LO_SA5_SHIFT
) |
1065 writel(sa_lo
, &rxmac
->sa_lo
);
1067 sa_hi
= (u32
)(adapter
->addr
[0] << ET_RX_WOL_HI_SA1_SHIFT
) |
1069 writel(sa_hi
, &rxmac
->sa_hi
);
1071 /* Disable all Packet Filtering */
1072 writel(0, &rxmac
->pf_ctrl
);
1074 /* Let's initialize the Unicast Packet filtering address */
1075 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_DIRECTED
) {
1076 et1310_setup_device_for_unicast(adapter
);
1077 pf_ctrl
|= ET_RX_PFCTRL_UNICST_FILTER_ENABLE
;
1079 writel(0, &rxmac
->uni_pf_addr1
);
1080 writel(0, &rxmac
->uni_pf_addr2
);
1081 writel(0, &rxmac
->uni_pf_addr3
);
1084 /* Let's initialize the Multicast hash */
1085 if (!(adapter
->packet_filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)) {
1086 pf_ctrl
|= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE
;
1087 et1310_setup_device_for_multicast(adapter
);
1090 /* Runt packet filtering. Didn't work in version A silicon. */
1091 pf_ctrl
|= (NIC_MIN_PACKET_SIZE
+ 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT
;
1092 pf_ctrl
|= ET_RX_PFCTRL_FRAG_FILTER_ENABLE
;
1094 if (adapter
->registry_jumbo_packet
> 8192)
1095 /* In order to transmit jumbo packets greater than 8k, the
1096 * FIFO between RxMAC and RxDMA needs to be reduced in size
1097 * to (16k - Jumbo packet size). In order to implement this,
1098 * we must use "cut through" mode in the RxMAC, which chops
1099 * packets down into segments which are (max_size * 16). In
1100 * this case we selected 256 bytes, since this is the size of
1101 * the PCI-Express TLP's that the 1310 uses.
1103 * seg_en on, fc_en off, size 0x10
1105 writel(0x41, &rxmac
->mcif_ctrl_max_seg
);
1107 writel(0, &rxmac
->mcif_ctrl_max_seg
);
1109 writel(0, &rxmac
->mcif_water_mark
);
1110 writel(0, &rxmac
->mif_ctrl
);
1111 writel(0, &rxmac
->space_avail
);
1113 /* Initialize the the mif_ctrl register
1114 * bit 3: Receive code error. One or more nibbles were signaled as
1115 * errors during the reception of the packet. Clear this
1116 * bit in Gigabit, set it in 100Mbit. This was derived
1117 * experimentally at UNH.
1118 * bit 4: Receive CRC error. The packet's CRC did not match the
1119 * internally generated CRC.
1120 * bit 5: Receive length check error. Indicates that frame length
1121 * field value in the packet does not match the actual data
1122 * byte length and is not a type field.
1123 * bit 16: Receive frame truncated.
1124 * bit 17: Drop packet enable
1126 if (phydev
&& phydev
->speed
== SPEED_100
)
1127 writel(0x30038, &rxmac
->mif_ctrl
);
1129 writel(0x30030, &rxmac
->mif_ctrl
);
1131 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1132 * filter is always enabled since it is where the runt packets are
1133 * supposed to be dropped. For version A silicon, runt packet
1134 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1135 * but we still leave the packet filter on.
1137 writel(pf_ctrl
, &rxmac
->pf_ctrl
);
1138 writel(ET_RX_CTRL_RXMAC_ENABLE
| ET_RX_CTRL_WOL_DISABLE
, &rxmac
->ctrl
);
1141 static void et1310_config_txmac_regs(struct et131x_adapter
*adapter
)
1143 struct txmac_regs __iomem
*txmac
= &adapter
->regs
->txmac
;
1145 /* We need to update the Control Frame Parameters
1146 * cfpt - control frame pause timer set to 64 (0x40)
1147 * cfep - control frame extended pause timer set to 0x0
1149 if (adapter
->flow
== FLOW_NONE
)
1150 writel(0, &txmac
->cf_param
);
1152 writel(0x40, &txmac
->cf_param
);
1155 static void et1310_config_macstat_regs(struct et131x_adapter
*adapter
)
1157 struct macstat_regs __iomem
*macstat
= &adapter
->regs
->macstat
;
1160 /* initialize all the macstat registers to zero on the device */
1161 for (reg
= &macstat
->txrx_0_64_byte_frames
;
1162 reg
<= &macstat
->carry_reg2
; reg
++)
1165 /* Unmask any counters that we want to track the overflow of.
1166 * Initially this will be all counters. It may become clear later
1167 * that we do not need to track all counters.
1169 writel(0xFFFFBE32, &macstat
->carry_reg1_mask
);
1170 writel(0xFFFE7E8B, &macstat
->carry_reg2_mask
);
1173 static int et131x_phy_mii_read(struct et131x_adapter
*adapter
, u8 addr
,
1176 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
1183 /* Save a local copy of the registers we are dealing with so we can
1186 mii_addr
= readl(&mac
->mii_mgmt_addr
);
1187 mii_cmd
= readl(&mac
->mii_mgmt_cmd
);
1189 /* Stop the current operation */
1190 writel(0, &mac
->mii_mgmt_cmd
);
1192 /* Set up the register we need to read from on the correct PHY */
1193 writel(ET_MAC_MII_ADDR(addr
, reg
), &mac
->mii_mgmt_addr
);
1195 writel(0x1, &mac
->mii_mgmt_cmd
);
1200 mii_indicator
= readl(&mac
->mii_mgmt_indicator
);
1201 } while ((mii_indicator
& ET_MAC_MGMT_WAIT
) && delay
< 50);
1203 /* If we hit the max delay, we could not read the register */
1205 dev_warn(&adapter
->pdev
->dev
,
1206 "reg 0x%08x could not be read\n", reg
);
1207 dev_warn(&adapter
->pdev
->dev
, "status is 0x%08x\n",
1214 /* If we hit here we were able to read the register and we need to
1215 * return the value to the caller
1217 *value
= readl(&mac
->mii_mgmt_stat
) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK
;
1220 /* Stop the read operation */
1221 writel(0, &mac
->mii_mgmt_cmd
);
1223 /* set the registers we touched back to the state at which we entered
1226 writel(mii_addr
, &mac
->mii_mgmt_addr
);
1227 writel(mii_cmd
, &mac
->mii_mgmt_cmd
);
1232 static int et131x_mii_read(struct et131x_adapter
*adapter
, u8 reg
, u16
*value
)
1234 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
1239 return et131x_phy_mii_read(adapter
, phydev
->mdio
.addr
, reg
, value
);
1242 static int et131x_mii_write(struct et131x_adapter
*adapter
, u8 addr
, u8 reg
,
1245 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
1252 /* Save a local copy of the registers we are dealing with so we can
1255 mii_addr
= readl(&mac
->mii_mgmt_addr
);
1256 mii_cmd
= readl(&mac
->mii_mgmt_cmd
);
1258 /* Stop the current operation */
1259 writel(0, &mac
->mii_mgmt_cmd
);
1261 /* Set up the register we need to write to on the correct PHY */
1262 writel(ET_MAC_MII_ADDR(addr
, reg
), &mac
->mii_mgmt_addr
);
1264 /* Add the value to write to the registers to the mac */
1265 writel(value
, &mac
->mii_mgmt_ctrl
);
1270 mii_indicator
= readl(&mac
->mii_mgmt_indicator
);
1271 } while ((mii_indicator
& ET_MAC_MGMT_BUSY
) && delay
< 100);
1273 /* If we hit the max delay, we could not write the register */
1277 dev_warn(&adapter
->pdev
->dev
,
1278 "reg 0x%08x could not be written", reg
);
1279 dev_warn(&adapter
->pdev
->dev
, "status is 0x%08x\n",
1281 dev_warn(&adapter
->pdev
->dev
, "command is 0x%08x\n",
1282 readl(&mac
->mii_mgmt_cmd
));
1284 et131x_mii_read(adapter
, reg
, &tmp
);
1288 /* Stop the write operation */
1289 writel(0, &mac
->mii_mgmt_cmd
);
1291 /* set the registers we touched back to the state at which we entered
1294 writel(mii_addr
, &mac
->mii_mgmt_addr
);
1295 writel(mii_cmd
, &mac
->mii_mgmt_cmd
);
1300 static void et1310_phy_read_mii_bit(struct et131x_adapter
*adapter
,
1306 u16 mask
= 1 << bitnum
;
1308 et131x_mii_read(adapter
, regnum
, ®
);
1310 *value
= (reg
& mask
) >> bitnum
;
1313 static void et1310_config_flow_control(struct et131x_adapter
*adapter
)
1315 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
1317 if (phydev
->duplex
== DUPLEX_HALF
) {
1318 adapter
->flow
= FLOW_NONE
;
1320 char remote_pause
, remote_async_pause
;
1322 et1310_phy_read_mii_bit(adapter
, 5, 10, &remote_pause
);
1323 et1310_phy_read_mii_bit(adapter
, 5, 11, &remote_async_pause
);
1325 if (remote_pause
&& remote_async_pause
) {
1326 adapter
->flow
= adapter
->wanted_flow
;
1327 } else if (remote_pause
&& !remote_async_pause
) {
1328 if (adapter
->wanted_flow
== FLOW_BOTH
)
1329 adapter
->flow
= FLOW_BOTH
;
1331 adapter
->flow
= FLOW_NONE
;
1332 } else if (!remote_pause
&& !remote_async_pause
) {
1333 adapter
->flow
= FLOW_NONE
;
1335 if (adapter
->wanted_flow
== FLOW_BOTH
)
1336 adapter
->flow
= FLOW_RXONLY
;
1338 adapter
->flow
= FLOW_NONE
;
1343 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1344 static void et1310_update_macstat_host_counters(struct et131x_adapter
*adapter
)
1346 struct ce_stats
*stats
= &adapter
->stats
;
1347 struct macstat_regs __iomem
*macstat
=
1348 &adapter
->regs
->macstat
;
1350 stats
->tx_collisions
+= readl(&macstat
->tx_total_collisions
);
1351 stats
->tx_first_collisions
+= readl(&macstat
->tx_single_collisions
);
1352 stats
->tx_deferred
+= readl(&macstat
->tx_deferred
);
1353 stats
->tx_excessive_collisions
+=
1354 readl(&macstat
->tx_multiple_collisions
);
1355 stats
->tx_late_collisions
+= readl(&macstat
->tx_late_collisions
);
1356 stats
->tx_underflows
+= readl(&macstat
->tx_undersize_frames
);
1357 stats
->tx_max_pkt_errs
+= readl(&macstat
->tx_oversize_frames
);
1359 stats
->rx_align_errs
+= readl(&macstat
->rx_align_errs
);
1360 stats
->rx_crc_errs
+= readl(&macstat
->rx_code_errs
);
1361 stats
->rcvd_pkts_dropped
+= readl(&macstat
->rx_drops
);
1362 stats
->rx_overflows
+= readl(&macstat
->rx_oversize_packets
);
1363 stats
->rx_code_violations
+= readl(&macstat
->rx_fcs_errs
);
1364 stats
->rx_length_errs
+= readl(&macstat
->rx_frame_len_errs
);
1365 stats
->rx_other_errs
+= readl(&macstat
->rx_fragment_packets
);
1368 /* et1310_handle_macstat_interrupt
1370 * One of the MACSTAT counters has wrapped. Update the local copy of
1371 * the statistics held in the adapter structure, checking the "wrap"
1372 * bit for each counter.
1374 static void et1310_handle_macstat_interrupt(struct et131x_adapter
*adapter
)
1379 /* Read the interrupt bits from the register(s). These are Clear On
1382 carry_reg1
= readl(&adapter
->regs
->macstat
.carry_reg1
);
1383 carry_reg2
= readl(&adapter
->regs
->macstat
.carry_reg2
);
1385 writel(carry_reg1
, &adapter
->regs
->macstat
.carry_reg1
);
1386 writel(carry_reg2
, &adapter
->regs
->macstat
.carry_reg2
);
1388 /* We need to do update the host copy of all the MAC_STAT counters.
1389 * For each counter, check it's overflow bit. If the overflow bit is
1390 * set, then increment the host version of the count by one complete
1391 * revolution of the counter. This routine is called when the counter
1392 * block indicates that one of the counters has wrapped.
1394 if (carry_reg1
& (1 << 14))
1395 adapter
->stats
.rx_code_violations
+= COUNTER_WRAP_16_BIT
;
1396 if (carry_reg1
& (1 << 8))
1397 adapter
->stats
.rx_align_errs
+= COUNTER_WRAP_12_BIT
;
1398 if (carry_reg1
& (1 << 7))
1399 adapter
->stats
.rx_length_errs
+= COUNTER_WRAP_16_BIT
;
1400 if (carry_reg1
& (1 << 2))
1401 adapter
->stats
.rx_other_errs
+= COUNTER_WRAP_16_BIT
;
1402 if (carry_reg1
& (1 << 6))
1403 adapter
->stats
.rx_crc_errs
+= COUNTER_WRAP_16_BIT
;
1404 if (carry_reg1
& (1 << 3))
1405 adapter
->stats
.rx_overflows
+= COUNTER_WRAP_16_BIT
;
1406 if (carry_reg1
& (1 << 0))
1407 adapter
->stats
.rcvd_pkts_dropped
+= COUNTER_WRAP_16_BIT
;
1408 if (carry_reg2
& (1 << 16))
1409 adapter
->stats
.tx_max_pkt_errs
+= COUNTER_WRAP_12_BIT
;
1410 if (carry_reg2
& (1 << 15))
1411 adapter
->stats
.tx_underflows
+= COUNTER_WRAP_12_BIT
;
1412 if (carry_reg2
& (1 << 6))
1413 adapter
->stats
.tx_first_collisions
+= COUNTER_WRAP_12_BIT
;
1414 if (carry_reg2
& (1 << 8))
1415 adapter
->stats
.tx_deferred
+= COUNTER_WRAP_12_BIT
;
1416 if (carry_reg2
& (1 << 5))
1417 adapter
->stats
.tx_excessive_collisions
+= COUNTER_WRAP_12_BIT
;
1418 if (carry_reg2
& (1 << 4))
1419 adapter
->stats
.tx_late_collisions
+= COUNTER_WRAP_12_BIT
;
1420 if (carry_reg2
& (1 << 2))
1421 adapter
->stats
.tx_collisions
+= COUNTER_WRAP_12_BIT
;
1424 static int et131x_mdio_read(struct mii_bus
*bus
, int phy_addr
, int reg
)
1426 struct net_device
*netdev
= bus
->priv
;
1427 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1431 ret
= et131x_phy_mii_read(adapter
, phy_addr
, reg
, &value
);
1439 static int et131x_mdio_write(struct mii_bus
*bus
, int phy_addr
,
1442 struct net_device
*netdev
= bus
->priv
;
1443 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1445 return et131x_mii_write(adapter
, phy_addr
, reg
, value
);
1448 /* et1310_phy_power_switch - PHY power control
1449 * @adapter: device to control
1450 * @down: true for off/false for back on
1452 * one hundred, ten, one thousand megs
1453 * How would you like to have your LAN accessed
1454 * Can't you see that this code processed
1455 * Phy power, phy power..
1457 static void et1310_phy_power_switch(struct et131x_adapter
*adapter
, bool down
)
1460 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
1462 et131x_mii_read(adapter
, MII_BMCR
, &data
);
1463 data
&= ~BMCR_PDOWN
;
1466 et131x_mii_write(adapter
, phydev
->mdio
.addr
, MII_BMCR
, data
);
1469 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1470 static void et131x_xcvr_init(struct et131x_adapter
*adapter
)
1473 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
1475 /* Set the LED behavior such that LED 1 indicates speed (off =
1476 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1477 * link and activity (on for link, blink off for activity).
1479 * NOTE: Some customizations have been added here for specific
1480 * vendors; The LED behavior is now determined by vendor data in the
1481 * EEPROM. However, the above description is the default.
1483 if ((adapter
->eeprom_data
[1] & 0x4) == 0) {
1484 et131x_mii_read(adapter
, PHY_LED_2
, &lcr2
);
1486 lcr2
&= (ET_LED2_LED_100TX
| ET_LED2_LED_1000T
);
1487 lcr2
|= (LED_VAL_LINKON_ACTIVE
<< LED_LINK_SHIFT
);
1489 if ((adapter
->eeprom_data
[1] & 0x8) == 0)
1490 lcr2
|= (LED_VAL_1000BT_100BTX
<< LED_TXRX_SHIFT
);
1492 lcr2
|= (LED_VAL_LINKON
<< LED_TXRX_SHIFT
);
1494 et131x_mii_write(adapter
, phydev
->mdio
.addr
, PHY_LED_2
, lcr2
);
1498 /* et131x_configure_global_regs - configure JAGCore global regs */
1499 static void et131x_configure_global_regs(struct et131x_adapter
*adapter
)
1501 struct global_regs __iomem
*regs
= &adapter
->regs
->global
;
1503 writel(0, ®s
->rxq_start_addr
);
1504 writel(INTERNAL_MEM_SIZE
- 1, ®s
->txq_end_addr
);
1506 if (adapter
->registry_jumbo_packet
< 2048) {
1507 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1508 * block of RAM that the driver can split between Tx
1509 * and Rx as it desires. Our default is to split it
1512 writel(PARM_RX_MEM_END_DEF
, ®s
->rxq_end_addr
);
1513 writel(PARM_RX_MEM_END_DEF
+ 1, ®s
->txq_start_addr
);
1514 } else if (adapter
->registry_jumbo_packet
< 8192) {
1515 /* For jumbo packets > 2k but < 8k, split 50-50. */
1516 writel(INTERNAL_MEM_RX_OFFSET
, ®s
->rxq_end_addr
);
1517 writel(INTERNAL_MEM_RX_OFFSET
+ 1, ®s
->txq_start_addr
);
1519 /* 9216 is the only packet size greater than 8k that
1520 * is available. The Tx buffer has to be big enough
1521 * for one whole packet on the Tx side. We'll make
1522 * the Tx 9408, and give the rest to Rx
1524 writel(0x01b3, ®s
->rxq_end_addr
);
1525 writel(0x01b4, ®s
->txq_start_addr
);
1528 /* Initialize the loopback register. Disable all loopbacks. */
1529 writel(0, ®s
->loopback
);
1531 writel(0, ®s
->msi_config
);
1533 /* By default, disable the watchdog timer. It will be enabled when
1534 * a packet is queued.
1536 writel(0, ®s
->watchdog_timer
);
1539 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1540 static void et131x_config_rx_dma_regs(struct et131x_adapter
*adapter
)
1542 struct rxdma_regs __iomem
*rx_dma
= &adapter
->regs
->rxdma
;
1543 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
1544 struct fbr_desc
*fbr_entry
;
1547 unsigned long flags
;
1550 et131x_rx_dma_disable(adapter
);
1552 /* Load the completion writeback physical address */
1553 writel(upper_32_bits(rx_local
->rx_status_bus
), &rx_dma
->dma_wb_base_hi
);
1554 writel(lower_32_bits(rx_local
->rx_status_bus
), &rx_dma
->dma_wb_base_lo
);
1556 memset(rx_local
->rx_status_block
, 0, sizeof(struct rx_status_block
));
1558 /* Set the address and parameters of the packet status ring */
1559 writel(upper_32_bits(rx_local
->ps_ring_physaddr
), &rx_dma
->psr_base_hi
);
1560 writel(lower_32_bits(rx_local
->ps_ring_physaddr
), &rx_dma
->psr_base_lo
);
1561 writel(rx_local
->psr_entries
- 1, &rx_dma
->psr_num_des
);
1562 writel(0, &rx_dma
->psr_full_offset
);
1564 psr_num_des
= readl(&rx_dma
->psr_num_des
) & ET_RXDMA_PSR_NUM_DES_MASK
;
1565 writel((psr_num_des
* LO_MARK_PERCENT_FOR_PSR
) / 100,
1566 &rx_dma
->psr_min_des
);
1568 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
1570 /* These local variables track the PSR in the adapter structure */
1571 rx_local
->local_psr_full
= 0;
1573 for (id
= 0; id
< NUM_FBRS
; id
++) {
1574 u32 __iomem
*num_des
;
1575 u32 __iomem
*full_offset
;
1576 u32 __iomem
*min_des
;
1577 u32 __iomem
*base_hi
;
1578 u32 __iomem
*base_lo
;
1579 struct fbr_lookup
*fbr
= rx_local
->fbr
[id
];
1582 num_des
= &rx_dma
->fbr0_num_des
;
1583 full_offset
= &rx_dma
->fbr0_full_offset
;
1584 min_des
= &rx_dma
->fbr0_min_des
;
1585 base_hi
= &rx_dma
->fbr0_base_hi
;
1586 base_lo
= &rx_dma
->fbr0_base_lo
;
1588 num_des
= &rx_dma
->fbr1_num_des
;
1589 full_offset
= &rx_dma
->fbr1_full_offset
;
1590 min_des
= &rx_dma
->fbr1_min_des
;
1591 base_hi
= &rx_dma
->fbr1_base_hi
;
1592 base_lo
= &rx_dma
->fbr1_base_lo
;
1595 /* Now's the best time to initialize FBR contents */
1596 fbr_entry
= fbr
->ring_virtaddr
;
1597 for (entry
= 0; entry
< fbr
->num_entries
; entry
++) {
1598 fbr_entry
->addr_hi
= fbr
->bus_high
[entry
];
1599 fbr_entry
->addr_lo
= fbr
->bus_low
[entry
];
1600 fbr_entry
->word2
= entry
;
1604 /* Set the address and parameters of Free buffer ring 1 and 0 */
1605 writel(upper_32_bits(fbr
->ring_physaddr
), base_hi
);
1606 writel(lower_32_bits(fbr
->ring_physaddr
), base_lo
);
1607 writel(fbr
->num_entries
- 1, num_des
);
1608 writel(ET_DMA10_WRAP
, full_offset
);
1610 /* This variable tracks the free buffer ring 1 full position,
1611 * so it has to match the above.
1613 fbr
->local_full
= ET_DMA10_WRAP
;
1614 writel(((fbr
->num_entries
* LO_MARK_PERCENT_FOR_RX
) / 100) - 1,
1618 /* Program the number of packets we will receive before generating an
1620 * For version B silicon, this value gets updated once autoneg is
1623 writel(PARM_RX_NUM_BUFS_DEF
, &rx_dma
->num_pkt_done
);
1625 /* The "time_done" is not working correctly to coalesce interrupts
1626 * after a given time period, but rather is giving us an interrupt
1627 * regardless of whether we have received packets.
1628 * This value gets updated once autoneg is complete.
1630 writel(PARM_RX_TIME_INT_DEF
, &rx_dma
->max_pkt_time
);
1632 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
1635 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1637 * Configure the transmit engine with the ring buffers we have created
1638 * and prepare it for use.
1640 static void et131x_config_tx_dma_regs(struct et131x_adapter
*adapter
)
1642 struct txdma_regs __iomem
*txdma
= &adapter
->regs
->txdma
;
1643 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
1645 /* Load the hardware with the start of the transmit descriptor ring. */
1646 writel(upper_32_bits(tx_ring
->tx_desc_ring_pa
), &txdma
->pr_base_hi
);
1647 writel(lower_32_bits(tx_ring
->tx_desc_ring_pa
), &txdma
->pr_base_lo
);
1649 /* Initialise the transmit DMA engine */
1650 writel(NUM_DESC_PER_RING_TX
- 1, &txdma
->pr_num_des
);
1652 /* Load the completion writeback physical address */
1653 writel(upper_32_bits(tx_ring
->tx_status_pa
), &txdma
->dma_wb_base_hi
);
1654 writel(lower_32_bits(tx_ring
->tx_status_pa
), &txdma
->dma_wb_base_lo
);
1656 *tx_ring
->tx_status
= 0;
1658 writel(0, &txdma
->service_request
);
1659 tx_ring
->send_idx
= 0;
1662 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1663 static void et131x_adapter_setup(struct et131x_adapter
*adapter
)
1665 et131x_configure_global_regs(adapter
);
1666 et1310_config_mac_regs1(adapter
);
1668 /* Configure the MMC registers */
1669 /* All we need to do is initialize the Memory Control Register */
1670 writel(ET_MMC_ENABLE
, &adapter
->regs
->mmc
.mmc_ctrl
);
1672 et1310_config_rxmac_regs(adapter
);
1673 et1310_config_txmac_regs(adapter
);
1675 et131x_config_rx_dma_regs(adapter
);
1676 et131x_config_tx_dma_regs(adapter
);
1678 et1310_config_macstat_regs(adapter
);
1680 et1310_phy_power_switch(adapter
, 0);
1681 et131x_xcvr_init(adapter
);
1684 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1685 static void et131x_soft_reset(struct et131x_adapter
*adapter
)
1689 /* Disable MAC Core */
1690 reg
= ET_MAC_CFG1_SOFT_RESET
| ET_MAC_CFG1_SIM_RESET
|
1691 ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
1692 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
;
1693 writel(reg
, &adapter
->regs
->mac
.cfg1
);
1696 writel(reg
, &adapter
->regs
->global
.sw_reset
);
1698 reg
= ET_MAC_CFG1_RESET_RXMC
| ET_MAC_CFG1_RESET_TXMC
|
1699 ET_MAC_CFG1_RESET_RXFUNC
| ET_MAC_CFG1_RESET_TXFUNC
;
1700 writel(reg
, &adapter
->regs
->mac
.cfg1
);
1701 writel(0, &adapter
->regs
->mac
.cfg1
);
1704 static void et131x_enable_interrupts(struct et131x_adapter
*adapter
)
1708 if (adapter
->flow
== FLOW_TXONLY
|| adapter
->flow
== FLOW_BOTH
)
1709 mask
= INT_MASK_ENABLE
;
1711 mask
= INT_MASK_ENABLE_NO_FLOW
;
1713 writel(mask
, &adapter
->regs
->global
.int_mask
);
1716 static void et131x_disable_interrupts(struct et131x_adapter
*adapter
)
1718 writel(INT_MASK_DISABLE
, &adapter
->regs
->global
.int_mask
);
1721 static void et131x_tx_dma_disable(struct et131x_adapter
*adapter
)
1723 /* Setup the transmit dma configuration register */
1724 writel(ET_TXDMA_CSR_HALT
| ET_TXDMA_SNGL_EPKT
,
1725 &adapter
->regs
->txdma
.csr
);
1728 static void et131x_enable_txrx(struct net_device
*netdev
)
1730 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1732 et131x_rx_dma_enable(adapter
);
1733 et131x_tx_dma_enable(adapter
);
1735 if (adapter
->flags
& FMP_ADAPTER_INTERRUPT_IN_USE
)
1736 et131x_enable_interrupts(adapter
);
1738 netif_start_queue(netdev
);
1741 static void et131x_disable_txrx(struct net_device
*netdev
)
1743 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
1745 netif_stop_queue(netdev
);
1747 et131x_rx_dma_disable(adapter
);
1748 et131x_tx_dma_disable(adapter
);
1750 et131x_disable_interrupts(adapter
);
1753 static void et131x_init_send(struct et131x_adapter
*adapter
)
1756 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
1757 struct tcb
*tcb
= tx_ring
->tcb_ring
;
1759 tx_ring
->tcb_qhead
= tcb
;
1761 memset(tcb
, 0, sizeof(struct tcb
) * NUM_TCB
);
1763 for (i
= 0; i
< NUM_TCB
; i
++) {
1764 tcb
->next
= tcb
+ 1;
1769 tx_ring
->tcb_qtail
= tcb
;
1771 /* Curr send queue should now be empty */
1772 tx_ring
->send_head
= NULL
;
1773 tx_ring
->send_tail
= NULL
;
1776 /* et1310_enable_phy_coma
1778 * driver receive an phy status change interrupt while in D0 and check that
1779 * phy_status is down.
1781 * -- gate off JAGCore;
1782 * -- set gigE PHY in Coma mode
1783 * -- wake on phy_interrupt; Perform software reset JAGCore,
1784 * re-initialize jagcore and gigE PHY
1786 static void et1310_enable_phy_coma(struct et131x_adapter
*adapter
)
1788 u32 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
1790 /* Stop sending packets. */
1791 adapter
->flags
|= FMP_ADAPTER_LOWER_POWER
;
1793 /* Wait for outstanding Receive packets */
1794 et131x_disable_txrx(adapter
->netdev
);
1796 /* Gate off JAGCore 3 clock domains */
1797 pmcsr
&= ~ET_PMCSR_INIT
;
1798 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1800 /* Program gigE PHY in to Coma mode */
1801 pmcsr
|= ET_PM_PHY_SW_COMA
;
1802 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1805 static void et1310_disable_phy_coma(struct et131x_adapter
*adapter
)
1809 pmcsr
= readl(&adapter
->regs
->global
.pm_csr
);
1811 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1812 pmcsr
|= ET_PMCSR_INIT
;
1813 pmcsr
&= ~ET_PM_PHY_SW_COMA
;
1814 writel(pmcsr
, &adapter
->regs
->global
.pm_csr
);
1816 /* Restore the GbE PHY speed and duplex modes;
1817 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1820 /* Re-initialize the send structures */
1821 et131x_init_send(adapter
);
1823 /* Bring the device back to the state it was during init prior to
1824 * autonegotiation being complete. This way, when we get the auto-neg
1825 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1827 et131x_soft_reset(adapter
);
1829 et131x_adapter_setup(adapter
);
1831 /* Allow Tx to restart */
1832 adapter
->flags
&= ~FMP_ADAPTER_LOWER_POWER
;
1834 et131x_enable_txrx(adapter
->netdev
);
1837 static inline u32
bump_free_buff_ring(u32
*free_buff_ring
, u32 limit
)
1839 u32 tmp_free_buff_ring
= *free_buff_ring
;
1841 tmp_free_buff_ring
++;
1842 /* This works for all cases where limit < 1024. The 1023 case
1843 * works because 1023++ is 1024 which means the if condition is not
1844 * taken but the carry of the bit into the wrap bit toggles the wrap
1847 if ((tmp_free_buff_ring
& ET_DMA10_MASK
) > limit
) {
1848 tmp_free_buff_ring
&= ~ET_DMA10_MASK
;
1849 tmp_free_buff_ring
^= ET_DMA10_WRAP
;
1851 /* For the 1023 case */
1852 tmp_free_buff_ring
&= (ET_DMA10_MASK
| ET_DMA10_WRAP
);
1853 *free_buff_ring
= tmp_free_buff_ring
;
1854 return tmp_free_buff_ring
;
1857 /* et131x_rx_dma_memory_alloc
1859 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
1860 * and the Packet Status Ring.
1862 static int et131x_rx_dma_memory_alloc(struct et131x_adapter
*adapter
)
1869 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
1870 struct fbr_lookup
*fbr
;
1872 /* Alloc memory for the lookup table */
1873 rx_ring
->fbr
[0] = kzalloc(sizeof(*fbr
), GFP_KERNEL
);
1874 if (rx_ring
->fbr
[0] == NULL
)
1876 rx_ring
->fbr
[1] = kzalloc(sizeof(*fbr
), GFP_KERNEL
);
1877 if (rx_ring
->fbr
[1] == NULL
)
1880 /* The first thing we will do is configure the sizes of the buffer
1881 * rings. These will change based on jumbo packet support. Larger
1882 * jumbo packets increases the size of each entry in FBR0, and the
1883 * number of entries in FBR0, while at the same time decreasing the
1884 * number of entries in FBR1.
1886 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
1887 * entries are huge in order to accommodate a "jumbo" frame, then it
1888 * will have less entries. Conversely, FBR1 will now be relied upon
1889 * to carry more "normal" frames, thus it's entry size also increases
1890 * and the number of entries goes up too (since it now carries
1891 * "small" + "regular" packets.
1893 * In this scheme, we try to maintain 512 entries between the two
1894 * rings. Also, FBR1 remains a constant size - when it's size doubles
1895 * the number of entries halves. FBR0 increases in size, however.
1897 if (adapter
->registry_jumbo_packet
< 2048) {
1898 rx_ring
->fbr
[0]->buffsize
= 256;
1899 rx_ring
->fbr
[0]->num_entries
= 512;
1900 rx_ring
->fbr
[1]->buffsize
= 2048;
1901 rx_ring
->fbr
[1]->num_entries
= 512;
1902 } else if (adapter
->registry_jumbo_packet
< 4096) {
1903 rx_ring
->fbr
[0]->buffsize
= 512;
1904 rx_ring
->fbr
[0]->num_entries
= 1024;
1905 rx_ring
->fbr
[1]->buffsize
= 4096;
1906 rx_ring
->fbr
[1]->num_entries
= 512;
1908 rx_ring
->fbr
[0]->buffsize
= 1024;
1909 rx_ring
->fbr
[0]->num_entries
= 768;
1910 rx_ring
->fbr
[1]->buffsize
= 16384;
1911 rx_ring
->fbr
[1]->num_entries
= 128;
1914 rx_ring
->psr_entries
= rx_ring
->fbr
[0]->num_entries
+
1915 rx_ring
->fbr
[1]->num_entries
;
1917 for (id
= 0; id
< NUM_FBRS
; id
++) {
1918 fbr
= rx_ring
->fbr
[id
];
1919 /* Allocate an area of memory for Free Buffer Ring */
1920 bufsize
= sizeof(struct fbr_desc
) * fbr
->num_entries
;
1921 fbr
->ring_virtaddr
= dma_alloc_coherent(&adapter
->pdev
->dev
,
1923 &fbr
->ring_physaddr
,
1925 if (!fbr
->ring_virtaddr
) {
1926 dev_err(&adapter
->pdev
->dev
,
1927 "Cannot alloc memory for Free Buffer Ring %d\n",
1933 for (id
= 0; id
< NUM_FBRS
; id
++) {
1934 fbr
= rx_ring
->fbr
[id
];
1935 fbr_chunksize
= (FBR_CHUNKS
* fbr
->buffsize
);
1937 for (i
= 0; i
< fbr
->num_entries
/ FBR_CHUNKS
; i
++) {
1938 dma_addr_t fbr_physaddr
;
1940 fbr
->mem_virtaddrs
[i
] = dma_alloc_coherent(
1941 &adapter
->pdev
->dev
, fbr_chunksize
,
1942 &fbr
->mem_physaddrs
[i
],
1945 if (!fbr
->mem_virtaddrs
[i
]) {
1946 dev_err(&adapter
->pdev
->dev
,
1947 "Could not alloc memory\n");
1951 /* See NOTE in "Save Physical Address" comment above */
1952 fbr_physaddr
= fbr
->mem_physaddrs
[i
];
1954 for (j
= 0; j
< FBR_CHUNKS
; j
++) {
1955 u32 k
= (i
* FBR_CHUNKS
) + j
;
1957 /* Save the Virtual address of this index for
1958 * quick access later
1960 fbr
->virt
[k
] = (u8
*)fbr
->mem_virtaddrs
[i
] +
1961 (j
* fbr
->buffsize
);
1963 /* now store the physical address in the
1964 * descriptor so the device can access it
1966 fbr
->bus_high
[k
] = upper_32_bits(fbr_physaddr
);
1967 fbr
->bus_low
[k
] = lower_32_bits(fbr_physaddr
);
1968 fbr_physaddr
+= fbr
->buffsize
;
1973 /* Allocate an area of memory for FIFO of Packet Status ring entries */
1974 psr_size
= sizeof(struct pkt_stat_desc
) * rx_ring
->psr_entries
;
1976 rx_ring
->ps_ring_virtaddr
= dma_alloc_coherent(&adapter
->pdev
->dev
,
1978 &rx_ring
->ps_ring_physaddr
,
1981 if (!rx_ring
->ps_ring_virtaddr
) {
1982 dev_err(&adapter
->pdev
->dev
,
1983 "Cannot alloc memory for Packet Status Ring\n");
1987 /* Allocate an area of memory for writeback of status information */
1988 rx_ring
->rx_status_block
= dma_alloc_coherent(&adapter
->pdev
->dev
,
1989 sizeof(struct rx_status_block
),
1990 &rx_ring
->rx_status_bus
,
1992 if (!rx_ring
->rx_status_block
) {
1993 dev_err(&adapter
->pdev
->dev
,
1994 "Cannot alloc memory for Status Block\n");
1997 rx_ring
->num_rfd
= NIC_DEFAULT_NUM_RFD
;
1999 /* The RFDs are going to be put on lists later on, so initialize the
2002 INIT_LIST_HEAD(&rx_ring
->recv_list
);
2006 static void et131x_rx_dma_memory_free(struct et131x_adapter
*adapter
)
2013 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2014 struct fbr_lookup
*fbr
;
2016 /* Free RFDs and associated packet descriptors */
2017 WARN_ON(rx_ring
->num_ready_recv
!= rx_ring
->num_rfd
);
2019 while (!list_empty(&rx_ring
->recv_list
)) {
2020 rfd
= list_entry(rx_ring
->recv_list
.next
,
2021 struct rfd
, list_node
);
2023 list_del(&rfd
->list_node
);
2028 /* Free Free Buffer Rings */
2029 for (id
= 0; id
< NUM_FBRS
; id
++) {
2030 fbr
= rx_ring
->fbr
[id
];
2032 if (!fbr
|| !fbr
->ring_virtaddr
)
2035 /* First the packet memory */
2036 for (ii
= 0; ii
< fbr
->num_entries
/ FBR_CHUNKS
; ii
++) {
2037 if (fbr
->mem_virtaddrs
[ii
]) {
2038 bufsize
= fbr
->buffsize
* FBR_CHUNKS
;
2040 dma_free_coherent(&adapter
->pdev
->dev
,
2042 fbr
->mem_virtaddrs
[ii
],
2043 fbr
->mem_physaddrs
[ii
]);
2045 fbr
->mem_virtaddrs
[ii
] = NULL
;
2049 bufsize
= sizeof(struct fbr_desc
) * fbr
->num_entries
;
2051 dma_free_coherent(&adapter
->pdev
->dev
,
2054 fbr
->ring_physaddr
);
2056 fbr
->ring_virtaddr
= NULL
;
2059 /* Free Packet Status Ring */
2060 if (rx_ring
->ps_ring_virtaddr
) {
2061 psr_size
= sizeof(struct pkt_stat_desc
) * rx_ring
->psr_entries
;
2063 dma_free_coherent(&adapter
->pdev
->dev
, psr_size
,
2064 rx_ring
->ps_ring_virtaddr
,
2065 rx_ring
->ps_ring_physaddr
);
2067 rx_ring
->ps_ring_virtaddr
= NULL
;
2070 /* Free area of memory for the writeback of status information */
2071 if (rx_ring
->rx_status_block
) {
2072 dma_free_coherent(&adapter
->pdev
->dev
,
2073 sizeof(struct rx_status_block
),
2074 rx_ring
->rx_status_block
,
2075 rx_ring
->rx_status_bus
);
2076 rx_ring
->rx_status_block
= NULL
;
2079 /* Free the FBR Lookup Table */
2080 kfree(rx_ring
->fbr
[0]);
2081 kfree(rx_ring
->fbr
[1]);
2083 /* Reset Counters */
2084 rx_ring
->num_ready_recv
= 0;
2087 /* et131x_init_recv - Initialize receive data structures */
2088 static int et131x_init_recv(struct et131x_adapter
*adapter
)
2092 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2094 /* Setup each RFD */
2095 for (rfdct
= 0; rfdct
< rx_ring
->num_rfd
; rfdct
++) {
2096 rfd
= kzalloc(sizeof(*rfd
), GFP_ATOMIC
| GFP_DMA
);
2102 /* Add this RFD to the recv_list */
2103 list_add_tail(&rfd
->list_node
, &rx_ring
->recv_list
);
2105 /* Increment the available RFD's */
2106 rx_ring
->num_ready_recv
++;
2112 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2113 static void et131x_set_rx_dma_timer(struct et131x_adapter
*adapter
)
2115 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
2117 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2118 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2120 if ((phydev
->speed
== SPEED_100
) || (phydev
->speed
== SPEED_10
)) {
2121 writel(0, &adapter
->regs
->rxdma
.max_pkt_time
);
2122 writel(1, &adapter
->regs
->rxdma
.num_pkt_done
);
2126 /* nic_return_rfd - Recycle a RFD and put it back onto the receive list */
2127 static void nic_return_rfd(struct et131x_adapter
*adapter
, struct rfd
*rfd
)
2129 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
2130 struct rxdma_regs __iomem
*rx_dma
= &adapter
->regs
->rxdma
;
2131 u16 buff_index
= rfd
->bufferindex
;
2132 u8 ring_index
= rfd
->ringindex
;
2133 unsigned long flags
;
2134 struct fbr_lookup
*fbr
= rx_local
->fbr
[ring_index
];
2136 /* We don't use any of the OOB data besides status. Otherwise, we
2137 * need to clean up OOB data
2139 if (buff_index
< fbr
->num_entries
) {
2141 u32 __iomem
*offset
;
2142 struct fbr_desc
*next
;
2144 if (ring_index
== 0)
2145 offset
= &rx_dma
->fbr0_full_offset
;
2147 offset
= &rx_dma
->fbr1_full_offset
;
2149 next
= (struct fbr_desc
*)(fbr
->ring_virtaddr
) +
2150 INDEX10(fbr
->local_full
);
2152 /* Handle the Free Buffer Ring advancement here. Write
2153 * the PA / Buffer Index for the returned buffer into
2154 * the oldest (next to be freed)FBR entry
2156 next
->addr_hi
= fbr
->bus_high
[buff_index
];
2157 next
->addr_lo
= fbr
->bus_low
[buff_index
];
2158 next
->word2
= buff_index
;
2160 free_buff_ring
= bump_free_buff_ring(&fbr
->local_full
,
2161 fbr
->num_entries
- 1);
2162 writel(free_buff_ring
, offset
);
2164 dev_err(&adapter
->pdev
->dev
,
2165 "%s illegal Buffer Index returned\n", __func__
);
2168 /* The processing on this RFD is done, so put it back on the tail of
2171 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
2172 list_add_tail(&rfd
->list_node
, &rx_local
->recv_list
);
2173 rx_local
->num_ready_recv
++;
2174 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2176 WARN_ON(rx_local
->num_ready_recv
> rx_local
->num_rfd
);
2179 /* nic_rx_pkts - Checks the hardware for available packets
2181 * Checks the hardware for available packets, using completion ring
2182 * If packets are available, it gets an RFD from the recv_list, attaches
2183 * the packet to it, puts the RFD in the RecvPendList, and also returns
2184 * the pointer to the RFD.
2186 static struct rfd
*nic_rx_pkts(struct et131x_adapter
*adapter
)
2188 struct rx_ring
*rx_local
= &adapter
->rx_ring
;
2189 struct rx_status_block
*status
;
2190 struct pkt_stat_desc
*psr
;
2192 unsigned long flags
;
2193 struct list_head
*element
;
2199 struct sk_buff
*skb
;
2200 struct fbr_lookup
*fbr
;
2202 /* RX Status block is written by the DMA engine prior to every
2203 * interrupt. It contains the next to be used entry in the Packet
2204 * Status Ring, and also the two Free Buffer rings.
2206 status
= rx_local
->rx_status_block
;
2207 word1
= status
->word1
>> 16;
2209 /* Check the PSR and wrap bits do not match */
2210 if ((word1
& 0x1FFF) == (rx_local
->local_psr_full
& 0x1FFF))
2211 return NULL
; /* Looks like this ring is not updated yet */
2213 /* The packet status ring indicates that data is available. */
2214 psr
= (struct pkt_stat_desc
*)(rx_local
->ps_ring_virtaddr
) +
2215 (rx_local
->local_psr_full
& 0xFFF);
2217 /* Grab any information that is required once the PSR is advanced,
2218 * since we can no longer rely on the memory being accurate
2220 len
= psr
->word1
& 0xFFFF;
2221 ring_index
= (psr
->word1
>> 26) & 0x03;
2222 fbr
= rx_local
->fbr
[ring_index
];
2223 buff_index
= (psr
->word1
>> 16) & 0x3FF;
2226 /* Indicate that we have used this PSR entry. */
2228 add_12bit(&rx_local
->local_psr_full
, 1);
2229 if ((rx_local
->local_psr_full
& 0xFFF) > rx_local
->psr_entries
- 1) {
2230 /* Clear psr full and toggle the wrap bit */
2231 rx_local
->local_psr_full
&= ~0xFFF;
2232 rx_local
->local_psr_full
^= 0x1000;
2235 writel(rx_local
->local_psr_full
, &adapter
->regs
->rxdma
.psr_full_offset
);
2237 if (ring_index
> 1 || buff_index
> fbr
->num_entries
- 1) {
2238 /* Illegal buffer or ring index cannot be used by S/W*/
2239 dev_err(&adapter
->pdev
->dev
,
2240 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2241 rx_local
->local_psr_full
& 0xFFF, len
, buff_index
);
2245 /* Get and fill the RFD. */
2246 spin_lock_irqsave(&adapter
->rcv_lock
, flags
);
2248 element
= rx_local
->recv_list
.next
;
2249 rfd
= list_entry(element
, struct rfd
, list_node
);
2252 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2256 list_del(&rfd
->list_node
);
2257 rx_local
->num_ready_recv
--;
2259 spin_unlock_irqrestore(&adapter
->rcv_lock
, flags
);
2261 rfd
->bufferindex
= buff_index
;
2262 rfd
->ringindex
= ring_index
;
2264 /* In V1 silicon, there is a bug which screws up filtering of runt
2265 * packets. Therefore runt packet filtering is disabled in the MAC and
2266 * the packets are dropped here. They are also counted here.
2268 if (len
< (NIC_MIN_PACKET_SIZE
+ 4)) {
2269 adapter
->stats
.rx_other_errs
++;
2274 if ((word0
& ALCATEL_MULTICAST_PKT
) && !(word0
& ALCATEL_BROADCAST_PKT
))
2275 adapter
->stats
.multicast_pkts_rcvd
++;
2279 skb
= dev_alloc_skb(rfd
->len
+ 2);
2283 adapter
->netdev
->stats
.rx_bytes
+= rfd
->len
;
2285 skb_put_data(skb
, fbr
->virt
[buff_index
], rfd
->len
);
2287 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
2288 skb
->ip_summed
= CHECKSUM_NONE
;
2289 netif_receive_skb(skb
);
2292 nic_return_rfd(adapter
, rfd
);
2296 static int et131x_handle_recv_pkts(struct et131x_adapter
*adapter
, int budget
)
2298 struct rfd
*rfd
= NULL
;
2302 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
2304 if (budget
> MAX_PACKETS_HANDLED
)
2305 limit
= MAX_PACKETS_HANDLED
;
2307 /* Process up to available RFD's */
2308 while (count
< limit
) {
2309 if (list_empty(&rx_ring
->recv_list
)) {
2310 WARN_ON(rx_ring
->num_ready_recv
!= 0);
2315 rfd
= nic_rx_pkts(adapter
);
2320 /* Do not receive any packets until a filter has been set.
2321 * Do not receive any packets until we have link.
2322 * If length is zero, return the RFD in order to advance the
2325 if (!adapter
->packet_filter
||
2326 !netif_carrier_ok(adapter
->netdev
) ||
2330 adapter
->netdev
->stats
.rx_packets
++;
2332 if (rx_ring
->num_ready_recv
< RFD_LOW_WATER_MARK
)
2333 dev_warn(&adapter
->pdev
->dev
, "RFD's are running out\n");
2338 if (count
== limit
|| !done
) {
2339 rx_ring
->unfinished_receives
= true;
2340 writel(PARM_TX_TIME_INT_DEF
* NANO_IN_A_MICRO
,
2341 &adapter
->regs
->global
.watchdog_timer
);
2343 /* Watchdog timer will disable itself if appropriate. */
2344 rx_ring
->unfinished_receives
= false;
2350 /* et131x_tx_dma_memory_alloc
2352 * Allocates memory that will be visible both to the device and to the CPU.
2353 * The OS will pass us packets, pointers to which we will insert in the Tx
2354 * Descriptor queue. The device will read this queue to find the packets in
2355 * memory. The device will update the "status" in memory each time it xmits a
2358 static int et131x_tx_dma_memory_alloc(struct et131x_adapter
*adapter
)
2361 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2363 /* Allocate memory for the TCB's (Transmit Control Block) */
2364 tx_ring
->tcb_ring
= kcalloc(NUM_TCB
, sizeof(struct tcb
),
2365 GFP_ATOMIC
| GFP_DMA
);
2366 if (!tx_ring
->tcb_ring
)
2369 desc_size
= (sizeof(struct tx_desc
) * NUM_DESC_PER_RING_TX
);
2370 tx_ring
->tx_desc_ring
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2372 &tx_ring
->tx_desc_ring_pa
,
2374 if (!tx_ring
->tx_desc_ring
) {
2375 dev_err(&adapter
->pdev
->dev
,
2376 "Cannot alloc memory for Tx Ring\n");
2380 tx_ring
->tx_status
= dma_alloc_coherent(&adapter
->pdev
->dev
,
2382 &tx_ring
->tx_status_pa
,
2384 if (!tx_ring
->tx_status
) {
2385 dev_err(&adapter
->pdev
->dev
,
2386 "Cannot alloc memory for Tx status block\n");
2392 static void et131x_tx_dma_memory_free(struct et131x_adapter
*adapter
)
2395 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2397 if (tx_ring
->tx_desc_ring
) {
2398 /* Free memory relating to Tx rings here */
2399 desc_size
= (sizeof(struct tx_desc
) * NUM_DESC_PER_RING_TX
);
2400 dma_free_coherent(&adapter
->pdev
->dev
,
2402 tx_ring
->tx_desc_ring
,
2403 tx_ring
->tx_desc_ring_pa
);
2404 tx_ring
->tx_desc_ring
= NULL
;
2407 /* Free memory for the Tx status block */
2408 if (tx_ring
->tx_status
) {
2409 dma_free_coherent(&adapter
->pdev
->dev
,
2412 tx_ring
->tx_status_pa
);
2414 tx_ring
->tx_status
= NULL
;
2416 /* Free the memory for the tcb structures */
2417 kfree(tx_ring
->tcb_ring
);
2420 /* nic_send_packet - NIC specific send handler for version B silicon. */
2421 static int nic_send_packet(struct et131x_adapter
*adapter
, struct tcb
*tcb
)
2424 struct tx_desc desc
[24];
2426 u32 thiscopy
, remainder
;
2427 struct sk_buff
*skb
= tcb
->skb
;
2428 u32 nr_frags
= skb_shinfo(skb
)->nr_frags
+ 1;
2429 struct skb_frag_struct
*frags
= &skb_shinfo(skb
)->frags
[0];
2430 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
2431 dma_addr_t dma_addr
;
2432 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2434 /* Part of the optimizations of this send routine restrict us to
2435 * sending 24 fragments at a pass. In practice we should never see
2436 * more than 5 fragments.
2439 /* nr_frags should be no more than 18. */
2440 BUILD_BUG_ON(MAX_SKB_FRAGS
+ 1 > 23);
2442 memset(desc
, 0, sizeof(struct tx_desc
) * (nr_frags
+ 1));
2444 for (i
= 0; i
< nr_frags
; i
++) {
2445 /* If there is something in this element, lets get a
2446 * descriptor from the ring and get the necessary data
2449 /* If the fragments are smaller than a standard MTU,
2450 * then map them to a single descriptor in the Tx
2451 * Desc ring. However, if they're larger, as is
2452 * possible with support for jumbo packets, then
2453 * split them each across 2 descriptors.
2455 * This will work until we determine why the hardware
2456 * doesn't seem to like large fragments.
2458 if (skb_headlen(skb
) <= 1514) {
2459 /* Low 16bits are length, high is vlan and
2460 * unused currently so zero
2462 desc
[frag
].len_vlan
= skb_headlen(skb
);
2463 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2467 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2468 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2471 desc
[frag
].len_vlan
= skb_headlen(skb
) / 2;
2472 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2474 skb_headlen(skb
) / 2,
2476 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2477 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2480 desc
[frag
].len_vlan
= skb_headlen(skb
) / 2;
2481 dma_addr
= dma_map_single(&adapter
->pdev
->dev
,
2483 skb_headlen(skb
) / 2,
2484 skb_headlen(skb
) / 2,
2486 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2487 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2491 desc
[frag
].len_vlan
= frags
[i
- 1].size
;
2492 dma_addr
= skb_frag_dma_map(&adapter
->pdev
->dev
,
2497 desc
[frag
].addr_lo
= lower_32_bits(dma_addr
);
2498 desc
[frag
].addr_hi
= upper_32_bits(dma_addr
);
2503 if (phydev
&& phydev
->speed
== SPEED_1000
) {
2504 if (++tx_ring
->since_irq
== PARM_TX_NUM_BUFS_DEF
) {
2505 /* Last element & Interrupt flag */
2506 desc
[frag
- 1].flags
=
2507 TXDESC_FLAG_INTPROC
| TXDESC_FLAG_LASTPKT
;
2508 tx_ring
->since_irq
= 0;
2509 } else { /* Last element */
2510 desc
[frag
- 1].flags
= TXDESC_FLAG_LASTPKT
;
2513 desc
[frag
- 1].flags
=
2514 TXDESC_FLAG_INTPROC
| TXDESC_FLAG_LASTPKT
;
2517 desc
[0].flags
|= TXDESC_FLAG_FIRSTPKT
;
2519 tcb
->index_start
= tx_ring
->send_idx
;
2522 thiscopy
= NUM_DESC_PER_RING_TX
- INDEX10(tx_ring
->send_idx
);
2524 if (thiscopy
>= frag
) {
2528 remainder
= frag
- thiscopy
;
2531 memcpy(tx_ring
->tx_desc_ring
+ INDEX10(tx_ring
->send_idx
),
2533 sizeof(struct tx_desc
) * thiscopy
);
2535 add_10bit(&tx_ring
->send_idx
, thiscopy
);
2537 if (INDEX10(tx_ring
->send_idx
) == 0 ||
2538 INDEX10(tx_ring
->send_idx
) == NUM_DESC_PER_RING_TX
) {
2539 tx_ring
->send_idx
&= ~ET_DMA10_MASK
;
2540 tx_ring
->send_idx
^= ET_DMA10_WRAP
;
2544 memcpy(tx_ring
->tx_desc_ring
,
2546 sizeof(struct tx_desc
) * remainder
);
2548 add_10bit(&tx_ring
->send_idx
, remainder
);
2551 if (INDEX10(tx_ring
->send_idx
) == 0) {
2552 if (tx_ring
->send_idx
)
2553 tcb
->index
= NUM_DESC_PER_RING_TX
- 1;
2555 tcb
->index
= ET_DMA10_WRAP
|(NUM_DESC_PER_RING_TX
- 1);
2557 tcb
->index
= tx_ring
->send_idx
- 1;
2560 spin_lock(&adapter
->tcb_send_qlock
);
2562 if (tx_ring
->send_tail
)
2563 tx_ring
->send_tail
->next
= tcb
;
2565 tx_ring
->send_head
= tcb
;
2567 tx_ring
->send_tail
= tcb
;
2569 WARN_ON(tcb
->next
!= NULL
);
2573 spin_unlock(&adapter
->tcb_send_qlock
);
2575 /* Write the new write pointer back to the device. */
2576 writel(tx_ring
->send_idx
, &adapter
->regs
->txdma
.service_request
);
2578 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2579 * timer to wake us up if this packet isn't followed by N more.
2581 if (phydev
&& phydev
->speed
== SPEED_1000
) {
2582 writel(PARM_TX_TIME_INT_DEF
* NANO_IN_A_MICRO
,
2583 &adapter
->regs
->global
.watchdog_timer
);
2588 static int send_packet(struct sk_buff
*skb
, struct et131x_adapter
*adapter
)
2592 unsigned long flags
;
2593 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2595 /* All packets must have at least a MAC address and a protocol type */
2596 if (skb
->len
< ETH_HLEN
)
2599 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2601 tcb
= tx_ring
->tcb_qhead
;
2604 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2608 tx_ring
->tcb_qhead
= tcb
->next
;
2610 if (tx_ring
->tcb_qhead
== NULL
)
2611 tx_ring
->tcb_qtail
= NULL
;
2613 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2618 status
= nic_send_packet(adapter
, tcb
);
2621 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2623 if (tx_ring
->tcb_qtail
)
2624 tx_ring
->tcb_qtail
->next
= tcb
;
2626 /* Apparently ready Q is empty. */
2627 tx_ring
->tcb_qhead
= tcb
;
2629 tx_ring
->tcb_qtail
= tcb
;
2630 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2633 WARN_ON(tx_ring
->used
> NUM_TCB
);
2637 /* free_send_packet - Recycle a struct tcb */
2638 static inline void free_send_packet(struct et131x_adapter
*adapter
,
2641 unsigned long flags
;
2642 struct tx_desc
*desc
= NULL
;
2643 struct net_device_stats
*stats
= &adapter
->netdev
->stats
;
2644 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2648 stats
->tx_bytes
+= tcb
->skb
->len
;
2650 /* Iterate through the TX descriptors on the ring
2651 * corresponding to this packet and umap the fragments
2655 desc
= tx_ring
->tx_desc_ring
+
2656 INDEX10(tcb
->index_start
);
2658 dma_addr
= desc
->addr_lo
;
2659 dma_addr
|= (u64
)desc
->addr_hi
<< 32;
2661 dma_unmap_single(&adapter
->pdev
->dev
,
2663 desc
->len_vlan
, DMA_TO_DEVICE
);
2665 add_10bit(&tcb
->index_start
, 1);
2666 if (INDEX10(tcb
->index_start
) >=
2667 NUM_DESC_PER_RING_TX
) {
2668 tcb
->index_start
&= ~ET_DMA10_MASK
;
2669 tcb
->index_start
^= ET_DMA10_WRAP
;
2671 } while (desc
!= tx_ring
->tx_desc_ring
+ INDEX10(tcb
->index
));
2673 dev_kfree_skb_any(tcb
->skb
);
2676 memset(tcb
, 0, sizeof(struct tcb
));
2678 /* Add the TCB to the Ready Q */
2679 spin_lock_irqsave(&adapter
->tcb_ready_qlock
, flags
);
2681 stats
->tx_packets
++;
2683 if (tx_ring
->tcb_qtail
)
2684 tx_ring
->tcb_qtail
->next
= tcb
;
2685 else /* Apparently ready Q is empty. */
2686 tx_ring
->tcb_qhead
= tcb
;
2688 tx_ring
->tcb_qtail
= tcb
;
2690 spin_unlock_irqrestore(&adapter
->tcb_ready_qlock
, flags
);
2691 WARN_ON(tx_ring
->used
< 0);
2694 /* et131x_free_busy_send_packets - Free and complete the stopped active sends */
2695 static void et131x_free_busy_send_packets(struct et131x_adapter
*adapter
)
2698 unsigned long flags
;
2700 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2702 /* Any packets being sent? Check the first TCB on the send list */
2703 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2705 tcb
= tx_ring
->send_head
;
2707 while (tcb
!= NULL
&& freed
< NUM_TCB
) {
2708 struct tcb
*next
= tcb
->next
;
2710 tx_ring
->send_head
= next
;
2713 tx_ring
->send_tail
= NULL
;
2717 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2720 free_send_packet(adapter
, tcb
);
2722 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2724 tcb
= tx_ring
->send_head
;
2727 WARN_ON(freed
== NUM_TCB
);
2729 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2734 /* et131x_handle_send_pkts
2736 * Re-claim the send resources, complete sends and get more to send from
2737 * the send wait queue.
2739 static void et131x_handle_send_pkts(struct et131x_adapter
*adapter
)
2741 unsigned long flags
;
2745 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
2747 serviced
= readl(&adapter
->regs
->txdma
.new_service_complete
);
2748 index
= INDEX10(serviced
);
2750 /* Has the ring wrapped? Process any descriptors that do not have
2751 * the same "wrap" indicator as the current completion indicator
2753 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2755 tcb
= tx_ring
->send_head
;
2758 ((serviced
^ tcb
->index
) & ET_DMA10_WRAP
) &&
2759 index
< INDEX10(tcb
->index
)) {
2761 tx_ring
->send_head
= tcb
->next
;
2762 if (tcb
->next
== NULL
)
2763 tx_ring
->send_tail
= NULL
;
2765 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2766 free_send_packet(adapter
, tcb
);
2767 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2769 /* Goto the next packet */
2770 tcb
= tx_ring
->send_head
;
2773 !((serviced
^ tcb
->index
) & ET_DMA10_WRAP
) &&
2774 index
> (tcb
->index
& ET_DMA10_MASK
)) {
2776 tx_ring
->send_head
= tcb
->next
;
2777 if (tcb
->next
== NULL
)
2778 tx_ring
->send_tail
= NULL
;
2780 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2781 free_send_packet(adapter
, tcb
);
2782 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
2784 /* Goto the next packet */
2785 tcb
= tx_ring
->send_head
;
2788 /* Wake up the queue when we hit a low-water mark */
2789 if (tx_ring
->used
<= NUM_TCB
/ 3)
2790 netif_wake_queue(adapter
->netdev
);
2792 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
2795 static int et131x_get_regs_len(struct net_device
*netdev
)
2797 #define ET131X_REGS_LEN 256
2798 return ET131X_REGS_LEN
* sizeof(u32
);
2801 static void et131x_get_regs(struct net_device
*netdev
,
2802 struct ethtool_regs
*regs
, void *regs_data
)
2804 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
2805 struct address_map __iomem
*aregs
= adapter
->regs
;
2806 u32
*regs_buff
= regs_data
;
2810 memset(regs_data
, 0, et131x_get_regs_len(netdev
));
2812 regs
->version
= (1 << 24) | (adapter
->pdev
->revision
<< 16) |
2813 adapter
->pdev
->device
;
2816 et131x_mii_read(adapter
, MII_BMCR
, &tmp
);
2817 regs_buff
[num
++] = tmp
;
2818 et131x_mii_read(adapter
, MII_BMSR
, &tmp
);
2819 regs_buff
[num
++] = tmp
;
2820 et131x_mii_read(adapter
, MII_PHYSID1
, &tmp
);
2821 regs_buff
[num
++] = tmp
;
2822 et131x_mii_read(adapter
, MII_PHYSID2
, &tmp
);
2823 regs_buff
[num
++] = tmp
;
2824 et131x_mii_read(adapter
, MII_ADVERTISE
, &tmp
);
2825 regs_buff
[num
++] = tmp
;
2826 et131x_mii_read(adapter
, MII_LPA
, &tmp
);
2827 regs_buff
[num
++] = tmp
;
2828 et131x_mii_read(adapter
, MII_EXPANSION
, &tmp
);
2829 regs_buff
[num
++] = tmp
;
2830 /* Autoneg next page transmit reg */
2831 et131x_mii_read(adapter
, 0x07, &tmp
);
2832 regs_buff
[num
++] = tmp
;
2833 /* Link partner next page reg */
2834 et131x_mii_read(adapter
, 0x08, &tmp
);
2835 regs_buff
[num
++] = tmp
;
2836 et131x_mii_read(adapter
, MII_CTRL1000
, &tmp
);
2837 regs_buff
[num
++] = tmp
;
2838 et131x_mii_read(adapter
, MII_STAT1000
, &tmp
);
2839 regs_buff
[num
++] = tmp
;
2840 et131x_mii_read(adapter
, 0x0b, &tmp
);
2841 regs_buff
[num
++] = tmp
;
2842 et131x_mii_read(adapter
, 0x0c, &tmp
);
2843 regs_buff
[num
++] = tmp
;
2844 et131x_mii_read(adapter
, MII_MMD_CTRL
, &tmp
);
2845 regs_buff
[num
++] = tmp
;
2846 et131x_mii_read(adapter
, MII_MMD_DATA
, &tmp
);
2847 regs_buff
[num
++] = tmp
;
2848 et131x_mii_read(adapter
, MII_ESTATUS
, &tmp
);
2849 regs_buff
[num
++] = tmp
;
2851 et131x_mii_read(adapter
, PHY_INDEX_REG
, &tmp
);
2852 regs_buff
[num
++] = tmp
;
2853 et131x_mii_read(adapter
, PHY_DATA_REG
, &tmp
);
2854 regs_buff
[num
++] = tmp
;
2855 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
, &tmp
);
2856 regs_buff
[num
++] = tmp
;
2857 et131x_mii_read(adapter
, PHY_LOOPBACK_CONTROL
, &tmp
);
2858 regs_buff
[num
++] = tmp
;
2859 et131x_mii_read(adapter
, PHY_LOOPBACK_CONTROL
+ 1, &tmp
);
2860 regs_buff
[num
++] = tmp
;
2862 et131x_mii_read(adapter
, PHY_REGISTER_MGMT_CONTROL
, &tmp
);
2863 regs_buff
[num
++] = tmp
;
2864 et131x_mii_read(adapter
, PHY_CONFIG
, &tmp
);
2865 regs_buff
[num
++] = tmp
;
2866 et131x_mii_read(adapter
, PHY_PHY_CONTROL
, &tmp
);
2867 regs_buff
[num
++] = tmp
;
2868 et131x_mii_read(adapter
, PHY_INTERRUPT_MASK
, &tmp
);
2869 regs_buff
[num
++] = tmp
;
2870 et131x_mii_read(adapter
, PHY_INTERRUPT_STATUS
, &tmp
);
2871 regs_buff
[num
++] = tmp
;
2872 et131x_mii_read(adapter
, PHY_PHY_STATUS
, &tmp
);
2873 regs_buff
[num
++] = tmp
;
2874 et131x_mii_read(adapter
, PHY_LED_1
, &tmp
);
2875 regs_buff
[num
++] = tmp
;
2876 et131x_mii_read(adapter
, PHY_LED_2
, &tmp
);
2877 regs_buff
[num
++] = tmp
;
2880 regs_buff
[num
++] = readl(&aregs
->global
.txq_start_addr
);
2881 regs_buff
[num
++] = readl(&aregs
->global
.txq_end_addr
);
2882 regs_buff
[num
++] = readl(&aregs
->global
.rxq_start_addr
);
2883 regs_buff
[num
++] = readl(&aregs
->global
.rxq_end_addr
);
2884 regs_buff
[num
++] = readl(&aregs
->global
.pm_csr
);
2885 regs_buff
[num
++] = adapter
->stats
.interrupt_status
;
2886 regs_buff
[num
++] = readl(&aregs
->global
.int_mask
);
2887 regs_buff
[num
++] = readl(&aregs
->global
.int_alias_clr_en
);
2888 regs_buff
[num
++] = readl(&aregs
->global
.int_status_alias
);
2889 regs_buff
[num
++] = readl(&aregs
->global
.sw_reset
);
2890 regs_buff
[num
++] = readl(&aregs
->global
.slv_timer
);
2891 regs_buff
[num
++] = readl(&aregs
->global
.msi_config
);
2892 regs_buff
[num
++] = readl(&aregs
->global
.loopback
);
2893 regs_buff
[num
++] = readl(&aregs
->global
.watchdog_timer
);
2896 regs_buff
[num
++] = readl(&aregs
->txdma
.csr
);
2897 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_base_hi
);
2898 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_base_lo
);
2899 regs_buff
[num
++] = readl(&aregs
->txdma
.pr_num_des
);
2900 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_wr_addr
);
2901 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_wr_addr_ext
);
2902 regs_buff
[num
++] = readl(&aregs
->txdma
.txq_rd_addr
);
2903 regs_buff
[num
++] = readl(&aregs
->txdma
.dma_wb_base_hi
);
2904 regs_buff
[num
++] = readl(&aregs
->txdma
.dma_wb_base_lo
);
2905 regs_buff
[num
++] = readl(&aregs
->txdma
.service_request
);
2906 regs_buff
[num
++] = readl(&aregs
->txdma
.service_complete
);
2907 regs_buff
[num
++] = readl(&aregs
->txdma
.cache_rd_index
);
2908 regs_buff
[num
++] = readl(&aregs
->txdma
.cache_wr_index
);
2909 regs_buff
[num
++] = readl(&aregs
->txdma
.tx_dma_error
);
2910 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_abort_cnt
);
2911 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_abort_cnt
);
2912 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_abort_cnt
);
2913 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_timeout_cnt
);
2914 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_timeout_cnt
);
2915 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_timeout_cnt
);
2916 regs_buff
[num
++] = readl(&aregs
->txdma
.desc_error_cnt
);
2917 regs_buff
[num
++] = readl(&aregs
->txdma
.payload_error_cnt
);
2918 regs_buff
[num
++] = readl(&aregs
->txdma
.writeback_error_cnt
);
2919 regs_buff
[num
++] = readl(&aregs
->txdma
.dropped_tlp_cnt
);
2920 regs_buff
[num
++] = readl(&aregs
->txdma
.new_service_complete
);
2921 regs_buff
[num
++] = readl(&aregs
->txdma
.ethernet_packet_cnt
);
2924 regs_buff
[num
++] = readl(&aregs
->rxdma
.csr
);
2925 regs_buff
[num
++] = readl(&aregs
->rxdma
.dma_wb_base_hi
);
2926 regs_buff
[num
++] = readl(&aregs
->rxdma
.dma_wb_base_lo
);
2927 regs_buff
[num
++] = readl(&aregs
->rxdma
.num_pkt_done
);
2928 regs_buff
[num
++] = readl(&aregs
->rxdma
.max_pkt_time
);
2929 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_rd_addr
);
2930 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_rd_addr_ext
);
2931 regs_buff
[num
++] = readl(&aregs
->rxdma
.rxq_wr_addr
);
2932 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_base_hi
);
2933 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_base_lo
);
2934 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_num_des
);
2935 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_avail_offset
);
2936 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_full_offset
);
2937 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_access_index
);
2938 regs_buff
[num
++] = readl(&aregs
->rxdma
.psr_min_des
);
2939 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_base_lo
);
2940 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_base_hi
);
2941 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_num_des
);
2942 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_avail_offset
);
2943 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_full_offset
);
2944 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_rd_index
);
2945 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr0_min_des
);
2946 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_base_lo
);
2947 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_base_hi
);
2948 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_num_des
);
2949 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_avail_offset
);
2950 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_full_offset
);
2951 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_rd_index
);
2952 regs_buff
[num
++] = readl(&aregs
->rxdma
.fbr1_min_des
);
2955 static void et131x_get_drvinfo(struct net_device
*netdev
,
2956 struct ethtool_drvinfo
*info
)
2958 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
2960 strlcpy(info
->driver
, DRIVER_NAME
, sizeof(info
->driver
));
2961 strlcpy(info
->version
, DRIVER_VERSION
, sizeof(info
->version
));
2962 strlcpy(info
->bus_info
, pci_name(adapter
->pdev
),
2963 sizeof(info
->bus_info
));
2966 static const struct ethtool_ops et131x_ethtool_ops
= {
2967 .get_drvinfo
= et131x_get_drvinfo
,
2968 .get_regs_len
= et131x_get_regs_len
,
2969 .get_regs
= et131x_get_regs
,
2970 .get_link
= ethtool_op_get_link
,
2971 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2972 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2975 /* et131x_hwaddr_init - set up the MAC Address */
2976 static void et131x_hwaddr_init(struct et131x_adapter
*adapter
)
2978 /* If have our default mac from init and no mac address from
2979 * EEPROM then we need to generate the last octet and set it on the
2982 if (is_zero_ether_addr(adapter
->rom_addr
)) {
2983 /* We need to randomly generate the last octet so we
2984 * decrease our chances of setting the mac address to
2985 * same as another one of our cards in the system
2987 get_random_bytes(&adapter
->addr
[5], 1);
2988 /* We have the default value in the register we are
2989 * working with so we need to copy the current
2990 * address into the permanent address
2992 ether_addr_copy(adapter
->rom_addr
, adapter
->addr
);
2994 /* We do not have an override address, so set the
2995 * current address to the permanent address and add
2998 ether_addr_copy(adapter
->addr
, adapter
->rom_addr
);
3002 static int et131x_pci_init(struct et131x_adapter
*adapter
,
3003 struct pci_dev
*pdev
)
3008 rc
= et131x_init_eeprom(adapter
);
3012 if (!pci_is_pcie(pdev
)) {
3013 dev_err(&pdev
->dev
, "Missing PCIe capabilities\n");
3017 /* Program the Ack/Nak latency and replay timers */
3018 max_payload
= pdev
->pcie_mpss
;
3020 if (max_payload
< 2) {
3021 static const u16 acknak
[2] = { 0x76, 0xD0 };
3022 static const u16 replay
[2] = { 0x1E0, 0x2ED };
3024 if (pci_write_config_word(pdev
, ET1310_PCI_ACK_NACK
,
3025 acknak
[max_payload
])) {
3027 "Could not write PCI config space for ACK/NAK\n");
3030 if (pci_write_config_word(pdev
, ET1310_PCI_REPLAY
,
3031 replay
[max_payload
])) {
3033 "Could not write PCI config space for Replay Timer\n");
3038 /* l0s and l1 latency timers. We are using default values.
3039 * Representing 001 for L0s and 010 for L1
3041 if (pci_write_config_byte(pdev
, ET1310_PCI_L0L1LATENCY
, 0x11)) {
3043 "Could not write PCI config space for Latency Timers\n");
3047 /* Change the max read size to 2k */
3048 if (pcie_set_readrq(pdev
, 2048)) {
3050 "Couldn't change PCI config space for Max read size\n");
3054 /* Get MAC address from config space if an eeprom exists, otherwise
3055 * the MAC address there will not be valid
3057 if (!adapter
->has_eeprom
) {
3058 et131x_hwaddr_init(adapter
);
3062 for (i
= 0; i
< ETH_ALEN
; i
++) {
3063 if (pci_read_config_byte(pdev
, ET1310_PCI_MAC_ADDRESS
+ i
,
3064 adapter
->rom_addr
+ i
)) {
3065 dev_err(&pdev
->dev
, "Could not read PCI config space for MAC address\n");
3069 ether_addr_copy(adapter
->addr
, adapter
->rom_addr
);
3077 /* et131x_error_timer_handler
3078 * @data: timer-specific variable; here a pointer to our adapter structure
3080 * The routine called when the error timer expires, to track the number of
3083 static void et131x_error_timer_handler(unsigned long data
)
3085 struct et131x_adapter
*adapter
= (struct et131x_adapter
*)data
;
3086 struct phy_device
*phydev
= adapter
->netdev
->phydev
;
3088 if (et1310_in_phy_coma(adapter
)) {
3089 /* Bring the device immediately out of coma, to
3090 * prevent it from sleeping indefinitely, this
3091 * mechanism could be improved!
3093 et1310_disable_phy_coma(adapter
);
3094 adapter
->boot_coma
= 20;
3096 et1310_update_macstat_host_counters(adapter
);
3099 if (!phydev
->link
&& adapter
->boot_coma
< 11)
3100 adapter
->boot_coma
++;
3102 if (adapter
->boot_coma
== 10) {
3103 if (!phydev
->link
) {
3104 if (!et1310_in_phy_coma(adapter
)) {
3105 /* NOTE - This was originally a 'sync with
3106 * interrupt'. How to do that under Linux?
3108 et131x_enable_interrupts(adapter
);
3109 et1310_enable_phy_coma(adapter
);
3114 /* This is a periodic timer, so reschedule */
3115 mod_timer(&adapter
->error_timer
, jiffies
+
3116 msecs_to_jiffies(TX_ERROR_PERIOD
));
3119 static void et131x_adapter_memory_free(struct et131x_adapter
*adapter
)
3121 et131x_tx_dma_memory_free(adapter
);
3122 et131x_rx_dma_memory_free(adapter
);
3125 static int et131x_adapter_memory_alloc(struct et131x_adapter
*adapter
)
3129 status
= et131x_tx_dma_memory_alloc(adapter
);
3131 dev_err(&adapter
->pdev
->dev
,
3132 "et131x_tx_dma_memory_alloc FAILED\n");
3133 et131x_tx_dma_memory_free(adapter
);
3137 status
= et131x_rx_dma_memory_alloc(adapter
);
3139 dev_err(&adapter
->pdev
->dev
,
3140 "et131x_rx_dma_memory_alloc FAILED\n");
3141 et131x_adapter_memory_free(adapter
);
3145 status
= et131x_init_recv(adapter
);
3147 dev_err(&adapter
->pdev
->dev
, "et131x_init_recv FAILED\n");
3148 et131x_adapter_memory_free(adapter
);
3153 static void et131x_adjust_link(struct net_device
*netdev
)
3155 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3156 struct phy_device
*phydev
= netdev
->phydev
;
3160 if (phydev
->link
== adapter
->link
)
3163 /* Check to see if we are in coma mode and if
3164 * so, disable it because we will not be able
3165 * to read PHY values until we are out.
3167 if (et1310_in_phy_coma(adapter
))
3168 et1310_disable_phy_coma(adapter
);
3170 adapter
->link
= phydev
->link
;
3171 phy_print_status(phydev
);
3174 adapter
->boot_coma
= 20;
3175 if (phydev
->speed
== SPEED_10
) {
3178 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
,
3180 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3181 PHY_MPHY_CONTROL_REG
,
3183 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3184 PHY_INDEX_REG
, register18
| 0x8402);
3185 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3186 PHY_DATA_REG
, register18
| 511);
3187 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3188 PHY_MPHY_CONTROL_REG
, register18
);
3191 et1310_config_flow_control(adapter
);
3193 if (phydev
->speed
== SPEED_1000
&&
3194 adapter
->registry_jumbo_packet
> 2048) {
3197 et131x_mii_read(adapter
, PHY_CONFIG
, ®
);
3198 reg
&= ~ET_PHY_CONFIG_TX_FIFO_DEPTH
;
3199 reg
|= ET_PHY_CONFIG_FIFO_DEPTH_32
;
3200 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3204 et131x_set_rx_dma_timer(adapter
);
3205 et1310_config_mac_regs2(adapter
);
3207 adapter
->boot_coma
= 0;
3209 if (phydev
->speed
== SPEED_10
) {
3212 et131x_mii_read(adapter
, PHY_MPHY_CONTROL_REG
,
3214 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3215 PHY_MPHY_CONTROL_REG
,
3217 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3218 PHY_INDEX_REG
, register18
| 0x8402);
3219 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3220 PHY_DATA_REG
, register18
| 511);
3221 et131x_mii_write(adapter
, phydev
->mdio
.addr
,
3222 PHY_MPHY_CONTROL_REG
, register18
);
3225 et131x_free_busy_send_packets(adapter
);
3226 et131x_init_send(adapter
);
3228 /* Bring the device back to the state it was during
3229 * init prior to autonegotiation being complete. This
3230 * way, when we get the auto-neg complete interrupt,
3231 * we can complete init by calling config_mac_regs2.
3233 et131x_soft_reset(adapter
);
3235 et131x_adapter_setup(adapter
);
3237 et131x_disable_txrx(netdev
);
3238 et131x_enable_txrx(netdev
);
3242 static int et131x_mii_probe(struct net_device
*netdev
)
3244 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3245 struct phy_device
*phydev
= NULL
;
3247 phydev
= phy_find_first(adapter
->mii_bus
);
3249 dev_err(&adapter
->pdev
->dev
, "no PHY found\n");
3253 phydev
= phy_connect(netdev
, phydev_name(phydev
),
3254 &et131x_adjust_link
, PHY_INTERFACE_MODE_MII
);
3256 if (IS_ERR(phydev
)) {
3257 dev_err(&adapter
->pdev
->dev
, "Could not attach to PHY\n");
3258 return PTR_ERR(phydev
);
3261 phydev
->supported
&= (SUPPORTED_10baseT_Half
|
3262 SUPPORTED_10baseT_Full
|
3263 SUPPORTED_100baseT_Half
|
3264 SUPPORTED_100baseT_Full
|
3269 if (adapter
->pdev
->device
!= ET131X_PCI_DEVICE_ID_FAST
)
3270 phydev
->supported
|= SUPPORTED_1000baseT_Half
|
3271 SUPPORTED_1000baseT_Full
;
3273 phydev
->advertising
= phydev
->supported
;
3274 phydev
->autoneg
= AUTONEG_ENABLE
;
3276 phy_attached_info(phydev
);
3281 static struct et131x_adapter
*et131x_adapter_init(struct net_device
*netdev
,
3282 struct pci_dev
*pdev
)
3284 static const u8 default_mac
[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3286 struct et131x_adapter
*adapter
;
3288 adapter
= netdev_priv(netdev
);
3289 adapter
->pdev
= pci_dev_get(pdev
);
3290 adapter
->netdev
= netdev
;
3292 spin_lock_init(&adapter
->tcb_send_qlock
);
3293 spin_lock_init(&adapter
->tcb_ready_qlock
);
3294 spin_lock_init(&adapter
->rcv_lock
);
3296 adapter
->registry_jumbo_packet
= 1514; /* 1514-9216 */
3298 ether_addr_copy(adapter
->addr
, default_mac
);
3303 static void et131x_pci_remove(struct pci_dev
*pdev
)
3305 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3306 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3308 unregister_netdev(netdev
);
3309 netif_napi_del(&adapter
->napi
);
3310 phy_disconnect(netdev
->phydev
);
3311 mdiobus_unregister(adapter
->mii_bus
);
3312 mdiobus_free(adapter
->mii_bus
);
3314 et131x_adapter_memory_free(adapter
);
3315 iounmap(adapter
->regs
);
3318 free_netdev(netdev
);
3319 pci_release_regions(pdev
);
3320 pci_disable_device(pdev
);
3323 static void et131x_up(struct net_device
*netdev
)
3325 et131x_enable_txrx(netdev
);
3326 phy_start(netdev
->phydev
);
3329 static void et131x_down(struct net_device
*netdev
)
3331 /* Save the timestamp for the TX watchdog, prevent a timeout */
3332 netif_trans_update(netdev
);
3334 phy_stop(netdev
->phydev
);
3335 et131x_disable_txrx(netdev
);
3338 #ifdef CONFIG_PM_SLEEP
3339 static int et131x_suspend(struct device
*dev
)
3341 struct pci_dev
*pdev
= to_pci_dev(dev
);
3342 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3344 if (netif_running(netdev
)) {
3345 netif_device_detach(netdev
);
3346 et131x_down(netdev
);
3347 pci_save_state(pdev
);
3353 static int et131x_resume(struct device
*dev
)
3355 struct pci_dev
*pdev
= to_pci_dev(dev
);
3356 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3358 if (netif_running(netdev
)) {
3359 pci_restore_state(pdev
);
3361 netif_device_attach(netdev
);
3368 static SIMPLE_DEV_PM_OPS(et131x_pm_ops
, et131x_suspend
, et131x_resume
);
3370 static irqreturn_t
et131x_isr(int irq
, void *dev_id
)
3372 bool handled
= true;
3373 bool enable_interrupts
= true;
3374 struct net_device
*netdev
= dev_id
;
3375 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3376 struct address_map __iomem
*iomem
= adapter
->regs
;
3377 struct rx_ring
*rx_ring
= &adapter
->rx_ring
;
3378 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
3381 if (!netif_device_present(netdev
)) {
3383 enable_interrupts
= false;
3387 et131x_disable_interrupts(adapter
);
3389 status
= readl(&adapter
->regs
->global
.int_status
);
3391 if (adapter
->flow
== FLOW_TXONLY
|| adapter
->flow
== FLOW_BOTH
)
3392 status
&= ~INT_MASK_ENABLE
;
3394 status
&= ~INT_MASK_ENABLE_NO_FLOW
;
3396 /* Make sure this is our interrupt */
3399 et131x_enable_interrupts(adapter
);
3403 /* This is our interrupt, so process accordingly */
3404 if (status
& ET_INTR_WATCHDOG
) {
3405 struct tcb
*tcb
= tx_ring
->send_head
;
3408 if (++tcb
->stale
> 1)
3409 status
|= ET_INTR_TXDMA_ISR
;
3411 if (rx_ring
->unfinished_receives
)
3412 status
|= ET_INTR_RXDMA_XFR_DONE
;
3413 else if (tcb
== NULL
)
3414 writel(0, &adapter
->regs
->global
.watchdog_timer
);
3416 status
&= ~ET_INTR_WATCHDOG
;
3419 if (status
& (ET_INTR_RXDMA_XFR_DONE
| ET_INTR_TXDMA_ISR
)) {
3420 enable_interrupts
= false;
3421 napi_schedule(&adapter
->napi
);
3424 status
&= ~(ET_INTR_TXDMA_ISR
| ET_INTR_RXDMA_XFR_DONE
);
3429 if (status
& ET_INTR_TXDMA_ERR
) {
3430 /* Following read also clears the register (COR) */
3431 u32 txdma_err
= readl(&iomem
->txdma
.tx_dma_error
);
3433 dev_warn(&adapter
->pdev
->dev
,
3434 "TXDMA_ERR interrupt, error = %d\n",
3438 if (status
& (ET_INTR_RXDMA_FB_R0_LOW
| ET_INTR_RXDMA_FB_R1_LOW
)) {
3439 /* This indicates the number of unused buffers in RXDMA free
3440 * buffer ring 0 is <= the limit you programmed. Free buffer
3441 * resources need to be returned. Free buffers are consumed as
3442 * packets are passed from the network to the host. The host
3443 * becomes aware of the packets from the contents of the packet
3444 * status ring. This ring is queried when the packet done
3445 * interrupt occurs. Packets are then passed to the OS. When
3446 * the OS is done with the packets the resources can be
3447 * returned to the ET1310 for re-use. This interrupt is one
3448 * method of returning resources.
3451 /* If the user has flow control on, then we will
3452 * send a pause packet, otherwise just exit
3454 if (adapter
->flow
== FLOW_TXONLY
|| adapter
->flow
== FLOW_BOTH
) {
3457 /* Tell the device to send a pause packet via the back
3458 * pressure register (bp req and bp xon/xoff)
3460 pm_csr
= readl(&iomem
->global
.pm_csr
);
3461 if (!et1310_in_phy_coma(adapter
))
3462 writel(3, &iomem
->txmac
.bp_ctrl
);
3466 /* Handle Packet Status Ring Low Interrupt */
3467 if (status
& ET_INTR_RXDMA_STAT_LOW
) {
3468 /* Same idea as with the two Free Buffer Rings. Packets going
3469 * from the network to the host each consume a free buffer
3470 * resource and a packet status resource. These resources are
3471 * passed to the OS. When the OS is done with the resources,
3472 * they need to be returned to the ET1310. This is one method
3473 * of returning the resources.
3477 if (status
& ET_INTR_RXDMA_ERR
) {
3478 /* The rxdma_error interrupt is sent when a time-out on a
3479 * request issued by the JAGCore has occurred or a completion is
3480 * returned with an un-successful status. In both cases the
3481 * request is considered complete. The JAGCore will
3482 * automatically re-try the request in question. Normally
3483 * information on events like these are sent to the host using
3484 * the "Advanced Error Reporting" capability. This interrupt is
3485 * another way of getting similar information. The only thing
3486 * required is to clear the interrupt by reading the ISR in the
3487 * global resources. The JAGCore will do a re-try on the
3488 * request. Normally you should never see this interrupt. If
3489 * you start to see this interrupt occurring frequently then
3490 * something bad has occurred. A reset might be the thing to do.
3494 dev_warn(&adapter
->pdev
->dev
, "RxDMA_ERR interrupt, error %x\n",
3495 readl(&iomem
->txmac
.tx_test
));
3498 /* Handle the Wake on LAN Event */
3499 if (status
& ET_INTR_WOL
) {
3500 /* This is a secondary interrupt for wake on LAN. The driver
3501 * should never see this, if it does, something serious is
3504 dev_err(&adapter
->pdev
->dev
, "WAKE_ON_LAN interrupt\n");
3507 if (status
& ET_INTR_TXMAC
) {
3508 u32 err
= readl(&iomem
->txmac
.err
);
3510 /* When any of the errors occur and TXMAC generates an
3511 * interrupt to report these errors, it usually means that
3512 * TXMAC has detected an error in the data stream retrieved
3513 * from the on-chip Tx Q. All of these errors are catastrophic
3514 * and TXMAC won't be able to recover data when these errors
3515 * occur. In a nutshell, the whole Tx path will have to be reset
3516 * and re-configured afterwards.
3518 dev_warn(&adapter
->pdev
->dev
, "TXMAC interrupt, error 0x%08x\n",
3521 /* If we are debugging, we want to see this error, otherwise we
3522 * just want the device to be reset and continue
3526 if (status
& ET_INTR_RXMAC
) {
3527 /* These interrupts are catastrophic to the device, what we need
3528 * to do is disable the interrupts and set the flag to cause us
3529 * to reset so we can solve this issue.
3531 dev_warn(&adapter
->pdev
->dev
,
3532 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
3533 readl(&iomem
->rxmac
.err_reg
));
3535 dev_warn(&adapter
->pdev
->dev
,
3536 "Enable 0x%08x, Diag 0x%08x\n",
3537 readl(&iomem
->rxmac
.ctrl
),
3538 readl(&iomem
->rxmac
.rxq_diag
));
3540 /* If we are debugging, we want to see this error, otherwise we
3541 * just want the device to be reset and continue
3545 if (status
& ET_INTR_MAC_STAT
) {
3546 /* This means at least one of the un-masked counters in the
3547 * MAC_STAT block has rolled over. Use this to maintain the top,
3548 * software managed bits of the counter(s).
3550 et1310_handle_macstat_interrupt(adapter
);
3553 if (status
& ET_INTR_SLV_TIMEOUT
) {
3554 /* This means a timeout has occurred on a read or write request
3555 * to one of the JAGCore registers. The Global Resources block
3556 * has terminated the request and on a read request, returned a
3557 * "fake" value. The most likely reasons are: Bad Address or the
3558 * addressed module is in a power-down state and can't respond.
3563 if (enable_interrupts
)
3564 et131x_enable_interrupts(adapter
);
3566 return IRQ_RETVAL(handled
);
3569 static int et131x_poll(struct napi_struct
*napi
, int budget
)
3571 struct et131x_adapter
*adapter
=
3572 container_of(napi
, struct et131x_adapter
, napi
);
3573 int work_done
= et131x_handle_recv_pkts(adapter
, budget
);
3575 et131x_handle_send_pkts(adapter
);
3577 if (work_done
< budget
) {
3578 napi_complete_done(&adapter
->napi
, work_done
);
3579 et131x_enable_interrupts(adapter
);
3585 /* et131x_stats - Return the current device statistics */
3586 static struct net_device_stats
*et131x_stats(struct net_device
*netdev
)
3588 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3589 struct net_device_stats
*stats
= &adapter
->netdev
->stats
;
3590 struct ce_stats
*devstat
= &adapter
->stats
;
3592 stats
->rx_errors
= devstat
->rx_length_errs
+
3593 devstat
->rx_align_errs
+
3594 devstat
->rx_crc_errs
+
3595 devstat
->rx_code_violations
+
3596 devstat
->rx_other_errs
;
3597 stats
->tx_errors
= devstat
->tx_max_pkt_errs
;
3598 stats
->multicast
= devstat
->multicast_pkts_rcvd
;
3599 stats
->collisions
= devstat
->tx_collisions
;
3601 stats
->rx_length_errors
= devstat
->rx_length_errs
;
3602 stats
->rx_over_errors
= devstat
->rx_overflows
;
3603 stats
->rx_crc_errors
= devstat
->rx_crc_errs
;
3604 stats
->rx_dropped
= devstat
->rcvd_pkts_dropped
;
3606 /* NOTE: Not used, can't find analogous statistics */
3607 /* stats->rx_frame_errors = devstat->; */
3608 /* stats->rx_fifo_errors = devstat->; */
3609 /* stats->rx_missed_errors = devstat->; */
3611 /* stats->tx_aborted_errors = devstat->; */
3612 /* stats->tx_carrier_errors = devstat->; */
3613 /* stats->tx_fifo_errors = devstat->; */
3614 /* stats->tx_heartbeat_errors = devstat->; */
3615 /* stats->tx_window_errors = devstat->; */
3619 static int et131x_open(struct net_device
*netdev
)
3621 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3622 struct pci_dev
*pdev
= adapter
->pdev
;
3623 unsigned int irq
= pdev
->irq
;
3626 /* Start the timer to track NIC errors */
3627 init_timer(&adapter
->error_timer
);
3628 adapter
->error_timer
.expires
= jiffies
+
3629 msecs_to_jiffies(TX_ERROR_PERIOD
);
3630 adapter
->error_timer
.function
= et131x_error_timer_handler
;
3631 adapter
->error_timer
.data
= (unsigned long)adapter
;
3632 add_timer(&adapter
->error_timer
);
3634 result
= request_irq(irq
, et131x_isr
,
3635 IRQF_SHARED
, netdev
->name
, netdev
);
3637 dev_err(&pdev
->dev
, "could not register IRQ %d\n", irq
);
3641 adapter
->flags
|= FMP_ADAPTER_INTERRUPT_IN_USE
;
3643 napi_enable(&adapter
->napi
);
3650 static int et131x_close(struct net_device
*netdev
)
3652 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3654 et131x_down(netdev
);
3655 napi_disable(&adapter
->napi
);
3657 adapter
->flags
&= ~FMP_ADAPTER_INTERRUPT_IN_USE
;
3658 free_irq(adapter
->pdev
->irq
, netdev
);
3660 /* Stop the error timer */
3661 return del_timer_sync(&adapter
->error_timer
);
3664 static int et131x_ioctl(struct net_device
*netdev
, struct ifreq
*reqbuf
,
3667 if (!netdev
->phydev
)
3670 return phy_mii_ioctl(netdev
->phydev
, reqbuf
, cmd
);
3673 /* et131x_set_packet_filter - Configures the Rx Packet filtering */
3674 static int et131x_set_packet_filter(struct et131x_adapter
*adapter
)
3676 int filter
= adapter
->packet_filter
;
3680 ctrl
= readl(&adapter
->regs
->rxmac
.ctrl
);
3681 pf_ctrl
= readl(&adapter
->regs
->rxmac
.pf_ctrl
);
3683 /* Default to disabled packet filtering */
3686 /* Set us to be in promiscuous mode so we receive everything, this
3687 * is also true when we get a packet filter of 0
3689 if ((filter
& ET131X_PACKET_TYPE_PROMISCUOUS
) || filter
== 0)
3690 pf_ctrl
&= ~7; /* Clear filter bits */
3692 /* Set us up with Multicast packet filtering. Three cases are
3693 * possible - (1) we have a multi-cast list, (2) we receive ALL
3694 * multicast entries or (3) we receive none.
3696 if (filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)
3697 pf_ctrl
&= ~2; /* Multicast filter bit */
3699 et1310_setup_device_for_multicast(adapter
);
3704 /* Set us up with Unicast packet filtering */
3705 if (filter
& ET131X_PACKET_TYPE_DIRECTED
) {
3706 et1310_setup_device_for_unicast(adapter
);
3711 /* Set us up with Broadcast packet filtering */
3712 if (filter
& ET131X_PACKET_TYPE_BROADCAST
) {
3713 pf_ctrl
|= 1; /* Broadcast filter bit */
3719 /* Setup the receive mac configuration registers - Packet
3720 * Filter control + the enable / disable for packet filter
3721 * in the control reg.
3723 writel(pf_ctrl
, &adapter
->regs
->rxmac
.pf_ctrl
);
3724 writel(ctrl
, &adapter
->regs
->rxmac
.ctrl
);
3729 static void et131x_multicast(struct net_device
*netdev
)
3731 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3733 struct netdev_hw_addr
*ha
;
3736 /* Before we modify the platform-independent filter flags, store them
3737 * locally. This allows us to determine if anything's changed and if
3738 * we even need to bother the hardware
3740 packet_filter
= adapter
->packet_filter
;
3742 /* Clear the 'multicast' flag locally; because we only have a single
3743 * flag to check multicast, and multiple multicast addresses can be
3744 * set, this is the easiest way to determine if more than one
3745 * multicast address is being set.
3747 packet_filter
&= ~ET131X_PACKET_TYPE_MULTICAST
;
3749 /* Check the net_device flags and set the device independent flags
3752 if (netdev
->flags
& IFF_PROMISC
)
3753 adapter
->packet_filter
|= ET131X_PACKET_TYPE_PROMISCUOUS
;
3755 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_PROMISCUOUS
;
3757 if ((netdev
->flags
& IFF_ALLMULTI
) ||
3758 (netdev_mc_count(netdev
) > NIC_MAX_MCAST_LIST
))
3759 adapter
->packet_filter
|= ET131X_PACKET_TYPE_ALL_MULTICAST
;
3761 if (netdev_mc_count(netdev
) < 1) {
3762 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_ALL_MULTICAST
;
3763 adapter
->packet_filter
&= ~ET131X_PACKET_TYPE_MULTICAST
;
3765 adapter
->packet_filter
|= ET131X_PACKET_TYPE_MULTICAST
;
3768 /* Set values in the private adapter struct */
3770 netdev_for_each_mc_addr(ha
, netdev
) {
3771 if (i
== NIC_MAX_MCAST_LIST
)
3773 ether_addr_copy(adapter
->multicast_list
[i
++], ha
->addr
);
3775 adapter
->multicast_addr_count
= i
;
3777 /* Are the new flags different from the previous ones? If not, then no
3778 * action is required
3780 * NOTE - This block will always update the multicast_list with the
3781 * hardware, even if the addresses aren't the same.
3783 if (packet_filter
!= adapter
->packet_filter
)
3784 et131x_set_packet_filter(adapter
);
3787 static netdev_tx_t
et131x_tx(struct sk_buff
*skb
, struct net_device
*netdev
)
3789 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3790 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
3792 /* stop the queue if it's getting full */
3793 if (tx_ring
->used
>= NUM_TCB
- 1 && !netif_queue_stopped(netdev
))
3794 netif_stop_queue(netdev
);
3796 /* Save the timestamp for the TX timeout watchdog */
3797 netif_trans_update(netdev
);
3799 /* TCB is not available */
3800 if (tx_ring
->used
>= NUM_TCB
)
3803 if ((adapter
->flags
& FMP_ADAPTER_FAIL_SEND_MASK
) ||
3804 !netif_carrier_ok(netdev
))
3807 if (send_packet(skb
, adapter
))
3810 return NETDEV_TX_OK
;
3813 dev_kfree_skb_any(skb
);
3814 adapter
->netdev
->stats
.tx_dropped
++;
3815 return NETDEV_TX_OK
;
3818 /* et131x_tx_timeout - Timeout handler
3820 * The handler called when a Tx request times out. The timeout period is
3821 * specified by the 'tx_timeo" element in the net_device structure (see
3822 * et131x_alloc_device() to see how this value is set).
3824 static void et131x_tx_timeout(struct net_device
*netdev
)
3826 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3827 struct tx_ring
*tx_ring
= &adapter
->tx_ring
;
3829 unsigned long flags
;
3831 /* If the device is closed, ignore the timeout */
3832 if (!(adapter
->flags
& FMP_ADAPTER_INTERRUPT_IN_USE
))
3835 /* Any nonrecoverable hardware error?
3836 * Checks adapter->flags for any failure in phy reading
3838 if (adapter
->flags
& FMP_ADAPTER_NON_RECOVER_ERROR
)
3841 /* Hardware failure? */
3842 if (adapter
->flags
& FMP_ADAPTER_HARDWARE_ERROR
) {
3843 dev_err(&adapter
->pdev
->dev
, "hardware error - reset\n");
3847 /* Is send stuck? */
3848 spin_lock_irqsave(&adapter
->tcb_send_qlock
, flags
);
3849 tcb
= tx_ring
->send_head
;
3850 spin_unlock_irqrestore(&adapter
->tcb_send_qlock
, flags
);
3855 if (tcb
->count
> NIC_SEND_HANG_THRESHOLD
) {
3856 dev_warn(&adapter
->pdev
->dev
,
3857 "Send stuck - reset. tcb->WrIndex %x\n",
3860 adapter
->netdev
->stats
.tx_errors
++;
3862 /* perform reset of tx/rx */
3863 et131x_disable_txrx(netdev
);
3864 et131x_enable_txrx(netdev
);
3869 static int et131x_change_mtu(struct net_device
*netdev
, int new_mtu
)
3872 struct et131x_adapter
*adapter
= netdev_priv(netdev
);
3874 et131x_disable_txrx(netdev
);
3876 netdev
->mtu
= new_mtu
;
3878 et131x_adapter_memory_free(adapter
);
3880 /* Set the config parameter for Jumbo Packet support */
3881 adapter
->registry_jumbo_packet
= new_mtu
+ 14;
3882 et131x_soft_reset(adapter
);
3884 result
= et131x_adapter_memory_alloc(adapter
);
3886 dev_warn(&adapter
->pdev
->dev
,
3887 "Change MTU failed; couldn't re-alloc DMA memory\n");
3891 et131x_init_send(adapter
);
3892 et131x_hwaddr_init(adapter
);
3893 ether_addr_copy(netdev
->dev_addr
, adapter
->addr
);
3895 /* Init the device with the new settings */
3896 et131x_adapter_setup(adapter
);
3897 et131x_enable_txrx(netdev
);
3902 static const struct net_device_ops et131x_netdev_ops
= {
3903 .ndo_open
= et131x_open
,
3904 .ndo_stop
= et131x_close
,
3905 .ndo_start_xmit
= et131x_tx
,
3906 .ndo_set_rx_mode
= et131x_multicast
,
3907 .ndo_tx_timeout
= et131x_tx_timeout
,
3908 .ndo_change_mtu
= et131x_change_mtu
,
3909 .ndo_set_mac_address
= eth_mac_addr
,
3910 .ndo_validate_addr
= eth_validate_addr
,
3911 .ndo_get_stats
= et131x_stats
,
3912 .ndo_do_ioctl
= et131x_ioctl
,
3915 static int et131x_pci_setup(struct pci_dev
*pdev
,
3916 const struct pci_device_id
*ent
)
3918 struct net_device
*netdev
;
3919 struct et131x_adapter
*adapter
;
3922 rc
= pci_enable_device(pdev
);
3924 dev_err(&pdev
->dev
, "pci_enable_device() failed\n");
3928 /* Perform some basic PCI checks */
3929 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
3930 dev_err(&pdev
->dev
, "Can't find PCI device's base address\n");
3935 rc
= pci_request_regions(pdev
, DRIVER_NAME
);
3937 dev_err(&pdev
->dev
, "Can't get PCI resources\n");
3941 pci_set_master(pdev
);
3943 /* Check the DMA addressing support of this device */
3944 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) &&
3945 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32))) {
3946 dev_err(&pdev
->dev
, "No usable DMA addressing method\n");
3948 goto err_release_res
;
3951 netdev
= alloc_etherdev(sizeof(struct et131x_adapter
));
3953 dev_err(&pdev
->dev
, "Couldn't alloc netdev struct\n");
3955 goto err_release_res
;
3958 netdev
->watchdog_timeo
= ET131X_TX_TIMEOUT
;
3959 netdev
->netdev_ops
= &et131x_netdev_ops
;
3960 netdev
->min_mtu
= ET131X_MIN_MTU
;
3961 netdev
->max_mtu
= ET131X_MAX_MTU
;
3963 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3964 netdev
->ethtool_ops
= &et131x_ethtool_ops
;
3966 adapter
= et131x_adapter_init(netdev
, pdev
);
3968 rc
= et131x_pci_init(adapter
, pdev
);
3972 /* Map the bus-relative registers to system virtual memory */
3973 adapter
->regs
= pci_ioremap_bar(pdev
, 0);
3974 if (!adapter
->regs
) {
3975 dev_err(&pdev
->dev
, "Cannot map device registers\n");
3980 /* If Phy COMA mode was enabled when we went down, disable it here. */
3981 writel(ET_PMCSR_INIT
, &adapter
->regs
->global
.pm_csr
);
3983 et131x_soft_reset(adapter
);
3984 et131x_disable_interrupts(adapter
);
3986 rc
= et131x_adapter_memory_alloc(adapter
);
3988 dev_err(&pdev
->dev
, "Could not alloc adapter memory (DMA)\n");
3992 et131x_init_send(adapter
);
3994 netif_napi_add(netdev
, &adapter
->napi
, et131x_poll
, 64);
3996 ether_addr_copy(netdev
->dev_addr
, adapter
->addr
);
4000 adapter
->mii_bus
= mdiobus_alloc();
4001 if (!adapter
->mii_bus
) {
4002 dev_err(&pdev
->dev
, "Alloc of mii_bus struct failed\n");
4006 adapter
->mii_bus
->name
= "et131x_eth_mii";
4007 snprintf(adapter
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x",
4008 (adapter
->pdev
->bus
->number
<< 8) | adapter
->pdev
->devfn
);
4009 adapter
->mii_bus
->priv
= netdev
;
4010 adapter
->mii_bus
->read
= et131x_mdio_read
;
4011 adapter
->mii_bus
->write
= et131x_mdio_write
;
4013 rc
= mdiobus_register(adapter
->mii_bus
);
4015 dev_err(&pdev
->dev
, "failed to register MII bus\n");
4019 rc
= et131x_mii_probe(netdev
);
4021 dev_err(&pdev
->dev
, "failed to probe MII bus\n");
4022 goto err_mdio_unregister
;
4025 et131x_adapter_setup(adapter
);
4027 /* Init variable for counting how long we do not have link status */
4028 adapter
->boot_coma
= 0;
4029 et1310_disable_phy_coma(adapter
);
4031 /* We can enable interrupts now
4033 * NOTE - Because registration of interrupt handler is done in the
4034 * device's open(), defer enabling device interrupts to that
4038 rc
= register_netdev(netdev
);
4040 dev_err(&pdev
->dev
, "register_netdev() failed\n");
4041 goto err_phy_disconnect
;
4044 /* Register the net_device struct with the PCI subsystem. Save a copy
4045 * of the PCI config space for this device now that the device has
4046 * been initialized, just in case it needs to be quickly restored.
4048 pci_set_drvdata(pdev
, netdev
);
4053 phy_disconnect(netdev
->phydev
);
4054 err_mdio_unregister
:
4055 mdiobus_unregister(adapter
->mii_bus
);
4057 mdiobus_free(adapter
->mii_bus
);
4059 et131x_adapter_memory_free(adapter
);
4061 iounmap(adapter
->regs
);
4064 free_netdev(netdev
);
4066 pci_release_regions(pdev
);
4068 pci_disable_device(pdev
);
4072 static const struct pci_device_id et131x_pci_table
[] = {
4073 { PCI_VDEVICE(ATT
, ET131X_PCI_DEVICE_ID_GIG
), 0UL},
4074 { PCI_VDEVICE(ATT
, ET131X_PCI_DEVICE_ID_FAST
), 0UL},
4077 MODULE_DEVICE_TABLE(pci
, et131x_pci_table
);
4079 static struct pci_driver et131x_driver
= {
4080 .name
= DRIVER_NAME
,
4081 .id_table
= et131x_pci_table
,
4082 .probe
= et131x_pci_setup
,
4083 .remove
= et131x_pci_remove
,
4084 .driver
.pm
= &et131x_pm_ops
,
4087 module_pci_driver(et131x_driver
);