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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-dev.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/phy.h>
118 #include <linux/clk.h>
119 #include <linux/bitrev.h>
120 #include <linux/crc32.h>
121
122 #include "xgbe.h"
123 #include "xgbe-common.h"
124
125 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
126 unsigned int usec)
127 {
128 unsigned long rate;
129 unsigned int ret;
130
131 DBGPR("-->xgbe_usec_to_riwt\n");
132
133 rate = clk_get_rate(pdata->sysclk);
134
135 /*
136 * Convert the input usec value to the watchdog timer value. Each
137 * watchdog timer value is equivalent to 256 clock cycles.
138 * Calculate the required value as:
139 * ( usec * ( system_clock_mhz / 10^6 ) / 256
140 */
141 ret = (usec * (rate / 1000000)) / 256;
142
143 DBGPR("<--xgbe_usec_to_riwt\n");
144
145 return ret;
146 }
147
148 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
149 unsigned int riwt)
150 {
151 unsigned long rate;
152 unsigned int ret;
153
154 DBGPR("-->xgbe_riwt_to_usec\n");
155
156 rate = clk_get_rate(pdata->sysclk);
157
158 /*
159 * Convert the input watchdog timer value to the usec value. Each
160 * watchdog timer value is equivalent to 256 clock cycles.
161 * Calculate the required value as:
162 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
163 */
164 ret = (riwt * 256) / (rate / 1000000);
165
166 DBGPR("<--xgbe_riwt_to_usec\n");
167
168 return ret;
169 }
170
171 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
172 {
173 struct xgbe_channel *channel;
174 unsigned int i;
175
176 channel = pdata->channel;
177 for (i = 0; i < pdata->channel_count; i++, channel++)
178 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
179 pdata->pblx8);
180
181 return 0;
182 }
183
184 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
185 {
186 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
187 }
188
189 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
190 {
191 struct xgbe_channel *channel;
192 unsigned int i;
193
194 channel = pdata->channel;
195 for (i = 0; i < pdata->channel_count; i++, channel++) {
196 if (!channel->tx_ring)
197 break;
198
199 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
200 pdata->tx_pbl);
201 }
202
203 return 0;
204 }
205
206 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
207 {
208 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
209 }
210
211 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
212 {
213 struct xgbe_channel *channel;
214 unsigned int i;
215
216 channel = pdata->channel;
217 for (i = 0; i < pdata->channel_count; i++, channel++) {
218 if (!channel->rx_ring)
219 break;
220
221 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
222 pdata->rx_pbl);
223 }
224
225 return 0;
226 }
227
228 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
229 {
230 struct xgbe_channel *channel;
231 unsigned int i;
232
233 channel = pdata->channel;
234 for (i = 0; i < pdata->channel_count; i++, channel++) {
235 if (!channel->tx_ring)
236 break;
237
238 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
239 pdata->tx_osp_mode);
240 }
241
242 return 0;
243 }
244
245 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
246 {
247 unsigned int i;
248
249 for (i = 0; i < pdata->rx_q_count; i++)
250 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
251
252 return 0;
253 }
254
255 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
256 {
257 unsigned int i;
258
259 for (i = 0; i < pdata->tx_q_count; i++)
260 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
261
262 return 0;
263 }
264
265 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
266 unsigned int val)
267 {
268 unsigned int i;
269
270 for (i = 0; i < pdata->rx_q_count; i++)
271 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
272
273 return 0;
274 }
275
276 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
277 unsigned int val)
278 {
279 unsigned int i;
280
281 for (i = 0; i < pdata->tx_q_count; i++)
282 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
283
284 return 0;
285 }
286
287 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
288 {
289 struct xgbe_channel *channel;
290 unsigned int i;
291
292 channel = pdata->channel;
293 for (i = 0; i < pdata->channel_count; i++, channel++) {
294 if (!channel->rx_ring)
295 break;
296
297 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
298 pdata->rx_riwt);
299 }
300
301 return 0;
302 }
303
304 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
305 {
306 return 0;
307 }
308
309 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
310 {
311 struct xgbe_channel *channel;
312 unsigned int i;
313
314 channel = pdata->channel;
315 for (i = 0; i < pdata->channel_count; i++, channel++) {
316 if (!channel->rx_ring)
317 break;
318
319 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
320 pdata->rx_buf_size);
321 }
322 }
323
324 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
325 {
326 struct xgbe_channel *channel;
327 unsigned int i;
328
329 channel = pdata->channel;
330 for (i = 0; i < pdata->channel_count; i++, channel++) {
331 if (!channel->tx_ring)
332 break;
333
334 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
335 }
336 }
337
338 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
339 {
340 struct xgbe_channel *channel;
341 unsigned int i;
342
343 channel = pdata->channel;
344 for (i = 0; i < pdata->channel_count; i++, channel++) {
345 if (!channel->rx_ring)
346 break;
347
348 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
349 }
350
351 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
352 }
353
354 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
355 unsigned int index, unsigned int val)
356 {
357 unsigned int wait;
358 int ret = 0;
359
360 mutex_lock(&pdata->rss_mutex);
361
362 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
363 ret = -EBUSY;
364 goto unlock;
365 }
366
367 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
368
369 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
373
374 wait = 1000;
375 while (wait--) {
376 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
377 goto unlock;
378
379 usleep_range(1000, 1500);
380 }
381
382 ret = -EBUSY;
383
384 unlock:
385 mutex_unlock(&pdata->rss_mutex);
386
387 return ret;
388 }
389
390 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
391 {
392 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
393 unsigned int *key = (unsigned int *)&pdata->rss_key;
394 int ret;
395
396 while (key_regs--) {
397 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
398 key_regs, *key++);
399 if (ret)
400 return ret;
401 }
402
403 return 0;
404 }
405
406 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
407 {
408 unsigned int i;
409 int ret;
410
411 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
412 ret = xgbe_write_rss_reg(pdata,
413 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
414 pdata->rss_table[i]);
415 if (ret)
416 return ret;
417 }
418
419 return 0;
420 }
421
422 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
423 {
424 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
425
426 return xgbe_write_rss_hash_key(pdata);
427 }
428
429 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
430 const u32 *table)
431 {
432 unsigned int i;
433
434 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
435 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
436
437 return xgbe_write_rss_lookup_table(pdata);
438 }
439
440 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
441 {
442 int ret;
443
444 if (!pdata->hw_feat.rss)
445 return -EOPNOTSUPP;
446
447 /* Program the hash key */
448 ret = xgbe_write_rss_hash_key(pdata);
449 if (ret)
450 return ret;
451
452 /* Program the lookup table */
453 ret = xgbe_write_rss_lookup_table(pdata);
454 if (ret)
455 return ret;
456
457 /* Set the RSS options */
458 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
459
460 /* Enable RSS */
461 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
462
463 return 0;
464 }
465
466 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
467 {
468 if (!pdata->hw_feat.rss)
469 return -EOPNOTSUPP;
470
471 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
472
473 return 0;
474 }
475
476 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
477 {
478 int ret;
479
480 if (!pdata->hw_feat.rss)
481 return;
482
483 if (pdata->netdev->features & NETIF_F_RXHASH)
484 ret = xgbe_enable_rss(pdata);
485 else
486 ret = xgbe_disable_rss(pdata);
487
488 if (ret)
489 netdev_err(pdata->netdev,
490 "error configuring RSS, RSS disabled\n");
491 }
492
493 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
494 {
495 unsigned int max_q_count, q_count;
496 unsigned int reg, reg_val;
497 unsigned int i;
498
499 /* Clear MTL flow control */
500 for (i = 0; i < pdata->rx_q_count; i++)
501 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
502
503 /* Clear MAC flow control */
504 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
505 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
506 reg = MAC_Q0TFCR;
507 for (i = 0; i < q_count; i++) {
508 reg_val = XGMAC_IOREAD(pdata, reg);
509 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
510 XGMAC_IOWRITE(pdata, reg, reg_val);
511
512 reg += MAC_QTFCR_INC;
513 }
514
515 return 0;
516 }
517
518 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
519 {
520 unsigned int max_q_count, q_count;
521 unsigned int reg, reg_val;
522 unsigned int i;
523
524 /* Set MTL flow control */
525 for (i = 0; i < pdata->rx_q_count; i++)
526 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
527
528 /* Set MAC flow control */
529 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
530 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
531 reg = MAC_Q0TFCR;
532 for (i = 0; i < q_count; i++) {
533 reg_val = XGMAC_IOREAD(pdata, reg);
534
535 /* Enable transmit flow control */
536 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
537 /* Set pause time */
538 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
539
540 XGMAC_IOWRITE(pdata, reg, reg_val);
541
542 reg += MAC_QTFCR_INC;
543 }
544
545 return 0;
546 }
547
548 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
549 {
550 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
551
552 return 0;
553 }
554
555 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
556 {
557 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
558
559 return 0;
560 }
561
562 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
563 {
564 struct ieee_pfc *pfc = pdata->pfc;
565
566 if (pdata->tx_pause || (pfc && pfc->pfc_en))
567 xgbe_enable_tx_flow_control(pdata);
568 else
569 xgbe_disable_tx_flow_control(pdata);
570
571 return 0;
572 }
573
574 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
575 {
576 struct ieee_pfc *pfc = pdata->pfc;
577
578 if (pdata->rx_pause || (pfc && pfc->pfc_en))
579 xgbe_enable_rx_flow_control(pdata);
580 else
581 xgbe_disable_rx_flow_control(pdata);
582
583 return 0;
584 }
585
586 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
587 {
588 struct ieee_pfc *pfc = pdata->pfc;
589
590 xgbe_config_tx_flow_control(pdata);
591 xgbe_config_rx_flow_control(pdata);
592
593 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
594 (pfc && pfc->pfc_en) ? 1 : 0);
595 }
596
597 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
598 {
599 struct xgbe_channel *channel;
600 unsigned int dma_ch_isr, dma_ch_ier;
601 unsigned int i;
602
603 channel = pdata->channel;
604 for (i = 0; i < pdata->channel_count; i++, channel++) {
605 /* Clear all the interrupts which are set */
606 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
607 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
608
609 /* Clear all interrupt enable bits */
610 dma_ch_ier = 0;
611
612 /* Enable following interrupts
613 * NIE - Normal Interrupt Summary Enable
614 * AIE - Abnormal Interrupt Summary Enable
615 * FBEE - Fatal Bus Error Enable
616 */
617 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
620
621 if (channel->tx_ring) {
622 /* Enable the following Tx interrupts
623 * TIE - Transmit Interrupt Enable (unless using
624 * per channel interrupts)
625 */
626 if (!pdata->per_channel_irq)
627 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
628 }
629 if (channel->rx_ring) {
630 /* Enable following Rx interrupts
631 * RBUE - Receive Buffer Unavailable Enable
632 * RIE - Receive Interrupt Enable (unless using
633 * per channel interrupts)
634 */
635 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
636 if (!pdata->per_channel_irq)
637 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
638 }
639
640 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
641 }
642 }
643
644 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
645 {
646 unsigned int mtl_q_isr;
647 unsigned int q_count, i;
648
649 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
650 for (i = 0; i < q_count; i++) {
651 /* Clear all the interrupts which are set */
652 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
653 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
654
655 /* No MTL interrupts to be enabled */
656 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
657 }
658 }
659
660 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
661 {
662 unsigned int mac_ier = 0;
663
664 /* Enable Timestamp interrupt */
665 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
666
667 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
668
669 /* Enable all counter interrupts */
670 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
671 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
672 }
673
674 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
675 {
676 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
677
678 return 0;
679 }
680
681 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
682 {
683 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
684
685 return 0;
686 }
687
688 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
689 {
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
691
692 return 0;
693 }
694
695 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
696 unsigned int enable)
697 {
698 unsigned int val = enable ? 1 : 0;
699
700 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
701 return 0;
702
703 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
704 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
705
706 return 0;
707 }
708
709 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
710 unsigned int enable)
711 {
712 unsigned int val = enable ? 1 : 0;
713
714 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
715 return 0;
716
717 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
718 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
719
720 return 0;
721 }
722
723 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
724 struct netdev_hw_addr *ha, unsigned int *mac_reg)
725 {
726 unsigned int mac_addr_hi, mac_addr_lo;
727 u8 *mac_addr;
728
729 mac_addr_lo = 0;
730 mac_addr_hi = 0;
731
732 if (ha) {
733 mac_addr = (u8 *)&mac_addr_lo;
734 mac_addr[0] = ha->addr[0];
735 mac_addr[1] = ha->addr[1];
736 mac_addr[2] = ha->addr[2];
737 mac_addr[3] = ha->addr[3];
738 mac_addr = (u8 *)&mac_addr_hi;
739 mac_addr[0] = ha->addr[4];
740 mac_addr[1] = ha->addr[5];
741
742 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
743 *mac_reg);
744
745 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
746 }
747
748 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
749 *mac_reg += MAC_MACA_INC;
750 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
751 *mac_reg += MAC_MACA_INC;
752 }
753
754 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
755 {
756 struct net_device *netdev = pdata->netdev;
757 struct netdev_hw_addr *ha;
758 unsigned int mac_reg;
759 unsigned int addn_macs;
760
761 mac_reg = MAC_MACA1HR;
762 addn_macs = pdata->hw_feat.addn_mac;
763
764 if (netdev_uc_count(netdev) > addn_macs) {
765 xgbe_set_promiscuous_mode(pdata, 1);
766 } else {
767 netdev_for_each_uc_addr(ha, netdev) {
768 xgbe_set_mac_reg(pdata, ha, &mac_reg);
769 addn_macs--;
770 }
771
772 if (netdev_mc_count(netdev) > addn_macs) {
773 xgbe_set_all_multicast_mode(pdata, 1);
774 } else {
775 netdev_for_each_mc_addr(ha, netdev) {
776 xgbe_set_mac_reg(pdata, ha, &mac_reg);
777 addn_macs--;
778 }
779 }
780 }
781
782 /* Clear remaining additional MAC address entries */
783 while (addn_macs--)
784 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
785 }
786
787 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
788 {
789 struct net_device *netdev = pdata->netdev;
790 struct netdev_hw_addr *ha;
791 unsigned int hash_reg;
792 unsigned int hash_table_shift, hash_table_count;
793 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
794 u32 crc;
795 unsigned int i;
796
797 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
798 hash_table_count = pdata->hw_feat.hash_table_size / 32;
799 memset(hash_table, 0, sizeof(hash_table));
800
801 /* Build the MAC Hash Table register values */
802 netdev_for_each_uc_addr(ha, netdev) {
803 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
804 crc >>= hash_table_shift;
805 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
806 }
807
808 netdev_for_each_mc_addr(ha, netdev) {
809 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
810 crc >>= hash_table_shift;
811 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
812 }
813
814 /* Set the MAC Hash Table registers */
815 hash_reg = MAC_HTR0;
816 for (i = 0; i < hash_table_count; i++) {
817 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
818 hash_reg += MAC_HTR_INC;
819 }
820 }
821
822 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
823 {
824 if (pdata->hw_feat.hash_table_size)
825 xgbe_set_mac_hash_table(pdata);
826 else
827 xgbe_set_mac_addn_addrs(pdata);
828
829 return 0;
830 }
831
832 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
833 {
834 unsigned int mac_addr_hi, mac_addr_lo;
835
836 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
837 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
838 (addr[1] << 8) | (addr[0] << 0);
839
840 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
841 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
842
843 return 0;
844 }
845
846 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
847 int mmd_reg)
848 {
849 unsigned int mmd_address;
850 int mmd_data;
851
852 if (mmd_reg & MII_ADDR_C45)
853 mmd_address = mmd_reg & ~MII_ADDR_C45;
854 else
855 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
856
857 /* The PCS registers are accessed using mmio. The underlying APB3
858 * management interface uses indirect addressing to access the MMD
859 * register sets. This requires accessing of the PCS register in two
860 * phases, an address phase and a data phase.
861 *
862 * The mmio interface is based on 32-bit offsets and values. All
863 * register offsets must therefore be adjusted by left shifting the
864 * offset 2 bits and reading 32 bits of data.
865 */
866 mutex_lock(&pdata->xpcs_mutex);
867 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
868 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
869 mutex_unlock(&pdata->xpcs_mutex);
870
871 return mmd_data;
872 }
873
874 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
875 int mmd_reg, int mmd_data)
876 {
877 unsigned int mmd_address;
878
879 if (mmd_reg & MII_ADDR_C45)
880 mmd_address = mmd_reg & ~MII_ADDR_C45;
881 else
882 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
883
884 /* The PCS registers are accessed using mmio. The underlying APB3
885 * management interface uses indirect addressing to access the MMD
886 * register sets. This requires accessing of the PCS register in two
887 * phases, an address phase and a data phase.
888 *
889 * The mmio interface is based on 32-bit offsets and values. All
890 * register offsets must therefore be adjusted by left shifting the
891 * offset 2 bits and reading 32 bits of data.
892 */
893 mutex_lock(&pdata->xpcs_mutex);
894 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
895 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
896 mutex_unlock(&pdata->xpcs_mutex);
897 }
898
899 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
900 {
901 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
902 }
903
904 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
905 {
906 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
907
908 return 0;
909 }
910
911 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
912 {
913 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
914
915 return 0;
916 }
917
918 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
919 {
920 /* Put the VLAN tag in the Rx descriptor */
921 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
922
923 /* Don't check the VLAN type */
924 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
925
926 /* Check only C-TAG (0x8100) packets */
927 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
928
929 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
930 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
931
932 /* Enable VLAN tag stripping */
933 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
934
935 return 0;
936 }
937
938 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
939 {
940 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
941
942 return 0;
943 }
944
945 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
946 {
947 /* Enable VLAN filtering */
948 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
949
950 /* Enable VLAN Hash Table filtering */
951 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
952
953 /* Disable VLAN tag inverse matching */
954 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
955
956 /* Only filter on the lower 12-bits of the VLAN tag */
957 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
958
959 /* In order for the VLAN Hash Table filtering to be effective,
960 * the VLAN tag identifier in the VLAN Tag Register must not
961 * be zero. Set the VLAN tag identifier to "1" to enable the
962 * VLAN Hash Table filtering. This implies that a VLAN tag of
963 * 1 will always pass filtering.
964 */
965 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
966
967 return 0;
968 }
969
970 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
971 {
972 /* Disable VLAN filtering */
973 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
974
975 return 0;
976 }
977
978 #ifndef CRCPOLY_LE
979 #define CRCPOLY_LE 0xedb88320
980 #endif
981 static u32 xgbe_vid_crc32_le(__le16 vid_le)
982 {
983 u32 poly = CRCPOLY_LE;
984 u32 crc = ~0;
985 u32 temp = 0;
986 unsigned char *data = (unsigned char *)&vid_le;
987 unsigned char data_byte = 0;
988 int i, bits;
989
990 bits = get_bitmask_order(VLAN_VID_MASK);
991 for (i = 0; i < bits; i++) {
992 if ((i % 8) == 0)
993 data_byte = data[i / 8];
994
995 temp = ((crc & 1) ^ data_byte) & 1;
996 crc >>= 1;
997 data_byte >>= 1;
998
999 if (temp)
1000 crc ^= poly;
1001 }
1002
1003 return crc;
1004 }
1005
1006 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1007 {
1008 u32 crc;
1009 u16 vid;
1010 __le16 vid_le;
1011 u16 vlan_hash_table = 0;
1012
1013 /* Generate the VLAN Hash Table value */
1014 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1015 /* Get the CRC32 value of the VLAN ID */
1016 vid_le = cpu_to_le16(vid);
1017 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1018
1019 vlan_hash_table |= (1 << crc);
1020 }
1021
1022 /* Set the VLAN Hash Table filtering register */
1023 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1024
1025 return 0;
1026 }
1027
1028 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1029 {
1030 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1031
1032 /* Reset the Tx descriptor
1033 * Set buffer 1 (lo) address to zero
1034 * Set buffer 1 (hi) address to zero
1035 * Reset all other control bits (IC, TTSE, B2L & B1L)
1036 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1037 */
1038 rdesc->desc0 = 0;
1039 rdesc->desc1 = 0;
1040 rdesc->desc2 = 0;
1041 rdesc->desc3 = 0;
1042
1043 /* Make sure ownership is written to the descriptor */
1044 wmb();
1045 }
1046
1047 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1048 {
1049 struct xgbe_ring *ring = channel->tx_ring;
1050 struct xgbe_ring_data *rdata;
1051 int i;
1052 int start_index = ring->cur;
1053
1054 DBGPR("-->tx_desc_init\n");
1055
1056 /* Initialze all descriptors */
1057 for (i = 0; i < ring->rdesc_count; i++) {
1058 rdata = XGBE_GET_DESC_DATA(ring, i);
1059
1060 /* Initialize Tx descriptor */
1061 xgbe_tx_desc_reset(rdata);
1062 }
1063
1064 /* Update the total number of Tx descriptors */
1065 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1066
1067 /* Update the starting address of descriptor ring */
1068 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1069 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1070 upper_32_bits(rdata->rdesc_dma));
1071 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1072 lower_32_bits(rdata->rdesc_dma));
1073
1074 DBGPR("<--tx_desc_init\n");
1075 }
1076
1077 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
1078 {
1079 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1080
1081 /* Reset the Rx descriptor
1082 * Set buffer 1 (lo) address to header dma address (lo)
1083 * Set buffer 1 (hi) address to header dma address (hi)
1084 * Set buffer 2 (lo) address to buffer dma address (lo)
1085 * Set buffer 2 (hi) address to buffer dma address (hi) and
1086 * set control bits OWN and INTE
1087 */
1088 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx_hdr.dma));
1089 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx_hdr.dma));
1090 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx_buf.dma));
1091 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx_buf.dma));
1092
1093 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
1094 rdata->interrupt ? 1 : 0);
1095
1096 /* Since the Rx DMA engine is likely running, make sure everything
1097 * is written to the descriptor(s) before setting the OWN bit
1098 * for the descriptor
1099 */
1100 wmb();
1101
1102 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1103
1104 /* Make sure ownership is written to the descriptor */
1105 wmb();
1106 }
1107
1108 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1109 {
1110 struct xgbe_prv_data *pdata = channel->pdata;
1111 struct xgbe_ring *ring = channel->rx_ring;
1112 struct xgbe_ring_data *rdata;
1113 unsigned int start_index = ring->cur;
1114 unsigned int rx_coalesce, rx_frames;
1115 unsigned int i;
1116
1117 DBGPR("-->rx_desc_init\n");
1118
1119 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
1120 rx_frames = pdata->rx_frames;
1121
1122 /* Initialize all descriptors */
1123 for (i = 0; i < ring->rdesc_count; i++) {
1124 rdata = XGBE_GET_DESC_DATA(ring, i);
1125
1126 /* Set interrupt on completion bit as appropriate */
1127 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames)))
1128 rdata->interrupt = 0;
1129 else
1130 rdata->interrupt = 1;
1131
1132 /* Initialize Rx descriptor */
1133 xgbe_rx_desc_reset(rdata);
1134 }
1135
1136 /* Update the total number of Rx descriptors */
1137 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1138
1139 /* Update the starting address of descriptor ring */
1140 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1141 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1142 upper_32_bits(rdata->rdesc_dma));
1143 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1144 lower_32_bits(rdata->rdesc_dma));
1145
1146 /* Update the Rx Descriptor Tail Pointer */
1147 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1148 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1149 lower_32_bits(rdata->rdesc_dma));
1150
1151 DBGPR("<--rx_desc_init\n");
1152 }
1153
1154 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1155 unsigned int addend)
1156 {
1157 /* Set the addend register value and tell the device */
1158 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1159 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1160
1161 /* Wait for addend update to complete */
1162 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1163 udelay(5);
1164 }
1165
1166 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1167 unsigned int nsec)
1168 {
1169 /* Set the time values and tell the device */
1170 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1171 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1172 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1173
1174 /* Wait for time update to complete */
1175 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1176 udelay(5);
1177 }
1178
1179 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1180 {
1181 u64 nsec;
1182
1183 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1184 nsec *= NSEC_PER_SEC;
1185 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1186
1187 return nsec;
1188 }
1189
1190 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1191 {
1192 unsigned int tx_snr;
1193 u64 nsec;
1194
1195 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1196 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1197 return 0;
1198
1199 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1200 nsec *= NSEC_PER_SEC;
1201 nsec += tx_snr;
1202
1203 return nsec;
1204 }
1205
1206 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1207 struct xgbe_ring_desc *rdesc)
1208 {
1209 u64 nsec;
1210
1211 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1212 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1213 nsec = le32_to_cpu(rdesc->desc1);
1214 nsec <<= 32;
1215 nsec |= le32_to_cpu(rdesc->desc0);
1216 if (nsec != 0xffffffffffffffffULL) {
1217 packet->rx_tstamp = nsec;
1218 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1219 RX_TSTAMP, 1);
1220 }
1221 }
1222 }
1223
1224 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1225 unsigned int mac_tscr)
1226 {
1227 /* Set one nano-second accuracy */
1228 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1229
1230 /* Set fine timestamp update */
1231 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1232
1233 /* Overwrite earlier timestamps */
1234 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1235
1236 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1237
1238 /* Exit if timestamping is not enabled */
1239 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1240 return 0;
1241
1242 /* Initialize time registers */
1243 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1244 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1245 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1246 xgbe_set_tstamp_time(pdata, 0, 0);
1247
1248 /* Initialize the timecounter */
1249 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1250 ktime_to_ns(ktime_get_real()));
1251
1252 return 0;
1253 }
1254
1255 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1256 {
1257 struct ieee_ets *ets = pdata->ets;
1258 unsigned int total_weight, min_weight, weight;
1259 unsigned int i;
1260
1261 if (!ets)
1262 return;
1263
1264 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1265 * traffic class is using ETS algorithm)
1266 */
1267 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1268
1269 /* Set Traffic Class algorithms */
1270 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1271 min_weight = total_weight / 100;
1272 if (!min_weight)
1273 min_weight = 1;
1274
1275 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1276 switch (ets->tc_tsa[i]) {
1277 case IEEE_8021QAZ_TSA_STRICT:
1278 DBGPR(" TC%u using SP\n", i);
1279 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1280 MTL_TSA_SP);
1281 break;
1282 case IEEE_8021QAZ_TSA_ETS:
1283 weight = total_weight * ets->tc_tx_bw[i] / 100;
1284 weight = clamp(weight, min_weight, total_weight);
1285
1286 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1287 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1288 MTL_TSA_ETS);
1289 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1290 weight);
1291 break;
1292 }
1293 }
1294 }
1295
1296 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1297 {
1298 struct ieee_pfc *pfc = pdata->pfc;
1299 struct ieee_ets *ets = pdata->ets;
1300 unsigned int mask, reg, reg_val;
1301 unsigned int tc, prio;
1302
1303 if (!pfc || !ets)
1304 return;
1305
1306 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1307 mask = 0;
1308 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1309 if ((pfc->pfc_en & (1 << prio)) &&
1310 (ets->prio_tc[prio] == tc))
1311 mask |= (1 << prio);
1312 }
1313 mask &= 0xff;
1314
1315 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1316 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1317 reg_val = XGMAC_IOREAD(pdata, reg);
1318
1319 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1320 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1321
1322 XGMAC_IOWRITE(pdata, reg, reg_val);
1323 }
1324
1325 xgbe_config_flow_control(pdata);
1326 }
1327
1328 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1329 {
1330 struct xgbe_prv_data *pdata = channel->pdata;
1331 struct xgbe_ring *ring = channel->tx_ring;
1332 struct xgbe_ring_data *rdata;
1333 struct xgbe_ring_desc *rdesc;
1334 struct xgbe_packet_data *packet = &ring->packet_data;
1335 unsigned int csum, tso, vlan;
1336 unsigned int tso_context, vlan_context;
1337 unsigned int tx_coalesce, tx_frames;
1338 int start_index = ring->cur;
1339 int i;
1340
1341 DBGPR("-->xgbe_dev_xmit\n");
1342
1343 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1344 CSUM_ENABLE);
1345 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1346 TSO_ENABLE);
1347 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1348 VLAN_CTAG);
1349
1350 if (tso && (packet->mss != ring->tx.cur_mss))
1351 tso_context = 1;
1352 else
1353 tso_context = 0;
1354
1355 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1356 vlan_context = 1;
1357 else
1358 vlan_context = 0;
1359
1360 tx_coalesce = (pdata->tx_usecs || pdata->tx_frames) ? 1 : 0;
1361 tx_frames = pdata->tx_frames;
1362 if (tx_coalesce && !channel->tx_timer_active)
1363 ring->coalesce_count = 0;
1364
1365 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1366 rdesc = rdata->rdesc;
1367
1368 /* Create a context descriptor if this is a TSO packet */
1369 if (tso_context || vlan_context) {
1370 if (tso_context) {
1371 DBGPR(" TSO context descriptor, mss=%u\n",
1372 packet->mss);
1373
1374 /* Set the MSS size */
1375 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1376 MSS, packet->mss);
1377
1378 /* Mark it as a CONTEXT descriptor */
1379 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1380 CTXT, 1);
1381
1382 /* Indicate this descriptor contains the MSS */
1383 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1384 TCMSSV, 1);
1385
1386 ring->tx.cur_mss = packet->mss;
1387 }
1388
1389 if (vlan_context) {
1390 DBGPR(" VLAN context descriptor, ctag=%u\n",
1391 packet->vlan_ctag);
1392
1393 /* Mark it as a CONTEXT descriptor */
1394 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1395 CTXT, 1);
1396
1397 /* Set the VLAN tag */
1398 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1399 VT, packet->vlan_ctag);
1400
1401 /* Indicate this descriptor contains the VLAN tag */
1402 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1403 VLTV, 1);
1404
1405 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1406 }
1407
1408 ring->cur++;
1409 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1410 rdesc = rdata->rdesc;
1411 }
1412
1413 /* Update buffer address (for TSO this is the header) */
1414 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1415 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1416
1417 /* Update the buffer length */
1418 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1419 rdata->skb_dma_len);
1420
1421 /* VLAN tag insertion check */
1422 if (vlan)
1423 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1424 TX_NORMAL_DESC2_VLAN_INSERT);
1425
1426 /* Timestamp enablement check */
1427 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1428 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1429
1430 /* Set IC bit based on Tx coalescing settings */
1431 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1432 if (tx_coalesce && (!tx_frames ||
1433 (++ring->coalesce_count % tx_frames)))
1434 /* Clear IC bit */
1435 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1436
1437 /* Mark it as First Descriptor */
1438 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1439
1440 /* Mark it as a NORMAL descriptor */
1441 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1442
1443 /* Set OWN bit if not the first descriptor */
1444 if (ring->cur != start_index)
1445 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1446
1447 if (tso) {
1448 /* Enable TSO */
1449 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1450 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1451 packet->tcp_payload_len);
1452 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1453 packet->tcp_header_len / 4);
1454 } else {
1455 /* Enable CRC and Pad Insertion */
1456 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1457
1458 /* Enable HW CSUM */
1459 if (csum)
1460 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1461 CIC, 0x3);
1462
1463 /* Set the total length to be transmitted */
1464 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1465 packet->length);
1466 }
1467
1468 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) {
1469 ring->cur++;
1470 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1471 rdesc = rdata->rdesc;
1472
1473 /* Update buffer address */
1474 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1475 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1476
1477 /* Update the buffer length */
1478 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1479 rdata->skb_dma_len);
1480
1481 /* Set IC bit based on Tx coalescing settings */
1482 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1483 if (tx_coalesce && (!tx_frames ||
1484 (++ring->coalesce_count % tx_frames)))
1485 /* Clear IC bit */
1486 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1487
1488 /* Set OWN bit */
1489 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1490
1491 /* Mark it as NORMAL descriptor */
1492 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1493
1494 /* Enable HW CSUM */
1495 if (csum)
1496 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1497 CIC, 0x3);
1498 }
1499
1500 /* Set LAST bit for the last descriptor */
1501 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1502
1503 /* In case the Tx DMA engine is running, make sure everything
1504 * is written to the descriptor(s) before setting the OWN bit
1505 * for the first descriptor
1506 */
1507 wmb();
1508
1509 /* Set OWN bit for the first descriptor */
1510 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1511 rdesc = rdata->rdesc;
1512 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1513
1514 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1515 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1516 #endif
1517
1518 /* Make sure ownership is written to the descriptor */
1519 wmb();
1520
1521 /* Issue a poll command to Tx DMA by writing address
1522 * of next immediate free descriptor */
1523 ring->cur++;
1524 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1525 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1526 lower_32_bits(rdata->rdesc_dma));
1527
1528 /* Start the Tx coalescing timer */
1529 if (tx_coalesce && !channel->tx_timer_active) {
1530 channel->tx_timer_active = 1;
1531 hrtimer_start(&channel->tx_timer,
1532 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1533 HRTIMER_MODE_REL);
1534 }
1535
1536 DBGPR(" %s: descriptors %u to %u written\n",
1537 channel->name, start_index & (ring->rdesc_count - 1),
1538 (ring->cur - 1) & (ring->rdesc_count - 1));
1539
1540 DBGPR("<--xgbe_dev_xmit\n");
1541 }
1542
1543 static int xgbe_dev_read(struct xgbe_channel *channel)
1544 {
1545 struct xgbe_ring *ring = channel->rx_ring;
1546 struct xgbe_ring_data *rdata;
1547 struct xgbe_ring_desc *rdesc;
1548 struct xgbe_packet_data *packet = &ring->packet_data;
1549 struct net_device *netdev = channel->pdata->netdev;
1550 unsigned int err, etlt, l34t;
1551
1552 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1553
1554 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1555 rdesc = rdata->rdesc;
1556
1557 /* Check for data availability */
1558 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1559 return 1;
1560
1561 /* Make sure descriptor fields are read after reading the OWN bit */
1562 rmb();
1563
1564 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1565 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1566 #endif
1567
1568 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1569 /* Timestamp Context Descriptor */
1570 xgbe_get_rx_tstamp(packet, rdesc);
1571
1572 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1573 CONTEXT, 1);
1574 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1575 CONTEXT_NEXT, 0);
1576 return 0;
1577 }
1578
1579 /* Normal Descriptor, be sure Context Descriptor bit is off */
1580 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1581
1582 /* Indicate if a Context Descriptor is next */
1583 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1584 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1585 CONTEXT_NEXT, 1);
1586
1587 /* Get the header length */
1588 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD))
1589 rdata->hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1590 RX_NORMAL_DESC2, HL);
1591
1592 /* Get the RSS hash */
1593 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1594 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1595 RSS_HASH, 1);
1596
1597 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1598
1599 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1600 switch (l34t) {
1601 case RX_DESC3_L34T_IPV4_TCP:
1602 case RX_DESC3_L34T_IPV4_UDP:
1603 case RX_DESC3_L34T_IPV6_TCP:
1604 case RX_DESC3_L34T_IPV6_UDP:
1605 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1606 break;
1607 default:
1608 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1609 }
1610 }
1611
1612 /* Get the packet length */
1613 rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1614
1615 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1616 /* Not all the data has been transferred for this packet */
1617 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1618 INCOMPLETE, 1);
1619 return 0;
1620 }
1621
1622 /* This is the last of the data for this packet */
1623 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1624 INCOMPLETE, 0);
1625
1626 /* Set checksum done indicator as appropriate */
1627 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1628 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1629 CSUM_DONE, 1);
1630
1631 /* Check for errors (only valid in last descriptor) */
1632 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1633 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1634 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1635
1636 if (!err || (err && !etlt)) {
1637 if ((etlt == 0x09) &&
1638 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1639 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1640 VLAN_CTAG, 1);
1641 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1642 RX_NORMAL_DESC0,
1643 OVT);
1644 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1645 }
1646 } else {
1647 if ((etlt == 0x05) || (etlt == 0x06))
1648 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1649 CSUM_DONE, 0);
1650 else
1651 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1652 FRAME, 1);
1653 }
1654
1655 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1656 ring->cur & (ring->rdesc_count - 1), ring->cur);
1657
1658 return 0;
1659 }
1660
1661 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1662 {
1663 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1664 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1665 }
1666
1667 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1668 {
1669 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1670 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1671 }
1672
1673 static int xgbe_enable_int(struct xgbe_channel *channel,
1674 enum xgbe_int int_id)
1675 {
1676 unsigned int dma_ch_ier;
1677
1678 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1679
1680 switch (int_id) {
1681 case XGMAC_INT_DMA_CH_SR_TI:
1682 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1683 break;
1684 case XGMAC_INT_DMA_CH_SR_TPS:
1685 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1686 break;
1687 case XGMAC_INT_DMA_CH_SR_TBU:
1688 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1689 break;
1690 case XGMAC_INT_DMA_CH_SR_RI:
1691 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1692 break;
1693 case XGMAC_INT_DMA_CH_SR_RBU:
1694 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1695 break;
1696 case XGMAC_INT_DMA_CH_SR_RPS:
1697 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1698 break;
1699 case XGMAC_INT_DMA_CH_SR_TI_RI:
1700 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1701 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1702 break;
1703 case XGMAC_INT_DMA_CH_SR_FBE:
1704 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1705 break;
1706 case XGMAC_INT_DMA_ALL:
1707 dma_ch_ier |= channel->saved_ier;
1708 break;
1709 default:
1710 return -1;
1711 }
1712
1713 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1714
1715 return 0;
1716 }
1717
1718 static int xgbe_disable_int(struct xgbe_channel *channel,
1719 enum xgbe_int int_id)
1720 {
1721 unsigned int dma_ch_ier;
1722
1723 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1724
1725 switch (int_id) {
1726 case XGMAC_INT_DMA_CH_SR_TI:
1727 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1728 break;
1729 case XGMAC_INT_DMA_CH_SR_TPS:
1730 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1731 break;
1732 case XGMAC_INT_DMA_CH_SR_TBU:
1733 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1734 break;
1735 case XGMAC_INT_DMA_CH_SR_RI:
1736 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1737 break;
1738 case XGMAC_INT_DMA_CH_SR_RBU:
1739 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1740 break;
1741 case XGMAC_INT_DMA_CH_SR_RPS:
1742 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1743 break;
1744 case XGMAC_INT_DMA_CH_SR_TI_RI:
1745 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1746 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1747 break;
1748 case XGMAC_INT_DMA_CH_SR_FBE:
1749 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1750 break;
1751 case XGMAC_INT_DMA_ALL:
1752 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1753 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1754 break;
1755 default:
1756 return -1;
1757 }
1758
1759 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1760
1761 return 0;
1762 }
1763
1764 static int xgbe_exit(struct xgbe_prv_data *pdata)
1765 {
1766 unsigned int count = 2000;
1767
1768 DBGPR("-->xgbe_exit\n");
1769
1770 /* Issue a software reset */
1771 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1772 usleep_range(10, 15);
1773
1774 /* Poll Until Poll Condition */
1775 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1776 usleep_range(500, 600);
1777
1778 if (!count)
1779 return -EBUSY;
1780
1781 DBGPR("<--xgbe_exit\n");
1782
1783 return 0;
1784 }
1785
1786 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1787 {
1788 unsigned int i, count;
1789
1790 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1791 return 0;
1792
1793 for (i = 0; i < pdata->tx_q_count; i++)
1794 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1795
1796 /* Poll Until Poll Condition */
1797 for (i = 0; i < pdata->tx_q_count; i++) {
1798 count = 2000;
1799 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1800 MTL_Q_TQOMR, FTQ))
1801 usleep_range(500, 600);
1802
1803 if (!count)
1804 return -EBUSY;
1805 }
1806
1807 return 0;
1808 }
1809
1810 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1811 {
1812 /* Set enhanced addressing mode */
1813 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1814
1815 /* Set the System Bus mode */
1816 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1817 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1818 }
1819
1820 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1821 {
1822 unsigned int arcache, awcache;
1823
1824 arcache = 0;
1825 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1826 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1827 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1828 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1829 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1830 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1831 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1832
1833 awcache = 0;
1834 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1835 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1836 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1837 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1838 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1839 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1840 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1841 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1842 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1843 }
1844
1845 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1846 {
1847 unsigned int i;
1848
1849 /* Set Tx to weighted round robin scheduling algorithm */
1850 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1851
1852 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1853 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1854 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1855 MTL_TSA_ETS);
1856 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1857 }
1858
1859 /* Set Rx to strict priority algorithm */
1860 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1861 }
1862
1863 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1864 unsigned int queue_count)
1865 {
1866 unsigned int q_fifo_size = 0;
1867 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1868
1869 /* Calculate Tx/Rx fifo share per queue */
1870 switch (fifo_size) {
1871 case 0:
1872 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1873 break;
1874 case 1:
1875 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1876 break;
1877 case 2:
1878 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1879 break;
1880 case 3:
1881 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1882 break;
1883 case 4:
1884 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1885 break;
1886 case 5:
1887 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1888 break;
1889 case 6:
1890 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1891 break;
1892 case 7:
1893 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1894 break;
1895 case 8:
1896 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1897 break;
1898 case 9:
1899 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1900 break;
1901 case 10:
1902 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1903 break;
1904 case 11:
1905 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1906 break;
1907 }
1908
1909 /* The configured value is not the actual amount of fifo RAM */
1910 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1911
1912 q_fifo_size = q_fifo_size / queue_count;
1913
1914 /* Set the queue fifo size programmable value */
1915 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1916 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1917 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1918 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1919 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1920 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1921 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1922 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1923 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1924 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1925 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
1926 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
1927 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
1928 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
1929 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
1930 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
1931 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
1932 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
1933 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
1934 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
1935 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
1936 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1937
1938 return p_fifo;
1939 }
1940
1941 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1942 {
1943 enum xgbe_mtl_fifo_size fifo_size;
1944 unsigned int i;
1945
1946 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
1947 pdata->tx_q_count);
1948
1949 for (i = 0; i < pdata->tx_q_count; i++)
1950 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
1951
1952 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
1953 pdata->tx_q_count, ((fifo_size + 1) * 256));
1954 }
1955
1956 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1957 {
1958 enum xgbe_mtl_fifo_size fifo_size;
1959 unsigned int i;
1960
1961 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
1962 pdata->rx_q_count);
1963
1964 for (i = 0; i < pdata->rx_q_count; i++)
1965 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
1966
1967 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
1968 pdata->rx_q_count, ((fifo_size + 1) * 256));
1969 }
1970
1971 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
1972 {
1973 unsigned int qptc, qptc_extra, queue;
1974 unsigned int prio_queues;
1975 unsigned int ppq, ppq_extra, prio;
1976 unsigned int mask;
1977 unsigned int i, j, reg, reg_val;
1978
1979 /* Map the MTL Tx Queues to Traffic Classes
1980 * Note: Tx Queues >= Traffic Classes
1981 */
1982 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1983 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1984
1985 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1986 for (j = 0; j < qptc; j++) {
1987 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1988 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1989 Q2TCMAP, i);
1990 pdata->q2tc_map[queue++] = i;
1991 }
1992
1993 if (i < qptc_extra) {
1994 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1995 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1996 Q2TCMAP, i);
1997 pdata->q2tc_map[queue++] = i;
1998 }
1999 }
2000
2001 /* Map the 8 VLAN priority values to available MTL Rx queues */
2002 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2003 pdata->rx_q_count);
2004 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2005 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2006
2007 reg = MAC_RQC2R;
2008 reg_val = 0;
2009 for (i = 0, prio = 0; i < prio_queues;) {
2010 mask = 0;
2011 for (j = 0; j < ppq; j++) {
2012 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2013 mask |= (1 << prio);
2014 pdata->prio2q_map[prio++] = i;
2015 }
2016
2017 if (i < ppq_extra) {
2018 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2019 mask |= (1 << prio);
2020 pdata->prio2q_map[prio++] = i;
2021 }
2022
2023 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2024
2025 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2026 continue;
2027
2028 XGMAC_IOWRITE(pdata, reg, reg_val);
2029 reg += MAC_RQC2_INC;
2030 reg_val = 0;
2031 }
2032
2033 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2034 reg = MTL_RQDCM0R;
2035 reg_val = 0;
2036 for (i = 0; i < pdata->rx_q_count;) {
2037 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2038
2039 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2040 continue;
2041
2042 XGMAC_IOWRITE(pdata, reg, reg_val);
2043
2044 reg += MTL_RQDCM_INC;
2045 reg_val = 0;
2046 }
2047 }
2048
2049 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2050 {
2051 unsigned int i;
2052
2053 for (i = 0; i < pdata->rx_q_count; i++) {
2054 /* Activate flow control when less than 4k left in fifo */
2055 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
2056
2057 /* De-activate flow control when more than 6k left in fifo */
2058 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);
2059 }
2060 }
2061
2062 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2063 {
2064 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2065
2066 /* Filtering is done using perfect filtering and hash filtering */
2067 if (pdata->hw_feat.hash_table_size) {
2068 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2069 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2070 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2071 }
2072 }
2073
2074 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2075 {
2076 unsigned int val;
2077
2078 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2079
2080 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2081 }
2082
2083 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2084 {
2085 if (pdata->netdev->features & NETIF_F_RXCSUM)
2086 xgbe_enable_rx_csum(pdata);
2087 else
2088 xgbe_disable_rx_csum(pdata);
2089 }
2090
2091 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2092 {
2093 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2094 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2095 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2096
2097 /* Set the current VLAN Hash Table register value */
2098 xgbe_update_vlan_hash_table(pdata);
2099
2100 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2101 xgbe_enable_rx_vlan_filtering(pdata);
2102 else
2103 xgbe_disable_rx_vlan_filtering(pdata);
2104
2105 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2106 xgbe_enable_rx_vlan_stripping(pdata);
2107 else
2108 xgbe_disable_rx_vlan_stripping(pdata);
2109 }
2110
2111 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2112 {
2113 bool read_hi;
2114 u64 val;
2115
2116 switch (reg_lo) {
2117 /* These registers are always 64 bit */
2118 case MMC_TXOCTETCOUNT_GB_LO:
2119 case MMC_TXOCTETCOUNT_G_LO:
2120 case MMC_RXOCTETCOUNT_GB_LO:
2121 case MMC_RXOCTETCOUNT_G_LO:
2122 read_hi = true;
2123 break;
2124
2125 default:
2126 read_hi = false;
2127 };
2128
2129 val = XGMAC_IOREAD(pdata, reg_lo);
2130
2131 if (read_hi)
2132 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2133
2134 return val;
2135 }
2136
2137 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2138 {
2139 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2140 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2141
2142 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2143 stats->txoctetcount_gb +=
2144 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2145
2146 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2147 stats->txframecount_gb +=
2148 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2149
2150 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2151 stats->txbroadcastframes_g +=
2152 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2153
2154 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2155 stats->txmulticastframes_g +=
2156 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2157
2158 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2159 stats->tx64octets_gb +=
2160 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2161
2162 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2163 stats->tx65to127octets_gb +=
2164 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2165
2166 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2167 stats->tx128to255octets_gb +=
2168 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2169
2170 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2171 stats->tx256to511octets_gb +=
2172 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2173
2174 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2175 stats->tx512to1023octets_gb +=
2176 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2177
2178 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2179 stats->tx1024tomaxoctets_gb +=
2180 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2181
2182 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2183 stats->txunicastframes_gb +=
2184 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2185
2186 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2187 stats->txmulticastframes_gb +=
2188 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2189
2190 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2191 stats->txbroadcastframes_g +=
2192 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2193
2194 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2195 stats->txunderflowerror +=
2196 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2197
2198 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2199 stats->txoctetcount_g +=
2200 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2201
2202 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2203 stats->txframecount_g +=
2204 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2205
2206 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2207 stats->txpauseframes +=
2208 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2209
2210 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2211 stats->txvlanframes_g +=
2212 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2213 }
2214
2215 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2216 {
2217 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2218 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2219
2220 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2221 stats->rxframecount_gb +=
2222 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2223
2224 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2225 stats->rxoctetcount_gb +=
2226 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2227
2228 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2229 stats->rxoctetcount_g +=
2230 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2231
2232 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2233 stats->rxbroadcastframes_g +=
2234 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2235
2236 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2237 stats->rxmulticastframes_g +=
2238 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2239
2240 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2241 stats->rxcrcerror +=
2242 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2243
2244 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2245 stats->rxrunterror +=
2246 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2247
2248 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2249 stats->rxjabbererror +=
2250 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2251
2252 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2253 stats->rxundersize_g +=
2254 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2255
2256 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2257 stats->rxoversize_g +=
2258 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2259
2260 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2261 stats->rx64octets_gb +=
2262 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2263
2264 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2265 stats->rx65to127octets_gb +=
2266 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2267
2268 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2269 stats->rx128to255octets_gb +=
2270 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2271
2272 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2273 stats->rx256to511octets_gb +=
2274 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2275
2276 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2277 stats->rx512to1023octets_gb +=
2278 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2279
2280 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2281 stats->rx1024tomaxoctets_gb +=
2282 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2283
2284 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2285 stats->rxunicastframes_g +=
2286 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2287
2288 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2289 stats->rxlengtherror +=
2290 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2291
2292 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2293 stats->rxoutofrangetype +=
2294 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2295
2296 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2297 stats->rxpauseframes +=
2298 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2299
2300 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2301 stats->rxfifooverflow +=
2302 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2303
2304 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2305 stats->rxvlanframes_gb +=
2306 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2307
2308 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2309 stats->rxwatchdogerror +=
2310 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2311 }
2312
2313 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2314 {
2315 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2316
2317 /* Freeze counters */
2318 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2319
2320 stats->txoctetcount_gb +=
2321 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2322
2323 stats->txframecount_gb +=
2324 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2325
2326 stats->txbroadcastframes_g +=
2327 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2328
2329 stats->txmulticastframes_g +=
2330 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2331
2332 stats->tx64octets_gb +=
2333 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2334
2335 stats->tx65to127octets_gb +=
2336 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2337
2338 stats->tx128to255octets_gb +=
2339 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2340
2341 stats->tx256to511octets_gb +=
2342 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2343
2344 stats->tx512to1023octets_gb +=
2345 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2346
2347 stats->tx1024tomaxoctets_gb +=
2348 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2349
2350 stats->txunicastframes_gb +=
2351 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2352
2353 stats->txmulticastframes_gb +=
2354 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2355
2356 stats->txbroadcastframes_g +=
2357 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2358
2359 stats->txunderflowerror +=
2360 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2361
2362 stats->txoctetcount_g +=
2363 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2364
2365 stats->txframecount_g +=
2366 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2367
2368 stats->txpauseframes +=
2369 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2370
2371 stats->txvlanframes_g +=
2372 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2373
2374 stats->rxframecount_gb +=
2375 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2376
2377 stats->rxoctetcount_gb +=
2378 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2379
2380 stats->rxoctetcount_g +=
2381 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2382
2383 stats->rxbroadcastframes_g +=
2384 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2385
2386 stats->rxmulticastframes_g +=
2387 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2388
2389 stats->rxcrcerror +=
2390 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2391
2392 stats->rxrunterror +=
2393 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2394
2395 stats->rxjabbererror +=
2396 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2397
2398 stats->rxundersize_g +=
2399 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2400
2401 stats->rxoversize_g +=
2402 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2403
2404 stats->rx64octets_gb +=
2405 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2406
2407 stats->rx65to127octets_gb +=
2408 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2409
2410 stats->rx128to255octets_gb +=
2411 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2412
2413 stats->rx256to511octets_gb +=
2414 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2415
2416 stats->rx512to1023octets_gb +=
2417 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2418
2419 stats->rx1024tomaxoctets_gb +=
2420 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2421
2422 stats->rxunicastframes_g +=
2423 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2424
2425 stats->rxlengtherror +=
2426 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2427
2428 stats->rxoutofrangetype +=
2429 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2430
2431 stats->rxpauseframes +=
2432 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2433
2434 stats->rxfifooverflow +=
2435 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2436
2437 stats->rxvlanframes_gb +=
2438 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2439
2440 stats->rxwatchdogerror +=
2441 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2442
2443 /* Un-freeze counters */
2444 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2445 }
2446
2447 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2448 {
2449 /* Set counters to reset on read */
2450 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2451
2452 /* Reset the counters */
2453 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2454 }
2455
2456 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2457 struct xgbe_channel *channel)
2458 {
2459 unsigned int tx_dsr, tx_pos, tx_qidx;
2460 unsigned int tx_status;
2461 unsigned long tx_timeout;
2462
2463 /* Calculate the status register to read and the position within */
2464 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2465 tx_dsr = DMA_DSR0;
2466 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2467 DMA_DSR0_TPS_START;
2468 } else {
2469 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2470
2471 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2472 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2473 DMA_DSRX_TPS_START;
2474 }
2475
2476 /* The Tx engine cannot be stopped if it is actively processing
2477 * descriptors. Wait for the Tx engine to enter the stopped or
2478 * suspended state. Don't wait forever though...
2479 */
2480 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2481 while (time_before(jiffies, tx_timeout)) {
2482 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2483 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2484 if ((tx_status == DMA_TPS_STOPPED) ||
2485 (tx_status == DMA_TPS_SUSPENDED))
2486 break;
2487
2488 usleep_range(500, 1000);
2489 }
2490
2491 if (!time_before(jiffies, tx_timeout))
2492 netdev_info(pdata->netdev,
2493 "timed out waiting for Tx DMA channel %u to stop\n",
2494 channel->queue_index);
2495 }
2496
2497 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2498 {
2499 struct xgbe_channel *channel;
2500 unsigned int i;
2501
2502 /* Enable each Tx DMA channel */
2503 channel = pdata->channel;
2504 for (i = 0; i < pdata->channel_count; i++, channel++) {
2505 if (!channel->tx_ring)
2506 break;
2507
2508 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2509 }
2510
2511 /* Enable each Tx queue */
2512 for (i = 0; i < pdata->tx_q_count; i++)
2513 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2514 MTL_Q_ENABLED);
2515
2516 /* Enable MAC Tx */
2517 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2518 }
2519
2520 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2521 {
2522 struct xgbe_channel *channel;
2523 unsigned int i;
2524
2525 /* Prepare for Tx DMA channel stop */
2526 channel = pdata->channel;
2527 for (i = 0; i < pdata->channel_count; i++, channel++) {
2528 if (!channel->tx_ring)
2529 break;
2530
2531 xgbe_prepare_tx_stop(pdata, channel);
2532 }
2533
2534 /* Disable MAC Tx */
2535 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2536
2537 /* Disable each Tx queue */
2538 for (i = 0; i < pdata->tx_q_count; i++)
2539 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2540
2541 /* Disable each Tx DMA channel */
2542 channel = pdata->channel;
2543 for (i = 0; i < pdata->channel_count; i++, channel++) {
2544 if (!channel->tx_ring)
2545 break;
2546
2547 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2548 }
2549 }
2550
2551 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2552 {
2553 struct xgbe_channel *channel;
2554 unsigned int reg_val, i;
2555
2556 /* Enable each Rx DMA channel */
2557 channel = pdata->channel;
2558 for (i = 0; i < pdata->channel_count; i++, channel++) {
2559 if (!channel->rx_ring)
2560 break;
2561
2562 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2563 }
2564
2565 /* Enable each Rx queue */
2566 reg_val = 0;
2567 for (i = 0; i < pdata->rx_q_count; i++)
2568 reg_val |= (0x02 << (i << 1));
2569 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2570
2571 /* Enable MAC Rx */
2572 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2573 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2574 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2575 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2576 }
2577
2578 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2579 {
2580 struct xgbe_channel *channel;
2581 unsigned int i;
2582
2583 /* Disable MAC Rx */
2584 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2585 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2586 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2587 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2588
2589 /* Disable each Rx queue */
2590 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2591
2592 /* Disable each Rx DMA channel */
2593 channel = pdata->channel;
2594 for (i = 0; i < pdata->channel_count; i++, channel++) {
2595 if (!channel->rx_ring)
2596 break;
2597
2598 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2599 }
2600 }
2601
2602 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2603 {
2604 struct xgbe_channel *channel;
2605 unsigned int i;
2606
2607 /* Enable each Tx DMA channel */
2608 channel = pdata->channel;
2609 for (i = 0; i < pdata->channel_count; i++, channel++) {
2610 if (!channel->tx_ring)
2611 break;
2612
2613 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2614 }
2615
2616 /* Enable MAC Tx */
2617 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2618 }
2619
2620 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2621 {
2622 struct xgbe_channel *channel;
2623 unsigned int i;
2624
2625 /* Prepare for Tx DMA channel stop */
2626 channel = pdata->channel;
2627 for (i = 0; i < pdata->channel_count; i++, channel++) {
2628 if (!channel->tx_ring)
2629 break;
2630
2631 xgbe_prepare_tx_stop(pdata, channel);
2632 }
2633
2634 /* Disable MAC Tx */
2635 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2636
2637 /* Disable each Tx DMA channel */
2638 channel = pdata->channel;
2639 for (i = 0; i < pdata->channel_count; i++, channel++) {
2640 if (!channel->tx_ring)
2641 break;
2642
2643 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2644 }
2645 }
2646
2647 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2648 {
2649 struct xgbe_channel *channel;
2650 unsigned int i;
2651
2652 /* Enable each Rx DMA channel */
2653 channel = pdata->channel;
2654 for (i = 0; i < pdata->channel_count; i++, channel++) {
2655 if (!channel->rx_ring)
2656 break;
2657
2658 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2659 }
2660 }
2661
2662 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2663 {
2664 struct xgbe_channel *channel;
2665 unsigned int i;
2666
2667 /* Disable each Rx DMA channel */
2668 channel = pdata->channel;
2669 for (i = 0; i < pdata->channel_count; i++, channel++) {
2670 if (!channel->rx_ring)
2671 break;
2672
2673 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2674 }
2675 }
2676
2677 static int xgbe_init(struct xgbe_prv_data *pdata)
2678 {
2679 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2680 int ret;
2681
2682 DBGPR("-->xgbe_init\n");
2683
2684 /* Flush Tx queues */
2685 ret = xgbe_flush_tx_queues(pdata);
2686 if (ret)
2687 return ret;
2688
2689 /*
2690 * Initialize DMA related features
2691 */
2692 xgbe_config_dma_bus(pdata);
2693 xgbe_config_dma_cache(pdata);
2694 xgbe_config_osp_mode(pdata);
2695 xgbe_config_pblx8(pdata);
2696 xgbe_config_tx_pbl_val(pdata);
2697 xgbe_config_rx_pbl_val(pdata);
2698 xgbe_config_rx_coalesce(pdata);
2699 xgbe_config_tx_coalesce(pdata);
2700 xgbe_config_rx_buffer_size(pdata);
2701 xgbe_config_tso_mode(pdata);
2702 xgbe_config_sph_mode(pdata);
2703 xgbe_config_rss(pdata);
2704 desc_if->wrapper_tx_desc_init(pdata);
2705 desc_if->wrapper_rx_desc_init(pdata);
2706 xgbe_enable_dma_interrupts(pdata);
2707
2708 /*
2709 * Initialize MTL related features
2710 */
2711 xgbe_config_mtl_mode(pdata);
2712 xgbe_config_queue_mapping(pdata);
2713 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2714 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2715 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2716 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2717 xgbe_config_tx_fifo_size(pdata);
2718 xgbe_config_rx_fifo_size(pdata);
2719 xgbe_config_flow_control_threshold(pdata);
2720 /*TODO: Error Packet and undersized good Packet forwarding enable
2721 (FEP and FUP)
2722 */
2723 xgbe_config_dcb_tc(pdata);
2724 xgbe_config_dcb_pfc(pdata);
2725 xgbe_enable_mtl_interrupts(pdata);
2726
2727 /*
2728 * Initialize MAC related features
2729 */
2730 xgbe_config_mac_address(pdata);
2731 xgbe_config_jumbo_enable(pdata);
2732 xgbe_config_flow_control(pdata);
2733 xgbe_config_checksum_offload(pdata);
2734 xgbe_config_vlan_support(pdata);
2735 xgbe_config_mmc(pdata);
2736 xgbe_enable_mac_interrupts(pdata);
2737
2738 DBGPR("<--xgbe_init\n");
2739
2740 return 0;
2741 }
2742
2743 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2744 {
2745 DBGPR("-->xgbe_init_function_ptrs\n");
2746
2747 hw_if->tx_complete = xgbe_tx_complete;
2748
2749 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2750 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
2751 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
2752 hw_if->set_mac_address = xgbe_set_mac_address;
2753
2754 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2755 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2756
2757 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2758 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2759 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2760 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2761 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2762
2763 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2764 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2765
2766 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2767 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2768 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2769
2770 hw_if->enable_tx = xgbe_enable_tx;
2771 hw_if->disable_tx = xgbe_disable_tx;
2772 hw_if->enable_rx = xgbe_enable_rx;
2773 hw_if->disable_rx = xgbe_disable_rx;
2774
2775 hw_if->powerup_tx = xgbe_powerup_tx;
2776 hw_if->powerdown_tx = xgbe_powerdown_tx;
2777 hw_if->powerup_rx = xgbe_powerup_rx;
2778 hw_if->powerdown_rx = xgbe_powerdown_rx;
2779
2780 hw_if->dev_xmit = xgbe_dev_xmit;
2781 hw_if->dev_read = xgbe_dev_read;
2782 hw_if->enable_int = xgbe_enable_int;
2783 hw_if->disable_int = xgbe_disable_int;
2784 hw_if->init = xgbe_init;
2785 hw_if->exit = xgbe_exit;
2786
2787 /* Descriptor related Sequences have to be initialized here */
2788 hw_if->tx_desc_init = xgbe_tx_desc_init;
2789 hw_if->rx_desc_init = xgbe_rx_desc_init;
2790 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2791 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2792 hw_if->is_last_desc = xgbe_is_last_desc;
2793 hw_if->is_context_desc = xgbe_is_context_desc;
2794
2795 /* For FLOW ctrl */
2796 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2797 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2798
2799 /* For RX coalescing */
2800 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2801 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2802 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2803 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2804
2805 /* For RX and TX threshold config */
2806 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2807 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2808
2809 /* For RX and TX Store and Forward Mode config */
2810 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2811 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2812
2813 /* For TX DMA Operating on Second Frame config */
2814 hw_if->config_osp_mode = xgbe_config_osp_mode;
2815
2816 /* For RX and TX PBL config */
2817 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2818 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2819 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2820 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2821 hw_if->config_pblx8 = xgbe_config_pblx8;
2822
2823 /* For MMC statistics support */
2824 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2825 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2826 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2827
2828 /* For PTP config */
2829 hw_if->config_tstamp = xgbe_config_tstamp;
2830 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2831 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2832 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2833 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2834
2835 /* For Data Center Bridging config */
2836 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2837 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2838
2839 /* For Receive Side Scaling */
2840 hw_if->enable_rss = xgbe_enable_rss;
2841 hw_if->disable_rss = xgbe_disable_rss;
2842 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2843 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
2844
2845 DBGPR("<--xgbe_init_function_ptrs\n");
2846 }
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