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net: fix amd-xgbe flow-control issue
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-mdio.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/interrupt.h>
118 #include <linux/module.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/of.h>
123 #include <linux/bitops.h>
124 #include <linux/jiffies.h>
125
126 #include "xgbe.h"
127 #include "xgbe-common.h"
128
129 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
130 {
131 int reg;
132
133 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
134 reg &= ~XGBE_AN_CL37_INT_MASK;
135 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
136 }
137
138 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
139 {
140 int reg;
141
142 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
143 reg &= ~XGBE_AN_CL37_INT_MASK;
144 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
145
146 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
147 reg &= ~XGBE_PCS_CL37_BP;
148 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
149 }
150
151 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
152 {
153 int reg;
154
155 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
156 reg |= XGBE_PCS_CL37_BP;
157 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
158
159 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
160 reg |= XGBE_AN_CL37_INT_MASK;
161 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
162 }
163
164 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
165 {
166 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
167 }
168
169 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
170 {
171 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
172 }
173
174 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
175 {
176 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
177 }
178
179 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
180 {
181 switch (pdata->an_mode) {
182 case XGBE_AN_MODE_CL73:
183 case XGBE_AN_MODE_CL73_REDRV:
184 xgbe_an73_enable_interrupts(pdata);
185 break;
186 case XGBE_AN_MODE_CL37:
187 case XGBE_AN_MODE_CL37_SGMII:
188 xgbe_an37_enable_interrupts(pdata);
189 break;
190 default:
191 break;
192 }
193 }
194
195 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
196 {
197 xgbe_an73_clear_interrupts(pdata);
198 xgbe_an37_clear_interrupts(pdata);
199 }
200
201 static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata)
202 {
203 unsigned int reg;
204
205 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
206
207 reg |= XGBE_KR_TRAINING_ENABLE;
208 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
209 }
210
211 static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata)
212 {
213 unsigned int reg;
214
215 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
216
217 reg &= ~XGBE_KR_TRAINING_ENABLE;
218 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
219 }
220
221 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
222 {
223 /* Enable KR training */
224 xgbe_an73_enable_kr_training(pdata);
225
226 /* Set MAC to 10G speed */
227 pdata->hw_if.set_speed(pdata, SPEED_10000);
228
229 /* Call PHY implementation support to complete rate change */
230 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
231 }
232
233 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
234 {
235 /* Disable KR training */
236 xgbe_an73_disable_kr_training(pdata);
237
238 /* Set MAC to 2.5G speed */
239 pdata->hw_if.set_speed(pdata, SPEED_2500);
240
241 /* Call PHY implementation support to complete rate change */
242 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
243 }
244
245 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
246 {
247 /* Disable KR training */
248 xgbe_an73_disable_kr_training(pdata);
249
250 /* Set MAC to 1G speed */
251 pdata->hw_if.set_speed(pdata, SPEED_1000);
252
253 /* Call PHY implementation support to complete rate change */
254 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
255 }
256
257 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
258 {
259 /* If a KR re-driver is present, change to KR mode instead */
260 if (pdata->kr_redrv)
261 return xgbe_kr_mode(pdata);
262
263 /* Disable KR training */
264 xgbe_an73_disable_kr_training(pdata);
265
266 /* Set MAC to 10G speed */
267 pdata->hw_if.set_speed(pdata, SPEED_10000);
268
269 /* Call PHY implementation support to complete rate change */
270 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
271 }
272
273 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
274 {
275 /* Disable KR training */
276 xgbe_an73_disable_kr_training(pdata);
277
278 /* Set MAC to 1G speed */
279 pdata->hw_if.set_speed(pdata, SPEED_1000);
280
281 /* Call PHY implementation support to complete rate change */
282 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
283 }
284
285 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
286 {
287 /* Disable KR training */
288 xgbe_an73_disable_kr_training(pdata);
289
290 /* Set MAC to 1G speed */
291 pdata->hw_if.set_speed(pdata, SPEED_1000);
292
293 /* Call PHY implementation support to complete rate change */
294 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
295 }
296
297 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
298 {
299 /* Disable KR training */
300 xgbe_an73_disable_kr_training(pdata);
301
302 /* Set MAC to 1G speed */
303 pdata->hw_if.set_speed(pdata, SPEED_1000);
304
305 /* Call PHY implementation support to complete rate change */
306 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
307 }
308
309 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
310 {
311 return pdata->phy_if.phy_impl.cur_mode(pdata);
312 }
313
314 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
315 {
316 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
317 }
318
319 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
320 enum xgbe_mode mode)
321 {
322 switch (mode) {
323 case XGBE_MODE_KX_1000:
324 xgbe_kx_1000_mode(pdata);
325 break;
326 case XGBE_MODE_KX_2500:
327 xgbe_kx_2500_mode(pdata);
328 break;
329 case XGBE_MODE_KR:
330 xgbe_kr_mode(pdata);
331 break;
332 case XGBE_MODE_SGMII_100:
333 xgbe_sgmii_100_mode(pdata);
334 break;
335 case XGBE_MODE_SGMII_1000:
336 xgbe_sgmii_1000_mode(pdata);
337 break;
338 case XGBE_MODE_X:
339 xgbe_x_mode(pdata);
340 break;
341 case XGBE_MODE_SFI:
342 xgbe_sfi_mode(pdata);
343 break;
344 case XGBE_MODE_UNKNOWN:
345 break;
346 default:
347 netif_dbg(pdata, link, pdata->netdev,
348 "invalid operation mode requested (%u)\n", mode);
349 }
350 }
351
352 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
353 {
354 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
355 }
356
357 static void xgbe_set_mode(struct xgbe_prv_data *pdata,
358 enum xgbe_mode mode)
359 {
360 if (mode == xgbe_cur_mode(pdata))
361 return;
362
363 xgbe_change_mode(pdata, mode);
364 }
365
366 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
367 enum xgbe_mode mode)
368 {
369 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
370 }
371
372 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
373 bool restart)
374 {
375 unsigned int reg;
376
377 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
378 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
379
380 if (enable)
381 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
382
383 if (restart)
384 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
385
386 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
387 }
388
389 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
390 {
391 xgbe_an37_enable_interrupts(pdata);
392 xgbe_an37_set(pdata, true, true);
393
394 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
395 }
396
397 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
398 {
399 xgbe_an37_set(pdata, false, false);
400 xgbe_an37_disable_interrupts(pdata);
401
402 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
403 }
404
405 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
406 bool restart)
407 {
408 unsigned int reg;
409
410 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
411 reg &= ~MDIO_AN_CTRL1_ENABLE;
412
413 if (enable)
414 reg |= MDIO_AN_CTRL1_ENABLE;
415
416 if (restart)
417 reg |= MDIO_AN_CTRL1_RESTART;
418
419 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
420 }
421
422 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
423 {
424 xgbe_an73_enable_interrupts(pdata);
425 xgbe_an73_set(pdata, true, true);
426
427 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
428 }
429
430 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
431 {
432 xgbe_an73_set(pdata, false, false);
433 xgbe_an73_disable_interrupts(pdata);
434
435 pdata->an_start = 0;
436
437 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
438 }
439
440 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
441 {
442 if (pdata->phy_if.phy_impl.an_pre)
443 pdata->phy_if.phy_impl.an_pre(pdata);
444
445 switch (pdata->an_mode) {
446 case XGBE_AN_MODE_CL73:
447 case XGBE_AN_MODE_CL73_REDRV:
448 xgbe_an73_restart(pdata);
449 break;
450 case XGBE_AN_MODE_CL37:
451 case XGBE_AN_MODE_CL37_SGMII:
452 xgbe_an37_restart(pdata);
453 break;
454 default:
455 break;
456 }
457 }
458
459 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
460 {
461 if (pdata->phy_if.phy_impl.an_post)
462 pdata->phy_if.phy_impl.an_post(pdata);
463
464 switch (pdata->an_mode) {
465 case XGBE_AN_MODE_CL73:
466 case XGBE_AN_MODE_CL73_REDRV:
467 xgbe_an73_disable(pdata);
468 break;
469 case XGBE_AN_MODE_CL37:
470 case XGBE_AN_MODE_CL37_SGMII:
471 xgbe_an37_disable(pdata);
472 break;
473 default:
474 break;
475 }
476 }
477
478 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
479 {
480 xgbe_an73_disable(pdata);
481 xgbe_an37_disable(pdata);
482 }
483
484 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
485 enum xgbe_rx *state)
486 {
487 unsigned int ad_reg, lp_reg, reg;
488
489 *state = XGBE_RX_COMPLETE;
490
491 /* If we're not in KR mode then we're done */
492 if (!xgbe_in_kr_mode(pdata))
493 return XGBE_AN_PAGE_RECEIVED;
494
495 /* Enable/Disable FEC */
496 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
497 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
498
499 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
500 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
501 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
502 reg |= pdata->fec_ability;
503
504 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
505
506 /* Start KR training */
507 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
508 if (reg & XGBE_KR_TRAINING_ENABLE) {
509 if (pdata->phy_if.phy_impl.kr_training_pre)
510 pdata->phy_if.phy_impl.kr_training_pre(pdata);
511
512 reg |= XGBE_KR_TRAINING_START;
513 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
514 reg);
515
516 netif_dbg(pdata, link, pdata->netdev,
517 "KR training initiated\n");
518
519 if (pdata->phy_if.phy_impl.kr_training_post)
520 pdata->phy_if.phy_impl.kr_training_post(pdata);
521 }
522
523 return XGBE_AN_PAGE_RECEIVED;
524 }
525
526 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
527 enum xgbe_rx *state)
528 {
529 u16 msg;
530
531 *state = XGBE_RX_XNP;
532
533 msg = XGBE_XNP_MCF_NULL_MESSAGE;
534 msg |= XGBE_XNP_MP_FORMATTED;
535
536 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
537 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
538 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
539
540 return XGBE_AN_PAGE_RECEIVED;
541 }
542
543 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
544 enum xgbe_rx *state)
545 {
546 unsigned int link_support;
547 unsigned int reg, ad_reg, lp_reg;
548
549 /* Read Base Ability register 2 first */
550 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
551
552 /* Check for a supported mode, otherwise restart in a different one */
553 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
554 if (!(reg & link_support))
555 return XGBE_AN_INCOMPAT_LINK;
556
557 /* Check Extended Next Page support */
558 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
559 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
560
561 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
562 (lp_reg & XGBE_XNP_NP_EXCHANGE))
563 ? xgbe_an73_tx_xnp(pdata, state)
564 : xgbe_an73_tx_training(pdata, state);
565 }
566
567 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
568 enum xgbe_rx *state)
569 {
570 unsigned int ad_reg, lp_reg;
571
572 /* Check Extended Next Page support */
573 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
574 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
575
576 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
577 (lp_reg & XGBE_XNP_NP_EXCHANGE))
578 ? xgbe_an73_tx_xnp(pdata, state)
579 : xgbe_an73_tx_training(pdata, state);
580 }
581
582 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
583 {
584 enum xgbe_rx *state;
585 unsigned long an_timeout;
586 enum xgbe_an ret;
587
588 if (!pdata->an_start) {
589 pdata->an_start = jiffies;
590 } else {
591 an_timeout = pdata->an_start +
592 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
593 if (time_after(jiffies, an_timeout)) {
594 /* Auto-negotiation timed out, reset state */
595 pdata->kr_state = XGBE_RX_BPA;
596 pdata->kx_state = XGBE_RX_BPA;
597
598 pdata->an_start = jiffies;
599
600 netif_dbg(pdata, link, pdata->netdev,
601 "CL73 AN timed out, resetting state\n");
602 }
603 }
604
605 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
606 : &pdata->kx_state;
607
608 switch (*state) {
609 case XGBE_RX_BPA:
610 ret = xgbe_an73_rx_bpa(pdata, state);
611 break;
612
613 case XGBE_RX_XNP:
614 ret = xgbe_an73_rx_xnp(pdata, state);
615 break;
616
617 default:
618 ret = XGBE_AN_ERROR;
619 }
620
621 return ret;
622 }
623
624 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
625 {
626 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
627
628 /* Be sure we aren't looping trying to negotiate */
629 if (xgbe_in_kr_mode(pdata)) {
630 pdata->kr_state = XGBE_RX_ERROR;
631
632 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
633 !XGBE_ADV(lks, 2500baseX_Full))
634 return XGBE_AN_NO_LINK;
635
636 if (pdata->kx_state != XGBE_RX_BPA)
637 return XGBE_AN_NO_LINK;
638 } else {
639 pdata->kx_state = XGBE_RX_ERROR;
640
641 if (!XGBE_ADV(lks, 10000baseKR_Full))
642 return XGBE_AN_NO_LINK;
643
644 if (pdata->kr_state != XGBE_RX_BPA)
645 return XGBE_AN_NO_LINK;
646 }
647
648 xgbe_an_disable(pdata);
649
650 xgbe_switch_mode(pdata);
651
652 xgbe_an_restart(pdata);
653
654 return XGBE_AN_INCOMPAT_LINK;
655 }
656
657 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
658 {
659 unsigned int reg;
660
661 /* Disable AN interrupts */
662 xgbe_an37_disable_interrupts(pdata);
663
664 /* Save the interrupt(s) that fired */
665 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
666 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
667 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
668
669 if (pdata->an_int) {
670 /* Clear the interrupt(s) that fired and process them */
671 reg &= ~XGBE_AN_CL37_INT_MASK;
672 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
673
674 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
675 } else {
676 /* Enable AN interrupts */
677 xgbe_an37_enable_interrupts(pdata);
678
679 /* Reissue interrupt if status is not clear */
680 if (pdata->vdata->irq_reissue_support)
681 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
682 }
683 }
684
685 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
686 {
687 /* Disable AN interrupts */
688 xgbe_an73_disable_interrupts(pdata);
689
690 /* Save the interrupt(s) that fired */
691 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
692
693 if (pdata->an_int) {
694 /* Clear the interrupt(s) that fired and process them */
695 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
696
697 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
698 } else {
699 /* Enable AN interrupts */
700 xgbe_an73_enable_interrupts(pdata);
701
702 /* Reissue interrupt if status is not clear */
703 if (pdata->vdata->irq_reissue_support)
704 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
705 }
706 }
707
708 static void xgbe_an_isr_task(unsigned long data)
709 {
710 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
711
712 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
713
714 switch (pdata->an_mode) {
715 case XGBE_AN_MODE_CL73:
716 case XGBE_AN_MODE_CL73_REDRV:
717 xgbe_an73_isr(pdata);
718 break;
719 case XGBE_AN_MODE_CL37:
720 case XGBE_AN_MODE_CL37_SGMII:
721 xgbe_an37_isr(pdata);
722 break;
723 default:
724 break;
725 }
726 }
727
728 static irqreturn_t xgbe_an_isr(int irq, void *data)
729 {
730 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
731
732 if (pdata->isr_as_tasklet)
733 tasklet_schedule(&pdata->tasklet_an);
734 else
735 xgbe_an_isr_task((unsigned long)pdata);
736
737 return IRQ_HANDLED;
738 }
739
740 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
741 {
742 xgbe_an_isr_task((unsigned long)pdata);
743
744 return IRQ_HANDLED;
745 }
746
747 static void xgbe_an_irq_work(struct work_struct *work)
748 {
749 struct xgbe_prv_data *pdata = container_of(work,
750 struct xgbe_prv_data,
751 an_irq_work);
752
753 /* Avoid a race between enabling the IRQ and exiting the work by
754 * waiting for the work to finish and then queueing it
755 */
756 flush_work(&pdata->an_work);
757 queue_work(pdata->an_workqueue, &pdata->an_work);
758 }
759
760 static const char *xgbe_state_as_string(enum xgbe_an state)
761 {
762 switch (state) {
763 case XGBE_AN_READY:
764 return "Ready";
765 case XGBE_AN_PAGE_RECEIVED:
766 return "Page-Received";
767 case XGBE_AN_INCOMPAT_LINK:
768 return "Incompatible-Link";
769 case XGBE_AN_COMPLETE:
770 return "Complete";
771 case XGBE_AN_NO_LINK:
772 return "No-Link";
773 case XGBE_AN_ERROR:
774 return "Error";
775 default:
776 return "Undefined";
777 }
778 }
779
780 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
781 {
782 enum xgbe_an cur_state = pdata->an_state;
783
784 if (!pdata->an_int)
785 return;
786
787 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
788 pdata->an_state = XGBE_AN_COMPLETE;
789 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
790
791 /* If SGMII is enabled, check the link status */
792 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
793 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
794 pdata->an_state = XGBE_AN_NO_LINK;
795 }
796
797 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
798 xgbe_state_as_string(pdata->an_state));
799
800 cur_state = pdata->an_state;
801
802 switch (pdata->an_state) {
803 case XGBE_AN_READY:
804 break;
805
806 case XGBE_AN_COMPLETE:
807 netif_dbg(pdata, link, pdata->netdev,
808 "Auto negotiation successful\n");
809 break;
810
811 case XGBE_AN_NO_LINK:
812 break;
813
814 default:
815 pdata->an_state = XGBE_AN_ERROR;
816 }
817
818 if (pdata->an_state == XGBE_AN_ERROR) {
819 netdev_err(pdata->netdev,
820 "error during auto-negotiation, state=%u\n",
821 cur_state);
822
823 pdata->an_int = 0;
824 xgbe_an37_clear_interrupts(pdata);
825 }
826
827 if (pdata->an_state >= XGBE_AN_COMPLETE) {
828 pdata->an_result = pdata->an_state;
829 pdata->an_state = XGBE_AN_READY;
830
831 if (pdata->phy_if.phy_impl.an_post)
832 pdata->phy_if.phy_impl.an_post(pdata);
833
834 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
835 xgbe_state_as_string(pdata->an_result));
836 }
837
838 xgbe_an37_enable_interrupts(pdata);
839 }
840
841 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
842 {
843 enum xgbe_an cur_state = pdata->an_state;
844
845 if (!pdata->an_int)
846 return;
847
848 next_int:
849 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
850 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
851 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
852 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
853 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
854 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
855 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
856 pdata->an_state = XGBE_AN_COMPLETE;
857 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
858 } else {
859 pdata->an_state = XGBE_AN_ERROR;
860 }
861
862 again:
863 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
864 xgbe_state_as_string(pdata->an_state));
865
866 cur_state = pdata->an_state;
867
868 switch (pdata->an_state) {
869 case XGBE_AN_READY:
870 pdata->an_supported = 0;
871 break;
872
873 case XGBE_AN_PAGE_RECEIVED:
874 pdata->an_state = xgbe_an73_page_received(pdata);
875 pdata->an_supported++;
876 break;
877
878 case XGBE_AN_INCOMPAT_LINK:
879 pdata->an_supported = 0;
880 pdata->parallel_detect = 0;
881 pdata->an_state = xgbe_an73_incompat_link(pdata);
882 break;
883
884 case XGBE_AN_COMPLETE:
885 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
886 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
887 pdata->an_supported ? "Auto negotiation"
888 : "Parallel detection");
889 break;
890
891 case XGBE_AN_NO_LINK:
892 break;
893
894 default:
895 pdata->an_state = XGBE_AN_ERROR;
896 }
897
898 if (pdata->an_state == XGBE_AN_NO_LINK) {
899 pdata->an_int = 0;
900 xgbe_an73_clear_interrupts(pdata);
901 } else if (pdata->an_state == XGBE_AN_ERROR) {
902 netdev_err(pdata->netdev,
903 "error during auto-negotiation, state=%u\n",
904 cur_state);
905
906 pdata->an_int = 0;
907 xgbe_an73_clear_interrupts(pdata);
908 }
909
910 if (pdata->an_state >= XGBE_AN_COMPLETE) {
911 pdata->an_result = pdata->an_state;
912 pdata->an_state = XGBE_AN_READY;
913 pdata->kr_state = XGBE_RX_BPA;
914 pdata->kx_state = XGBE_RX_BPA;
915 pdata->an_start = 0;
916
917 if (pdata->phy_if.phy_impl.an_post)
918 pdata->phy_if.phy_impl.an_post(pdata);
919
920 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
921 xgbe_state_as_string(pdata->an_result));
922 }
923
924 if (cur_state != pdata->an_state)
925 goto again;
926
927 if (pdata->an_int)
928 goto next_int;
929
930 xgbe_an73_enable_interrupts(pdata);
931 }
932
933 static void xgbe_an_state_machine(struct work_struct *work)
934 {
935 struct xgbe_prv_data *pdata = container_of(work,
936 struct xgbe_prv_data,
937 an_work);
938
939 mutex_lock(&pdata->an_mutex);
940
941 switch (pdata->an_mode) {
942 case XGBE_AN_MODE_CL73:
943 case XGBE_AN_MODE_CL73_REDRV:
944 xgbe_an73_state_machine(pdata);
945 break;
946 case XGBE_AN_MODE_CL37:
947 case XGBE_AN_MODE_CL37_SGMII:
948 xgbe_an37_state_machine(pdata);
949 break;
950 default:
951 break;
952 }
953
954 /* Reissue interrupt if status is not clear */
955 if (pdata->vdata->irq_reissue_support)
956 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
957
958 mutex_unlock(&pdata->an_mutex);
959 }
960
961 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
962 {
963 struct ethtool_link_ksettings lks;
964 unsigned int reg;
965
966 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
967
968 /* Set up Advertisement register */
969 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
970 if (XGBE_ADV(&lks, Pause))
971 reg |= 0x100;
972 else
973 reg &= ~0x100;
974
975 if (XGBE_ADV(&lks, Asym_Pause))
976 reg |= 0x80;
977 else
978 reg &= ~0x80;
979
980 /* Full duplex, but not half */
981 reg |= XGBE_AN_CL37_FD_MASK;
982 reg &= ~XGBE_AN_CL37_HD_MASK;
983
984 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
985
986 /* Set up the Control register */
987 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
988 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
989 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
990
991 switch (pdata->an_mode) {
992 case XGBE_AN_MODE_CL37:
993 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
994 break;
995 case XGBE_AN_MODE_CL37_SGMII:
996 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
997 break;
998 default:
999 break;
1000 }
1001
1002 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
1003
1004 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1005
1006 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
1007 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
1008 }
1009
1010 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1011 {
1012 struct ethtool_link_ksettings lks;
1013 unsigned int reg;
1014
1015 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1016
1017 /* Set up Advertisement register 3 first */
1018 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1019 if (XGBE_ADV(&lks, 10000baseR_FEC))
1020 reg |= 0xc000;
1021 else
1022 reg &= ~0xc000;
1023
1024 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1025
1026 /* Set up Advertisement register 2 next */
1027 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1028 if (XGBE_ADV(&lks, 10000baseKR_Full))
1029 reg |= 0x80;
1030 else
1031 reg &= ~0x80;
1032
1033 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1034 XGBE_ADV(&lks, 2500baseX_Full))
1035 reg |= 0x20;
1036 else
1037 reg &= ~0x20;
1038
1039 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1040
1041 /* Set up Advertisement register 1 last */
1042 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1043 if (XGBE_ADV(&lks, Pause))
1044 reg |= 0x400;
1045 else
1046 reg &= ~0x400;
1047
1048 if (XGBE_ADV(&lks, Asym_Pause))
1049 reg |= 0x800;
1050 else
1051 reg &= ~0x800;
1052
1053 /* We don't intend to perform XNP */
1054 reg &= ~XGBE_XNP_NP_EXCHANGE;
1055
1056 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1057
1058 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1059 }
1060
1061 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1062 {
1063 /* Set up advertisement registers based on current settings */
1064 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1065 switch (pdata->an_mode) {
1066 case XGBE_AN_MODE_CL73:
1067 case XGBE_AN_MODE_CL73_REDRV:
1068 xgbe_an73_init(pdata);
1069 break;
1070 case XGBE_AN_MODE_CL37:
1071 case XGBE_AN_MODE_CL37_SGMII:
1072 xgbe_an37_init(pdata);
1073 break;
1074 default:
1075 break;
1076 }
1077 }
1078
1079 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1080 {
1081 if (pdata->tx_pause && pdata->rx_pause)
1082 return "rx/tx";
1083 else if (pdata->rx_pause)
1084 return "rx";
1085 else if (pdata->tx_pause)
1086 return "tx";
1087 else
1088 return "off";
1089 }
1090
1091 static const char *xgbe_phy_speed_string(int speed)
1092 {
1093 switch (speed) {
1094 case SPEED_100:
1095 return "100Mbps";
1096 case SPEED_1000:
1097 return "1Gbps";
1098 case SPEED_2500:
1099 return "2.5Gbps";
1100 case SPEED_10000:
1101 return "10Gbps";
1102 case SPEED_UNKNOWN:
1103 return "Unknown";
1104 default:
1105 return "Unsupported";
1106 }
1107 }
1108
1109 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1110 {
1111 if (pdata->phy.link)
1112 netdev_info(pdata->netdev,
1113 "Link is Up - %s/%s - flow control %s\n",
1114 xgbe_phy_speed_string(pdata->phy.speed),
1115 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1116 xgbe_phy_fc_string(pdata));
1117 else
1118 netdev_info(pdata->netdev, "Link is Down\n");
1119 }
1120
1121 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1122 {
1123 int new_state = 0;
1124
1125 if (pdata->phy.link) {
1126 /* Flow control support */
1127 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1128
1129 if (pdata->tx_pause != pdata->phy.tx_pause) {
1130 new_state = 1;
1131 pdata->tx_pause = pdata->phy.tx_pause;
1132 pdata->hw_if.config_tx_flow_control(pdata);
1133 }
1134
1135 if (pdata->rx_pause != pdata->phy.rx_pause) {
1136 new_state = 1;
1137 pdata->rx_pause = pdata->phy.rx_pause;
1138 pdata->hw_if.config_rx_flow_control(pdata);
1139 }
1140
1141 /* Speed support */
1142 if (pdata->phy_speed != pdata->phy.speed) {
1143 new_state = 1;
1144 pdata->phy_speed = pdata->phy.speed;
1145 }
1146
1147 if (pdata->phy_link != pdata->phy.link) {
1148 new_state = 1;
1149 pdata->phy_link = pdata->phy.link;
1150 }
1151 } else if (pdata->phy_link) {
1152 new_state = 1;
1153 pdata->phy_link = 0;
1154 pdata->phy_speed = SPEED_UNKNOWN;
1155 }
1156
1157 if (new_state && netif_msg_link(pdata))
1158 xgbe_phy_print_status(pdata);
1159 }
1160
1161 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1162 {
1163 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1164 }
1165
1166 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1167 {
1168 enum xgbe_mode mode;
1169
1170 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1171
1172 /* Disable auto-negotiation */
1173 xgbe_an_disable(pdata);
1174
1175 /* Set specified mode for specified speed */
1176 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1177 switch (mode) {
1178 case XGBE_MODE_KX_1000:
1179 case XGBE_MODE_KX_2500:
1180 case XGBE_MODE_KR:
1181 case XGBE_MODE_SGMII_100:
1182 case XGBE_MODE_SGMII_1000:
1183 case XGBE_MODE_X:
1184 case XGBE_MODE_SFI:
1185 break;
1186 case XGBE_MODE_UNKNOWN:
1187 default:
1188 return -EINVAL;
1189 }
1190
1191 /* Validate duplex mode */
1192 if (pdata->phy.duplex != DUPLEX_FULL)
1193 return -EINVAL;
1194
1195 xgbe_set_mode(pdata, mode);
1196
1197 return 0;
1198 }
1199
1200 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1201 {
1202 int ret;
1203
1204 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1205 pdata->link_check = jiffies;
1206
1207 ret = pdata->phy_if.phy_impl.an_config(pdata);
1208 if (ret)
1209 return ret;
1210
1211 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1212 ret = xgbe_phy_config_fixed(pdata);
1213 if (ret || !pdata->kr_redrv)
1214 return ret;
1215
1216 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1217 } else {
1218 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1219 }
1220
1221 /* Disable auto-negotiation interrupt */
1222 disable_irq(pdata->an_irq);
1223
1224 /* Start auto-negotiation in a supported mode */
1225 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1226 xgbe_set_mode(pdata, XGBE_MODE_KR);
1227 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1228 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1229 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1230 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1231 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1232 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1233 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1234 xgbe_set_mode(pdata, XGBE_MODE_X);
1235 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1236 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1237 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1238 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1239 } else {
1240 enable_irq(pdata->an_irq);
1241 return -EINVAL;
1242 }
1243
1244 /* Disable and stop any in progress auto-negotiation */
1245 xgbe_an_disable_all(pdata);
1246
1247 /* Clear any auto-negotitation interrupts */
1248 xgbe_an_clear_interrupts_all(pdata);
1249
1250 pdata->an_result = XGBE_AN_READY;
1251 pdata->an_state = XGBE_AN_READY;
1252 pdata->kr_state = XGBE_RX_BPA;
1253 pdata->kx_state = XGBE_RX_BPA;
1254
1255 /* Re-enable auto-negotiation interrupt */
1256 enable_irq(pdata->an_irq);
1257
1258 xgbe_an_init(pdata);
1259 xgbe_an_restart(pdata);
1260
1261 return 0;
1262 }
1263
1264 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1265 {
1266 int ret;
1267
1268 mutex_lock(&pdata->an_mutex);
1269
1270 ret = __xgbe_phy_config_aneg(pdata);
1271 if (ret)
1272 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1273 else
1274 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1275
1276 mutex_unlock(&pdata->an_mutex);
1277
1278 return ret;
1279 }
1280
1281 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1282 {
1283 return (pdata->an_result == XGBE_AN_COMPLETE);
1284 }
1285
1286 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1287 {
1288 unsigned long link_timeout;
1289
1290 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1291 if (time_after(jiffies, link_timeout)) {
1292 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1293 xgbe_phy_config_aneg(pdata);
1294 }
1295 }
1296
1297 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1298 {
1299 return pdata->phy_if.phy_impl.an_outcome(pdata);
1300 }
1301
1302 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1303 {
1304 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1305 enum xgbe_mode mode;
1306
1307 XGBE_ZERO_LP_ADV(lks);
1308
1309 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1310 mode = xgbe_cur_mode(pdata);
1311 else
1312 mode = xgbe_phy_status_aneg(pdata);
1313
1314 switch (mode) {
1315 case XGBE_MODE_SGMII_100:
1316 pdata->phy.speed = SPEED_100;
1317 break;
1318 case XGBE_MODE_X:
1319 case XGBE_MODE_KX_1000:
1320 case XGBE_MODE_SGMII_1000:
1321 pdata->phy.speed = SPEED_1000;
1322 break;
1323 case XGBE_MODE_KX_2500:
1324 pdata->phy.speed = SPEED_2500;
1325 break;
1326 case XGBE_MODE_KR:
1327 case XGBE_MODE_SFI:
1328 pdata->phy.speed = SPEED_10000;
1329 break;
1330 case XGBE_MODE_UNKNOWN:
1331 default:
1332 pdata->phy.speed = SPEED_UNKNOWN;
1333 }
1334
1335 pdata->phy.duplex = DUPLEX_FULL;
1336
1337 xgbe_set_mode(pdata, mode);
1338 }
1339
1340 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1341 {
1342 unsigned int link_aneg;
1343 int an_restart;
1344
1345 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1346 netif_carrier_off(pdata->netdev);
1347
1348 pdata->phy.link = 0;
1349 goto adjust_link;
1350 }
1351
1352 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1353
1354 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1355 &an_restart);
1356 if (an_restart) {
1357 xgbe_phy_config_aneg(pdata);
1358 return;
1359 }
1360
1361 if (pdata->phy.link) {
1362 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1363 xgbe_check_link_timeout(pdata);
1364 return;
1365 }
1366
1367 xgbe_phy_status_result(pdata);
1368
1369 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1370 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1371
1372 netif_carrier_on(pdata->netdev);
1373 } else {
1374 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1375 xgbe_check_link_timeout(pdata);
1376
1377 if (link_aneg)
1378 return;
1379 }
1380
1381 xgbe_phy_status_result(pdata);
1382
1383 netif_carrier_off(pdata->netdev);
1384 }
1385
1386 adjust_link:
1387 xgbe_phy_adjust_link(pdata);
1388 }
1389
1390 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1391 {
1392 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1393
1394 if (!pdata->phy_started)
1395 return;
1396
1397 /* Indicate the PHY is down */
1398 pdata->phy_started = 0;
1399
1400 /* Disable auto-negotiation */
1401 xgbe_an_disable_all(pdata);
1402
1403 if (pdata->dev_irq != pdata->an_irq)
1404 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1405
1406 pdata->phy_if.phy_impl.stop(pdata);
1407
1408 pdata->phy.link = 0;
1409 netif_carrier_off(pdata->netdev);
1410
1411 xgbe_phy_adjust_link(pdata);
1412 }
1413
1414 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1415 {
1416 struct net_device *netdev = pdata->netdev;
1417 int ret;
1418
1419 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1420
1421 ret = pdata->phy_if.phy_impl.start(pdata);
1422 if (ret)
1423 return ret;
1424
1425 /* If we have a separate AN irq, enable it */
1426 if (pdata->dev_irq != pdata->an_irq) {
1427 tasklet_init(&pdata->tasklet_an, xgbe_an_isr_task,
1428 (unsigned long)pdata);
1429
1430 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1431 xgbe_an_isr, 0, pdata->an_name,
1432 pdata);
1433 if (ret) {
1434 netdev_err(netdev, "phy irq request failed\n");
1435 goto err_stop;
1436 }
1437 }
1438
1439 /* Set initial mode - call the mode setting routines
1440 * directly to insure we are properly configured
1441 */
1442 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1443 xgbe_kr_mode(pdata);
1444 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1445 xgbe_kx_2500_mode(pdata);
1446 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1447 xgbe_kx_1000_mode(pdata);
1448 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1449 xgbe_sfi_mode(pdata);
1450 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1451 xgbe_x_mode(pdata);
1452 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1453 xgbe_sgmii_1000_mode(pdata);
1454 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1455 xgbe_sgmii_100_mode(pdata);
1456 } else {
1457 ret = -EINVAL;
1458 goto err_irq;
1459 }
1460
1461 /* Indicate the PHY is up and running */
1462 pdata->phy_started = 1;
1463
1464 xgbe_an_init(pdata);
1465 xgbe_an_enable_interrupts(pdata);
1466
1467 return xgbe_phy_config_aneg(pdata);
1468
1469 err_irq:
1470 if (pdata->dev_irq != pdata->an_irq)
1471 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1472
1473 err_stop:
1474 pdata->phy_if.phy_impl.stop(pdata);
1475
1476 return ret;
1477 }
1478
1479 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1480 {
1481 int ret;
1482
1483 ret = pdata->phy_if.phy_impl.reset(pdata);
1484 if (ret)
1485 return ret;
1486
1487 /* Disable auto-negotiation for now */
1488 xgbe_an_disable_all(pdata);
1489
1490 /* Clear auto-negotiation interrupts */
1491 xgbe_an_clear_interrupts_all(pdata);
1492
1493 return 0;
1494 }
1495
1496 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1497 {
1498 struct device *dev = pdata->dev;
1499
1500 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1501
1502 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1503 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1504 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1505 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1506 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1507 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1508 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1509 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1510 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1511 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1512 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1513 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1514
1515 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1516 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1517 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1518 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1519 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1520 MDIO_AN_ADVERTISE,
1521 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1522 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1523 MDIO_AN_ADVERTISE + 1,
1524 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1525 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1526 MDIO_AN_ADVERTISE + 2,
1527 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1528 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1529 MDIO_AN_COMP_STAT,
1530 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1531
1532 dev_dbg(dev, "\n*************************************************\n");
1533 }
1534
1535 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1536 {
1537 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1538
1539 if (XGBE_ADV(lks, 10000baseKR_Full))
1540 return SPEED_10000;
1541 else if (XGBE_ADV(lks, 10000baseT_Full))
1542 return SPEED_10000;
1543 else if (XGBE_ADV(lks, 2500baseX_Full))
1544 return SPEED_2500;
1545 else if (XGBE_ADV(lks, 2500baseT_Full))
1546 return SPEED_2500;
1547 else if (XGBE_ADV(lks, 1000baseKX_Full))
1548 return SPEED_1000;
1549 else if (XGBE_ADV(lks, 1000baseT_Full))
1550 return SPEED_1000;
1551 else if (XGBE_ADV(lks, 100baseT_Full))
1552 return SPEED_100;
1553
1554 return SPEED_UNKNOWN;
1555 }
1556
1557 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1558 {
1559 pdata->phy_if.phy_impl.exit(pdata);
1560 }
1561
1562 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1563 {
1564 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1565 int ret;
1566
1567 mutex_init(&pdata->an_mutex);
1568 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1569 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1570 pdata->mdio_mmd = MDIO_MMD_PCS;
1571
1572 /* Check for FEC support */
1573 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1574 MDIO_PMA_10GBR_FECABLE);
1575 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1576 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1577
1578 /* Setup the phy (including supported features) */
1579 ret = pdata->phy_if.phy_impl.init(pdata);
1580 if (ret)
1581 return ret;
1582
1583 /* Copy supported link modes to advertising link modes */
1584 XGBE_LM_COPY(lks, advertising, lks, supported);
1585
1586 pdata->phy.address = 0;
1587
1588 if (XGBE_ADV(lks, Autoneg)) {
1589 pdata->phy.autoneg = AUTONEG_ENABLE;
1590 pdata->phy.speed = SPEED_UNKNOWN;
1591 pdata->phy.duplex = DUPLEX_UNKNOWN;
1592 } else {
1593 pdata->phy.autoneg = AUTONEG_DISABLE;
1594 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1595 pdata->phy.duplex = DUPLEX_FULL;
1596 }
1597
1598 pdata->phy.link = 0;
1599
1600 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1601 pdata->phy.tx_pause = pdata->tx_pause;
1602 pdata->phy.rx_pause = pdata->rx_pause;
1603
1604 /* Fix up Flow Control advertising */
1605 XGBE_CLR_ADV(lks, Pause);
1606 XGBE_CLR_ADV(lks, Asym_Pause);
1607
1608 if (pdata->rx_pause) {
1609 XGBE_SET_ADV(lks, Pause);
1610 XGBE_SET_ADV(lks, Asym_Pause);
1611 }
1612
1613 if (pdata->tx_pause) {
1614 /* Equivalent to XOR of Asym_Pause */
1615 if (XGBE_ADV(lks, Asym_Pause))
1616 XGBE_CLR_ADV(lks, Asym_Pause);
1617 else
1618 XGBE_SET_ADV(lks, Asym_Pause);
1619 }
1620
1621 if (netif_msg_drv(pdata))
1622 xgbe_dump_phy_registers(pdata);
1623
1624 return 0;
1625 }
1626
1627 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1628 {
1629 phy_if->phy_init = xgbe_phy_init;
1630 phy_if->phy_exit = xgbe_phy_exit;
1631
1632 phy_if->phy_reset = xgbe_phy_reset;
1633 phy_if->phy_start = xgbe_phy_start;
1634 phy_if->phy_stop = xgbe_phy_stop;
1635
1636 phy_if->phy_status = xgbe_phy_status;
1637 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1638
1639 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1640
1641 phy_if->an_isr = xgbe_an_combined_isr;
1642 }
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