drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/kmod.h>
 119 #include <linux/device.h>
 120 #include <linux/property.h>
 121 #include <linux/mdio.h>
 122 #include <linux/phy.h>
 123
 124 #include "xgbe.h"
 125 #include "xgbe-common.h"
 126
 127 #define XGBE_BLWC_PROPERTY              "amd,serdes-blwc"
 128 #define XGBE_CDR_RATE_PROPERTY          "amd,serdes-cdr-rate"
 129 #define XGBE_PQ_SKEW_PROPERTY           "amd,serdes-pq-skew"
 130 #define XGBE_TX_AMP_PROPERTY            "amd,serdes-tx-amp"
 131 #define XGBE_DFE_CFG_PROPERTY           "amd,serdes-dfe-tap-config"
 132 #define XGBE_DFE_ENA_PROPERTY           "amd,serdes-dfe-tap-enable"
 133
 134 /* Default SerDes settings */
 135 #define XGBE_SPEED_1000_BLWC            1
 136 #define XGBE_SPEED_1000_CDR             0x2
 137 #define XGBE_SPEED_1000_PLL             0x0
 138 #define XGBE_SPEED_1000_PQ              0xa
 139 #define XGBE_SPEED_1000_RATE            0x3
 140 #define XGBE_SPEED_1000_TXAMP           0xf
 141 #define XGBE_SPEED_1000_WORD            0x1
 142 #define XGBE_SPEED_1000_DFE_TAP_CONFIG  0x3
 143 #define XGBE_SPEED_1000_DFE_TAP_ENABLE  0x0
 144
 145 #define XGBE_SPEED_2500_BLWC            1
 146 #define XGBE_SPEED_2500_CDR             0x2
 147 #define XGBE_SPEED_2500_PLL             0x0
 148 #define XGBE_SPEED_2500_PQ              0xa
 149 #define XGBE_SPEED_2500_RATE            0x1
 150 #define XGBE_SPEED_2500_TXAMP           0xf
 151 #define XGBE_SPEED_2500_WORD            0x1
 152 #define XGBE_SPEED_2500_DFE_TAP_CONFIG  0x3
 153 #define XGBE_SPEED_2500_DFE_TAP_ENABLE  0x0
 154
 155 #define XGBE_SPEED_10000_BLWC           0
 156 #define XGBE_SPEED_10000_CDR            0x7
 157 #define XGBE_SPEED_10000_PLL            0x1
 158 #define XGBE_SPEED_10000_PQ             0x12
 159 #define XGBE_SPEED_10000_RATE           0x0
 160 #define XGBE_SPEED_10000_TXAMP          0xa
 161 #define XGBE_SPEED_10000_WORD           0x7
 162 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
 163 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
 164
 165 /* Rate-change complete wait/retry count */
 166 #define XGBE_RATECHANGE_COUNT           500
 167
 168 static const u32 xgbe_phy_blwc[] = {
 169         XGBE_SPEED_1000_BLWC,
 170         XGBE_SPEED_2500_BLWC,
 171         XGBE_SPEED_10000_BLWC,
 172 };
 173
 174 static const u32 xgbe_phy_cdr_rate[] = {
 175         XGBE_SPEED_1000_CDR,
 176         XGBE_SPEED_2500_CDR,
 177         XGBE_SPEED_10000_CDR,
 178 };
 179
 180 static const u32 xgbe_phy_pq_skew[] = {
 181         XGBE_SPEED_1000_PQ,
 182         XGBE_SPEED_2500_PQ,
 183         XGBE_SPEED_10000_PQ,
 184 };
 185
 186 static const u32 xgbe_phy_tx_amp[] = {
 187         XGBE_SPEED_1000_TXAMP,
 188         XGBE_SPEED_2500_TXAMP,
 189         XGBE_SPEED_10000_TXAMP,
 190 };
 191
 192 static const u32 xgbe_phy_dfe_tap_cfg[] = {
 193         XGBE_SPEED_1000_DFE_TAP_CONFIG,
 194         XGBE_SPEED_2500_DFE_TAP_CONFIG,
 195         XGBE_SPEED_10000_DFE_TAP_CONFIG,
 196 };
 197
 198 static const u32 xgbe_phy_dfe_tap_ena[] = {
 199         XGBE_SPEED_1000_DFE_TAP_ENABLE,
 200         XGBE_SPEED_2500_DFE_TAP_ENABLE,
 201         XGBE_SPEED_10000_DFE_TAP_ENABLE,
 202 };
 203
 204 struct xgbe_phy_data {
 205         /* 1000/10000 vs 2500/10000 indicator */
 206         unsigned int speed_set;
 207
 208         /* SerDes UEFI configurable settings.
 209          *   Switching between modes/speeds requires new values for some
 210          *   SerDes settings.  The values can be supplied as device
 211          *   properties in array format.  The first array entry is for
 212          *   1GbE, second for 2.5GbE and third for 10GbE
 213          */
 214         u32 blwc[XGBE_SPEEDS];
 215         u32 cdr_rate[XGBE_SPEEDS];
 216         u32 pq_skew[XGBE_SPEEDS];
 217         u32 tx_amp[XGBE_SPEEDS];
 218         u32 dfe_tap_cfg[XGBE_SPEEDS];
 219         u32 dfe_tap_ena[XGBE_SPEEDS];
 220 };
 221
 222 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
 223 {
 224                 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
 225 }
 226
 227 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
 228 {
 229                 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
 230 }
 231
 232 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
 233 {
 234         struct xgbe_phy_data *phy_data = pdata->phy_data;
 235         enum xgbe_mode mode;
 236         unsigned int ad_reg, lp_reg;
 237
 238         pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
 239         pdata->phy.lp_advertising |= ADVERTISED_Backplane;
 240
 241         /* Compare Advertisement and Link Partner register 1 */
 242         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
 243         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
 244         if (lp_reg & 0x400)
 245                 pdata->phy.lp_advertising |= ADVERTISED_Pause;
 246         if (lp_reg & 0x800)
 247                 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
 248
 249         if (pdata->phy.pause_autoneg) {
 250                 /* Set flow control based on auto-negotiation result */
 251                 pdata->phy.tx_pause = 0;
 252                 pdata->phy.rx_pause = 0;
 253
 254                 if (ad_reg & lp_reg & 0x400) {
 255                         pdata->phy.tx_pause = 1;
 256                         pdata->phy.rx_pause = 1;
 257                 } else if (ad_reg & lp_reg & 0x800) {
 258                         if (ad_reg & 0x400)
 259                                 pdata->phy.rx_pause = 1;
 260                         else if (lp_reg & 0x400)
 261                                 pdata->phy.tx_pause = 1;
 262                 }
 263         }
 264
 265         /* Compare Advertisement and Link Partner register 2 */
 266         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
 267         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
 268         if (lp_reg & 0x80)
 269                 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
 270         if (lp_reg & 0x20) {
 271                 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
 272                         pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full;
 273                 else
 274                         pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
 275         }
 276
 277         ad_reg &= lp_reg;
 278         if (ad_reg & 0x80) {
 279                 mode = XGBE_MODE_KR;
 280         } else if (ad_reg & 0x20) {
 281                 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
 282                         mode = XGBE_MODE_KX_2500;
 283                 else
 284                         mode = XGBE_MODE_KX_1000;
 285         } else {
 286                 mode = XGBE_MODE_UNKNOWN;
 287         }
 288
 289         /* Compare Advertisement and Link Partner register 3 */
 290         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
 291         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
 292         if (lp_reg & 0xc000)
 293                 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
 294
 295         return mode;
 296 }
 297
 298 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
 299 {
 300         /* Nothing uniquely required for an configuration */
 301         return 0;
 302 }
 303
 304 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
 305 {
 306         return XGBE_AN_MODE_CL73;
 307 }
 308
 309 static void xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata)
 310 {
 311         unsigned int reg;
 312
 313         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 314
 315         reg |= MDIO_CTRL1_LPOWER;
 316         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 317
 318         usleep_range(75, 100);
 319
 320         reg &= ~MDIO_CTRL1_LPOWER;
 321         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 322 }
 323
 324 static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
 325 {
 326         /* Assert Rx and Tx ratechange */
 327         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
 328 }
 329
 330 static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
 331 {
 332         unsigned int wait;
 333         u16 status;
 334
 335         /* Release Rx and Tx ratechange */
 336         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
 337
 338         /* Wait for Rx and Tx ready */
 339         wait = XGBE_RATECHANGE_COUNT;
 340         while (wait--) {
 341                 usleep_range(50, 75);
 342
 343                 status = XSIR0_IOREAD(pdata, SIR0_STATUS);
 344                 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
 345                     XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
 346                         goto rx_reset;
 347         }
 348
 349         netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",
 350                   status);
 351
 352 rx_reset:
 353         /* Perform Rx reset for the DFE changes */
 354         XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
 355         XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
 356 }
 357
 358 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
 359 {
 360         struct xgbe_phy_data *phy_data = pdata->phy_data;
 361         unsigned int reg;
 362
 363         /* Set PCS to KR/10G speed */
 364         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
 365         reg &= ~MDIO_PCS_CTRL2_TYPE;
 366         reg |= MDIO_PCS_CTRL2_10GBR;
 367         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
 368
 369         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 370         reg &= ~MDIO_CTRL1_SPEEDSEL;
 371         reg |= MDIO_CTRL1_SPEED10G;
 372         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 373
 374         xgbe_phy_pcs_power_cycle(pdata);
 375
 376         /* Set SerDes to 10G speed */
 377         xgbe_phy_start_ratechange(pdata);
 378
 379         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
 380         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
 381         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
 382
 383         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
 384                            phy_data->cdr_rate[XGBE_SPEED_10000]);
 385         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
 386                            phy_data->tx_amp[XGBE_SPEED_10000]);
 387         XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
 388                            phy_data->blwc[XGBE_SPEED_10000]);
 389         XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
 390                            phy_data->pq_skew[XGBE_SPEED_10000]);
 391         XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
 392                            phy_data->dfe_tap_cfg[XGBE_SPEED_10000]);
 393         XRXTX_IOWRITE(pdata, RXTX_REG22,
 394                       phy_data->dfe_tap_ena[XGBE_SPEED_10000]);
 395
 396         xgbe_phy_complete_ratechange(pdata);
 397
 398         netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
 399 }
 400
 401 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
 402 {
 403         struct xgbe_phy_data *phy_data = pdata->phy_data;
 404         unsigned int reg;
 405
 406         /* Set PCS to KX/1G speed */
 407         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
 408         reg &= ~MDIO_PCS_CTRL2_TYPE;
 409         reg |= MDIO_PCS_CTRL2_10GBX;
 410         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
 411
 412         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 413         reg &= ~MDIO_CTRL1_SPEEDSEL;
 414         reg |= MDIO_CTRL1_SPEED1G;
 415         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 416
 417         xgbe_phy_pcs_power_cycle(pdata);
 418
 419         /* Set SerDes to 2.5G speed */
 420         xgbe_phy_start_ratechange(pdata);
 421
 422         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
 423         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
 424         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
 425
 426         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
 427                            phy_data->cdr_rate[XGBE_SPEED_2500]);
 428         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
 429                            phy_data->tx_amp[XGBE_SPEED_2500]);
 430         XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
 431                            phy_data->blwc[XGBE_SPEED_2500]);
 432         XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
 433                            phy_data->pq_skew[XGBE_SPEED_2500]);
 434         XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
 435                            phy_data->dfe_tap_cfg[XGBE_SPEED_2500]);
 436         XRXTX_IOWRITE(pdata, RXTX_REG22,
 437                       phy_data->dfe_tap_ena[XGBE_SPEED_2500]);
 438
 439         xgbe_phy_complete_ratechange(pdata);
 440
 441         netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
 442 }
 443
 444 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
 445 {
 446         struct xgbe_phy_data *phy_data = pdata->phy_data;
 447         unsigned int reg;
 448
 449         /* Set PCS to KX/1G speed */
 450         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
 451         reg &= ~MDIO_PCS_CTRL2_TYPE;
 452         reg |= MDIO_PCS_CTRL2_10GBX;
 453         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
 454
 455         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 456         reg &= ~MDIO_CTRL1_SPEEDSEL;
 457         reg |= MDIO_CTRL1_SPEED1G;
 458         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 459
 460         xgbe_phy_pcs_power_cycle(pdata);
 461
 462         /* Set SerDes to 1G speed */
 463         xgbe_phy_start_ratechange(pdata);
 464
 465         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
 466         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
 467         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
 468
 469         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
 470                            phy_data->cdr_rate[XGBE_SPEED_1000]);
 471         XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
 472                            phy_data->tx_amp[XGBE_SPEED_1000]);
 473         XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
 474                            phy_data->blwc[XGBE_SPEED_1000]);
 475         XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
 476                            phy_data->pq_skew[XGBE_SPEED_1000]);
 477         XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
 478                            phy_data->dfe_tap_cfg[XGBE_SPEED_1000]);
 479         XRXTX_IOWRITE(pdata, RXTX_REG22,
 480                       phy_data->dfe_tap_ena[XGBE_SPEED_1000]);
 481
 482         xgbe_phy_complete_ratechange(pdata);
 483
 484         netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
 485 }
 486
 487 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
 488 {
 489         struct xgbe_phy_data *phy_data = pdata->phy_data;
 490         enum xgbe_mode mode;
 491         unsigned int reg;
 492
 493         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
 494         reg &= MDIO_PCS_CTRL2_TYPE;
 495
 496         if (reg == MDIO_PCS_CTRL2_10GBR) {
 497                 mode = XGBE_MODE_KR;
 498         } else {
 499                 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
 500                         mode = XGBE_MODE_KX_2500;
 501                 else
 502                         mode = XGBE_MODE_KX_1000;
 503         }
 504
 505         return mode;
 506 }
 507
 508 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
 509 {
 510         struct xgbe_phy_data *phy_data = pdata->phy_data;
 511         enum xgbe_mode mode;
 512
 513         /* If we are in KR switch to KX, and vice-versa */
 514         if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) {
 515                 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
 516                         mode = XGBE_MODE_KX_2500;
 517                 else
 518                         mode = XGBE_MODE_KX_1000;
 519         } else {
 520                 mode = XGBE_MODE_KR;
 521         }
 522
 523         return mode;
 524 }
 525
 526 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
 527                                         int speed)
 528 {
 529         struct xgbe_phy_data *phy_data = pdata->phy_data;
 530
 531         switch (speed) {
 532         case SPEED_1000:
 533                 return (phy_data->speed_set == XGBE_SPEEDSET_1000_10000)
 534                         ? XGBE_MODE_KX_1000 : XGBE_MODE_UNKNOWN;
 535         case SPEED_2500:
 536                 return (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
 537                         ? XGBE_MODE_KX_2500 : XGBE_MODE_UNKNOWN;
 538         case SPEED_10000:
 539                 return XGBE_MODE_KR;
 540         default:
 541                 return XGBE_MODE_UNKNOWN;
 542         }
 543 }
 544
 545 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
 546 {
 547         switch (mode) {
 548         case XGBE_MODE_KX_1000:
 549                 xgbe_phy_kx_1000_mode(pdata);
 550                 break;
 551         case XGBE_MODE_KX_2500:
 552                 xgbe_phy_kx_2500_mode(pdata);
 553                 break;
 554         case XGBE_MODE_KR:
 555                 xgbe_phy_kr_mode(pdata);
 556                 break;
 557         default:
 558                 break;
 559         }
 560 }
 561
 562 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
 563                                 enum xgbe_mode mode, u32 advert)
 564 {
 565         if (pdata->phy.autoneg == AUTONEG_ENABLE) {
 566                 if (pdata->phy.advertising & advert)
 567                         return true;
 568         } else {
 569                 enum xgbe_mode cur_mode;
 570
 571                 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
 572                 if (cur_mode == mode)
 573                         return true;
 574         }
 575
 576         return false;
 577 }
 578
 579 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
 580 {
 581         switch (mode) {
 582         case XGBE_MODE_KX_1000:
 583                 return xgbe_phy_check_mode(pdata, mode,
 584                                            ADVERTISED_1000baseKX_Full);
 585         case XGBE_MODE_KX_2500:
 586                 return xgbe_phy_check_mode(pdata, mode,
 587                                            ADVERTISED_2500baseX_Full);
 588         case XGBE_MODE_KR:
 589                 return xgbe_phy_check_mode(pdata, mode,
 590                                            ADVERTISED_10000baseKR_Full);
 591         default:
 592                 return false;
 593         }
 594 }
 595
 596 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
 597 {
 598         struct xgbe_phy_data *phy_data = pdata->phy_data;
 599
 600         switch (speed) {
 601         case SPEED_1000:
 602                 if (phy_data->speed_set != XGBE_SPEEDSET_1000_10000)
 603                         return false;
 604                 return true;
 605         case SPEED_2500:
 606                 if (phy_data->speed_set != XGBE_SPEEDSET_2500_10000)
 607                         return false;
 608                 return true;
 609         case SPEED_10000:
 610                 return true;
 611         default:
 612                 return false;
 613         }
 614 }
 615
 616 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
 617 {
 618         unsigned int reg;
 619
 620         *an_restart = 0;
 621
 622         /* Link status is latched low, so read once to clear
 623          * and then read again to get current state
 624          */
 625         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
 626         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
 627
 628         return (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;
 629 }
 630
 631 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
 632 {
 633         /* Nothing uniquely required for stop */
 634 }
 635
 636 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
 637 {
 638         /* Nothing uniquely required for start */
 639         return 0;
 640 }
 641
 642 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
 643 {
 644         unsigned int reg, count;
 645
 646         /* Perform a software reset of the PCS */
 647         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 648         reg |= MDIO_CTRL1_RESET;
 649         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
 650
 651         count = 50;
 652         do {
 653                 msleep(20);
 654                 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
 655         } while ((reg & MDIO_CTRL1_RESET) && --count);
 656
 657         if (reg & MDIO_CTRL1_RESET)
 658                 return -ETIMEDOUT;
 659
 660         return 0;
 661 }
 662
 663 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
 664 {
 665         /* Nothing uniquely required for exit */
 666 }
 667
 668 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
 669 {
 670         struct xgbe_phy_data *phy_data;
 671         int ret;
 672
 673         phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
 674         if (!phy_data)
 675                 return -ENOMEM;
 676
 677         /* Retrieve the PHY speedset */
 678         ret = device_property_read_u32(pdata->phy_dev, XGBE_SPEEDSET_PROPERTY,
 679                                        &phy_data->speed_set);
 680         if (ret) {
 681                 dev_err(pdata->dev, "invalid %s property\n",
 682                         XGBE_SPEEDSET_PROPERTY);
 683                 return ret;
 684         }
 685
 686         switch (phy_data->speed_set) {
 687         case XGBE_SPEEDSET_1000_10000:
 688         case XGBE_SPEEDSET_2500_10000:
 689                 break;
 690         default:
 691                 dev_err(pdata->dev, "invalid %s property\n",
 692                         XGBE_SPEEDSET_PROPERTY);
 693                 return -EINVAL;
 694         }
 695
 696         /* Retrieve the PHY configuration properties */
 697         if (device_property_present(pdata->phy_dev, XGBE_BLWC_PROPERTY)) {
 698                 ret = device_property_read_u32_array(pdata->phy_dev,
 699                                                      XGBE_BLWC_PROPERTY,
 700                                                      phy_data->blwc,
 701                                                      XGBE_SPEEDS);
 702                 if (ret) {
 703                         dev_err(pdata->dev, "invalid %s property\n",
 704                                 XGBE_BLWC_PROPERTY);
 705                         return ret;
 706                 }
 707         } else {
 708                 memcpy(phy_data->blwc, xgbe_phy_blwc,
 709                        sizeof(phy_data->blwc));
 710         }
 711
 712         if (device_property_present(pdata->phy_dev, XGBE_CDR_RATE_PROPERTY)) {
 713                 ret = device_property_read_u32_array(pdata->phy_dev,
 714                                                      XGBE_CDR_RATE_PROPERTY,
 715                                                      phy_data->cdr_rate,
 716                                                      XGBE_SPEEDS);
 717                 if (ret) {
 718                         dev_err(pdata->dev, "invalid %s property\n",
 719                                 XGBE_CDR_RATE_PROPERTY);
 720                         return ret;
 721                 }
 722         } else {
 723                 memcpy(phy_data->cdr_rate, xgbe_phy_cdr_rate,
 724                        sizeof(phy_data->cdr_rate));
 725         }
 726
 727         if (device_property_present(pdata->phy_dev, XGBE_PQ_SKEW_PROPERTY)) {
 728                 ret = device_property_read_u32_array(pdata->phy_dev,
 729                                                      XGBE_PQ_SKEW_PROPERTY,
 730                                                      phy_data->pq_skew,
 731                                                      XGBE_SPEEDS);
 732                 if (ret) {
 733                         dev_err(pdata->dev, "invalid %s property\n",
 734                                 XGBE_PQ_SKEW_PROPERTY);
 735                         return ret;
 736                 }
 737         } else {
 738                 memcpy(phy_data->pq_skew, xgbe_phy_pq_skew,
 739                        sizeof(phy_data->pq_skew));
 740         }
 741
 742         if (device_property_present(pdata->phy_dev, XGBE_TX_AMP_PROPERTY)) {
 743                 ret = device_property_read_u32_array(pdata->phy_dev,
 744                                                      XGBE_TX_AMP_PROPERTY,
 745                                                      phy_data->tx_amp,
 746                                                      XGBE_SPEEDS);
 747                 if (ret) {
 748                         dev_err(pdata->dev, "invalid %s property\n",
 749                                 XGBE_TX_AMP_PROPERTY);
 750                         return ret;
 751                 }
 752         } else {
 753                 memcpy(phy_data->tx_amp, xgbe_phy_tx_amp,
 754                        sizeof(phy_data->tx_amp));
 755         }
 756
 757         if (device_property_present(pdata->phy_dev, XGBE_DFE_CFG_PROPERTY)) {
 758                 ret = device_property_read_u32_array(pdata->phy_dev,
 759                                                      XGBE_DFE_CFG_PROPERTY,
 760                                                      phy_data->dfe_tap_cfg,
 761                                                      XGBE_SPEEDS);
 762                 if (ret) {
 763                         dev_err(pdata->dev, "invalid %s property\n",
 764                                 XGBE_DFE_CFG_PROPERTY);
 765                         return ret;
 766                 }
 767         } else {
 768                 memcpy(phy_data->dfe_tap_cfg, xgbe_phy_dfe_tap_cfg,
 769                        sizeof(phy_data->dfe_tap_cfg));
 770         }
 771
 772         if (device_property_present(pdata->phy_dev, XGBE_DFE_ENA_PROPERTY)) {
 773                 ret = device_property_read_u32_array(pdata->phy_dev,
 774                                                      XGBE_DFE_ENA_PROPERTY,
 775                                                      phy_data->dfe_tap_ena,
 776                                                      XGBE_SPEEDS);
 777                 if (ret) {
 778                         dev_err(pdata->dev, "invalid %s property\n",
 779                                 XGBE_DFE_ENA_PROPERTY);
 780                         return ret;
 781                 }
 782         } else {
 783                 memcpy(phy_data->dfe_tap_ena, xgbe_phy_dfe_tap_ena,
 784                        sizeof(phy_data->dfe_tap_ena));
 785         }
 786
 787         /* Initialize supported features */
 788         pdata->phy.supported = SUPPORTED_Autoneg;
 789         pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
 790         pdata->phy.supported |= SUPPORTED_Backplane;
 791         pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
 792         switch (phy_data->speed_set) {
 793         case XGBE_SPEEDSET_1000_10000:
 794                 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
 795                 break;
 796         case XGBE_SPEEDSET_2500_10000:
 797                 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
 798                 break;
 799         }
 800
 801         if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
 802                 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
 803
 804         pdata->phy_data = phy_data;
 805
 806         return 0;
 807 }
 808
 809 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *phy_if)
 810 {
 811         struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
 812
 813         phy_impl->init                  = xgbe_phy_init;
 814         phy_impl->exit                  = xgbe_phy_exit;
 815
 816         phy_impl->reset                 = xgbe_phy_reset;
 817         phy_impl->start                 = xgbe_phy_start;
 818         phy_impl->stop                  = xgbe_phy_stop;
 819
 820         phy_impl->link_status           = xgbe_phy_link_status;
 821
 822         phy_impl->valid_speed           = xgbe_phy_valid_speed;
 823
 824         phy_impl->use_mode              = xgbe_phy_use_mode;
 825         phy_impl->set_mode              = xgbe_phy_set_mode;
 826         phy_impl->get_mode              = xgbe_phy_get_mode;
 827         phy_impl->switch_mode           = xgbe_phy_switch_mode;
 828         phy_impl->cur_mode              = xgbe_phy_cur_mode;
 829
 830         phy_impl->an_mode               = xgbe_phy_an_mode;
 831
 832         phy_impl->an_config             = xgbe_phy_an_config;
 833
 834         phy_impl->an_outcome            = xgbe_phy_an_outcome;
 835
 836         phy_impl->kr_training_pre       = xgbe_phy_kr_training_pre;
 837         phy_impl->kr_training_post      = xgbe_phy_kr_training_post;
 838 }