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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-phy-v2.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122
123 #include "xgbe.h"
124 #include "xgbe-common.h"
125
126 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
130
131 #define XGBE_MUTEX_RELEASE 0x80000000
132
133 #define XGBE_SFP_DIRECT 7
134
135 /* I2C target addresses */
136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
138 #define XGBE_SFP_PHY_ADDRESS 0x56
139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
140
141 /* SFP sideband signal indicators */
142 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
145 #define XGBE_GPIO_NO_RX_LOS BIT(3)
146
147 /* Rate-change complete wait/retry count */
148 #define XGBE_RATECHANGE_COUNT 500
149
150 enum xgbe_port_mode {
151 XGBE_PORT_MODE_RSVD = 0,
152 XGBE_PORT_MODE_BACKPLANE,
153 XGBE_PORT_MODE_BACKPLANE_2500,
154 XGBE_PORT_MODE_1000BASE_T,
155 XGBE_PORT_MODE_1000BASE_X,
156 XGBE_PORT_MODE_NBASE_T,
157 XGBE_PORT_MODE_10GBASE_T,
158 XGBE_PORT_MODE_10GBASE_R,
159 XGBE_PORT_MODE_SFP,
160 XGBE_PORT_MODE_MAX,
161 };
162
163 enum xgbe_conn_type {
164 XGBE_CONN_TYPE_NONE = 0,
165 XGBE_CONN_TYPE_SFP,
166 XGBE_CONN_TYPE_MDIO,
167 XGBE_CONN_TYPE_BACKPLANE,
168 XGBE_CONN_TYPE_MAX,
169 };
170
171 /* SFP/SFP+ related definitions */
172 enum xgbe_sfp_comm {
173 XGBE_SFP_COMM_DIRECT = 0,
174 XGBE_SFP_COMM_PCA9545,
175 };
176
177 enum xgbe_sfp_cable {
178 XGBE_SFP_CABLE_UNKNOWN = 0,
179 XGBE_SFP_CABLE_ACTIVE,
180 XGBE_SFP_CABLE_PASSIVE,
181 };
182
183 enum xgbe_sfp_base {
184 XGBE_SFP_BASE_UNKNOWN = 0,
185 XGBE_SFP_BASE_1000_T,
186 XGBE_SFP_BASE_1000_SX,
187 XGBE_SFP_BASE_1000_LX,
188 XGBE_SFP_BASE_1000_CX,
189 XGBE_SFP_BASE_10000_SR,
190 XGBE_SFP_BASE_10000_LR,
191 XGBE_SFP_BASE_10000_LRM,
192 XGBE_SFP_BASE_10000_ER,
193 XGBE_SFP_BASE_10000_CR,
194 };
195
196 enum xgbe_sfp_speed {
197 XGBE_SFP_SPEED_UNKNOWN = 0,
198 XGBE_SFP_SPEED_100_1000,
199 XGBE_SFP_SPEED_1000,
200 XGBE_SFP_SPEED_10000,
201 };
202
203 /* SFP Serial ID Base ID values relative to an offset of 0 */
204 #define XGBE_SFP_BASE_ID 0
205 #define XGBE_SFP_ID_SFP 0x03
206
207 #define XGBE_SFP_BASE_EXT_ID 1
208 #define XGBE_SFP_EXT_ID_SFP 0x04
209
210 #define XGBE_SFP_BASE_10GBE_CC 3
211 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
212 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
213 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
214 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
215
216 #define XGBE_SFP_BASE_1GBE_CC 6
217 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
218 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
219 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
220 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
221
222 #define XGBE_SFP_BASE_CABLE 8
223 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
224 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
225
226 #define XGBE_SFP_BASE_BR 12
227 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
228 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
229 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
230 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
231
232 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
233
234 #define XGBE_SFP_BASE_VENDOR_NAME 20
235 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
236 #define XGBE_SFP_BASE_VENDOR_PN 40
237 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
238 #define XGBE_SFP_BASE_VENDOR_REV 56
239 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
240
241 #define XGBE_SFP_BASE_CC 63
242
243 /* SFP Serial ID Extended ID values relative to an offset of 64 */
244 #define XGBE_SFP_BASE_VENDOR_SN 4
245 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
246
247 #define XGBE_SFP_EXTD_DIAG 28
248 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
249
250 #define XGBE_SFP_EXTD_SFF_8472 30
251
252 #define XGBE_SFP_EXTD_CC 31
253
254 struct xgbe_sfp_eeprom {
255 u8 base[64];
256 u8 extd[32];
257 u8 vendor[32];
258 };
259
260 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
261 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
262
263 struct xgbe_sfp_ascii {
264 union {
265 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
266 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
267 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
268 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
269 } u;
270 };
271
272 /* MDIO PHY reset types */
273 enum xgbe_mdio_reset {
274 XGBE_MDIO_RESET_NONE = 0,
275 XGBE_MDIO_RESET_I2C_GPIO,
276 XGBE_MDIO_RESET_INT_GPIO,
277 XGBE_MDIO_RESET_MAX,
278 };
279
280 /* Re-driver related definitions */
281 enum xgbe_phy_redrv_if {
282 XGBE_PHY_REDRV_IF_MDIO = 0,
283 XGBE_PHY_REDRV_IF_I2C,
284 XGBE_PHY_REDRV_IF_MAX,
285 };
286
287 enum xgbe_phy_redrv_model {
288 XGBE_PHY_REDRV_MODEL_4223 = 0,
289 XGBE_PHY_REDRV_MODEL_4227,
290 XGBE_PHY_REDRV_MODEL_MAX,
291 };
292
293 enum xgbe_phy_redrv_mode {
294 XGBE_PHY_REDRV_MODE_CX = 5,
295 XGBE_PHY_REDRV_MODE_SR = 9,
296 };
297
298 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
299
300 /* PHY related configuration information */
301 struct xgbe_phy_data {
302 enum xgbe_port_mode port_mode;
303
304 unsigned int port_id;
305
306 unsigned int port_speeds;
307
308 enum xgbe_conn_type conn_type;
309
310 enum xgbe_mode cur_mode;
311 enum xgbe_mode start_mode;
312
313 unsigned int rrc_count;
314
315 unsigned int mdio_addr;
316
317 unsigned int comm_owned;
318
319 /* SFP Support */
320 enum xgbe_sfp_comm sfp_comm;
321 unsigned int sfp_mux_address;
322 unsigned int sfp_mux_channel;
323
324 unsigned int sfp_gpio_address;
325 unsigned int sfp_gpio_mask;
326 unsigned int sfp_gpio_rx_los;
327 unsigned int sfp_gpio_tx_fault;
328 unsigned int sfp_gpio_mod_absent;
329 unsigned int sfp_gpio_rate_select;
330
331 unsigned int sfp_rx_los;
332 unsigned int sfp_tx_fault;
333 unsigned int sfp_mod_absent;
334 unsigned int sfp_diags;
335 unsigned int sfp_changed;
336 unsigned int sfp_phy_avail;
337 unsigned int sfp_cable_len;
338 enum xgbe_sfp_base sfp_base;
339 enum xgbe_sfp_cable sfp_cable;
340 enum xgbe_sfp_speed sfp_speed;
341 struct xgbe_sfp_eeprom sfp_eeprom;
342
343 /* External PHY support */
344 enum xgbe_mdio_mode phydev_mode;
345 struct mii_bus *mii;
346 struct phy_device *phydev;
347 enum xgbe_mdio_reset mdio_reset;
348 unsigned int mdio_reset_addr;
349 unsigned int mdio_reset_gpio;
350
351 /* Re-driver support */
352 unsigned int redrv;
353 unsigned int redrv_if;
354 unsigned int redrv_addr;
355 unsigned int redrv_lane;
356 unsigned int redrv_model;
357 };
358
359 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
360 static DEFINE_MUTEX(xgbe_phy_comm_lock);
361
362 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
363
364 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
365 struct xgbe_i2c_op *i2c_op)
366 {
367 struct xgbe_phy_data *phy_data = pdata->phy_data;
368
369 /* Be sure we own the bus */
370 if (WARN_ON(!phy_data->comm_owned))
371 return -EIO;
372
373 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
374 }
375
376 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
377 unsigned int val)
378 {
379 struct xgbe_phy_data *phy_data = pdata->phy_data;
380 struct xgbe_i2c_op i2c_op;
381 __be16 *redrv_val;
382 u8 redrv_data[5], csum;
383 unsigned int i, retry;
384 int ret;
385
386 /* High byte of register contains read/write indicator */
387 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
388 redrv_data[1] = reg & 0xff;
389 redrv_val = (__be16 *)&redrv_data[2];
390 *redrv_val = cpu_to_be16(val);
391
392 /* Calculate 1 byte checksum */
393 csum = 0;
394 for (i = 0; i < 4; i++) {
395 csum += redrv_data[i];
396 if (redrv_data[i] > csum)
397 csum++;
398 }
399 redrv_data[4] = ~csum;
400
401 retry = 1;
402 again1:
403 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
404 i2c_op.target = phy_data->redrv_addr;
405 i2c_op.len = sizeof(redrv_data);
406 i2c_op.buf = redrv_data;
407 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
408 if (ret) {
409 if ((ret == -EAGAIN) && retry--)
410 goto again1;
411
412 return ret;
413 }
414
415 retry = 1;
416 again2:
417 i2c_op.cmd = XGBE_I2C_CMD_READ;
418 i2c_op.target = phy_data->redrv_addr;
419 i2c_op.len = 1;
420 i2c_op.buf = redrv_data;
421 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
422 if (ret) {
423 if ((ret == -EAGAIN) && retry--)
424 goto again2;
425
426 return ret;
427 }
428
429 if (redrv_data[0] != 0xff) {
430 netif_dbg(pdata, drv, pdata->netdev,
431 "Redriver write checksum error\n");
432 ret = -EIO;
433 }
434
435 return ret;
436 }
437
438 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
439 void *val, unsigned int val_len)
440 {
441 struct xgbe_i2c_op i2c_op;
442 int retry, ret;
443
444 retry = 1;
445 again:
446 /* Write the specfied register */
447 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
448 i2c_op.target = target;
449 i2c_op.len = val_len;
450 i2c_op.buf = val;
451 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
452 if ((ret == -EAGAIN) && retry--)
453 goto again;
454
455 return ret;
456 }
457
458 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
459 void *reg, unsigned int reg_len,
460 void *val, unsigned int val_len)
461 {
462 struct xgbe_i2c_op i2c_op;
463 int retry, ret;
464
465 retry = 1;
466 again1:
467 /* Set the specified register to read */
468 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
469 i2c_op.target = target;
470 i2c_op.len = reg_len;
471 i2c_op.buf = reg;
472 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
473 if (ret) {
474 if ((ret == -EAGAIN) && retry--)
475 goto again1;
476
477 return ret;
478 }
479
480 retry = 1;
481 again2:
482 /* Read the specfied register */
483 i2c_op.cmd = XGBE_I2C_CMD_READ;
484 i2c_op.target = target;
485 i2c_op.len = val_len;
486 i2c_op.buf = val;
487 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
488 if ((ret == -EAGAIN) && retry--)
489 goto again2;
490
491 return ret;
492 }
493
494 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
495 {
496 struct xgbe_phy_data *phy_data = pdata->phy_data;
497 struct xgbe_i2c_op i2c_op;
498 u8 mux_channel;
499
500 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
501 return 0;
502
503 /* Select no mux channels */
504 mux_channel = 0;
505 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
506 i2c_op.target = phy_data->sfp_mux_address;
507 i2c_op.len = sizeof(mux_channel);
508 i2c_op.buf = &mux_channel;
509
510 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
511 }
512
513 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
514 {
515 struct xgbe_phy_data *phy_data = pdata->phy_data;
516 struct xgbe_i2c_op i2c_op;
517 u8 mux_channel;
518
519 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
520 return 0;
521
522 /* Select desired mux channel */
523 mux_channel = 1 << phy_data->sfp_mux_channel;
524 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
525 i2c_op.target = phy_data->sfp_mux_address;
526 i2c_op.len = sizeof(mux_channel);
527 i2c_op.buf = &mux_channel;
528
529 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
530 }
531
532 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
533 {
534 struct xgbe_phy_data *phy_data = pdata->phy_data;
535
536 phy_data->comm_owned = 0;
537
538 mutex_unlock(&xgbe_phy_comm_lock);
539 }
540
541 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
542 {
543 struct xgbe_phy_data *phy_data = pdata->phy_data;
544 unsigned long timeout;
545 unsigned int mutex_id;
546
547 if (phy_data->comm_owned)
548 return 0;
549
550 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
551 * the driver needs to take the software mutex and then the hardware
552 * mutexes before being able to use the busses.
553 */
554 mutex_lock(&xgbe_phy_comm_lock);
555
556 /* Clear the mutexes */
557 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
558 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
559
560 /* Mutex formats are the same for I2C and MDIO/GPIO */
561 mutex_id = 0;
562 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
563 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
564
565 timeout = jiffies + (5 * HZ);
566 while (time_before(jiffies, timeout)) {
567 /* Must be all zeroes in order to obtain the mutex */
568 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
569 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
570 usleep_range(100, 200);
571 continue;
572 }
573
574 /* Obtain the mutex */
575 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
577
578 phy_data->comm_owned = 1;
579 return 0;
580 }
581
582 mutex_unlock(&xgbe_phy_comm_lock);
583
584 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
585
586 return -ETIMEDOUT;
587 }
588
589 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
590 int reg, u16 val)
591 {
592 struct xgbe_phy_data *phy_data = pdata->phy_data;
593
594 if (reg & MII_ADDR_C45) {
595 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
596 return -ENOTSUPP;
597 } else {
598 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
599 return -ENOTSUPP;
600 }
601
602 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
603 }
604
605 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
606 {
607 __be16 *mii_val;
608 u8 mii_data[3];
609 int ret;
610
611 ret = xgbe_phy_sfp_get_mux(pdata);
612 if (ret)
613 return ret;
614
615 mii_data[0] = reg & 0xff;
616 mii_val = (__be16 *)&mii_data[1];
617 *mii_val = cpu_to_be16(val);
618
619 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
620 mii_data, sizeof(mii_data));
621
622 xgbe_phy_sfp_put_mux(pdata);
623
624 return ret;
625 }
626
627 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
628 {
629 struct xgbe_prv_data *pdata = mii->priv;
630 struct xgbe_phy_data *phy_data = pdata->phy_data;
631 int ret;
632
633 ret = xgbe_phy_get_comm_ownership(pdata);
634 if (ret)
635 return ret;
636
637 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
638 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
639 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
640 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
641 else
642 ret = -ENOTSUPP;
643
644 xgbe_phy_put_comm_ownership(pdata);
645
646 return ret;
647 }
648
649 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
650 int reg)
651 {
652 struct xgbe_phy_data *phy_data = pdata->phy_data;
653
654 if (reg & MII_ADDR_C45) {
655 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
656 return -ENOTSUPP;
657 } else {
658 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
659 return -ENOTSUPP;
660 }
661
662 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
663 }
664
665 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
666 {
667 __be16 mii_val;
668 u8 mii_reg;
669 int ret;
670
671 ret = xgbe_phy_sfp_get_mux(pdata);
672 if (ret)
673 return ret;
674
675 mii_reg = reg;
676 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
677 &mii_reg, sizeof(mii_reg),
678 &mii_val, sizeof(mii_val));
679 if (!ret)
680 ret = be16_to_cpu(mii_val);
681
682 xgbe_phy_sfp_put_mux(pdata);
683
684 return ret;
685 }
686
687 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
688 {
689 struct xgbe_prv_data *pdata = mii->priv;
690 struct xgbe_phy_data *phy_data = pdata->phy_data;
691 int ret;
692
693 ret = xgbe_phy_get_comm_ownership(pdata);
694 if (ret)
695 return ret;
696
697 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
698 ret = xgbe_phy_i2c_mii_read(pdata, reg);
699 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
700 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
701 else
702 ret = -ENOTSUPP;
703
704 xgbe_phy_put_comm_ownership(pdata);
705
706 return ret;
707 }
708
709 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
710 {
711 struct xgbe_phy_data *phy_data = pdata->phy_data;
712
713 if (phy_data->sfp_mod_absent) {
714 pdata->phy.speed = SPEED_UNKNOWN;
715 pdata->phy.duplex = DUPLEX_UNKNOWN;
716 pdata->phy.autoneg = AUTONEG_ENABLE;
717 pdata->phy.advertising = pdata->phy.supported;
718 }
719
720 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
721 pdata->phy.advertising &= ~ADVERTISED_TP;
722 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
723 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
724 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
725 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
726 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
727
728 switch (phy_data->sfp_base) {
729 case XGBE_SFP_BASE_1000_T:
730 case XGBE_SFP_BASE_1000_SX:
731 case XGBE_SFP_BASE_1000_LX:
732 case XGBE_SFP_BASE_1000_CX:
733 pdata->phy.speed = SPEED_UNKNOWN;
734 pdata->phy.duplex = DUPLEX_UNKNOWN;
735 pdata->phy.autoneg = AUTONEG_ENABLE;
736 pdata->phy.advertising |= ADVERTISED_Autoneg;
737 break;
738 case XGBE_SFP_BASE_10000_SR:
739 case XGBE_SFP_BASE_10000_LR:
740 case XGBE_SFP_BASE_10000_LRM:
741 case XGBE_SFP_BASE_10000_ER:
742 case XGBE_SFP_BASE_10000_CR:
743 default:
744 pdata->phy.speed = SPEED_10000;
745 pdata->phy.duplex = DUPLEX_FULL;
746 pdata->phy.autoneg = AUTONEG_DISABLE;
747 break;
748 }
749
750 switch (phy_data->sfp_base) {
751 case XGBE_SFP_BASE_1000_T:
752 case XGBE_SFP_BASE_1000_CX:
753 case XGBE_SFP_BASE_10000_CR:
754 pdata->phy.advertising |= ADVERTISED_TP;
755 break;
756 default:
757 pdata->phy.advertising |= ADVERTISED_FIBRE;
758 }
759
760 switch (phy_data->sfp_speed) {
761 case XGBE_SFP_SPEED_100_1000:
762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
763 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
764 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
765 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
766 break;
767 case XGBE_SFP_SPEED_1000:
768 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
769 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
770 break;
771 case XGBE_SFP_SPEED_10000:
772 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
773 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
774 break;
775 default:
776 /* Choose the fastest supported speed */
777 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
778 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
779 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
780 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
781 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
782 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
783 }
784 }
785
786 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
787 enum xgbe_sfp_speed sfp_speed)
788 {
789 u8 *sfp_base, min, max;
790
791 sfp_base = sfp_eeprom->base;
792
793 switch (sfp_speed) {
794 case XGBE_SFP_SPEED_1000:
795 min = XGBE_SFP_BASE_BR_1GBE_MIN;
796 max = XGBE_SFP_BASE_BR_1GBE_MAX;
797 break;
798 case XGBE_SFP_SPEED_10000:
799 min = XGBE_SFP_BASE_BR_10GBE_MIN;
800 max = XGBE_SFP_BASE_BR_10GBE_MAX;
801 break;
802 default:
803 return false;
804 }
805
806 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
807 (sfp_base[XGBE_SFP_BASE_BR] <= max));
808 }
809
810 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
811 {
812 struct xgbe_phy_data *phy_data = pdata->phy_data;
813
814 if (phy_data->phydev) {
815 phy_detach(phy_data->phydev);
816 phy_device_remove(phy_data->phydev);
817 phy_device_free(phy_data->phydev);
818 phy_data->phydev = NULL;
819 }
820 }
821
822 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
823 {
824 struct xgbe_phy_data *phy_data = pdata->phy_data;
825 unsigned int phy_id = phy_data->phydev->phy_id;
826
827 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
828 return false;
829
830 /* Enable Base-T AN */
831 phy_write(phy_data->phydev, 0x16, 0x0001);
832 phy_write(phy_data->phydev, 0x00, 0x9140);
833 phy_write(phy_data->phydev, 0x16, 0x0000);
834
835 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
836 phy_write(phy_data->phydev, 0x1b, 0x9084);
837 phy_write(phy_data->phydev, 0x09, 0x0e00);
838 phy_write(phy_data->phydev, 0x00, 0x8140);
839 phy_write(phy_data->phydev, 0x04, 0x0d01);
840 phy_write(phy_data->phydev, 0x00, 0x9140);
841
842 phy_data->phydev->supported = PHY_GBIT_FEATURES;
843 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
844 phy_data->phydev->advertising = phy_data->phydev->supported;
845
846 netif_dbg(pdata, drv, pdata->netdev,
847 "Finisar PHY quirk in place\n");
848
849 return true;
850 }
851
852 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
853 {
854 if (xgbe_phy_finisar_phy_quirks(pdata))
855 return;
856 }
857
858 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
859 {
860 struct xgbe_phy_data *phy_data = pdata->phy_data;
861 struct phy_device *phydev;
862 int ret;
863
864 /* If we already have a PHY, just return */
865 if (phy_data->phydev)
866 return 0;
867
868 /* Check for the use of an external PHY */
869 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
870 return 0;
871
872 /* For SFP, only use an external PHY if available */
873 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
874 !phy_data->sfp_phy_avail)
875 return 0;
876
877 /* Create and connect to the PHY device */
878 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
879 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
880 if (IS_ERR(phydev)) {
881 netdev_err(pdata->netdev, "get_phy_device failed\n");
882 return -ENODEV;
883 }
884 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
885 phydev->phy_id);
886
887 /*TODO: If c45, add request_module based on one of the MMD ids? */
888
889 ret = phy_device_register(phydev);
890 if (ret) {
891 netdev_err(pdata->netdev, "phy_device_register failed\n");
892 phy_device_free(phydev);
893 return ret;
894 }
895
896 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
897 PHY_INTERFACE_MODE_SGMII);
898 if (ret) {
899 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
900 phy_device_remove(phydev);
901 phy_device_free(phydev);
902 return ret;
903 }
904 phy_data->phydev = phydev;
905
906 xgbe_phy_external_phy_quirks(pdata);
907 phydev->advertising &= pdata->phy.advertising;
908
909 phy_start_aneg(phy_data->phydev);
910
911 return 0;
912 }
913
914 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
915 {
916 struct xgbe_phy_data *phy_data = pdata->phy_data;
917 int ret;
918
919 if (!phy_data->sfp_changed)
920 return;
921
922 phy_data->sfp_phy_avail = 0;
923
924 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
925 return;
926
927 /* Check access to the PHY by reading CTRL1 */
928 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
929 if (ret < 0)
930 return;
931
932 /* Successfully accessed the PHY */
933 phy_data->sfp_phy_avail = 1;
934 }
935
936 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
937 {
938 struct xgbe_phy_data *phy_data = pdata->phy_data;
939 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
940
941 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
942 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
943 return false;
944
945 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
946 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
947 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
948 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
949 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
950 if (phy_data->sfp_changed)
951 netif_dbg(pdata, drv, pdata->netdev,
952 "Bel-Fuse SFP quirk in place\n");
953 return true;
954 }
955
956 return false;
957 }
958
959 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
960 {
961 if (xgbe_phy_belfuse_parse_quirks(pdata))
962 return true;
963
964 return false;
965 }
966
967 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
968 {
969 struct xgbe_phy_data *phy_data = pdata->phy_data;
970 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
971 u8 *sfp_base;
972
973 sfp_base = sfp_eeprom->base;
974
975 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
976 return;
977
978 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
979 return;
980
981 if (xgbe_phy_sfp_parse_quirks(pdata))
982 return;
983
984 /* Assume ACTIVE cable unless told it is PASSIVE */
985 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
986 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
987 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
988 } else {
989 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
990 }
991
992 /* Determine the type of SFP */
993 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
994 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
995 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
996 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
997 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
998 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
999 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1000 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1001 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1002 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1003 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1004 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1005 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1006 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1007 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1008 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1009 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1010 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1011 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1012
1013 switch (phy_data->sfp_base) {
1014 case XGBE_SFP_BASE_1000_T:
1015 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1016 break;
1017 case XGBE_SFP_BASE_1000_SX:
1018 case XGBE_SFP_BASE_1000_LX:
1019 case XGBE_SFP_BASE_1000_CX:
1020 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1021 break;
1022 case XGBE_SFP_BASE_10000_SR:
1023 case XGBE_SFP_BASE_10000_LR:
1024 case XGBE_SFP_BASE_10000_LRM:
1025 case XGBE_SFP_BASE_10000_ER:
1026 case XGBE_SFP_BASE_10000_CR:
1027 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1028 break;
1029 default:
1030 break;
1031 }
1032 }
1033
1034 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1035 struct xgbe_sfp_eeprom *sfp_eeprom)
1036 {
1037 struct xgbe_sfp_ascii sfp_ascii;
1038 char *sfp_data = (char *)&sfp_ascii;
1039
1040 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1041 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1042 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1043 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1044 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1045 sfp_data);
1046
1047 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1048 XGBE_SFP_BASE_VENDOR_PN_LEN);
1049 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1050 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1051 sfp_data);
1052
1053 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1054 XGBE_SFP_BASE_VENDOR_REV_LEN);
1055 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1056 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1057 sfp_data);
1058
1059 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1060 XGBE_SFP_BASE_VENDOR_SN_LEN);
1061 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1062 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1063 sfp_data);
1064 }
1065
1066 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1067 {
1068 u8 cc;
1069
1070 for (cc = 0; len; buf++, len--)
1071 cc += *buf;
1072
1073 return (cc == cc_in) ? true : false;
1074 }
1075
1076 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1077 {
1078 struct xgbe_phy_data *phy_data = pdata->phy_data;
1079 struct xgbe_sfp_eeprom sfp_eeprom;
1080 u8 eeprom_addr;
1081 int ret;
1082
1083 ret = xgbe_phy_sfp_get_mux(pdata);
1084 if (ret) {
1085 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1086 return ret;
1087 }
1088
1089 /* Read the SFP serial ID eeprom */
1090 eeprom_addr = 0;
1091 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1092 &eeprom_addr, sizeof(eeprom_addr),
1093 &sfp_eeprom, sizeof(sfp_eeprom));
1094 if (ret) {
1095 netdev_err(pdata->netdev, "I2C error reading SFP EEPROM\n");
1096 goto put;
1097 }
1098
1099 /* Validate the contents read */
1100 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1101 sfp_eeprom.base,
1102 sizeof(sfp_eeprom.base) - 1)) {
1103 ret = -EINVAL;
1104 goto put;
1105 }
1106
1107 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1108 sfp_eeprom.extd,
1109 sizeof(sfp_eeprom.extd) - 1)) {
1110 ret = -EINVAL;
1111 goto put;
1112 }
1113
1114 /* Check for an added or changed SFP */
1115 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1116 phy_data->sfp_changed = 1;
1117
1118 if (netif_msg_drv(pdata))
1119 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1120
1121 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1122
1123 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
1124 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
1125
1126 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
1127 phy_data->sfp_diags = 1;
1128 }
1129
1130 xgbe_phy_free_phy_device(pdata);
1131 } else {
1132 phy_data->sfp_changed = 0;
1133 }
1134
1135 put:
1136 xgbe_phy_sfp_put_mux(pdata);
1137
1138 return ret;
1139 }
1140
1141 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1142 {
1143 struct xgbe_phy_data *phy_data = pdata->phy_data;
1144 unsigned int gpio_input;
1145 u8 gpio_reg, gpio_ports[2];
1146 int ret;
1147
1148 /* Read the input port registers */
1149 gpio_reg = 0;
1150 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1151 &gpio_reg, sizeof(gpio_reg),
1152 gpio_ports, sizeof(gpio_ports));
1153 if (ret) {
1154 netdev_err(pdata->netdev, "I2C error reading SFP GPIOs\n");
1155 return;
1156 }
1157
1158 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
1159
1160 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) {
1161 /* No GPIO, just assume the module is present for now */
1162 phy_data->sfp_mod_absent = 0;
1163 } else {
1164 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
1165 phy_data->sfp_mod_absent = 0;
1166 }
1167
1168 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) &&
1169 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
1170 phy_data->sfp_rx_los = 1;
1171
1172 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) &&
1173 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
1174 phy_data->sfp_tx_fault = 1;
1175 }
1176
1177 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1178 {
1179 struct xgbe_phy_data *phy_data = pdata->phy_data;
1180
1181 xgbe_phy_free_phy_device(pdata);
1182
1183 phy_data->sfp_mod_absent = 1;
1184 phy_data->sfp_phy_avail = 0;
1185 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1186 }
1187
1188 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1189 {
1190 phy_data->sfp_rx_los = 0;
1191 phy_data->sfp_tx_fault = 0;
1192 phy_data->sfp_mod_absent = 1;
1193 phy_data->sfp_diags = 0;
1194 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1195 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1196 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1197 }
1198
1199 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1200 {
1201 struct xgbe_phy_data *phy_data = pdata->phy_data;
1202 int ret;
1203
1204 /* Reset the SFP signals and info */
1205 xgbe_phy_sfp_reset(phy_data);
1206
1207 ret = xgbe_phy_get_comm_ownership(pdata);
1208 if (ret)
1209 return;
1210
1211 /* Read the SFP signals and check for module presence */
1212 xgbe_phy_sfp_signals(pdata);
1213 if (phy_data->sfp_mod_absent) {
1214 xgbe_phy_sfp_mod_absent(pdata);
1215 goto put;
1216 }
1217
1218 ret = xgbe_phy_sfp_read_eeprom(pdata);
1219 if (ret) {
1220 /* Treat any error as if there isn't an SFP plugged in */
1221 xgbe_phy_sfp_reset(phy_data);
1222 xgbe_phy_sfp_mod_absent(pdata);
1223 goto put;
1224 }
1225
1226 xgbe_phy_sfp_parse_eeprom(pdata);
1227
1228 xgbe_phy_sfp_external_phy(pdata);
1229
1230 put:
1231 xgbe_phy_sfp_phy_settings(pdata);
1232
1233 xgbe_phy_put_comm_ownership(pdata);
1234 }
1235
1236 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1237 {
1238 struct xgbe_phy_data *phy_data = pdata->phy_data;
1239 u16 lcl_adv = 0, rmt_adv = 0;
1240 u8 fc;
1241
1242 pdata->phy.tx_pause = 0;
1243 pdata->phy.rx_pause = 0;
1244
1245 if (!phy_data->phydev)
1246 return;
1247
1248 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1249 lcl_adv |= ADVERTISE_PAUSE_CAP;
1250 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1251 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1252
1253 if (phy_data->phydev->pause) {
1254 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1255 rmt_adv |= LPA_PAUSE_CAP;
1256 }
1257 if (phy_data->phydev->asym_pause) {
1258 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1259 rmt_adv |= LPA_PAUSE_ASYM;
1260 }
1261
1262 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1263 if (fc & FLOW_CTRL_TX)
1264 pdata->phy.tx_pause = 1;
1265 if (fc & FLOW_CTRL_RX)
1266 pdata->phy.rx_pause = 1;
1267 }
1268
1269 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1270 {
1271 enum xgbe_mode mode;
1272
1273 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1274 pdata->phy.lp_advertising |= ADVERTISED_TP;
1275
1276 /* Use external PHY to determine flow control */
1277 if (pdata->phy.pause_autoneg)
1278 xgbe_phy_phydev_flowctrl(pdata);
1279
1280 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1281 case XGBE_SGMII_AN_LINK_SPEED_100:
1282 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1283 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
1284 mode = XGBE_MODE_SGMII_100;
1285 } else {
1286 /* Half-duplex not supported */
1287 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half;
1288 mode = XGBE_MODE_UNKNOWN;
1289 }
1290 break;
1291 case XGBE_SGMII_AN_LINK_SPEED_1000:
1292 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1293 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1294 mode = XGBE_MODE_SGMII_1000;
1295 } else {
1296 /* Half-duplex not supported */
1297 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
1298 mode = XGBE_MODE_UNKNOWN;
1299 }
1300 break;
1301 default:
1302 mode = XGBE_MODE_UNKNOWN;
1303 }
1304
1305 return mode;
1306 }
1307
1308 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1309 {
1310 enum xgbe_mode mode;
1311 unsigned int ad_reg, lp_reg;
1312
1313 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1314 pdata->phy.lp_advertising |= ADVERTISED_FIBRE;
1315
1316 /* Compare Advertisement and Link Partner register */
1317 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1318 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1319 if (lp_reg & 0x100)
1320 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1321 if (lp_reg & 0x80)
1322 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1323
1324 if (pdata->phy.pause_autoneg) {
1325 /* Set flow control based on auto-negotiation result */
1326 pdata->phy.tx_pause = 0;
1327 pdata->phy.rx_pause = 0;
1328
1329 if (ad_reg & lp_reg & 0x100) {
1330 pdata->phy.tx_pause = 1;
1331 pdata->phy.rx_pause = 1;
1332 } else if (ad_reg & lp_reg & 0x80) {
1333 if (ad_reg & 0x100)
1334 pdata->phy.rx_pause = 1;
1335 else if (lp_reg & 0x100)
1336 pdata->phy.tx_pause = 1;
1337 }
1338 }
1339
1340 if (lp_reg & 0x40)
1341 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
1342 if (lp_reg & 0x20)
1343 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1344
1345 /* Half duplex is not supported */
1346 ad_reg &= lp_reg;
1347 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1348
1349 return mode;
1350 }
1351
1352 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1353 {
1354 struct xgbe_phy_data *phy_data = pdata->phy_data;
1355 enum xgbe_mode mode;
1356 unsigned int ad_reg, lp_reg;
1357
1358 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1359 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
1360
1361 /* Use external PHY to determine flow control */
1362 if (pdata->phy.pause_autoneg)
1363 xgbe_phy_phydev_flowctrl(pdata);
1364
1365 /* Compare Advertisement and Link Partner register 2 */
1366 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1367 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1368 if (lp_reg & 0x80)
1369 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1370 if (lp_reg & 0x20)
1371 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1372
1373 ad_reg &= lp_reg;
1374 if (ad_reg & 0x80) {
1375 switch (phy_data->port_mode) {
1376 case XGBE_PORT_MODE_BACKPLANE:
1377 mode = XGBE_MODE_KR;
1378 break;
1379 default:
1380 mode = XGBE_MODE_SFI;
1381 break;
1382 }
1383 } else if (ad_reg & 0x20) {
1384 switch (phy_data->port_mode) {
1385 case XGBE_PORT_MODE_BACKPLANE:
1386 mode = XGBE_MODE_KX_1000;
1387 break;
1388 case XGBE_PORT_MODE_1000BASE_X:
1389 mode = XGBE_MODE_X;
1390 break;
1391 case XGBE_PORT_MODE_SFP:
1392 switch (phy_data->sfp_base) {
1393 case XGBE_SFP_BASE_1000_T:
1394 if (phy_data->phydev &&
1395 (phy_data->phydev->speed == SPEED_100))
1396 mode = XGBE_MODE_SGMII_100;
1397 else
1398 mode = XGBE_MODE_SGMII_1000;
1399 break;
1400 case XGBE_SFP_BASE_1000_SX:
1401 case XGBE_SFP_BASE_1000_LX:
1402 case XGBE_SFP_BASE_1000_CX:
1403 default:
1404 mode = XGBE_MODE_X;
1405 break;
1406 }
1407 break;
1408 default:
1409 if (phy_data->phydev &&
1410 (phy_data->phydev->speed == SPEED_100))
1411 mode = XGBE_MODE_SGMII_100;
1412 else
1413 mode = XGBE_MODE_SGMII_1000;
1414 break;
1415 }
1416 } else {
1417 mode = XGBE_MODE_UNKNOWN;
1418 }
1419
1420 /* Compare Advertisement and Link Partner register 3 */
1421 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1422 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1423 if (lp_reg & 0xc000)
1424 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1425
1426 return mode;
1427 }
1428
1429 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1430 {
1431 enum xgbe_mode mode;
1432 unsigned int ad_reg, lp_reg;
1433
1434 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1435 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
1436
1437 /* Compare Advertisement and Link Partner register 1 */
1438 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1439 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1440 if (lp_reg & 0x400)
1441 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1442 if (lp_reg & 0x800)
1443 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1444
1445 if (pdata->phy.pause_autoneg) {
1446 /* Set flow control based on auto-negotiation result */
1447 pdata->phy.tx_pause = 0;
1448 pdata->phy.rx_pause = 0;
1449
1450 if (ad_reg & lp_reg & 0x400) {
1451 pdata->phy.tx_pause = 1;
1452 pdata->phy.rx_pause = 1;
1453 } else if (ad_reg & lp_reg & 0x800) {
1454 if (ad_reg & 0x400)
1455 pdata->phy.rx_pause = 1;
1456 else if (lp_reg & 0x400)
1457 pdata->phy.tx_pause = 1;
1458 }
1459 }
1460
1461 /* Compare Advertisement and Link Partner register 2 */
1462 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1463 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1464 if (lp_reg & 0x80)
1465 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1466 if (lp_reg & 0x20)
1467 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1468
1469 ad_reg &= lp_reg;
1470 if (ad_reg & 0x80)
1471 mode = XGBE_MODE_KR;
1472 else if (ad_reg & 0x20)
1473 mode = XGBE_MODE_KX_1000;
1474 else
1475 mode = XGBE_MODE_UNKNOWN;
1476
1477 /* Compare Advertisement and Link Partner register 3 */
1478 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1479 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1480 if (lp_reg & 0xc000)
1481 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1482
1483 return mode;
1484 }
1485
1486 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1487 {
1488 switch (pdata->an_mode) {
1489 case XGBE_AN_MODE_CL73:
1490 return xgbe_phy_an73_outcome(pdata);
1491 case XGBE_AN_MODE_CL73_REDRV:
1492 return xgbe_phy_an73_redrv_outcome(pdata);
1493 case XGBE_AN_MODE_CL37:
1494 return xgbe_phy_an37_outcome(pdata);
1495 case XGBE_AN_MODE_CL37_SGMII:
1496 return xgbe_phy_an37_sgmii_outcome(pdata);
1497 default:
1498 return XGBE_MODE_UNKNOWN;
1499 }
1500 }
1501
1502 static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata)
1503 {
1504 struct xgbe_phy_data *phy_data = pdata->phy_data;
1505 unsigned int advertising;
1506
1507 /* Without a re-driver, just return current advertising */
1508 if (!phy_data->redrv)
1509 return pdata->phy.advertising;
1510
1511 /* With the KR re-driver we need to advertise a single speed */
1512 advertising = pdata->phy.advertising;
1513 advertising &= ~ADVERTISED_1000baseKX_Full;
1514 advertising &= ~ADVERTISED_10000baseKR_Full;
1515
1516 switch (phy_data->port_mode) {
1517 case XGBE_PORT_MODE_BACKPLANE:
1518 advertising |= ADVERTISED_10000baseKR_Full;
1519 break;
1520 case XGBE_PORT_MODE_BACKPLANE_2500:
1521 advertising |= ADVERTISED_1000baseKX_Full;
1522 break;
1523 case XGBE_PORT_MODE_1000BASE_T:
1524 case XGBE_PORT_MODE_1000BASE_X:
1525 case XGBE_PORT_MODE_NBASE_T:
1526 advertising |= ADVERTISED_1000baseKX_Full;
1527 break;
1528 case XGBE_PORT_MODE_10GBASE_T:
1529 if (phy_data->phydev &&
1530 (phy_data->phydev->speed == SPEED_10000))
1531 advertising |= ADVERTISED_10000baseKR_Full;
1532 else
1533 advertising |= ADVERTISED_1000baseKX_Full;
1534 break;
1535 case XGBE_PORT_MODE_10GBASE_R:
1536 advertising |= ADVERTISED_10000baseKR_Full;
1537 break;
1538 case XGBE_PORT_MODE_SFP:
1539 switch (phy_data->sfp_base) {
1540 case XGBE_SFP_BASE_1000_T:
1541 case XGBE_SFP_BASE_1000_SX:
1542 case XGBE_SFP_BASE_1000_LX:
1543 case XGBE_SFP_BASE_1000_CX:
1544 advertising |= ADVERTISED_1000baseKX_Full;
1545 break;
1546 default:
1547 advertising |= ADVERTISED_10000baseKR_Full;
1548 break;
1549 }
1550 break;
1551 default:
1552 advertising |= ADVERTISED_10000baseKR_Full;
1553 break;
1554 }
1555
1556 return advertising;
1557 }
1558
1559 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1560 {
1561 struct xgbe_phy_data *phy_data = pdata->phy_data;
1562 int ret;
1563
1564 ret = xgbe_phy_find_phy_device(pdata);
1565 if (ret)
1566 return ret;
1567
1568 if (!phy_data->phydev)
1569 return 0;
1570
1571 phy_data->phydev->autoneg = pdata->phy.autoneg;
1572 phy_data->phydev->advertising = phy_data->phydev->supported &
1573 pdata->phy.advertising;
1574
1575 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1576 phy_data->phydev->speed = pdata->phy.speed;
1577 phy_data->phydev->duplex = pdata->phy.duplex;
1578 }
1579
1580 ret = phy_start_aneg(phy_data->phydev);
1581
1582 return ret;
1583 }
1584
1585 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1586 {
1587 switch (phy_data->sfp_base) {
1588 case XGBE_SFP_BASE_1000_T:
1589 return XGBE_AN_MODE_CL37_SGMII;
1590 case XGBE_SFP_BASE_1000_SX:
1591 case XGBE_SFP_BASE_1000_LX:
1592 case XGBE_SFP_BASE_1000_CX:
1593 return XGBE_AN_MODE_CL37;
1594 default:
1595 return XGBE_AN_MODE_NONE;
1596 }
1597 }
1598
1599 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1600 {
1601 struct xgbe_phy_data *phy_data = pdata->phy_data;
1602
1603 /* A KR re-driver will always require CL73 AN */
1604 if (phy_data->redrv)
1605 return XGBE_AN_MODE_CL73_REDRV;
1606
1607 switch (phy_data->port_mode) {
1608 case XGBE_PORT_MODE_BACKPLANE:
1609 return XGBE_AN_MODE_CL73;
1610 case XGBE_PORT_MODE_BACKPLANE_2500:
1611 return XGBE_AN_MODE_NONE;
1612 case XGBE_PORT_MODE_1000BASE_T:
1613 return XGBE_AN_MODE_CL37_SGMII;
1614 case XGBE_PORT_MODE_1000BASE_X:
1615 return XGBE_AN_MODE_CL37;
1616 case XGBE_PORT_MODE_NBASE_T:
1617 return XGBE_AN_MODE_CL37_SGMII;
1618 case XGBE_PORT_MODE_10GBASE_T:
1619 return XGBE_AN_MODE_CL73;
1620 case XGBE_PORT_MODE_10GBASE_R:
1621 return XGBE_AN_MODE_NONE;
1622 case XGBE_PORT_MODE_SFP:
1623 return xgbe_phy_an_sfp_mode(phy_data);
1624 default:
1625 return XGBE_AN_MODE_NONE;
1626 }
1627 }
1628
1629 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1630 enum xgbe_phy_redrv_mode mode)
1631 {
1632 struct xgbe_phy_data *phy_data = pdata->phy_data;
1633 u16 redrv_reg, redrv_val;
1634
1635 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1636 redrv_val = (u16)mode;
1637
1638 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1639 redrv_reg, redrv_val);
1640 }
1641
1642 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1643 enum xgbe_phy_redrv_mode mode)
1644 {
1645 struct xgbe_phy_data *phy_data = pdata->phy_data;
1646 unsigned int redrv_reg;
1647 int ret;
1648
1649 /* Calculate the register to write */
1650 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1651
1652 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1653
1654 return ret;
1655 }
1656
1657 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1658 {
1659 struct xgbe_phy_data *phy_data = pdata->phy_data;
1660 enum xgbe_phy_redrv_mode mode;
1661 int ret;
1662
1663 if (!phy_data->redrv)
1664 return;
1665
1666 mode = XGBE_PHY_REDRV_MODE_CX;
1667 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1668 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1669 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1670 mode = XGBE_PHY_REDRV_MODE_SR;
1671
1672 ret = xgbe_phy_get_comm_ownership(pdata);
1673 if (ret)
1674 return;
1675
1676 if (phy_data->redrv_if)
1677 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1678 else
1679 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1680
1681 xgbe_phy_put_comm_ownership(pdata);
1682 }
1683
1684 static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
1685 {
1686 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1687 return;
1688
1689 /* Log if a previous command did not complete */
1690 netif_dbg(pdata, link, pdata->netdev,
1691 "firmware mailbox not ready for command\n");
1692 }
1693
1694 static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
1695 {
1696 unsigned int wait;
1697
1698 /* Wait for command to complete */
1699 wait = XGBE_RATECHANGE_COUNT;
1700 while (wait--) {
1701 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1702 return;
1703
1704 usleep_range(1000, 2000);
1705 }
1706
1707 netif_dbg(pdata, link, pdata->netdev,
1708 "firmware mailbox command did not complete\n");
1709 }
1710
1711 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1712 {
1713 unsigned int s0;
1714
1715 xgbe_phy_start_ratechange(pdata);
1716
1717 /* Receiver Reset Cycle */
1718 s0 = 0;
1719 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1720 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1721
1722 /* Call FW to make the change */
1723 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1724 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1725 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1726
1727 xgbe_phy_complete_ratechange(pdata);
1728
1729 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1730 }
1731
1732 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1733 {
1734 struct xgbe_phy_data *phy_data = pdata->phy_data;
1735
1736 xgbe_phy_start_ratechange(pdata);
1737
1738 /* Call FW to make the change */
1739 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1740 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1741 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1742
1743 xgbe_phy_complete_ratechange(pdata);
1744
1745 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
1746
1747 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
1748 }
1749
1750 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
1751 {
1752 struct xgbe_phy_data *phy_data = pdata->phy_data;
1753 unsigned int s0;
1754
1755 xgbe_phy_set_redrv_mode(pdata);
1756
1757 xgbe_phy_start_ratechange(pdata);
1758
1759 /* 10G/SFI */
1760 s0 = 0;
1761 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1762 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
1763 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1764 } else {
1765 if (phy_data->sfp_cable_len <= 1)
1766 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1767 else if (phy_data->sfp_cable_len <= 3)
1768 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1769 else if (phy_data->sfp_cable_len <= 5)
1770 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1771 else
1772 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1773 }
1774
1775 /* Call FW to make the change */
1776 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1777 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1778 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1779
1780 xgbe_phy_complete_ratechange(pdata);
1781
1782 phy_data->cur_mode = XGBE_MODE_SFI;
1783
1784 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
1785 }
1786
1787 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
1788 {
1789 struct xgbe_phy_data *phy_data = pdata->phy_data;
1790 unsigned int s0;
1791
1792 xgbe_phy_set_redrv_mode(pdata);
1793
1794 xgbe_phy_start_ratechange(pdata);
1795
1796 /* 1G/X */
1797 s0 = 0;
1798 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1799 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1800
1801 /* Call FW to make the change */
1802 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1803 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1804 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1805
1806 xgbe_phy_complete_ratechange(pdata);
1807
1808 phy_data->cur_mode = XGBE_MODE_X;
1809
1810 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
1811 }
1812
1813 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
1814 {
1815 struct xgbe_phy_data *phy_data = pdata->phy_data;
1816 unsigned int s0;
1817
1818 xgbe_phy_set_redrv_mode(pdata);
1819
1820 xgbe_phy_start_ratechange(pdata);
1821
1822 /* 1G/SGMII */
1823 s0 = 0;
1824 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1825 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1826
1827 /* Call FW to make the change */
1828 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1829 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1830 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1831
1832 xgbe_phy_complete_ratechange(pdata);
1833
1834 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
1835
1836 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
1837 }
1838
1839 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
1840 {
1841 struct xgbe_phy_data *phy_data = pdata->phy_data;
1842 unsigned int s0;
1843
1844 xgbe_phy_set_redrv_mode(pdata);
1845
1846 xgbe_phy_start_ratechange(pdata);
1847
1848 /* 1G/SGMII */
1849 s0 = 0;
1850 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1851 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1852
1853 /* Call FW to make the change */
1854 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1855 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1856 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1857
1858 xgbe_phy_complete_ratechange(pdata);
1859
1860 phy_data->cur_mode = XGBE_MODE_SGMII_100;
1861
1862 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
1863 }
1864
1865 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
1866 {
1867 struct xgbe_phy_data *phy_data = pdata->phy_data;
1868 unsigned int s0;
1869
1870 xgbe_phy_set_redrv_mode(pdata);
1871
1872 xgbe_phy_start_ratechange(pdata);
1873
1874 /* 10G/KR */
1875 s0 = 0;
1876 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1877 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1878
1879 /* Call FW to make the change */
1880 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1881 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1882 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1883
1884 xgbe_phy_complete_ratechange(pdata);
1885
1886 phy_data->cur_mode = XGBE_MODE_KR;
1887
1888 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
1889 }
1890
1891 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
1892 {
1893 struct xgbe_phy_data *phy_data = pdata->phy_data;
1894 unsigned int s0;
1895
1896 xgbe_phy_set_redrv_mode(pdata);
1897
1898 xgbe_phy_start_ratechange(pdata);
1899
1900 /* 2.5G/KX */
1901 s0 = 0;
1902 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
1903 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1904
1905 /* Call FW to make the change */
1906 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1907 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1908 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1909
1910 xgbe_phy_complete_ratechange(pdata);
1911
1912 phy_data->cur_mode = XGBE_MODE_KX_2500;
1913
1914 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
1915 }
1916
1917 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
1918 {
1919 struct xgbe_phy_data *phy_data = pdata->phy_data;
1920 unsigned int s0;
1921
1922 xgbe_phy_set_redrv_mode(pdata);
1923
1924 xgbe_phy_start_ratechange(pdata);
1925
1926 /* 1G/KX */
1927 s0 = 0;
1928 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1929 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1930
1931 /* Call FW to make the change */
1932 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1933 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1934 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1935
1936 xgbe_phy_complete_ratechange(pdata);
1937
1938 phy_data->cur_mode = XGBE_MODE_KX_1000;
1939
1940 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
1941 }
1942
1943 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
1944 {
1945 struct xgbe_phy_data *phy_data = pdata->phy_data;
1946
1947 return phy_data->cur_mode;
1948 }
1949
1950 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
1951 {
1952 struct xgbe_phy_data *phy_data = pdata->phy_data;
1953
1954 /* No switching if not 10GBase-T */
1955 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
1956 return xgbe_phy_cur_mode(pdata);
1957
1958 switch (xgbe_phy_cur_mode(pdata)) {
1959 case XGBE_MODE_SGMII_100:
1960 case XGBE_MODE_SGMII_1000:
1961 return XGBE_MODE_KR;
1962 case XGBE_MODE_KR:
1963 default:
1964 return XGBE_MODE_SGMII_1000;
1965 }
1966 }
1967
1968 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
1969 {
1970 return XGBE_MODE_KX_2500;
1971 }
1972
1973 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
1974 {
1975 /* If we are in KR switch to KX, and vice-versa */
1976 switch (xgbe_phy_cur_mode(pdata)) {
1977 case XGBE_MODE_KX_1000:
1978 return XGBE_MODE_KR;
1979 case XGBE_MODE_KR:
1980 default:
1981 return XGBE_MODE_KX_1000;
1982 }
1983 }
1984
1985 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
1986 {
1987 struct xgbe_phy_data *phy_data = pdata->phy_data;
1988
1989 switch (phy_data->port_mode) {
1990 case XGBE_PORT_MODE_BACKPLANE:
1991 return xgbe_phy_switch_bp_mode(pdata);
1992 case XGBE_PORT_MODE_BACKPLANE_2500:
1993 return xgbe_phy_switch_bp_2500_mode(pdata);
1994 case XGBE_PORT_MODE_1000BASE_T:
1995 case XGBE_PORT_MODE_NBASE_T:
1996 case XGBE_PORT_MODE_10GBASE_T:
1997 return xgbe_phy_switch_baset_mode(pdata);
1998 case XGBE_PORT_MODE_1000BASE_X:
1999 case XGBE_PORT_MODE_10GBASE_R:
2000 case XGBE_PORT_MODE_SFP:
2001 /* No switching, so just return current mode */
2002 return xgbe_phy_cur_mode(pdata);
2003 default:
2004 return XGBE_MODE_UNKNOWN;
2005 }
2006 }
2007
2008 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2009 int speed)
2010 {
2011 switch (speed) {
2012 case SPEED_1000:
2013 return XGBE_MODE_X;
2014 case SPEED_10000:
2015 return XGBE_MODE_KR;
2016 default:
2017 return XGBE_MODE_UNKNOWN;
2018 }
2019 }
2020
2021 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2022 int speed)
2023 {
2024 switch (speed) {
2025 case SPEED_100:
2026 return XGBE_MODE_SGMII_100;
2027 case SPEED_1000:
2028 return XGBE_MODE_SGMII_1000;
2029 case SPEED_10000:
2030 return XGBE_MODE_KR;
2031 default:
2032 return XGBE_MODE_UNKNOWN;
2033 }
2034 }
2035
2036 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2037 int speed)
2038 {
2039 switch (speed) {
2040 case SPEED_100:
2041 return XGBE_MODE_SGMII_100;
2042 case SPEED_1000:
2043 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2044 return XGBE_MODE_SGMII_1000;
2045 else
2046 return XGBE_MODE_X;
2047 case SPEED_10000:
2048 case SPEED_UNKNOWN:
2049 return XGBE_MODE_SFI;
2050 default:
2051 return XGBE_MODE_UNKNOWN;
2052 }
2053 }
2054
2055 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2056 {
2057 switch (speed) {
2058 case SPEED_2500:
2059 return XGBE_MODE_KX_2500;
2060 default:
2061 return XGBE_MODE_UNKNOWN;
2062 }
2063 }
2064
2065 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2066 {
2067 switch (speed) {
2068 case SPEED_1000:
2069 return XGBE_MODE_KX_1000;
2070 case SPEED_10000:
2071 return XGBE_MODE_KR;
2072 default:
2073 return XGBE_MODE_UNKNOWN;
2074 }
2075 }
2076
2077 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2078 int speed)
2079 {
2080 struct xgbe_phy_data *phy_data = pdata->phy_data;
2081
2082 switch (phy_data->port_mode) {
2083 case XGBE_PORT_MODE_BACKPLANE:
2084 return xgbe_phy_get_bp_mode(speed);
2085 case XGBE_PORT_MODE_BACKPLANE_2500:
2086 return xgbe_phy_get_bp_2500_mode(speed);
2087 case XGBE_PORT_MODE_1000BASE_T:
2088 case XGBE_PORT_MODE_NBASE_T:
2089 case XGBE_PORT_MODE_10GBASE_T:
2090 return xgbe_phy_get_baset_mode(phy_data, speed);
2091 case XGBE_PORT_MODE_1000BASE_X:
2092 case XGBE_PORT_MODE_10GBASE_R:
2093 return xgbe_phy_get_basex_mode(phy_data, speed);
2094 case XGBE_PORT_MODE_SFP:
2095 return xgbe_phy_get_sfp_mode(phy_data, speed);
2096 default:
2097 return XGBE_MODE_UNKNOWN;
2098 }
2099 }
2100
2101 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2102 {
2103 switch (mode) {
2104 case XGBE_MODE_KX_1000:
2105 xgbe_phy_kx_1000_mode(pdata);
2106 break;
2107 case XGBE_MODE_KX_2500:
2108 xgbe_phy_kx_2500_mode(pdata);
2109 break;
2110 case XGBE_MODE_KR:
2111 xgbe_phy_kr_mode(pdata);
2112 break;
2113 case XGBE_MODE_SGMII_100:
2114 xgbe_phy_sgmii_100_mode(pdata);
2115 break;
2116 case XGBE_MODE_SGMII_1000:
2117 xgbe_phy_sgmii_1000_mode(pdata);
2118 break;
2119 case XGBE_MODE_X:
2120 xgbe_phy_x_mode(pdata);
2121 break;
2122 case XGBE_MODE_SFI:
2123 xgbe_phy_sfi_mode(pdata);
2124 break;
2125 default:
2126 break;
2127 }
2128 }
2129
2130 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2131 enum xgbe_mode mode, u32 advert)
2132 {
2133 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2134 if (pdata->phy.advertising & advert)
2135 return true;
2136 } else {
2137 enum xgbe_mode cur_mode;
2138
2139 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2140 if (cur_mode == mode)
2141 return true;
2142 }
2143
2144 return false;
2145 }
2146
2147 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2148 enum xgbe_mode mode)
2149 {
2150 switch (mode) {
2151 case XGBE_MODE_X:
2152 return xgbe_phy_check_mode(pdata, mode,
2153 ADVERTISED_1000baseT_Full);
2154 case XGBE_MODE_KR:
2155 return xgbe_phy_check_mode(pdata, mode,
2156 ADVERTISED_10000baseT_Full);
2157 default:
2158 return false;
2159 }
2160 }
2161
2162 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2163 enum xgbe_mode mode)
2164 {
2165 switch (mode) {
2166 case XGBE_MODE_SGMII_100:
2167 return xgbe_phy_check_mode(pdata, mode,
2168 ADVERTISED_100baseT_Full);
2169 case XGBE_MODE_SGMII_1000:
2170 return xgbe_phy_check_mode(pdata, mode,
2171 ADVERTISED_1000baseT_Full);
2172 case XGBE_MODE_KR:
2173 return xgbe_phy_check_mode(pdata, mode,
2174 ADVERTISED_10000baseT_Full);
2175 default:
2176 return false;
2177 }
2178 }
2179
2180 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2181 enum xgbe_mode mode)
2182 {
2183 struct xgbe_phy_data *phy_data = pdata->phy_data;
2184
2185 switch (mode) {
2186 case XGBE_MODE_X:
2187 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2188 return false;
2189 return xgbe_phy_check_mode(pdata, mode,
2190 ADVERTISED_1000baseT_Full);
2191 case XGBE_MODE_SGMII_100:
2192 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2193 return false;
2194 return xgbe_phy_check_mode(pdata, mode,
2195 ADVERTISED_100baseT_Full);
2196 case XGBE_MODE_SGMII_1000:
2197 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2198 return false;
2199 return xgbe_phy_check_mode(pdata, mode,
2200 ADVERTISED_1000baseT_Full);
2201 case XGBE_MODE_SFI:
2202 return xgbe_phy_check_mode(pdata, mode,
2203 ADVERTISED_10000baseT_Full);
2204 default:
2205 return false;
2206 }
2207 }
2208
2209 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2210 enum xgbe_mode mode)
2211 {
2212 switch (mode) {
2213 case XGBE_MODE_KX_2500:
2214 return xgbe_phy_check_mode(pdata, mode,
2215 ADVERTISED_2500baseX_Full);
2216 default:
2217 return false;
2218 }
2219 }
2220
2221 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2222 enum xgbe_mode mode)
2223 {
2224 switch (mode) {
2225 case XGBE_MODE_KX_1000:
2226 return xgbe_phy_check_mode(pdata, mode,
2227 ADVERTISED_1000baseKX_Full);
2228 case XGBE_MODE_KR:
2229 return xgbe_phy_check_mode(pdata, mode,
2230 ADVERTISED_10000baseKR_Full);
2231 default:
2232 return false;
2233 }
2234 }
2235
2236 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2237 {
2238 struct xgbe_phy_data *phy_data = pdata->phy_data;
2239
2240 switch (phy_data->port_mode) {
2241 case XGBE_PORT_MODE_BACKPLANE:
2242 return xgbe_phy_use_bp_mode(pdata, mode);
2243 case XGBE_PORT_MODE_BACKPLANE_2500:
2244 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2245 case XGBE_PORT_MODE_1000BASE_T:
2246 case XGBE_PORT_MODE_NBASE_T:
2247 case XGBE_PORT_MODE_10GBASE_T:
2248 return xgbe_phy_use_baset_mode(pdata, mode);
2249 case XGBE_PORT_MODE_1000BASE_X:
2250 case XGBE_PORT_MODE_10GBASE_R:
2251 return xgbe_phy_use_basex_mode(pdata, mode);
2252 case XGBE_PORT_MODE_SFP:
2253 return xgbe_phy_use_sfp_mode(pdata, mode);
2254 default:
2255 return false;
2256 }
2257 }
2258
2259 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2260 int speed)
2261 {
2262 switch (speed) {
2263 case SPEED_1000:
2264 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2265 case SPEED_10000:
2266 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2267 default:
2268 return false;
2269 }
2270 }
2271
2272 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2273 int speed)
2274 {
2275 switch (speed) {
2276 case SPEED_100:
2277 case SPEED_1000:
2278 return true;
2279 case SPEED_10000:
2280 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2281 default:
2282 return false;
2283 }
2284 }
2285
2286 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2287 int speed)
2288 {
2289 switch (speed) {
2290 case SPEED_100:
2291 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2292 case SPEED_1000:
2293 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2294 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2295 case SPEED_10000:
2296 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2297 default:
2298 return false;
2299 }
2300 }
2301
2302 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2303 {
2304 switch (speed) {
2305 case SPEED_2500:
2306 return true;
2307 default:
2308 return false;
2309 }
2310 }
2311
2312 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2313 {
2314 switch (speed) {
2315 case SPEED_1000:
2316 case SPEED_10000:
2317 return true;
2318 default:
2319 return false;
2320 }
2321 }
2322
2323 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2324 {
2325 struct xgbe_phy_data *phy_data = pdata->phy_data;
2326
2327 switch (phy_data->port_mode) {
2328 case XGBE_PORT_MODE_BACKPLANE:
2329 return xgbe_phy_valid_speed_bp_mode(speed);
2330 case XGBE_PORT_MODE_BACKPLANE_2500:
2331 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2332 case XGBE_PORT_MODE_1000BASE_T:
2333 case XGBE_PORT_MODE_NBASE_T:
2334 case XGBE_PORT_MODE_10GBASE_T:
2335 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2336 case XGBE_PORT_MODE_1000BASE_X:
2337 case XGBE_PORT_MODE_10GBASE_R:
2338 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2339 case XGBE_PORT_MODE_SFP:
2340 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2341 default:
2342 return false;
2343 }
2344 }
2345
2346 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2347 {
2348 struct xgbe_phy_data *phy_data = pdata->phy_data;
2349 unsigned int ret, reg;
2350
2351 *an_restart = 0;
2352
2353 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2354 /* Check SFP signals */
2355 xgbe_phy_sfp_detect(pdata);
2356
2357 if (phy_data->sfp_changed) {
2358 *an_restart = 1;
2359 return 0;
2360 }
2361
2362 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2363 return 0;
2364 }
2365
2366 if (phy_data->phydev) {
2367 /* Check external PHY */
2368 ret = phy_read_status(phy_data->phydev);
2369 if (ret < 0)
2370 return 0;
2371
2372 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2373 !phy_aneg_done(phy_data->phydev))
2374 return 0;
2375
2376 if (!phy_data->phydev->link)
2377 return 0;
2378 }
2379
2380 /* Link status is latched low, so read once to clear
2381 * and then read again to get current state
2382 */
2383 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2384 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2385 if (reg & MDIO_STAT1_LSTATUS)
2386 return 1;
2387
2388 /* No link, attempt a receiver reset cycle */
2389 if (phy_data->rrc_count++) {
2390 phy_data->rrc_count = 0;
2391 xgbe_phy_rrc(pdata);
2392 }
2393
2394 return 0;
2395 }
2396
2397 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2398 {
2399 struct xgbe_phy_data *phy_data = pdata->phy_data;
2400 unsigned int reg;
2401
2402 reg = XP_IOREAD(pdata, XP_PROP_3);
2403
2404 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2405 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
2406
2407 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
2408
2409 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
2410 GPIO_RX_LOS);
2411 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
2412 GPIO_TX_FAULT);
2413 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
2414 GPIO_MOD_ABS);
2415 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
2416 GPIO_RATE_SELECT);
2417
2418 if (netif_msg_probe(pdata)) {
2419 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2420 phy_data->sfp_gpio_address);
2421 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2422 phy_data->sfp_gpio_mask);
2423 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2424 phy_data->sfp_gpio_rx_los);
2425 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2426 phy_data->sfp_gpio_tx_fault);
2427 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2428 phy_data->sfp_gpio_mod_absent);
2429 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2430 phy_data->sfp_gpio_rate_select);
2431 }
2432 }
2433
2434 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2435 {
2436 struct xgbe_phy_data *phy_data = pdata->phy_data;
2437 unsigned int reg, mux_addr_hi, mux_addr_lo;
2438
2439 reg = XP_IOREAD(pdata, XP_PROP_4);
2440
2441 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
2442 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
2443 if (mux_addr_lo == XGBE_SFP_DIRECT)
2444 return;
2445
2446 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2447 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2448 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
2449
2450 if (netif_msg_probe(pdata)) {
2451 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2452 phy_data->sfp_mux_address);
2453 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2454 phy_data->sfp_mux_channel);
2455 }
2456 }
2457
2458 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2459 {
2460 xgbe_phy_sfp_comm_setup(pdata);
2461 xgbe_phy_sfp_gpio_setup(pdata);
2462 }
2463
2464 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2465 {
2466 struct xgbe_phy_data *phy_data = pdata->phy_data;
2467 unsigned int ret;
2468
2469 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2470 if (ret)
2471 return ret;
2472
2473 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2474
2475 return ret;
2476 }
2477
2478 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2479 {
2480 struct xgbe_phy_data *phy_data = pdata->phy_data;
2481 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2482 int ret;
2483
2484 /* Read the output port registers */
2485 gpio_reg = 2;
2486 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2487 &gpio_reg, sizeof(gpio_reg),
2488 gpio_ports, sizeof(gpio_ports));
2489 if (ret)
2490 return ret;
2491
2492 /* Prepare to write the GPIO data */
2493 gpio_data[0] = 2;
2494 gpio_data[1] = gpio_ports[0];
2495 gpio_data[2] = gpio_ports[1];
2496
2497 /* Set the GPIO pin */
2498 if (phy_data->mdio_reset_gpio < 8)
2499 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2500 else
2501 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2502
2503 /* Write the output port registers */
2504 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2505 gpio_data, sizeof(gpio_data));
2506 if (ret)
2507 return ret;
2508
2509 /* Clear the GPIO pin */
2510 if (phy_data->mdio_reset_gpio < 8)
2511 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2512 else
2513 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2514
2515 /* Write the output port registers */
2516 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2517 gpio_data, sizeof(gpio_data));
2518
2519 return ret;
2520 }
2521
2522 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2523 {
2524 struct xgbe_phy_data *phy_data = pdata->phy_data;
2525 int ret;
2526
2527 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2528 return 0;
2529
2530 ret = xgbe_phy_get_comm_ownership(pdata);
2531 if (ret)
2532 return ret;
2533
2534 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2535 ret = xgbe_phy_i2c_mdio_reset(pdata);
2536 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2537 ret = xgbe_phy_int_mdio_reset(pdata);
2538
2539 xgbe_phy_put_comm_ownership(pdata);
2540
2541 return ret;
2542 }
2543
2544 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2545 {
2546 if (!phy_data->redrv)
2547 return false;
2548
2549 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2550 return true;
2551
2552 switch (phy_data->redrv_model) {
2553 case XGBE_PHY_REDRV_MODEL_4223:
2554 if (phy_data->redrv_lane > 3)
2555 return true;
2556 break;
2557 case XGBE_PHY_REDRV_MODEL_4227:
2558 if (phy_data->redrv_lane > 1)
2559 return true;
2560 break;
2561 default:
2562 return true;
2563 }
2564
2565 return false;
2566 }
2567
2568 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2569 {
2570 struct xgbe_phy_data *phy_data = pdata->phy_data;
2571 unsigned int reg;
2572
2573 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2574 return 0;
2575
2576 reg = XP_IOREAD(pdata, XP_PROP_3);
2577 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
2578 switch (phy_data->mdio_reset) {
2579 case XGBE_MDIO_RESET_NONE:
2580 case XGBE_MDIO_RESET_I2C_GPIO:
2581 case XGBE_MDIO_RESET_INT_GPIO:
2582 break;
2583 default:
2584 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2585 phy_data->mdio_reset);
2586 return -EINVAL;
2587 }
2588
2589 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2590 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2591 XP_GET_BITS(reg, XP_PROP_3,
2592 MDIO_RESET_I2C_ADDR);
2593 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2594 MDIO_RESET_I2C_GPIO);
2595 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2596 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2597 MDIO_RESET_INT_GPIO);
2598 }
2599
2600 return 0;
2601 }
2602
2603 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2604 {
2605 struct xgbe_phy_data *phy_data = pdata->phy_data;
2606
2607 switch (phy_data->port_mode) {
2608 case XGBE_PORT_MODE_BACKPLANE:
2609 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2610 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2611 return false;
2612 break;
2613 case XGBE_PORT_MODE_BACKPLANE_2500:
2614 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2615 return false;
2616 break;
2617 case XGBE_PORT_MODE_1000BASE_T:
2618 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2619 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2620 return false;
2621 break;
2622 case XGBE_PORT_MODE_1000BASE_X:
2623 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2624 return false;
2625 break;
2626 case XGBE_PORT_MODE_NBASE_T:
2627 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2628 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2629 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2630 return false;
2631 break;
2632 case XGBE_PORT_MODE_10GBASE_T:
2633 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2634 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2635 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2636 return false;
2637 break;
2638 case XGBE_PORT_MODE_10GBASE_R:
2639 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2640 return false;
2641 break;
2642 case XGBE_PORT_MODE_SFP:
2643 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2644 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2645 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2646 return false;
2647 break;
2648 default:
2649 break;
2650 }
2651
2652 return true;
2653 }
2654
2655 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2656 {
2657 struct xgbe_phy_data *phy_data = pdata->phy_data;
2658
2659 switch (phy_data->port_mode) {
2660 case XGBE_PORT_MODE_BACKPLANE:
2661 case XGBE_PORT_MODE_BACKPLANE_2500:
2662 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2663 return false;
2664 break;
2665 case XGBE_PORT_MODE_1000BASE_T:
2666 case XGBE_PORT_MODE_1000BASE_X:
2667 case XGBE_PORT_MODE_NBASE_T:
2668 case XGBE_PORT_MODE_10GBASE_T:
2669 case XGBE_PORT_MODE_10GBASE_R:
2670 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2671 return false;
2672 break;
2673 case XGBE_PORT_MODE_SFP:
2674 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2675 return false;
2676 break;
2677 default:
2678 break;
2679 }
2680
2681 return true;
2682 }
2683
2684 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2685 {
2686 unsigned int reg;
2687
2688 reg = XP_IOREAD(pdata, XP_PROP_0);
2689 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
2690 return false;
2691 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
2692 return false;
2693
2694 return true;
2695 }
2696
2697 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2698 {
2699 struct xgbe_phy_data *phy_data = pdata->phy_data;
2700
2701 /* If we have an external PHY, free it */
2702 xgbe_phy_free_phy_device(pdata);
2703
2704 /* Reset SFP data */
2705 xgbe_phy_sfp_reset(phy_data);
2706 xgbe_phy_sfp_mod_absent(pdata);
2707
2708 /* Power off the PHY */
2709 xgbe_phy_power_off(pdata);
2710
2711 /* Stop the I2C controller */
2712 pdata->i2c_if.i2c_stop(pdata);
2713 }
2714
2715 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2716 {
2717 struct xgbe_phy_data *phy_data = pdata->phy_data;
2718 int ret;
2719
2720 /* Start the I2C controller */
2721 ret = pdata->i2c_if.i2c_start(pdata);
2722 if (ret)
2723 return ret;
2724
2725 /* Start in highest supported mode */
2726 xgbe_phy_set_mode(pdata, phy_data->start_mode);
2727
2728 /* After starting the I2C controller, we can check for an SFP */
2729 switch (phy_data->port_mode) {
2730 case XGBE_PORT_MODE_SFP:
2731 xgbe_phy_sfp_detect(pdata);
2732 break;
2733 default:
2734 break;
2735 }
2736
2737 /* If we have an external PHY, start it */
2738 ret = xgbe_phy_find_phy_device(pdata);
2739 if (ret)
2740 goto err_i2c;
2741
2742 return 0;
2743
2744 err_i2c:
2745 pdata->i2c_if.i2c_stop(pdata);
2746
2747 return ret;
2748 }
2749
2750 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
2751 {
2752 struct xgbe_phy_data *phy_data = pdata->phy_data;
2753 enum xgbe_mode cur_mode;
2754 int ret;
2755
2756 /* Reset by power cycling the PHY */
2757 cur_mode = phy_data->cur_mode;
2758 xgbe_phy_power_off(pdata);
2759 xgbe_phy_set_mode(pdata, cur_mode);
2760
2761 if (!phy_data->phydev)
2762 return 0;
2763
2764 /* Reset the external PHY */
2765 ret = xgbe_phy_mdio_reset(pdata);
2766 if (ret)
2767 return ret;
2768
2769 return phy_init_hw(phy_data->phydev);
2770 }
2771
2772 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
2773 {
2774 struct xgbe_phy_data *phy_data = pdata->phy_data;
2775
2776 /* Unregister for driving external PHYs */
2777 mdiobus_unregister(phy_data->mii);
2778 }
2779
2780 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
2781 {
2782 struct xgbe_phy_data *phy_data;
2783 struct mii_bus *mii;
2784 unsigned int reg;
2785 int ret;
2786
2787 /* Check if enabled */
2788 if (!xgbe_phy_port_enabled(pdata)) {
2789 dev_info(pdata->dev, "device is not enabled\n");
2790 return -ENODEV;
2791 }
2792
2793 /* Initialize the I2C controller */
2794 ret = pdata->i2c_if.i2c_init(pdata);
2795 if (ret)
2796 return ret;
2797
2798 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
2799 if (!phy_data)
2800 return -ENOMEM;
2801 pdata->phy_data = phy_data;
2802
2803 reg = XP_IOREAD(pdata, XP_PROP_0);
2804 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2805 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2806 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2807 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2808 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2809 if (netif_msg_probe(pdata)) {
2810 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
2811 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
2812 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
2813 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
2814 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
2815 }
2816
2817 reg = XP_IOREAD(pdata, XP_PROP_4);
2818 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2819 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2820 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2821 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2822 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2823 if (phy_data->redrv && netif_msg_probe(pdata)) {
2824 dev_dbg(pdata->dev, "redrv present\n");
2825 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
2826 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
2827 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
2828 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
2829 }
2830
2831 /* Validate the connection requested */
2832 if (xgbe_phy_conn_type_mismatch(pdata)) {
2833 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
2834 phy_data->port_mode, phy_data->conn_type);
2835 }
2836
2837 /* Validate the mode requested */
2838 if (xgbe_phy_port_mode_mismatch(pdata)) {
2839 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
2840 phy_data->port_mode, phy_data->port_speeds);
2841 return -EINVAL;
2842 }
2843
2844 /* Check for and validate MDIO reset support */
2845 ret = xgbe_phy_mdio_reset_setup(pdata);
2846 if (ret)
2847 return ret;
2848
2849 /* Validate the re-driver information */
2850 if (xgbe_phy_redrv_error(phy_data)) {
2851 dev_err(pdata->dev, "phy re-driver settings error\n");
2852 return -EINVAL;
2853 }
2854 pdata->kr_redrv = phy_data->redrv;
2855
2856 /* Indicate current mode is unknown */
2857 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2858
2859 /* Initialize supported features */
2860 pdata->phy.supported = 0;
2861
2862 switch (phy_data->port_mode) {
2863 /* Backplane support */
2864 case XGBE_PORT_MODE_BACKPLANE:
2865 pdata->phy.supported |= SUPPORTED_Autoneg;
2866 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2867 pdata->phy.supported |= SUPPORTED_Backplane;
2868 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2869 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2870 phy_data->start_mode = XGBE_MODE_KX_1000;
2871 }
2872 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2873 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2874 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2875 pdata->phy.supported |=
2876 SUPPORTED_10000baseR_FEC;
2877 phy_data->start_mode = XGBE_MODE_KR;
2878 }
2879
2880 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2881 break;
2882 case XGBE_PORT_MODE_BACKPLANE_2500:
2883 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2884 pdata->phy.supported |= SUPPORTED_Backplane;
2885 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2886 phy_data->start_mode = XGBE_MODE_KX_2500;
2887
2888 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2889 break;
2890
2891 /* MDIO 1GBase-T support */
2892 case XGBE_PORT_MODE_1000BASE_T:
2893 pdata->phy.supported |= SUPPORTED_Autoneg;
2894 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2895 pdata->phy.supported |= SUPPORTED_TP;
2896 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2897 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2898 phy_data->start_mode = XGBE_MODE_SGMII_100;
2899 }
2900 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2901 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2902 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2903 }
2904
2905 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2906 break;
2907
2908 /* MDIO Base-X support */
2909 case XGBE_PORT_MODE_1000BASE_X:
2910 pdata->phy.supported |= SUPPORTED_Autoneg;
2911 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2912 pdata->phy.supported |= SUPPORTED_FIBRE;
2913 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2914 phy_data->start_mode = XGBE_MODE_X;
2915
2916 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2917 break;
2918
2919 /* MDIO NBase-T support */
2920 case XGBE_PORT_MODE_NBASE_T:
2921 pdata->phy.supported |= SUPPORTED_Autoneg;
2922 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2923 pdata->phy.supported |= SUPPORTED_TP;
2924 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2925 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2926 phy_data->start_mode = XGBE_MODE_SGMII_100;
2927 }
2928 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2929 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2930 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2931 }
2932 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
2933 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2934 phy_data->start_mode = XGBE_MODE_KX_2500;
2935 }
2936
2937 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
2938 break;
2939
2940 /* 10GBase-T support */
2941 case XGBE_PORT_MODE_10GBASE_T:
2942 pdata->phy.supported |= SUPPORTED_Autoneg;
2943 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2944 pdata->phy.supported |= SUPPORTED_TP;
2945 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2946 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2947 phy_data->start_mode = XGBE_MODE_SGMII_100;
2948 }
2949 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2950 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2951 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2952 }
2953 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2954 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2955 phy_data->start_mode = XGBE_MODE_KR;
2956 }
2957
2958 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2959 break;
2960
2961 /* 10GBase-R support */
2962 case XGBE_PORT_MODE_10GBASE_R:
2963 pdata->phy.supported |= SUPPORTED_Autoneg;
2964 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2965 pdata->phy.supported |= SUPPORTED_TP;
2966 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2967 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2968 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2969 phy_data->start_mode = XGBE_MODE_SFI;
2970
2971 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2972 break;
2973
2974 /* SFP support */
2975 case XGBE_PORT_MODE_SFP:
2976 pdata->phy.supported |= SUPPORTED_Autoneg;
2977 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2978 pdata->phy.supported |= SUPPORTED_TP;
2979 pdata->phy.supported |= SUPPORTED_FIBRE;
2980 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2981 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2982 phy_data->start_mode = XGBE_MODE_SGMII_100;
2983 }
2984 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2985 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2986 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2987 }
2988 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2989 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2990 phy_data->start_mode = XGBE_MODE_SFI;
2991 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2992 pdata->phy.supported |=
2993 SUPPORTED_10000baseR_FEC;
2994 }
2995
2996 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2997
2998 xgbe_phy_sfp_setup(pdata);
2999 break;
3000 default:
3001 return -EINVAL;
3002 }
3003
3004 if (netif_msg_probe(pdata))
3005 dev_dbg(pdata->dev, "phy supported=%#x\n",
3006 pdata->phy.supported);
3007
3008 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3009 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3010 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3011 phy_data->phydev_mode);
3012 if (ret) {
3013 dev_err(pdata->dev,
3014 "mdio port/clause not compatible (%d/%u)\n",
3015 phy_data->mdio_addr, phy_data->phydev_mode);
3016 return -EINVAL;
3017 }
3018 }
3019
3020 if (phy_data->redrv && !phy_data->redrv_if) {
3021 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3022 XGBE_MDIO_MODE_CL22);
3023 if (ret) {
3024 dev_err(pdata->dev,
3025 "redriver mdio port not compatible (%u)\n",
3026 phy_data->redrv_addr);
3027 return -EINVAL;
3028 }
3029 }
3030
3031 /* Register for driving external PHYs */
3032 mii = devm_mdiobus_alloc(pdata->dev);
3033 if (!mii) {
3034 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3035 return -ENOMEM;
3036 }
3037
3038 mii->priv = pdata;
3039 mii->name = "amd-xgbe-mii";
3040 mii->read = xgbe_phy_mii_read;
3041 mii->write = xgbe_phy_mii_write;
3042 mii->parent = pdata->dev;
3043 mii->phy_mask = ~0;
3044 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3045 ret = mdiobus_register(mii);
3046 if (ret) {
3047 dev_err(pdata->dev, "mdiobus_register failed\n");
3048 return ret;
3049 }
3050 phy_data->mii = mii;
3051
3052 return 0;
3053 }
3054
3055 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3056 {
3057 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3058
3059 phy_impl->init = xgbe_phy_init;
3060 phy_impl->exit = xgbe_phy_exit;
3061
3062 phy_impl->reset = xgbe_phy_reset;
3063 phy_impl->start = xgbe_phy_start;
3064 phy_impl->stop = xgbe_phy_stop;
3065
3066 phy_impl->link_status = xgbe_phy_link_status;
3067
3068 phy_impl->valid_speed = xgbe_phy_valid_speed;
3069
3070 phy_impl->use_mode = xgbe_phy_use_mode;
3071 phy_impl->set_mode = xgbe_phy_set_mode;
3072 phy_impl->get_mode = xgbe_phy_get_mode;
3073 phy_impl->switch_mode = xgbe_phy_switch_mode;
3074 phy_impl->cur_mode = xgbe_phy_cur_mode;
3075
3076 phy_impl->an_mode = xgbe_phy_an_mode;
3077
3078 phy_impl->an_config = xgbe_phy_an_config;
3079
3080 phy_impl->an_advertising = xgbe_phy_an_advertising;
3081
3082 phy_impl->an_outcome = xgbe_phy_an_outcome;
3083 }
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