1 /* Applied Micro X-Gene SoC Ethernet Classifier structures
3 * Copyright (c) 2016, Applied Micro Circuits Corporation
4 * Authors: Khuong Dinh <kdinh@apm.com>
5 * Tanmay Inamdar <tinamdar@apm.com>
6 * Iyappan Subramanian <isubramanian@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
24 /* interfaces to convert structures to HW recognized bit formats */
25 static void xgene_cle_sband_to_hw(u8 frag
, enum xgene_cle_prot_version ver
,
26 enum xgene_cle_prot_type type
, u32 len
,
29 *reg
= SET_VAL(SB_IPFRAG
, frag
) |
30 SET_VAL(SB_IPPROT
, type
) |
31 SET_VAL(SB_IPVER
, ver
) |
32 SET_VAL(SB_HDRLEN
, len
);
35 static void xgene_cle_idt_to_hw(u32 dstqid
, u32 fpsel
,
36 u32 nfpsel
, u32
*idt_reg
)
38 *idt_reg
= SET_VAL(IDT_DSTQID
, dstqid
) |
39 SET_VAL(IDT_FPSEL
, fpsel
) |
40 SET_VAL(IDT_NFPSEL
, nfpsel
);
43 static void xgene_cle_dbptr_to_hw(struct xgene_enet_pdata
*pdata
,
44 struct xgene_cle_dbptr
*dbptr
, u32
*buf
)
46 buf
[4] = SET_VAL(CLE_FPSEL
, dbptr
->fpsel
) |
47 SET_VAL(CLE_DSTQIDL
, dbptr
->dstqid
);
49 buf
[5] = SET_VAL(CLE_DSTQIDH
, (u32
)dbptr
->dstqid
>> CLE_DSTQIDL_LEN
) |
50 SET_VAL(CLE_PRIORITY
, dbptr
->cle_priority
);
53 static void xgene_cle_kn_to_hw(struct xgene_cle_ptree_kn
*kn
, u32
*buf
)
58 buf
[j
++] = SET_VAL(CLE_TYPE
, kn
->node_type
);
59 for (i
= 0; i
< kn
->num_keys
; i
++) {
60 struct xgene_cle_ptree_key
*key
= &kn
->key
[i
];
63 buf
[j
] = SET_VAL(CLE_KN_PRIO
, key
->priority
) |
64 SET_VAL(CLE_KN_RPTR
, key
->result_pointer
);
66 data
= SET_VAL(CLE_KN_PRIO
, key
->priority
) |
67 SET_VAL(CLE_KN_RPTR
, key
->result_pointer
);
68 buf
[j
++] |= (data
<< 16);
73 static void xgene_cle_dn_to_hw(struct xgene_cle_ptree_ewdn
*dn
,
76 struct xgene_cle_ptree_branch
*br
;
80 buf
[j
++] = SET_VAL(CLE_DN_TYPE
, dn
->node_type
) |
81 SET_VAL(CLE_DN_LASTN
, dn
->last_node
) |
82 SET_VAL(CLE_DN_HLS
, dn
->hdr_len_store
) |
83 SET_VAL(CLE_DN_EXT
, dn
->hdr_extn
) |
84 SET_VAL(CLE_DN_BSTOR
, dn
->byte_store
) |
85 SET_VAL(CLE_DN_SBSTOR
, dn
->search_byte_store
) |
86 SET_VAL(CLE_DN_RPTR
, dn
->result_pointer
);
88 for (i
= 0; i
< dn
->num_branches
; i
++) {
90 npp
= br
->next_packet_pointer
;
92 if ((br
->jump_rel
== JMP_ABS
) && (npp
< CLE_PKTRAM_SIZE
))
95 buf
[j
++] = SET_VAL(CLE_BR_VALID
, br
->valid
) |
96 SET_VAL(CLE_BR_NPPTR
, npp
) |
97 SET_VAL(CLE_BR_JB
, br
->jump_bw
) |
98 SET_VAL(CLE_BR_JR
, br
->jump_rel
) |
99 SET_VAL(CLE_BR_OP
, br
->operation
) |
100 SET_VAL(CLE_BR_NNODE
, br
->next_node
) |
101 SET_VAL(CLE_BR_NBR
, br
->next_branch
);
103 buf
[j
++] = SET_VAL(CLE_BR_DATA
, br
->data
) |
104 SET_VAL(CLE_BR_MASK
, br
->mask
);
108 static int xgene_cle_poll_cmd_done(void __iomem
*base
,
109 enum xgene_cle_cmd_type cmd
)
111 u32 status
, loop
= 10;
115 status
= ioread32(base
+ INDCMD_STATUS
);
120 usleep_range(1000, 2000);
126 static int xgene_cle_dram_wr(struct xgene_enet_cle
*cle
, u32
*data
, u8 nregs
,
127 u32 index
, enum xgene_cle_dram_type type
,
128 enum xgene_cle_cmd_type cmd
)
130 enum xgene_cle_parser parser
= cle
->active_parser
;
131 void __iomem
*base
= cle
->base
;
136 /* PTREE_RAM onwards, DRAM regions are common for all parsers */
137 nparsers
= (type
>= PTREE_RAM
) ? 1 : cle
->parsers
;
139 for (i
= 0; i
< nparsers
; i
++) {
141 if ((type
< PTREE_RAM
) && (parser
!= PARSER_ALL
))
144 ind_addr
= XGENE_CLE_DRAM(type
+ (port
* 4)) | index
;
145 iowrite32(ind_addr
, base
+ INDADDR
);
146 for (j
= 0; j
< nregs
; j
++)
147 iowrite32(data
[j
], base
+ DATA_RAM0
+ (j
* 4));
148 iowrite32(cmd
, base
+ INDCMD
);
150 ret
= xgene_cle_poll_cmd_done(base
, cmd
);
158 static void xgene_cle_enable_ptree(struct xgene_enet_pdata
*pdata
,
159 struct xgene_enet_cle
*cle
)
161 struct xgene_cle_ptree
*ptree
= &cle
->ptree
;
162 void __iomem
*addr
, *base
= cle
->base
;
163 u32 offset
= CLE_PORT_OFFSET
;
166 /* 1G port has to advance 4 bytes and 10G has to advance 8 bytes */
167 ptree
->start_pkt
+= cle
->jump_bytes
;
168 for (i
= 0; i
< cle
->parsers
; i
++) {
169 if (cle
->active_parser
!= PARSER_ALL
)
170 addr
= base
+ cle
->active_parser
* offset
;
172 addr
= base
+ (i
* offset
);
174 iowrite32(ptree
->start_node
& 0x3fff, addr
+ SNPTR0
);
175 iowrite32(ptree
->start_pkt
& 0x1ff, addr
+ SPPTR0
);
179 static int xgene_cle_setup_dbptr(struct xgene_enet_pdata
*pdata
,
180 struct xgene_enet_cle
*cle
)
182 struct xgene_cle_ptree
*ptree
= &cle
->ptree
;
183 u32 buf
[CLE_DRAM_REGS
];
187 memset(buf
, 0, sizeof(buf
));
188 for (i
= 0; i
< ptree
->num_dbptr
; i
++) {
189 xgene_cle_dbptr_to_hw(pdata
, &ptree
->dbptr
[i
], buf
);
190 ret
= xgene_cle_dram_wr(cle
, buf
, 6, i
+ ptree
->start_dbptr
,
199 static int xgene_cle_setup_node(struct xgene_enet_pdata
*pdata
,
200 struct xgene_enet_cle
*cle
)
202 struct xgene_cle_ptree
*ptree
= &cle
->ptree
;
203 struct xgene_cle_ptree_ewdn
*dn
= ptree
->dn
;
204 struct xgene_cle_ptree_kn
*kn
= ptree
->kn
;
205 u32 buf
[CLE_DRAM_REGS
];
208 memset(buf
, 0, sizeof(buf
));
209 for (i
= 0; i
< ptree
->num_dn
; i
++) {
210 xgene_cle_dn_to_hw(&dn
[i
], buf
, cle
->jump_bytes
);
211 ret
= xgene_cle_dram_wr(cle
, buf
, 17, i
+ ptree
->start_node
,
212 PTREE_RAM
, CLE_CMD_WR
);
217 /* continue node index for key node */
218 memset(buf
, 0, sizeof(buf
));
219 for (j
= i
; j
< (ptree
->num_kn
+ ptree
->num_dn
); j
++) {
220 xgene_cle_kn_to_hw(&kn
[j
- ptree
->num_dn
], buf
);
221 ret
= xgene_cle_dram_wr(cle
, buf
, 17, j
+ ptree
->start_node
,
222 PTREE_RAM
, CLE_CMD_WR
);
230 static int xgene_cle_setup_ptree(struct xgene_enet_pdata
*pdata
,
231 struct xgene_enet_cle
*cle
)
235 ret
= xgene_cle_setup_node(pdata
, cle
);
239 ret
= xgene_cle_setup_dbptr(pdata
, cle
);
243 xgene_cle_enable_ptree(pdata
, cle
);
248 static void xgene_cle_setup_def_dbptr(struct xgene_enet_pdata
*pdata
,
249 struct xgene_enet_cle
*enet_cle
,
250 struct xgene_cle_dbptr
*dbptr
,
251 u32 index
, u8 priority
)
253 void __iomem
*base
= enet_cle
->base
;
254 void __iomem
*base_addr
;
255 u32 buf
[CLE_DRAM_REGS
];
259 memset(buf
, 0, sizeof(buf
));
260 xgene_cle_dbptr_to_hw(pdata
, dbptr
, buf
);
262 for (i
= 0; i
< enet_cle
->parsers
; i
++) {
263 if (enet_cle
->active_parser
!= PARSER_ALL
) {
264 offset
= enet_cle
->active_parser
*
267 offset
= i
* CLE_PORT_OFFSET
;
270 base_addr
= base
+ DFCLSRESDB00
+ offset
;
271 for (j
= 0; j
< 6; j
++)
272 iowrite32(buf
[j
], base_addr
+ (j
* 4));
274 def_cls
= ((priority
& 0x7) << 10) | (index
& 0x3ff);
275 iowrite32(def_cls
, base
+ DFCLSRESDBPTR0
+ offset
);
279 static int xgene_cle_set_rss_sband(struct xgene_enet_cle
*cle
)
281 u32 idx
= CLE_PKTRAM_SIZE
/ sizeof(u32
);
282 u32 mac_hdr_len
= ETH_HLEN
;
288 /* Sideband: IPV4/TCP packets */
289 hdr_len
= (mac_hdr_len
<< 5) | ipv4_ihl
;
290 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4
, XGENE_CLE_TCP
, hdr_len
, ®
);
293 /* Sideband: IPv4/UDP packets */
294 hdr_len
= (mac_hdr_len
<< 5) | ipv4_ihl
;
295 xgene_cle_sband_to_hw(1, XGENE_CLE_IPV4
, XGENE_CLE_UDP
, hdr_len
, ®
);
296 sband
|= (reg
<< 16);
298 ret
= xgene_cle_dram_wr(cle
, &sband
, 1, idx
, PKT_RAM
, CLE_CMD_WR
);
302 /* Sideband: IPv4/RAW packets */
303 hdr_len
= (mac_hdr_len
<< 5) | ipv4_ihl
;
304 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4
, XGENE_CLE_OTHER
,
308 /* Sideband: Ethernet II/RAW packets */
309 hdr_len
= (mac_hdr_len
<< 5);
310 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4
, XGENE_CLE_OTHER
,
312 sband
|= (reg
<< 16);
314 ret
= xgene_cle_dram_wr(cle
, &sband
, 1, idx
+ 1, PKT_RAM
, CLE_CMD_WR
);
321 static int xgene_cle_set_rss_skeys(struct xgene_enet_cle
*cle
)
323 u32 secret_key_ipv4
[4]; /* 16 Bytes*/
326 get_random_bytes(secret_key_ipv4
, 16);
327 ret
= xgene_cle_dram_wr(cle
, secret_key_ipv4
, 4, 0,
328 RSS_IPV4_HASH_SKEY
, CLE_CMD_WR
);
332 static int xgene_cle_set_rss_idt(struct xgene_enet_pdata
*pdata
)
334 u32 fpsel
, dstqid
, nfpsel
, idt_reg
, idx
;
338 for (i
= 0; i
< XGENE_CLE_IDT_ENTRIES
; i
++) {
339 idx
= i
% pdata
->rxq_cnt
;
340 pool_id
= pdata
->rx_ring
[idx
]->buf_pool
->id
;
341 fpsel
= xgene_enet_ring_bufnum(pool_id
) - 0x20;
342 dstqid
= xgene_enet_dst_ring_num(pdata
->rx_ring
[idx
]);
346 xgene_cle_idt_to_hw(dstqid
, fpsel
, nfpsel
, &idt_reg
);
347 ret
= xgene_cle_dram_wr(&pdata
->cle
, &idt_reg
, 1, i
,
348 RSS_IDT
, CLE_CMD_WR
);
353 ret
= xgene_cle_set_rss_skeys(&pdata
->cle
);
360 static int xgene_cle_setup_rss(struct xgene_enet_pdata
*pdata
)
362 struct xgene_enet_cle
*cle
= &pdata
->cle
;
363 void __iomem
*base
= cle
->base
;
367 offset
= CLE_PORT_OFFSET
;
368 for (i
= 0; i
< cle
->parsers
; i
++) {
369 if (cle
->active_parser
!= PARSER_ALL
)
370 offset
= cle
->active_parser
* CLE_PORT_OFFSET
;
372 offset
= i
* CLE_PORT_OFFSET
;
375 val
= (RSS_IPV4_12B
<< 1) | 0x1;
376 writel(val
, base
+ RSS_CTRL0
+ offset
);
379 /* setup sideband data */
380 ret
= xgene_cle_set_rss_sband(cle
);
384 /* setup indirection table */
385 ret
= xgene_cle_set_rss_idt(pdata
);
392 static int xgene_enet_cle_init(struct xgene_enet_pdata
*pdata
)
394 struct xgene_enet_cle
*enet_cle
= &pdata
->cle
;
395 struct xgene_cle_dbptr dbptr
[DB_MAX_PTRS
];
396 struct xgene_cle_ptree_branch
*br
;
397 u32 def_qid
, def_fpsel
, pool_id
;
398 struct xgene_cle_ptree
*ptree
;
399 struct xgene_cle_ptree_kn kn
;
401 struct xgene_cle_ptree_ewdn ptree_dn
[] = {
408 .byte_store
= NO_BYTE
,
409 .search_byte_store
= NO_BYTE
,
410 .result_pointer
= DB_RES_DROP
,
416 .next_packet_pointer
= 22,
420 .next_node
= PKT_PROT_NODE
,
427 .next_packet_pointer
= 262,
431 .next_node
= LAST_NODE
,
444 .byte_store
= NO_BYTE
,
445 .search_byte_store
= NO_BYTE
,
446 .result_pointer
= DB_RES_DROP
,
452 .next_packet_pointer
= 26,
456 .next_node
= RSS_IPV4_TCP_NODE
,
464 .next_packet_pointer
= 26,
468 .next_node
= RSS_IPV4_UDP_NODE
,
475 .next_packet_pointer
= 260,
479 .next_node
= LAST_NODE
,
487 /* RSS_IPV4_TCP_NODE */
492 .byte_store
= NO_BYTE
,
493 .search_byte_store
= BOTH_BYTES
,
494 .result_pointer
= DB_RES_DROP
,
500 .next_packet_pointer
= 28,
504 .next_node
= RSS_IPV4_TCP_NODE
,
512 .next_packet_pointer
= 30,
516 .next_node
= RSS_IPV4_TCP_NODE
,
524 .next_packet_pointer
= 32,
528 .next_node
= RSS_IPV4_TCP_NODE
,
536 .next_packet_pointer
= 34,
540 .next_node
= RSS_IPV4_TCP_NODE
,
548 .next_packet_pointer
= 36,
552 .next_node
= RSS_IPV4_TCP_NODE
,
560 .next_packet_pointer
= 256,
564 .next_node
= LAST_NODE
,
572 /* RSS_IPV4_UDP_NODE */
577 .byte_store
= NO_BYTE
,
578 .search_byte_store
= BOTH_BYTES
,
579 .result_pointer
= DB_RES_DROP
,
585 .next_packet_pointer
= 28,
589 .next_node
= RSS_IPV4_UDP_NODE
,
597 .next_packet_pointer
= 30,
601 .next_node
= RSS_IPV4_UDP_NODE
,
609 .next_packet_pointer
= 32,
613 .next_node
= RSS_IPV4_UDP_NODE
,
621 .next_packet_pointer
= 34,
625 .next_node
= RSS_IPV4_UDP_NODE
,
633 .next_packet_pointer
= 36,
637 .next_node
= RSS_IPV4_UDP_NODE
,
645 .next_packet_pointer
= 256,
649 .next_node
= LAST_NODE
,
662 .byte_store
= NO_BYTE
,
663 .search_byte_store
= NO_BYTE
,
664 .result_pointer
= DB_RES_DROP
,
669 .next_packet_pointer
= 0,
673 .next_node
= MAX_NODES
,
682 ptree
= &enet_cle
->ptree
;
683 ptree
->start_pkt
= 12; /* Ethertype */
684 if (pdata
->phy_mode
== PHY_INTERFACE_MODE_XGMII
) {
685 ret
= xgene_cle_setup_rss(pdata
);
687 netdev_err(pdata
->ndev
, "RSS initialization failed\n");
691 br
= &ptree_dn
[PKT_PROT_NODE
].branch
[0];
693 br
->next_packet_pointer
= 260;
694 br
->next_node
= LAST_NODE
;
699 def_qid
= xgene_enet_dst_ring_num(pdata
->rx_ring
[0]);
700 pool_id
= pdata
->rx_ring
[0]->buf_pool
->id
;
701 def_fpsel
= xgene_enet_ring_bufnum(pool_id
) - 0x20;
703 memset(dbptr
, 0, sizeof(struct xgene_cle_dbptr
) * DB_MAX_PTRS
);
704 dbptr
[DB_RES_ACCEPT
].fpsel
= def_fpsel
;
705 dbptr
[DB_RES_ACCEPT
].dstqid
= def_qid
;
706 dbptr
[DB_RES_ACCEPT
].cle_priority
= 1;
708 dbptr
[DB_RES_DEF
].fpsel
= def_fpsel
;
709 dbptr
[DB_RES_DEF
].dstqid
= def_qid
;
710 dbptr
[DB_RES_DEF
].cle_priority
= 7;
711 xgene_cle_setup_def_dbptr(pdata
, enet_cle
, &dbptr
[DB_RES_DEF
],
714 dbptr
[DB_RES_DROP
].drop
= 1;
716 memset(&kn
, 0, sizeof(kn
));
719 kn
.key
[0].priority
= 0;
720 kn
.key
[0].result_pointer
= DB_RES_ACCEPT
;
722 ptree
->dn
= ptree_dn
;
724 ptree
->dbptr
= dbptr
;
725 ptree
->num_dn
= MAX_NODES
;
727 ptree
->num_dbptr
= DB_MAX_PTRS
;
729 return xgene_cle_setup_ptree(pdata
, enet_cle
);
732 struct xgene_cle_ops xgene_cle3in_ops
= {
733 .cle_init
= xgene_enet_cle_init
,