drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Ravi Patel <rapatel@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "xgene_enet_main.h"
  23 #include "xgene_enet_hw.h"
  24
  25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
  26 {
  27         u32 *ring_cfg = ring->state;
  28         u64 addr = ring->dma;
  29         enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
  30
  31         ring_cfg[4] |= (1 << SELTHRSH_POS) &
  32                         CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
  33         ring_cfg[3] |= ACCEPTLERR;
  34         ring_cfg[2] |= QCOHERENT;
  35
  36         addr >>= 8;
  37         ring_cfg[2] |= (addr << RINGADDRL_POS) &
  38                         CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
  39         addr >>= RINGADDRL_LEN;
  40         ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
  41         ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
  42                         CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
  43 }
  44
  45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
  46 {
  47         u32 *ring_cfg = ring->state;
  48         bool is_bufpool;
  49         u32 val;
  50
  51         is_bufpool = xgene_enet_is_bufpool(ring->id);
  52         val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
  53         ring_cfg[4] |= (val << RINGTYPE_POS) &
  54                         CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
  55
  56         if (is_bufpool) {
  57                 ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
  58                                 CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
  59         }
  60 }
  61
  62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
  63 {
  64         u32 *ring_cfg = ring->state;
  65
  66         ring_cfg[3] |= RECOMBBUF;
  67         ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
  68                         CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
  69         ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
  70 }
  71
  72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
  73                                  u32 offset, u32 data)
  74 {
  75         struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  76
  77         iowrite32(data, pdata->ring_csr_addr + offset);
  78 }
  79
  80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
  81                                  u32 offset, u32 *data)
  82 {
  83         struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  84
  85         *data = ioread32(pdata->ring_csr_addr + offset);
  86 }
  87
  88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
  89 {
  90         struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  91         int i;
  92
  93         xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
  94         for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
  95                 xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
  96                                      ring->state[i]);
  97         }
  98 }
  99
 100 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
 101 {
 102         memset(ring->state, 0, sizeof(ring->state));
 103         xgene_enet_write_ring_state(ring);
 104 }
 105
 106 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
 107 {
 108         xgene_enet_ring_set_type(ring);
 109
 110         if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
 111             xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
 112                 xgene_enet_ring_set_recombbuf(ring);
 113
 114         xgene_enet_ring_init(ring);
 115         xgene_enet_write_ring_state(ring);
 116 }
 117
 118 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
 119 {
 120         u32 ring_id_val, ring_id_buf;
 121         bool is_bufpool;
 122
 123         is_bufpool = xgene_enet_is_bufpool(ring->id);
 124
 125         ring_id_val = ring->id & GENMASK(9, 0);
 126         ring_id_val |= OVERWRITE;
 127
 128         ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
 129         ring_id_buf |= PREFETCH_BUF_EN;
 130         if (is_bufpool)
 131                 ring_id_buf |= IS_BUFFER_POOL;
 132
 133         xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
 134         xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
 135 }
 136
 137 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
 138 {
 139         u32 ring_id;
 140
 141         ring_id = ring->id | OVERWRITE;
 142         xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
 143         xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
 144 }
 145
 146 static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
 147                                     struct xgene_enet_desc_ring *ring)
 148 {
 149         u32 size = ring->size;
 150         u32 i, data;
 151         bool is_bufpool;
 152
 153         xgene_enet_clr_ring_state(ring);
 154         xgene_enet_set_ring_state(ring);
 155         xgene_enet_set_ring_id(ring);
 156
 157         ring->slots = xgene_enet_get_numslots(ring->id, size);
 158
 159         is_bufpool = xgene_enet_is_bufpool(ring->id);
 160         if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
 161                 return ring;
 162
 163         for (i = 0; i < ring->slots; i++)
 164                 xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
 165
 166         xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
 167         data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
 168         xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
 169
 170         return ring;
 171 }
 172
 173 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
 174 {
 175         u32 data;
 176         bool is_bufpool;
 177
 178         is_bufpool = xgene_enet_is_bufpool(ring->id);
 179         if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
 180                 goto out;
 181
 182         xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
 183         data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
 184         xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
 185
 186 out:
 187         xgene_enet_clr_desc_ring_id(ring);
 188         xgene_enet_clr_ring_state(ring);
 189 }
 190
 191 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
 192 {
 193         iowrite32(count, ring->cmd);
 194 }
 195
 196 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
 197 {
 198         u32 __iomem *cmd_base = ring->cmd_base;
 199         u32 ring_state, num_msgs;
 200
 201         ring_state = ioread32(&cmd_base[1]);
 202         num_msgs = GET_VAL(NUMMSGSINQ, ring_state);
 203
 204         return num_msgs;
 205 }
 206
 207 static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
 208 {
 209         u32 data = 0x7777;
 210
 211         xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);
 212         xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);
 213         xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16);
 214         xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40);
 215         xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);
 216 }
 217
 218 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
 219                             struct xgene_enet_pdata *pdata,
 220                             enum xgene_enet_err_code status)
 221 {
 222         struct rtnl_link_stats64 *stats = &pdata->stats;
 223
 224         switch (status) {
 225         case INGRESS_CRC:
 226                 stats->rx_crc_errors++;
 227                 break;
 228         case INGRESS_CHECKSUM:
 229         case INGRESS_CHECKSUM_COMPUTE:
 230                 stats->rx_errors++;
 231                 break;
 232         case INGRESS_TRUNC_FRAME:
 233                 stats->rx_frame_errors++;
 234                 break;
 235         case INGRESS_PKT_LEN:
 236                 stats->rx_length_errors++;
 237                 break;
 238         case INGRESS_PKT_UNDER:
 239                 stats->rx_frame_errors++;
 240                 break;
 241         case INGRESS_FIFO_OVERRUN:
 242                 stats->rx_fifo_errors++;
 243                 break;
 244         default:
 245                 break;
 246         }
 247 }
 248
 249 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
 250                               u32 offset, u32 val)
 251 {
 252         void __iomem *addr = pdata->eth_csr_addr + offset;
 253
 254         iowrite32(val, addr);
 255 }
 256
 257 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
 258                                   u32 offset, u32 val)
 259 {
 260         void __iomem *addr = pdata->eth_ring_if_addr + offset;
 261
 262         iowrite32(val, addr);
 263 }
 264
 265 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
 266                                    u32 offset, u32 val)
 267 {
 268         void __iomem *addr = pdata->eth_diag_csr_addr + offset;
 269
 270         iowrite32(val, addr);
 271 }
 272
 273 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
 274                                   u32 offset, u32 val)
 275 {
 276         void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
 277
 278         iowrite32(val, addr);
 279 }
 280
 281 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
 282                                    void __iomem *cmd, void __iomem *cmd_done,
 283                                    u32 wr_addr, u32 wr_data)
 284 {
 285         u32 done;
 286         u8 wait = 10;
 287
 288         iowrite32(wr_addr, addr);
 289         iowrite32(wr_data, wr);
 290         iowrite32(XGENE_ENET_WR_CMD, cmd);
 291
 292         /* wait for write command to complete */
 293         while (!(done = ioread32(cmd_done)) && wait--)
 294                 udelay(1);
 295
 296         if (!done)
 297                 return false;
 298
 299         iowrite32(0, cmd);
 300
 301         return true;
 302 }
 303
 304 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata,
 305                                   u32 wr_addr, u32 wr_data)
 306 {
 307         void __iomem *addr, *wr, *cmd, *cmd_done;
 308
 309         addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
 310         wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
 311         cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
 312         cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
 313
 314         if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
 315                 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
 316                            wr_addr);
 317 }
 318
 319 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
 320                               u32 offset, u32 *val)
 321 {
 322         void __iomem *addr = pdata->eth_csr_addr + offset;
 323
 324         *val = ioread32(addr);
 325 }
 326
 327 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
 328                                    u32 offset, u32 *val)
 329 {
 330         void __iomem *addr = pdata->eth_diag_csr_addr + offset;
 331
 332         *val = ioread32(addr);
 333 }
 334
 335 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
 336                                   u32 offset, u32 *val)
 337 {
 338         void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
 339
 340         *val = ioread32(addr);
 341 }
 342
 343 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
 344                                    void __iomem *cmd, void __iomem *cmd_done,
 345                                    u32 rd_addr, u32 *rd_data)
 346 {
 347         u32 done;
 348         u8 wait = 10;
 349
 350         iowrite32(rd_addr, addr);
 351         iowrite32(XGENE_ENET_RD_CMD, cmd);
 352
 353         /* wait for read command to complete */
 354         while (!(done = ioread32(cmd_done)) && wait--)
 355                 udelay(1);
 356
 357         if (!done)
 358                 return false;
 359
 360         *rd_data = ioread32(rd);
 361         iowrite32(0, cmd);
 362
 363         return true;
 364 }
 365
 366 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata,
 367                                   u32 rd_addr, u32 *rd_data)
 368 {
 369         void __iomem *addr, *rd, *cmd, *cmd_done;
 370
 371         addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
 372         rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
 373         cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
 374         cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
 375
 376         if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
 377                 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
 378                            rd_addr);
 379 }
 380
 381 static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id,
 382                                u32 reg, u16 data)
 383 {
 384         u32 addr = 0, wr_data = 0;
 385         u32 done;
 386         u8 wait = 10;
 387
 388         PHY_ADDR_SET(&addr, phy_id);
 389         REG_ADDR_SET(&addr, reg);
 390         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
 391
 392         PHY_CONTROL_SET(&wr_data, data);
 393         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data);
 394         do {
 395                 usleep_range(5, 10);
 396                 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
 397         } while ((done & BUSY_MASK) && wait--);
 398
 399         if (done & BUSY_MASK) {
 400                 netdev_err(pdata->ndev, "MII_MGMT write failed\n");
 401                 return -EBUSY;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata,
 408                               u8 phy_id, u32 reg)
 409 {
 410         u32 addr = 0;
 411         u32 data, done;
 412         u8 wait = 10;
 413
 414         PHY_ADDR_SET(&addr, phy_id);
 415         REG_ADDR_SET(&addr, reg);
 416         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
 417         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
 418         do {
 419                 usleep_range(5, 10);
 420                 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
 421         } while ((done & BUSY_MASK) && wait--);
 422
 423         if (done & BUSY_MASK) {
 424                 netdev_err(pdata->ndev, "MII_MGMT read failed\n");
 425                 return -EBUSY;
 426         }
 427
 428         xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data);
 429         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0);
 430
 431         return data;
 432 }
 433
 434 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
 435 {
 436         u32 addr0, addr1;
 437         u8 *dev_addr = pdata->ndev->dev_addr;
 438
 439         addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
 440                 (dev_addr[1] << 8) | dev_addr[0];
 441         addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
 442
 443         xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
 444         xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
 445 }
 446
 447 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
 448 {
 449         struct net_device *ndev = pdata->ndev;
 450         u32 data;
 451         u8 wait = 10;
 452
 453         xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
 454         do {
 455                 usleep_range(100, 110);
 456                 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
 457         } while ((data != 0xffffffff) && wait--);
 458
 459         if (data != 0xffffffff) {
 460                 netdev_err(ndev, "Failed to release memory from shutdown\n");
 461                 return -ENODEV;
 462         }
 463
 464         return 0;
 465 }
 466
 467 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
 468 {
 469         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
 470         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
 471 }
 472
 473 static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
 474 {
 475         struct device *dev = &pdata->pdev->dev;
 476
 477         if (dev->of_node) {
 478                 struct clk *parent = clk_get_parent(pdata->clk);
 479
 480                 switch (pdata->phy_speed) {
 481                 case SPEED_10:
 482                         clk_set_rate(parent, 2500000);
 483                         break;
 484                 case SPEED_100:
 485                         clk_set_rate(parent, 25000000);
 486                         break;
 487                 default:
 488                         clk_set_rate(parent, 125000000);
 489                         break;
 490                 }
 491         }
 492 #ifdef CONFIG_ACPI
 493         else {
 494                 switch (pdata->phy_speed) {
 495                 case SPEED_10:
 496                         acpi_evaluate_object(ACPI_HANDLE(dev),
 497                                              "S10", NULL, NULL);
 498                         break;
 499                 case SPEED_100:
 500                         acpi_evaluate_object(ACPI_HANDLE(dev),
 501                                              "S100", NULL, NULL);
 502                         break;
 503                 default:
 504                         acpi_evaluate_object(ACPI_HANDLE(dev),
 505                                              "S1G", NULL, NULL);
 506                         break;
 507                 }
 508         }
 509 #endif
 510 }
 511
 512 static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
 513 {
 514         struct device *dev = &pdata->pdev->dev;
 515         u32 value, mc2;
 516         u32 intf_ctl, rgmii;
 517         u32 icm0, icm2;
 518
 519         xgene_gmac_reset(pdata);
 520
 521         xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
 522         xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
 523         xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2);
 524         xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl);
 525         xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
 526
 527         switch (pdata->phy_speed) {
 528         case SPEED_10:
 529                 ENET_INTERFACE_MODE2_SET(&mc2, 1);
 530                 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
 531                 CFG_MACMODE_SET(&icm0, 0);
 532                 CFG_WAITASYNCRD_SET(&icm2, 500);
 533                 rgmii &= ~CFG_SPEED_1250;
 534                 break;
 535         case SPEED_100:
 536                 ENET_INTERFACE_MODE2_SET(&mc2, 1);
 537                 intf_ctl &= ~ENET_GHD_MODE;
 538                 intf_ctl |= ENET_LHD_MODE;
 539                 CFG_MACMODE_SET(&icm0, 1);
 540                 CFG_WAITASYNCRD_SET(&icm2, 80);
 541                 rgmii &= ~CFG_SPEED_1250;
 542                 break;
 543         default:
 544                 ENET_INTERFACE_MODE2_SET(&mc2, 2);
 545                 intf_ctl &= ~ENET_LHD_MODE;
 546                 intf_ctl |= ENET_GHD_MODE;
 547                 CFG_MACMODE_SET(&icm0, 2);
 548                 CFG_WAITASYNCRD_SET(&icm2, 0);
 549                 if (dev->of_node) {
 550                         CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
 551                         CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
 552                 }
 553                 rgmii |= CFG_SPEED_1250;
 554
 555                 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
 556                 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
 557                 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
 558                 break;
 559         }
 560
 561         mc2 |= FULL_DUPLEX2 | PAD_CRC;
 562         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
 563         xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
 564
 565         xgene_gmac_set_mac_addr(pdata);
 566
 567         /* Adjust MDC clock frequency */
 568         xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value);
 569         MGMT_CLOCK_SEL_SET(&value, 7);
 570         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
 571
 572         /* Enable drop if bufpool not available */
 573         xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
 574         value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
 575         xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
 576
 577         /* Rtype should be copied from FP */
 578         xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
 579         xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
 580         xgene_enet_configure_clock(pdata);
 581
 582         /* Rx-Tx traffic resume */
 583         xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
 584
 585         xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
 586         xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
 587
 588         xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
 589         value &= ~TX_DV_GATE_EN0;
 590         value &= ~RX_DV_GATE_EN0;
 591         value |= RESUME_RX0;
 592         xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
 593
 594         xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
 595 }
 596
 597 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
 598 {
 599         u32 val = 0xffffffff;
 600
 601         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
 602         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
 603         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
 604         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
 605 }
 606
 607 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
 608                                   u32 dst_ring_num, u16 bufpool_id)
 609 {
 610         u32 cb;
 611         u32 fpsel;
 612
 613         fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
 614
 615         xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
 616         cb |= CFG_CLE_BYPASS_EN0;
 617         CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
 618         xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
 619
 620         xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
 621         CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
 622         CFG_CLE_FPSEL0_SET(&cb, fpsel);
 623         xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
 624 }
 625
 626 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
 627 {
 628         u32 data;
 629
 630         xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
 631         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
 632 }
 633
 634 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
 635 {
 636         u32 data;
 637
 638         xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
 639         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
 640 }
 641
 642 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
 643 {
 644         u32 data;
 645
 646         xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
 647         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
 648 }
 649
 650 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
 651 {
 652         u32 data;
 653
 654         xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
 655         xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
 656 }
 657
 658 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
 659 {
 660         if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
 661                 return false;
 662
 663         if (ioread32(p->ring_csr_addr + SRST_ADDR))
 664                 return false;
 665
 666         return true;
 667 }
 668
 669 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
 670 {
 671         u32 val;
 672
 673         if (!xgene_ring_mgr_init(pdata))
 674                 return -ENODEV;
 675
 676         if (!IS_ERR(pdata->clk)) {
 677                 clk_prepare_enable(pdata->clk);
 678                 clk_disable_unprepare(pdata->clk);
 679                 clk_prepare_enable(pdata->clk);
 680                 xgene_enet_ecc_init(pdata);
 681         }
 682         xgene_enet_config_ring_if_assoc(pdata);
 683
 684         /* Enable auto-incr for scanning */
 685         xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val);
 686         val |= SCAN_AUTO_INCR;
 687         MGMT_CLOCK_SEL_SET(&val, 1);
 688         xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val);
 689
 690         return 0;
 691 }
 692
 693 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
 694 {
 695         if (!IS_ERR(pdata->clk))
 696                 clk_disable_unprepare(pdata->clk);
 697 }
 698
 699 static int xgene_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 700 {
 701         struct xgene_enet_pdata *pdata = bus->priv;
 702         u32 val;
 703
 704         val = xgene_mii_phy_read(pdata, mii_id, regnum);
 705         netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n",
 706                    mii_id, regnum, val);
 707
 708         return val;
 709 }
 710
 711 static int xgene_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 712                                  u16 val)
 713 {
 714         struct xgene_enet_pdata *pdata = bus->priv;
 715
 716         netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n",
 717                    mii_id, regnum, val);
 718         return xgene_mii_phy_write(pdata, mii_id, regnum, val);
 719 }
 720
 721 static void xgene_enet_adjust_link(struct net_device *ndev)
 722 {
 723         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 724         struct phy_device *phydev = pdata->phy_dev;
 725
 726         if (phydev->link) {
 727                 if (pdata->phy_speed != phydev->speed) {
 728                         pdata->phy_speed = phydev->speed;
 729                         xgene_gmac_init(pdata);
 730                         xgene_gmac_rx_enable(pdata);
 731                         xgene_gmac_tx_enable(pdata);
 732                         phy_print_status(phydev);
 733                 }
 734         } else {
 735                 xgene_gmac_rx_disable(pdata);
 736                 xgene_gmac_tx_disable(pdata);
 737                 pdata->phy_speed = SPEED_UNKNOWN;
 738                 phy_print_status(phydev);
 739         }
 740 }
 741
 742 static int xgene_enet_phy_connect(struct net_device *ndev)
 743 {
 744         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 745         struct device_node *phy_np;
 746         struct phy_device *phy_dev;
 747         struct device *dev = &pdata->pdev->dev;
 748
 749         if (dev->of_node) {
 750                 phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
 751                 if (!phy_np) {
 752                         netdev_dbg(ndev, "No phy-handle found in DT\n");
 753                         return -ENODEV;
 754                 }
 755
 756                 phy_dev = of_phy_connect(ndev, phy_np, &xgene_enet_adjust_link,
 757                                          0, pdata->phy_mode);
 758                 if (!phy_dev) {
 759                         netdev_err(ndev, "Could not connect to PHY\n");
 760                         return -ENODEV;
 761                 }
 762
 763                 pdata->phy_dev = phy_dev;
 764         } else {
 765                 phy_dev = pdata->phy_dev;
 766
 767                 if (!phy_dev ||
 768                     phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
 769                                        pdata->phy_mode)) {
 770                         netdev_err(ndev, "Could not connect to PHY\n");
 771                         return  -ENODEV;
 772                 }
 773         }
 774
 775         pdata->phy_speed = SPEED_UNKNOWN;
 776         phy_dev->supported &= ~SUPPORTED_10baseT_Half &
 777                               ~SUPPORTED_100baseT_Half &
 778                               ~SUPPORTED_1000baseT_Half;
 779         phy_dev->advertising = phy_dev->supported;
 780
 781         return 0;
 782 }
 783
 784 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
 785                                   struct mii_bus *mdio)
 786 {
 787         struct device *dev = &pdata->pdev->dev;
 788         struct net_device *ndev = pdata->ndev;
 789         struct phy_device *phy;
 790         struct device_node *child_np;
 791         struct device_node *mdio_np = NULL;
 792         int ret;
 793         u32 phy_id;
 794
 795         if (dev->of_node) {
 796                 for_each_child_of_node(dev->of_node, child_np) {
 797                         if (of_device_is_compatible(child_np,
 798                                                     "apm,xgene-mdio")) {
 799                                 mdio_np = child_np;
 800                                 break;
 801                         }
 802                 }
 803
 804                 if (!mdio_np) {
 805                         netdev_dbg(ndev, "No mdio node in the dts\n");
 806                         return -ENXIO;
 807                 }
 808
 809                 return of_mdiobus_register(mdio, mdio_np);
 810         }
 811
 812         /* Mask out all PHYs from auto probing. */
 813         mdio->phy_mask = ~0;
 814
 815         /* Register the MDIO bus */
 816         ret = mdiobus_register(mdio);
 817         if (ret)
 818                 return ret;
 819
 820         ret = device_property_read_u32(dev, "phy-channel", &phy_id);
 821         if (ret)
 822                 ret = device_property_read_u32(dev, "phy-addr", &phy_id);
 823         if (ret)
 824                 return -EINVAL;
 825
 826         phy = get_phy_device(mdio, phy_id, false);
 827         if (!phy || IS_ERR(phy))
 828                 return -EIO;
 829
 830         ret = phy_device_register(phy);
 831         if (ret)
 832                 phy_device_free(phy);
 833         else
 834                 pdata->phy_dev = phy;
 835
 836         return ret;
 837 }
 838
 839 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
 840 {
 841         struct net_device *ndev = pdata->ndev;
 842         struct mii_bus *mdio_bus;
 843         int ret;
 844
 845         mdio_bus = mdiobus_alloc();
 846         if (!mdio_bus)
 847                 return -ENOMEM;
 848
 849         mdio_bus->name = "APM X-Gene MDIO bus";
 850         mdio_bus->read = xgene_enet_mdio_read;
 851         mdio_bus->write = xgene_enet_mdio_write;
 852         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
 853                  ndev->name);
 854
 855         mdio_bus->priv = pdata;
 856         mdio_bus->parent = &ndev->dev;
 857
 858         ret = xgene_mdiobus_register(pdata, mdio_bus);
 859         if (ret) {
 860                 netdev_err(ndev, "Failed to register MDIO bus\n");
 861                 mdiobus_free(mdio_bus);
 862                 return ret;
 863         }
 864         pdata->mdio_bus = mdio_bus;
 865
 866         ret = xgene_enet_phy_connect(ndev);
 867         if (ret)
 868                 xgene_enet_mdio_remove(pdata);
 869
 870         return ret;
 871 }
 872
 873 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
 874 {
 875         if (pdata->phy_dev)
 876                 phy_disconnect(pdata->phy_dev);
 877
 878         mdiobus_unregister(pdata->mdio_bus);
 879         mdiobus_free(pdata->mdio_bus);
 880         pdata->mdio_bus = NULL;
 881 }
 882
 883 const struct xgene_mac_ops xgene_gmac_ops = {
 884         .init = xgene_gmac_init,
 885         .reset = xgene_gmac_reset,
 886         .rx_enable = xgene_gmac_rx_enable,
 887         .tx_enable = xgene_gmac_tx_enable,
 888         .rx_disable = xgene_gmac_rx_disable,
 889         .tx_disable = xgene_gmac_tx_disable,
 890         .set_mac_addr = xgene_gmac_set_mac_addr,
 891 };
 892
 893 const struct xgene_port_ops xgene_gport_ops = {
 894         .reset = xgene_enet_reset,
 895         .cle_bypass = xgene_enet_cle_bypass,
 896         .shutdown = xgene_gport_shutdown,
 897 };
 898
 899 struct xgene_ring_ops xgene_ring1_ops = {
 900         .num_ring_config = NUM_RING_CONFIG,
 901         .num_ring_id_shift = 6,
 902         .setup = xgene_enet_setup_ring,
 903         .clear = xgene_enet_clear_ring,
 904         .wr_cmd = xgene_enet_wr_cmd,
 905         .len = xgene_enet_ring_len,
 906         .coalesce = xgene_enet_setup_coalescing,
 907 };