1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
23 #include "xgene_enet_hw.h"
25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring
*ring
)
27 u32
*ring_cfg
= ring
->state
;
29 enum xgene_enet_ring_cfgsize cfgsize
= ring
->cfgsize
;
31 ring_cfg
[4] |= (1 << SELTHRSH_POS
) &
32 CREATE_MASK(SELTHRSH_POS
, SELTHRSH_LEN
);
33 ring_cfg
[3] |= ACCEPTLERR
;
34 ring_cfg
[2] |= QCOHERENT
;
37 ring_cfg
[2] |= (addr
<< RINGADDRL_POS
) &
38 CREATE_MASK_ULL(RINGADDRL_POS
, RINGADDRL_LEN
);
39 addr
>>= RINGADDRL_LEN
;
40 ring_cfg
[3] |= addr
& CREATE_MASK_ULL(RINGADDRH_POS
, RINGADDRH_LEN
);
41 ring_cfg
[3] |= ((u32
)cfgsize
<< RINGSIZE_POS
) &
42 CREATE_MASK(RINGSIZE_POS
, RINGSIZE_LEN
);
45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring
*ring
)
47 u32
*ring_cfg
= ring
->state
;
51 is_bufpool
= xgene_enet_is_bufpool(ring
->id
);
52 val
= (is_bufpool
) ? RING_BUFPOOL
: RING_REGULAR
;
53 ring_cfg
[4] |= (val
<< RINGTYPE_POS
) &
54 CREATE_MASK(RINGTYPE_POS
, RINGTYPE_LEN
);
57 ring_cfg
[3] |= (BUFPOOL_MODE
<< RINGMODE_POS
) &
58 CREATE_MASK(RINGMODE_POS
, RINGMODE_LEN
);
62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring
*ring
)
64 u32
*ring_cfg
= ring
->state
;
66 ring_cfg
[3] |= RECOMBBUF
;
67 ring_cfg
[3] |= (0xf << RECOMTIMEOUTL_POS
) &
68 CREATE_MASK(RECOMTIMEOUTL_POS
, RECOMTIMEOUTL_LEN
);
69 ring_cfg
[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS
, RECOMTIMEOUTH_LEN
);
72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring
*ring
,
75 struct xgene_enet_pdata
*pdata
= netdev_priv(ring
->ndev
);
77 iowrite32(data
, pdata
->ring_csr_addr
+ offset
);
80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring
*ring
,
81 u32 offset
, u32
*data
)
83 struct xgene_enet_pdata
*pdata
= netdev_priv(ring
->ndev
);
85 *data
= ioread32(pdata
->ring_csr_addr
+ offset
);
88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring
*ring
)
90 struct xgene_enet_pdata
*pdata
= netdev_priv(ring
->ndev
);
93 xgene_enet_ring_wr32(ring
, CSR_RING_CONFIG
, ring
->num
);
94 for (i
= 0; i
< pdata
->ring_ops
->num_ring_config
; i
++) {
95 xgene_enet_ring_wr32(ring
, CSR_RING_WR_BASE
+ (i
* 4),
100 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring
*ring
)
102 memset(ring
->state
, 0, sizeof(ring
->state
));
103 xgene_enet_write_ring_state(ring
);
106 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring
*ring
)
108 xgene_enet_ring_set_type(ring
);
110 if (xgene_enet_ring_owner(ring
->id
) == RING_OWNER_ETH0
)
111 xgene_enet_ring_set_recombbuf(ring
);
113 xgene_enet_ring_init(ring
);
114 xgene_enet_write_ring_state(ring
);
117 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring
*ring
)
119 u32 ring_id_val
, ring_id_buf
;
122 is_bufpool
= xgene_enet_is_bufpool(ring
->id
);
124 ring_id_val
= ring
->id
& GENMASK(9, 0);
125 ring_id_val
|= OVERWRITE
;
127 ring_id_buf
= (ring
->num
<< 9) & GENMASK(18, 9);
128 ring_id_buf
|= PREFETCH_BUF_EN
;
130 ring_id_buf
|= IS_BUFFER_POOL
;
132 xgene_enet_ring_wr32(ring
, CSR_RING_ID
, ring_id_val
);
133 xgene_enet_ring_wr32(ring
, CSR_RING_ID_BUF
, ring_id_buf
);
136 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring
*ring
)
140 ring_id
= ring
->id
| OVERWRITE
;
141 xgene_enet_ring_wr32(ring
, CSR_RING_ID
, ring_id
);
142 xgene_enet_ring_wr32(ring
, CSR_RING_ID_BUF
, 0);
145 static struct xgene_enet_desc_ring
*xgene_enet_setup_ring(
146 struct xgene_enet_desc_ring
*ring
)
148 u32 size
= ring
->size
;
152 xgene_enet_clr_ring_state(ring
);
153 xgene_enet_set_ring_state(ring
);
154 xgene_enet_set_ring_id(ring
);
156 ring
->slots
= xgene_enet_get_numslots(ring
->id
, size
);
158 is_bufpool
= xgene_enet_is_bufpool(ring
->id
);
159 if (is_bufpool
|| xgene_enet_ring_owner(ring
->id
) != RING_OWNER_CPU
)
162 for (i
= 0; i
< ring
->slots
; i
++)
163 xgene_enet_mark_desc_slot_empty(&ring
->raw_desc
[i
]);
165 xgene_enet_ring_rd32(ring
, CSR_RING_NE_INT_MODE
, &data
);
166 data
|= BIT(31 - xgene_enet_ring_bufnum(ring
->id
));
167 xgene_enet_ring_wr32(ring
, CSR_RING_NE_INT_MODE
, data
);
172 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring
*ring
)
177 is_bufpool
= xgene_enet_is_bufpool(ring
->id
);
178 if (is_bufpool
|| xgene_enet_ring_owner(ring
->id
) != RING_OWNER_CPU
)
181 xgene_enet_ring_rd32(ring
, CSR_RING_NE_INT_MODE
, &data
);
182 data
&= ~BIT(31 - xgene_enet_ring_bufnum(ring
->id
));
183 xgene_enet_ring_wr32(ring
, CSR_RING_NE_INT_MODE
, data
);
186 xgene_enet_clr_desc_ring_id(ring
);
187 xgene_enet_clr_ring_state(ring
);
190 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring
*ring
, int count
)
192 iowrite32(count
, ring
->cmd
);
195 static u32
xgene_enet_ring_len(struct xgene_enet_desc_ring
*ring
)
197 u32 __iomem
*cmd_base
= ring
->cmd_base
;
198 u32 ring_state
, num_msgs
;
200 ring_state
= ioread32(&cmd_base
[1]);
201 num_msgs
= GET_VAL(NUMMSGSINQ
, ring_state
);
206 void xgene_enet_parse_error(struct xgene_enet_desc_ring
*ring
,
207 struct xgene_enet_pdata
*pdata
,
208 enum xgene_enet_err_code status
)
210 struct rtnl_link_stats64
*stats
= &pdata
->stats
;
214 stats
->rx_crc_errors
++;
216 case INGRESS_CHECKSUM
:
217 case INGRESS_CHECKSUM_COMPUTE
:
220 case INGRESS_TRUNC_FRAME
:
221 stats
->rx_frame_errors
++;
223 case INGRESS_PKT_LEN
:
224 stats
->rx_length_errors
++;
226 case INGRESS_PKT_UNDER
:
227 stats
->rx_frame_errors
++;
229 case INGRESS_FIFO_OVERRUN
:
230 stats
->rx_fifo_errors
++;
237 static void xgene_enet_wr_csr(struct xgene_enet_pdata
*pdata
,
240 void __iomem
*addr
= pdata
->eth_csr_addr
+ offset
;
242 iowrite32(val
, addr
);
245 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata
*pdata
,
248 void __iomem
*addr
= pdata
->eth_ring_if_addr
+ offset
;
250 iowrite32(val
, addr
);
253 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata
*pdata
,
256 void __iomem
*addr
= pdata
->eth_diag_csr_addr
+ offset
;
258 iowrite32(val
, addr
);
261 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata
*pdata
,
264 void __iomem
*addr
= pdata
->mcx_mac_csr_addr
+ offset
;
266 iowrite32(val
, addr
);
269 static bool xgene_enet_wr_indirect(void __iomem
*addr
, void __iomem
*wr
,
270 void __iomem
*cmd
, void __iomem
*cmd_done
,
271 u32 wr_addr
, u32 wr_data
)
276 iowrite32(wr_addr
, addr
);
277 iowrite32(wr_data
, wr
);
278 iowrite32(XGENE_ENET_WR_CMD
, cmd
);
280 /* wait for write command to complete */
281 while (!(done
= ioread32(cmd_done
)) && wait
--)
292 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata
*pdata
,
293 u32 wr_addr
, u32 wr_data
)
295 void __iomem
*addr
, *wr
, *cmd
, *cmd_done
;
297 addr
= pdata
->mcx_mac_addr
+ MAC_ADDR_REG_OFFSET
;
298 wr
= pdata
->mcx_mac_addr
+ MAC_WRITE_REG_OFFSET
;
299 cmd
= pdata
->mcx_mac_addr
+ MAC_COMMAND_REG_OFFSET
;
300 cmd_done
= pdata
->mcx_mac_addr
+ MAC_COMMAND_DONE_REG_OFFSET
;
302 if (!xgene_enet_wr_indirect(addr
, wr
, cmd
, cmd_done
, wr_addr
, wr_data
))
303 netdev_err(pdata
->ndev
, "MCX mac write failed, addr: %04x\n",
307 static void xgene_enet_rd_csr(struct xgene_enet_pdata
*pdata
,
308 u32 offset
, u32
*val
)
310 void __iomem
*addr
= pdata
->eth_csr_addr
+ offset
;
312 *val
= ioread32(addr
);
315 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata
*pdata
,
316 u32 offset
, u32
*val
)
318 void __iomem
*addr
= pdata
->eth_diag_csr_addr
+ offset
;
320 *val
= ioread32(addr
);
323 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata
*pdata
,
324 u32 offset
, u32
*val
)
326 void __iomem
*addr
= pdata
->mcx_mac_csr_addr
+ offset
;
328 *val
= ioread32(addr
);
331 static bool xgene_enet_rd_indirect(void __iomem
*addr
, void __iomem
*rd
,
332 void __iomem
*cmd
, void __iomem
*cmd_done
,
333 u32 rd_addr
, u32
*rd_data
)
338 iowrite32(rd_addr
, addr
);
339 iowrite32(XGENE_ENET_RD_CMD
, cmd
);
341 /* wait for read command to complete */
342 while (!(done
= ioread32(cmd_done
)) && wait
--)
348 *rd_data
= ioread32(rd
);
354 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata
*pdata
,
355 u32 rd_addr
, u32
*rd_data
)
357 void __iomem
*addr
, *rd
, *cmd
, *cmd_done
;
359 addr
= pdata
->mcx_mac_addr
+ MAC_ADDR_REG_OFFSET
;
360 rd
= pdata
->mcx_mac_addr
+ MAC_READ_REG_OFFSET
;
361 cmd
= pdata
->mcx_mac_addr
+ MAC_COMMAND_REG_OFFSET
;
362 cmd_done
= pdata
->mcx_mac_addr
+ MAC_COMMAND_DONE_REG_OFFSET
;
364 if (!xgene_enet_rd_indirect(addr
, rd
, cmd
, cmd_done
, rd_addr
, rd_data
))
365 netdev_err(pdata
->ndev
, "MCX mac read failed, addr: %04x\n",
369 static int xgene_mii_phy_write(struct xgene_enet_pdata
*pdata
, int phy_id
,
372 u32 addr
= 0, wr_data
= 0;
376 PHY_ADDR_SET(&addr
, phy_id
);
377 REG_ADDR_SET(&addr
, reg
);
378 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_ADDRESS_ADDR
, addr
);
380 PHY_CONTROL_SET(&wr_data
, data
);
381 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_CONTROL_ADDR
, wr_data
);
384 xgene_enet_rd_mcx_mac(pdata
, MII_MGMT_INDICATORS_ADDR
, &done
);
385 } while ((done
& BUSY_MASK
) && wait
--);
387 if (done
& BUSY_MASK
) {
388 netdev_err(pdata
->ndev
, "MII_MGMT write failed\n");
395 static int xgene_mii_phy_read(struct xgene_enet_pdata
*pdata
,
402 PHY_ADDR_SET(&addr
, phy_id
);
403 REG_ADDR_SET(&addr
, reg
);
404 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_ADDRESS_ADDR
, addr
);
405 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_COMMAND_ADDR
, READ_CYCLE_MASK
);
408 xgene_enet_rd_mcx_mac(pdata
, MII_MGMT_INDICATORS_ADDR
, &done
);
409 } while ((done
& BUSY_MASK
) && wait
--);
411 if (done
& BUSY_MASK
) {
412 netdev_err(pdata
->ndev
, "MII_MGMT read failed\n");
416 xgene_enet_rd_mcx_mac(pdata
, MII_MGMT_STATUS_ADDR
, &data
);
417 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_COMMAND_ADDR
, 0);
422 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata
*pdata
)
425 u8
*dev_addr
= pdata
->ndev
->dev_addr
;
427 addr0
= (dev_addr
[3] << 24) | (dev_addr
[2] << 16) |
428 (dev_addr
[1] << 8) | dev_addr
[0];
429 addr1
= (dev_addr
[5] << 24) | (dev_addr
[4] << 16);
431 xgene_enet_wr_mcx_mac(pdata
, STATION_ADDR0_ADDR
, addr0
);
432 xgene_enet_wr_mcx_mac(pdata
, STATION_ADDR1_ADDR
, addr1
);
435 static int xgene_enet_ecc_init(struct xgene_enet_pdata
*pdata
)
437 struct net_device
*ndev
= pdata
->ndev
;
441 xgene_enet_wr_diag_csr(pdata
, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR
, 0x0);
443 usleep_range(100, 110);
444 xgene_enet_rd_diag_csr(pdata
, ENET_BLOCK_MEM_RDY_ADDR
, &data
);
445 } while ((data
!= 0xffffffff) && wait
--);
447 if (data
!= 0xffffffff) {
448 netdev_err(ndev
, "Failed to release memory from shutdown\n");
455 static void xgene_gmac_reset(struct xgene_enet_pdata
*pdata
)
457 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, SOFT_RESET1
);
458 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, 0);
461 static void xgene_gmac_init(struct xgene_enet_pdata
*pdata
)
467 xgene_gmac_reset(pdata
);
469 xgene_enet_rd_mcx_csr(pdata
, ICM_CONFIG0_REG_0_ADDR
, &icm0
);
470 xgene_enet_rd_mcx_csr(pdata
, ICM_CONFIG2_REG_0_ADDR
, &icm2
);
471 xgene_enet_rd_mcx_mac(pdata
, MAC_CONFIG_2_ADDR
, &mc2
);
472 xgene_enet_rd_mcx_mac(pdata
, INTERFACE_CONTROL_ADDR
, &intf_ctl
);
473 xgene_enet_rd_csr(pdata
, RGMII_REG_0_ADDR
, &rgmii
);
475 switch (pdata
->phy_speed
) {
477 ENET_INTERFACE_MODE2_SET(&mc2
, 1);
478 CFG_MACMODE_SET(&icm0
, 0);
479 CFG_WAITASYNCRD_SET(&icm2
, 500);
480 rgmii
&= ~CFG_SPEED_1250
;
483 ENET_INTERFACE_MODE2_SET(&mc2
, 1);
484 intf_ctl
|= ENET_LHD_MODE
;
485 CFG_MACMODE_SET(&icm0
, 1);
486 CFG_WAITASYNCRD_SET(&icm2
, 80);
487 rgmii
&= ~CFG_SPEED_1250
;
490 ENET_INTERFACE_MODE2_SET(&mc2
, 2);
491 intf_ctl
|= ENET_GHD_MODE
;
492 CFG_TXCLK_MUXSEL0_SET(&rgmii
, 4);
493 xgene_enet_rd_csr(pdata
, DEBUG_REG_ADDR
, &value
);
494 value
|= CFG_BYPASS_UNISEC_TX
| CFG_BYPASS_UNISEC_RX
;
495 xgene_enet_wr_csr(pdata
, DEBUG_REG_ADDR
, value
);
500 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_2_ADDR
, mc2
);
501 xgene_enet_wr_mcx_mac(pdata
, INTERFACE_CONTROL_ADDR
, intf_ctl
);
503 xgene_gmac_set_mac_addr(pdata
);
505 /* Adjust MDC clock frequency */
506 xgene_enet_rd_mcx_mac(pdata
, MII_MGMT_CONFIG_ADDR
, &value
);
507 MGMT_CLOCK_SEL_SET(&value
, 7);
508 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_CONFIG_ADDR
, value
);
510 /* Enable drop if bufpool not available */
511 xgene_enet_rd_csr(pdata
, RSIF_CONFIG_REG_ADDR
, &value
);
512 value
|= CFG_RSIF_FPBUFF_TIMEOUT_EN
;
513 xgene_enet_wr_csr(pdata
, RSIF_CONFIG_REG_ADDR
, value
);
515 /* Rtype should be copied from FP */
516 xgene_enet_wr_csr(pdata
, RSIF_RAM_DBG_REG0_ADDR
, 0);
517 xgene_enet_wr_csr(pdata
, RGMII_REG_0_ADDR
, rgmii
);
519 /* Rx-Tx traffic resume */
520 xgene_enet_wr_csr(pdata
, CFG_LINK_AGGR_RESUME_0_ADDR
, TX_PORT0
);
522 xgene_enet_wr_mcx_csr(pdata
, ICM_CONFIG0_REG_0_ADDR
, icm0
);
523 xgene_enet_wr_mcx_csr(pdata
, ICM_CONFIG2_REG_0_ADDR
, icm2
);
525 xgene_enet_rd_mcx_csr(pdata
, RX_DV_GATE_REG_0_ADDR
, &value
);
526 value
&= ~TX_DV_GATE_EN0
;
527 value
&= ~RX_DV_GATE_EN0
;
529 xgene_enet_wr_mcx_csr(pdata
, RX_DV_GATE_REG_0_ADDR
, value
);
531 xgene_enet_wr_csr(pdata
, CFG_BYPASS_ADDR
, RESUME_TX
);
534 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata
*pdata
)
536 u32 val
= 0xffffffff;
538 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIWQASSOC_ADDR
, val
);
539 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIFPQASSOC_ADDR
, val
);
540 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIQMLITEWQASSOC_ADDR
, val
);
541 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR
, val
);
544 static void xgene_enet_cle_bypass(struct xgene_enet_pdata
*pdata
,
545 u32 dst_ring_num
, u16 bufpool_id
)
550 fpsel
= xgene_enet_ring_bufnum(bufpool_id
) - 0x20;
552 xgene_enet_rd_csr(pdata
, CLE_BYPASS_REG0_0_ADDR
, &cb
);
553 cb
|= CFG_CLE_BYPASS_EN0
;
554 CFG_CLE_IP_PROTOCOL0_SET(&cb
, 3);
555 xgene_enet_wr_csr(pdata
, CLE_BYPASS_REG0_0_ADDR
, cb
);
557 xgene_enet_rd_csr(pdata
, CLE_BYPASS_REG1_0_ADDR
, &cb
);
558 CFG_CLE_DSTQID0_SET(&cb
, dst_ring_num
);
559 CFG_CLE_FPSEL0_SET(&cb
, fpsel
);
560 xgene_enet_wr_csr(pdata
, CLE_BYPASS_REG1_0_ADDR
, cb
);
563 static void xgene_gmac_rx_enable(struct xgene_enet_pdata
*pdata
)
567 xgene_enet_rd_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, &data
);
568 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, data
| RX_EN
);
571 static void xgene_gmac_tx_enable(struct xgene_enet_pdata
*pdata
)
575 xgene_enet_rd_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, &data
);
576 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, data
| TX_EN
);
579 static void xgene_gmac_rx_disable(struct xgene_enet_pdata
*pdata
)
583 xgene_enet_rd_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, &data
);
584 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, data
& ~RX_EN
);
587 static void xgene_gmac_tx_disable(struct xgene_enet_pdata
*pdata
)
591 xgene_enet_rd_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, &data
);
592 xgene_enet_wr_mcx_mac(pdata
, MAC_CONFIG_1_ADDR
, data
& ~TX_EN
);
595 bool xgene_ring_mgr_init(struct xgene_enet_pdata
*p
)
597 if (!ioread32(p
->ring_csr_addr
+ CLKEN_ADDR
))
600 if (ioread32(p
->ring_csr_addr
+ SRST_ADDR
))
606 static int xgene_enet_reset(struct xgene_enet_pdata
*pdata
)
610 if (!xgene_ring_mgr_init(pdata
))
613 if (!IS_ERR(pdata
->clk
)) {
614 clk_prepare_enable(pdata
->clk
);
615 clk_disable_unprepare(pdata
->clk
);
616 clk_prepare_enable(pdata
->clk
);
617 xgene_enet_ecc_init(pdata
);
619 xgene_enet_config_ring_if_assoc(pdata
);
621 /* Enable auto-incr for scanning */
622 xgene_enet_rd_mcx_mac(pdata
, MII_MGMT_CONFIG_ADDR
, &val
);
623 val
|= SCAN_AUTO_INCR
;
624 MGMT_CLOCK_SEL_SET(&val
, 1);
625 xgene_enet_wr_mcx_mac(pdata
, MII_MGMT_CONFIG_ADDR
, val
);
630 static void xgene_gport_shutdown(struct xgene_enet_pdata
*pdata
)
632 if (!IS_ERR(pdata
->clk
))
633 clk_disable_unprepare(pdata
->clk
);
636 static int xgene_enet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
638 struct xgene_enet_pdata
*pdata
= bus
->priv
;
641 val
= xgene_mii_phy_read(pdata
, mii_id
, regnum
);
642 netdev_dbg(pdata
->ndev
, "mdio_rd: bus=%d reg=%d val=%x\n",
643 mii_id
, regnum
, val
);
648 static int xgene_enet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
651 struct xgene_enet_pdata
*pdata
= bus
->priv
;
653 netdev_dbg(pdata
->ndev
, "mdio_wr: bus=%d reg=%d val=%x\n",
654 mii_id
, regnum
, val
);
655 return xgene_mii_phy_write(pdata
, mii_id
, regnum
, val
);
658 static void xgene_enet_adjust_link(struct net_device
*ndev
)
660 struct xgene_enet_pdata
*pdata
= netdev_priv(ndev
);
661 struct phy_device
*phydev
= pdata
->phy_dev
;
664 if (pdata
->phy_speed
!= phydev
->speed
) {
665 pdata
->phy_speed
= phydev
->speed
;
666 xgene_gmac_init(pdata
);
667 xgene_gmac_rx_enable(pdata
);
668 xgene_gmac_tx_enable(pdata
);
669 phy_print_status(phydev
);
672 xgene_gmac_rx_disable(pdata
);
673 xgene_gmac_tx_disable(pdata
);
674 pdata
->phy_speed
= SPEED_UNKNOWN
;
675 phy_print_status(phydev
);
679 static int xgene_enet_phy_connect(struct net_device
*ndev
)
681 struct xgene_enet_pdata
*pdata
= netdev_priv(ndev
);
682 struct device_node
*phy_np
;
683 struct phy_device
*phy_dev
;
684 struct device
*dev
= &pdata
->pdev
->dev
;
687 phy_np
= of_parse_phandle(dev
->of_node
, "phy-handle", 0);
689 netdev_dbg(ndev
, "No phy-handle found in DT\n");
692 pdata
->phy_dev
= of_phy_find_device(phy_np
);
695 phy_dev
= pdata
->phy_dev
;
698 phy_connect_direct(ndev
, phy_dev
, &xgene_enet_adjust_link
,
700 netdev_err(ndev
, "Could not connect to PHY\n");
704 pdata
->phy_speed
= SPEED_UNKNOWN
;
705 phy_dev
->supported
&= ~SUPPORTED_10baseT_Half
&
706 ~SUPPORTED_100baseT_Half
&
707 ~SUPPORTED_1000baseT_Half
;
708 phy_dev
->advertising
= phy_dev
->supported
;
713 static int xgene_mdiobus_register(struct xgene_enet_pdata
*pdata
,
714 struct mii_bus
*mdio
)
716 struct device
*dev
= &pdata
->pdev
->dev
;
717 struct net_device
*ndev
= pdata
->ndev
;
718 struct phy_device
*phy
;
719 struct device_node
*child_np
;
720 struct device_node
*mdio_np
= NULL
;
725 for_each_child_of_node(dev
->of_node
, child_np
) {
726 if (of_device_is_compatible(child_np
,
734 netdev_dbg(ndev
, "No mdio node in the dts\n");
738 return of_mdiobus_register(mdio
, mdio_np
);
741 /* Mask out all PHYs from auto probing. */
744 /* Register the MDIO bus */
745 ret
= mdiobus_register(mdio
);
749 ret
= device_property_read_u32(dev
, "phy-channel", &phy_id
);
751 ret
= device_property_read_u32(dev
, "phy-addr", &phy_id
);
755 phy
= get_phy_device(mdio
, phy_id
, false);
756 if (!phy
|| IS_ERR(phy
))
759 ret
= phy_device_register(phy
);
761 phy_device_free(phy
);
763 pdata
->phy_dev
= phy
;
768 int xgene_enet_mdio_config(struct xgene_enet_pdata
*pdata
)
770 struct net_device
*ndev
= pdata
->ndev
;
771 struct mii_bus
*mdio_bus
;
774 mdio_bus
= mdiobus_alloc();
778 mdio_bus
->name
= "APM X-Gene MDIO bus";
779 mdio_bus
->read
= xgene_enet_mdio_read
;
780 mdio_bus
->write
= xgene_enet_mdio_write
;
781 snprintf(mdio_bus
->id
, MII_BUS_ID_SIZE
, "%s-%s", "xgene-mii",
784 mdio_bus
->priv
= pdata
;
785 mdio_bus
->parent
= &ndev
->dev
;
787 ret
= xgene_mdiobus_register(pdata
, mdio_bus
);
789 netdev_err(ndev
, "Failed to register MDIO bus\n");
790 mdiobus_free(mdio_bus
);
793 pdata
->mdio_bus
= mdio_bus
;
795 ret
= xgene_enet_phy_connect(ndev
);
797 xgene_enet_mdio_remove(pdata
);
802 void xgene_enet_mdio_remove(struct xgene_enet_pdata
*pdata
)
805 phy_disconnect(pdata
->phy_dev
);
807 mdiobus_unregister(pdata
->mdio_bus
);
808 mdiobus_free(pdata
->mdio_bus
);
809 pdata
->mdio_bus
= NULL
;
812 struct xgene_mac_ops xgene_gmac_ops
= {
813 .init
= xgene_gmac_init
,
814 .reset
= xgene_gmac_reset
,
815 .rx_enable
= xgene_gmac_rx_enable
,
816 .tx_enable
= xgene_gmac_tx_enable
,
817 .rx_disable
= xgene_gmac_rx_disable
,
818 .tx_disable
= xgene_gmac_tx_disable
,
819 .set_mac_addr
= xgene_gmac_set_mac_addr
,
822 struct xgene_port_ops xgene_gport_ops
= {
823 .reset
= xgene_enet_reset
,
824 .cle_bypass
= xgene_enet_cle_bypass
,
825 .shutdown
= xgene_gport_shutdown
,
828 struct xgene_ring_ops xgene_ring1_ops
= {
829 .num_ring_config
= NUM_RING_CONFIG
,
830 .num_ring_id_shift
= 6,
831 .setup
= xgene_enet_setup_ring
,
832 .clear
= xgene_enet_clear_ring
,
833 .wr_cmd
= xgene_enet_wr_cmd
,
834 .len
= xgene_enet_ring_len
,