drivers/net/ethernet/apm/xgene/xgene_enet_main.h

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Ravi Patel <rapatel@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef __XGENE_ENET_MAIN_H__
  23 #define __XGENE_ENET_MAIN_H__
  24
  25 #include <linux/acpi.h>
  26 #include <linux/clk.h>
  27 #include <linux/efi.h>
  28 #include <linux/irq.h>
  29 #include <linux/io.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_mdio.h>
  33 #include <linux/module.h>
  34 #include <net/ip.h>
  35 #include <linux/prefetch.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/phy.h>
  38 #include "xgene_enet_hw.h"
  39 #include "xgene_enet_cle.h"
  40 #include "xgene_enet_ring2.h"
  41 #include "../../../phy/mdio-xgene.h"
  42
  43 #define XGENE_DRV_VERSION       "v1.0"
  44 #define XGENE_ENET_STD_MTU      1536
  45 #define XGENE_ENET_MAX_MTU      9600
  46 #define SKB_BUFFER_SIZE         (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
  47
  48 #define BUFLEN_16K      (16 * 1024)
  49 #define NUM_PKT_BUF     1024
  50 #define NUM_BUFPOOL     32
  51 #define NUM_NXTBUFPOOL  8
  52 #define MAX_EXP_BUFFS   256
  53 #define NUM_MSS_REG     4
  54 #define XGENE_MIN_ENET_FRAME_SIZE       60
  55
  56 #define XGENE_MAX_ENET_IRQ      16
  57 #define XGENE_NUM_RX_RING       8
  58 #define XGENE_NUM_TX_RING       8
  59 #define XGENE_NUM_TXC_RING      8
  60
  61 #define START_CPU_BUFNUM_0      0
  62 #define START_ETH_BUFNUM_0      2
  63 #define START_BP_BUFNUM_0       0x22
  64 #define START_RING_NUM_0        8
  65 #define START_CPU_BUFNUM_1      12
  66 #define START_ETH_BUFNUM_1      10
  67 #define START_BP_BUFNUM_1       0x2A
  68 #define START_RING_NUM_1        264
  69
  70 #define XG_START_CPU_BUFNUM_1   12
  71 #define XG_START_ETH_BUFNUM_1   2
  72 #define XG_START_BP_BUFNUM_1    0x22
  73 #define XG_START_RING_NUM_1     264
  74
  75 #define X2_START_CPU_BUFNUM_0   0
  76 #define X2_START_ETH_BUFNUM_0   0
  77 #define X2_START_BP_BUFNUM_0    0x20
  78 #define X2_START_RING_NUM_0     0
  79 #define X2_START_CPU_BUFNUM_1   0xc
  80 #define X2_START_ETH_BUFNUM_1   0
  81 #define X2_START_BP_BUFNUM_1    0x20
  82 #define X2_START_RING_NUM_1     256
  83
  84 #define IRQ_ID_SIZE             16
  85
  86 #define PHY_POLL_LINK_ON        (10 * HZ)
  87 #define PHY_POLL_LINK_OFF       (PHY_POLL_LINK_ON / 5)
  88
  89 enum xgene_enet_id {
  90         XGENE_ENET1 = 1,
  91         XGENE_ENET2
  92 };
  93
  94 enum xgene_enet_buf_len {
  95         SIZE_2K = 2048,
  96         SIZE_4K = 4096,
  97         SIZE_16K = 16384
  98 };
  99
 100 /* software context of a descriptor ring */
 101 struct xgene_enet_desc_ring {
 102         struct net_device *ndev;
 103         u16 id;
 104         u16 num;
 105         u16 head;
 106         u16 tail;
 107         u16 exp_buf_tail;
 108         u16 slots;
 109         u16 irq;
 110         char irq_name[IRQ_ID_SIZE];
 111         u32 size;
 112         u32 state[X2_NUM_RING_CONFIG];
 113         void __iomem *cmd_base;
 114         void __iomem *cmd;
 115         dma_addr_t dma;
 116         dma_addr_t irq_mbox_dma;
 117         void *irq_mbox_addr;
 118         u16 dst_ring_num;
 119         u16 nbufpool;
 120         int npagepool;
 121         u8 index;
 122         u32 flags;
 123         struct sk_buff *(*rx_skb);
 124         struct sk_buff *(*cp_skb);
 125         dma_addr_t *frag_dma_addr;
 126         struct page *(*frag_page);
 127         enum xgene_enet_ring_cfgsize cfgsize;
 128         struct xgene_enet_desc_ring *cp_ring;
 129         struct xgene_enet_desc_ring *buf_pool;
 130         struct xgene_enet_desc_ring *page_pool;
 131         struct napi_struct napi;
 132         union {
 133                 void *desc_addr;
 134                 struct xgene_enet_raw_desc *raw_desc;
 135                 struct xgene_enet_raw_desc16 *raw_desc16;
 136         };
 137         __le64 *exp_bufs;
 138         u64 tx_packets;
 139         u64 tx_bytes;
 140         u64 rx_packets;
 141         u64 rx_bytes;
 142         u64 rx_dropped;
 143         u64 rx_errors;
 144         u64 rx_length_errors;
 145         u64 rx_crc_errors;
 146         u64 rx_frame_errors;
 147         u64 rx_fifo_errors;
 148 };
 149
 150 struct xgene_mac_ops {
 151         void (*init)(struct xgene_enet_pdata *pdata);
 152         void (*reset)(struct xgene_enet_pdata *pdata);
 153         void (*tx_enable)(struct xgene_enet_pdata *pdata);
 154         void (*rx_enable)(struct xgene_enet_pdata *pdata);
 155         void (*tx_disable)(struct xgene_enet_pdata *pdata);
 156         void (*rx_disable)(struct xgene_enet_pdata *pdata);
 157         void (*set_speed)(struct xgene_enet_pdata *pdata);
 158         void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
 159         void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
 160         void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
 161         void (*link_state)(struct work_struct *work);
 162 };
 163
 164 struct xgene_port_ops {
 165         int (*reset)(struct xgene_enet_pdata *pdata);
 166         void (*clear)(struct xgene_enet_pdata *pdata,
 167                       struct xgene_enet_desc_ring *ring);
 168         void (*cle_bypass)(struct xgene_enet_pdata *pdata,
 169                            u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
 170         void (*shutdown)(struct xgene_enet_pdata *pdata);
 171 };
 172
 173 struct xgene_ring_ops {
 174         u8 num_ring_config;
 175         u8 num_ring_id_shift;
 176         struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
 177         void (*clear)(struct xgene_enet_desc_ring *);
 178         void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
 179         u32 (*len)(struct xgene_enet_desc_ring *);
 180         void (*coalesce)(struct xgene_enet_desc_ring *);
 181 };
 182
 183 struct xgene_cle_ops {
 184         int (*cle_init)(struct xgene_enet_pdata *pdata);
 185 };
 186
 187 /* ethernet private data */
 188 struct xgene_enet_pdata {
 189         struct net_device *ndev;
 190         struct mii_bus *mdio_bus;
 191         int phy_speed;
 192         struct clk *clk;
 193         struct platform_device *pdev;
 194         enum xgene_enet_id enet_id;
 195         struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
 196         struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
 197         u16 tx_level[XGENE_NUM_TX_RING];
 198         u16 txc_level[XGENE_NUM_TX_RING];
 199         char *dev_name;
 200         u32 rx_buff_cnt;
 201         u32 tx_qcnt_hi;
 202         u32 irqs[XGENE_MAX_ENET_IRQ];
 203         u8 rxq_cnt;
 204         u8 txq_cnt;
 205         u8 cq_cnt;
 206         void __iomem *eth_csr_addr;
 207         void __iomem *eth_ring_if_addr;
 208         void __iomem *eth_diag_csr_addr;
 209         void __iomem *mcx_mac_addr;
 210         void __iomem *mcx_mac_csr_addr;
 211         void __iomem *base_addr;
 212         void __iomem *pcs_addr;
 213         void __iomem *ring_csr_addr;
 214         void __iomem *ring_cmd_addr;
 215         int phy_mode;
 216         enum xgene_enet_rm rm;
 217         struct xgene_enet_cle cle;
 218         struct rtnl_link_stats64 stats;
 219         const struct xgene_mac_ops *mac_ops;
 220         const struct xgene_port_ops *port_ops;
 221         struct xgene_ring_ops *ring_ops;
 222         const struct xgene_cle_ops *cle_ops;
 223         struct delayed_work link_work;
 224         u32 port_id;
 225         u8 cpu_bufnum;
 226         u8 eth_bufnum;
 227         u8 bp_bufnum;
 228         u16 ring_num;
 229         u32 mss[NUM_MSS_REG];
 230         u32 mss_refcnt[NUM_MSS_REG];
 231         spinlock_t mss_lock;  /* mss lock */
 232         u8 tx_delay;
 233         u8 rx_delay;
 234         bool mdio_driver;
 235         struct gpio_desc *sfp_rdy;
 236         bool sfp_gpio_en;
 237 };
 238
 239 struct xgene_indirect_ctl {
 240         void __iomem *addr;
 241         void __iomem *ctl;
 242         void __iomem *cmd;
 243         void __iomem *cmd_done;
 244 };
 245
 246 static inline struct device *ndev_to_dev(struct net_device *ndev)
 247 {
 248         return ndev->dev.parent;
 249 }
 250
 251 static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
 252 {
 253         struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
 254
 255         return ((u16)pdata->rm << 10) | ring->num;
 256 }
 257
 258 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
 259
 260 #endif /* __XGENE_ENET_MAIN_H__ */