1 // SPDX-License-Identifier: GPL-2.0-only
3 * aQuantia Corporation Network Driver
4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
7 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
10 #include "../aq_hw_utils.h"
11 #include "../aq_ring.h"
12 #include "../aq_nic.h"
13 #include "hw_atl_a0.h"
14 #include "hw_atl_utils.h"
15 #include "hw_atl_llh.h"
16 #include "hw_atl_a0_internal.h"
18 #define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
22 .vecs = HW_ATL_A0_RSS_MAX, \
23 .tcs = HW_ATL_A0_TC_MAX, \
24 .rxd_alignment = 1U, \
25 .rxd_size = HW_ATL_A0_RXD_SIZE, \
26 .rxds_max = HW_ATL_A0_MAX_RXD, \
27 .rxds_min = HW_ATL_A0_MIN_RXD, \
28 .txd_alignment = 1U, \
29 .txd_size = HW_ATL_A0_TXD_SIZE, \
30 .txds_max = HW_ATL_A0_MAX_TXD, \
31 .txds_min = HW_ATL_A0_MIN_RXD, \
32 .txhwb_alignment = 4096U, \
33 .tx_rings = HW_ATL_A0_TX_RINGS, \
34 .rx_rings = HW_ATL_A0_RX_RINGS, \
35 .hw_features = NETIF_F_HW_CSUM | \
40 .hw_priv_flags = IFF_UNICAST_FLT, \
41 .flow_control = true, \
42 .mtu = HW_ATL_A0_MTU_JUMBO, \
43 .mac_regs_count = 88, \
44 .hw_alive_check_addr = 0x10U
46 const struct aq_hw_caps_s hw_atl_a0_caps_aqc100
= {
47 DEFAULT_A0_BOARD_BASIC_CAPABILITIES
,
48 .media_type
= AQ_HW_MEDIA_TYPE_FIBRE
,
49 .link_speed_msk
= AQ_NIC_RATE_5G
|
55 const struct aq_hw_caps_s hw_atl_a0_caps_aqc107
= {
56 DEFAULT_A0_BOARD_BASIC_CAPABILITIES
,
57 .media_type
= AQ_HW_MEDIA_TYPE_TP
,
58 .link_speed_msk
= AQ_NIC_RATE_10G
|
65 const struct aq_hw_caps_s hw_atl_a0_caps_aqc108
= {
66 DEFAULT_A0_BOARD_BASIC_CAPABILITIES
,
67 .media_type
= AQ_HW_MEDIA_TYPE_TP
,
68 .link_speed_msk
= AQ_NIC_RATE_5G
|
74 const struct aq_hw_caps_s hw_atl_a0_caps_aqc109
= {
75 DEFAULT_A0_BOARD_BASIC_CAPABILITIES
,
76 .media_type
= AQ_HW_MEDIA_TYPE_TP
,
77 .link_speed_msk
= AQ_NIC_RATE_2GS
|
82 static int hw_atl_a0_hw_reset(struct aq_hw_s
*self
)
87 hw_atl_glb_glb_reg_res_dis_set(self
, 1U);
88 hw_atl_pci_pci_reg_res_dis_set(self
, 0U);
89 hw_atl_rx_rx_reg_res_dis_set(self
, 0U);
90 hw_atl_tx_tx_reg_res_dis_set(self
, 0U);
93 hw_atl_glb_soft_res_set(self
, 1);
95 /* check 10 times by 1ms */
96 err
= readx_poll_timeout_atomic(hw_atl_glb_soft_res_get
,
102 hw_atl_itr_irq_reg_res_dis_set(self
, 0U);
103 hw_atl_itr_res_irq_set(self
, 1U);
105 /* check 10 times by 1ms */
106 err
= readx_poll_timeout_atomic(hw_atl_itr_res_irq_get
,
112 self
->aq_fw_ops
->set_state(self
, MPI_RESET
);
114 err
= aq_hw_err_from_flags(self
);
120 static int hw_atl_a0_hw_qos_set(struct aq_hw_s
*self
)
124 unsigned int i_priority
= 0U;
125 bool is_rx_flow_control
= false;
127 /* TPS Descriptor rate init */
128 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self
, 0x0U
);
129 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self
, 0xA);
132 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self
, 0U);
134 /* TPS TC credits init */
135 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self
, 0U);
136 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self
, 0U);
138 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self
, 0xFFF, 0U);
139 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self
, 0x64, 0U);
140 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self
, 0x50, 0U);
141 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self
, 0x1E, 0U);
144 buff_size
= HW_ATL_A0_TXBUF_MAX
;
146 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
147 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self
,
149 (1024 / 32U) * 66U) /
151 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self
,
153 (1024 / 32U) * 50U) /
156 /* QoS Rx buf size per TC */
158 is_rx_flow_control
= (AQ_NIC_FC_RX
& self
->aq_nic_cfg
->flow_control
);
159 buff_size
= HW_ATL_A0_RXBUF_MAX
;
161 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
162 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self
,
164 (1024U / 32U) * 66U) /
166 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self
,
168 (1024U / 32U) * 50U) /
170 hw_atl_rpb_rx_xoff_en_per_tc_set(self
, is_rx_flow_control
? 1U : 0U, tc
);
172 /* QoS 802.1p priority -> TC mapping */
173 for (i_priority
= 8U; i_priority
--;)
174 hw_atl_rpf_rpb_user_priority_tc_map_set(self
, i_priority
, 0U);
176 return aq_hw_err_from_flags(self
);
179 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s
*self
,
180 struct aq_rss_parameters
*rss_params
)
182 struct aq_nic_cfg_s
*cfg
= self
->aq_nic_cfg
;
185 unsigned int addr
= 0U;
188 for (i
= 10, addr
= 0U; i
--; ++addr
) {
189 u32 key_data
= cfg
->is_rss
?
190 __swab32(rss_params
->hash_secret_key
[i
]) : 0U;
191 hw_atl_rpf_rss_key_wr_data_set(self
, key_data
);
192 hw_atl_rpf_rss_key_addr_set(self
, addr
);
193 hw_atl_rpf_rss_key_wr_en_set(self
, 1U);
194 err
= readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get
,
201 err
= aq_hw_err_from_flags(self
);
207 static int hw_atl_a0_hw_rss_set(struct aq_hw_s
*self
,
208 struct aq_rss_parameters
*rss_params
)
210 u8
*indirection_table
= rss_params
->indirection_table
;
212 u32 num_rss_queues
= max(1U, self
->aq_nic_cfg
->num_rss_queues
);
214 u16 bitary
[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX
*
215 HW_ATL_A0_RSS_REDIRECTION_BITS
/ 16U)];
218 memset(bitary
, 0, sizeof(bitary
));
220 for (i
= HW_ATL_A0_RSS_REDIRECTION_MAX
; i
--; ) {
221 (*(u32
*)(bitary
+ ((i
* 3U) / 16U))) |=
222 ((indirection_table
[i
] % num_rss_queues
) <<
226 for (i
= ARRAY_SIZE(bitary
); i
--;) {
227 hw_atl_rpf_rss_redir_tbl_wr_data_set(self
, bitary
[i
]);
228 hw_atl_rpf_rss_redir_tbl_addr_set(self
, i
);
229 hw_atl_rpf_rss_redir_wr_en_set(self
, 1U);
230 err
= readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get
,
237 err
= aq_hw_err_from_flags(self
);
243 static int hw_atl_a0_hw_offload_set(struct aq_hw_s
*self
,
244 struct aq_nic_cfg_s
*aq_nic_cfg
)
246 /* TX checksums offloads*/
247 hw_atl_tpo_ipv4header_crc_offload_en_set(self
, 1);
248 hw_atl_tpo_tcp_udp_crc_offload_en_set(self
, 1);
250 /* RX checksums offloads*/
251 hw_atl_rpo_ipv4header_crc_offload_en_set(self
, 1);
252 hw_atl_rpo_tcp_udp_crc_offload_en_set(self
, 1);
255 hw_atl_tdm_large_send_offload_en_set(self
, 0xFFFFFFFFU
);
257 return aq_hw_err_from_flags(self
);
260 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s
*self
)
262 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self
, 0x0FF6U
);
263 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self
, 0x0FF6U
);
264 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self
, 0x0F7FU
);
267 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
270 aq_hw_write_reg(self
, 0x00007040U
, IS_CHIP_FEATURE(TPO2
) ?
271 0x00010000U
: 0x00000000U
);
272 hw_atl_tdm_tx_dca_en_set(self
, 0U);
273 hw_atl_tdm_tx_dca_mode_set(self
, 0U);
275 hw_atl_tpb_tx_path_scp_ins_en_set(self
, 1U);
277 return aq_hw_err_from_flags(self
);
280 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s
*self
)
282 struct aq_nic_cfg_s
*cfg
= self
->aq_nic_cfg
;
285 /* Rx TC/RSS number config */
286 hw_atl_rpb_rpf_rx_traf_class_mode_set(self
, 1U);
288 /* Rx flow control */
289 hw_atl_rpb_rx_flow_ctl_mode_set(self
, 1U);
291 /* RSS Ring selection */
292 hw_atl_reg_rx_flr_rss_control1set(self
, cfg
->is_rss
?
293 0xB3333333U
: 0x00000000U
);
295 /* Multicast filters */
296 for (i
= HW_ATL_A0_MAC_MAX
; i
--;) {
297 hw_atl_rpfl2_uc_flr_en_set(self
, (i
== 0U) ? 1U : 0U, i
);
298 hw_atl_rpfl2unicast_flr_act_set(self
, 1U, i
);
301 hw_atl_reg_rx_flr_mcst_flr_msk_set(self
, 0x00000000U
);
302 hw_atl_reg_rx_flr_mcst_flr_set(self
, 0x00010FFFU
, 0U);
305 hw_atl_rpf_vlan_outer_etht_set(self
, 0x88A8U
);
306 hw_atl_rpf_vlan_inner_etht_set(self
, 0x8100U
);
307 hw_atl_rpf_vlan_prom_mode_en_set(self
, 1);
310 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
313 hw_atl_rpfl2broadcast_flr_act_set(self
, 1U);
314 hw_atl_rpfl2broadcast_count_threshold_set(self
, 0xFFFFU
& (~0U / 256U));
316 hw_atl_rdm_rx_dca_en_set(self
, 0U);
317 hw_atl_rdm_rx_dca_mode_set(self
, 0U);
319 return aq_hw_err_from_flags(self
);
322 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s
*self
, u8
*mac_addr
)
332 h
= (mac_addr
[0] << 8) | (mac_addr
[1]);
333 l
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
334 (mac_addr
[4] << 8) | mac_addr
[5];
336 hw_atl_rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_A0_MAC
);
337 hw_atl_rpfl2unicast_dest_addresslsw_set(self
, l
, HW_ATL_A0_MAC
);
338 hw_atl_rpfl2unicast_dest_addressmsw_set(self
, h
, HW_ATL_A0_MAC
);
339 hw_atl_rpfl2_uc_flr_en_set(self
, 1U, HW_ATL_A0_MAC
);
341 err
= aq_hw_err_from_flags(self
);
347 static int hw_atl_a0_hw_init(struct aq_hw_s
*self
, u8
*mac_addr
)
349 static u32 aq_hw_atl_igcr_table_
[4][2] = {
350 [AQ_HW_IRQ_INVALID
] = { 0x20000000U
, 0x20000000U
},
351 [AQ_HW_IRQ_LEGACY
] = { 0x20000080U
, 0x20000080U
},
352 [AQ_HW_IRQ_MSI
] = { 0x20000021U
, 0x20000025U
},
353 [AQ_HW_IRQ_MSIX
] = { 0x20000022U
, 0x20000026U
},
358 struct aq_nic_cfg_s
*aq_nic_cfg
= self
->aq_nic_cfg
;
360 hw_atl_a0_hw_init_tx_path(self
);
361 hw_atl_a0_hw_init_rx_path(self
);
363 hw_atl_a0_hw_mac_addr_set(self
, mac_addr
);
365 self
->aq_fw_ops
->set_link_speed(self
, aq_nic_cfg
->link_speed_msk
);
366 self
->aq_fw_ops
->set_state(self
, MPI_INIT
);
368 hw_atl_reg_tx_dma_debug_ctl_set(self
, 0x800000b8U
);
369 hw_atl_reg_tx_dma_debug_ctl_set(self
, 0x000000b8U
);
371 hw_atl_a0_hw_qos_set(self
);
372 hw_atl_a0_hw_rss_set(self
, &aq_nic_cfg
->aq_rss
);
373 hw_atl_a0_hw_rss_hash_set(self
, &aq_nic_cfg
->aq_rss
);
375 /* Reset link status and read out initial hardware counters */
376 self
->aq_link_status
.mbps
= 0;
377 self
->aq_fw_ops
->update_stats(self
);
379 err
= aq_hw_err_from_flags(self
);
384 hw_atl_reg_irq_glb_ctl_set(self
,
385 aq_hw_atl_igcr_table_
[aq_nic_cfg
->irq_type
]
386 [(aq_nic_cfg
->vecs
> 1U) ? 1 : 0]);
388 hw_atl_itr_irq_auto_masklsw_set(self
, aq_nic_cfg
->aq_hw_caps
->irq_mask
);
391 hw_atl_reg_gen_irq_map_set(self
,
392 ((HW_ATL_A0_ERR_INT
<< 0x18) | (1U << 0x1F)) |
393 ((HW_ATL_A0_ERR_INT
<< 0x10) | (1U << 0x17)) |
394 ((HW_ATL_A0_ERR_INT
<< 8) | (1U << 0xF)) |
395 ((HW_ATL_A0_ERR_INT
) | (1U << 0x7)), 0U);
397 hw_atl_a0_hw_offload_set(self
, aq_nic_cfg
);
403 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s
*self
,
404 struct aq_ring_s
*ring
)
406 hw_atl_tdm_tx_desc_en_set(self
, 1, ring
->idx
);
407 return aq_hw_err_from_flags(self
);
410 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s
*self
,
411 struct aq_ring_s
*ring
)
413 hw_atl_rdm_rx_desc_en_set(self
, 1, ring
->idx
);
414 return aq_hw_err_from_flags(self
);
417 static int hw_atl_a0_hw_start(struct aq_hw_s
*self
)
419 hw_atl_tpb_tx_buff_en_set(self
, 1);
420 hw_atl_rpb_rx_buff_en_set(self
, 1);
421 return aq_hw_err_from_flags(self
);
424 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s
*self
,
425 struct aq_ring_s
*ring
)
427 hw_atl_reg_tx_dma_desc_tail_ptr_set(self
, ring
->sw_tail
, ring
->idx
);
431 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s
*self
,
432 struct aq_ring_s
*ring
,
435 struct aq_ring_buff_s
*buff
= NULL
;
436 struct hw_atl_txd_s
*txd
= NULL
;
437 unsigned int buff_pa_len
= 0U;
438 unsigned int pkt_len
= 0U;
439 unsigned int frag_count
= 0U;
442 buff
= &ring
->buff_ring
[ring
->sw_tail
];
443 pkt_len
= (buff
->is_eop
&& buff
->is_sop
) ? buff
->len
: buff
->len_pkt
;
445 for (frag_count
= 0; frag_count
< frags
; frag_count
++) {
446 txd
= (struct hw_atl_txd_s
*)&ring
->dx_ring
[ring
->sw_tail
*
452 buff
= &ring
->buff_ring
[ring
->sw_tail
];
455 txd
->ctl
|= (buff
->len_l3
<< 31) |
456 (buff
->len_l2
<< 24) |
457 HW_ATL_A0_TXD_CTL_CMD_TCP
|
458 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC
;
459 txd
->ctl2
|= (buff
->mss
<< 16) |
460 (buff
->len_l4
<< 8) |
463 pkt_len
-= (buff
->len_l4
+
469 txd
->ctl
|= HW_ATL_A0_TXD_CTL_CMD_IPV6
;
471 buff_pa_len
= buff
->len
;
473 txd
->buf_addr
= buff
->pa
;
474 txd
->ctl
|= (HW_ATL_A0_TXD_CTL_BLEN
&
475 ((u32
)buff_pa_len
<< 4));
476 txd
->ctl
|= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD
;
478 txd
->ctl2
|= HW_ATL_A0_TXD_CTL2_LEN
& (pkt_len
<< 14);
481 txd
->ctl
|= HW_ATL_A0_TXD_CTL_CMD_LSO
;
482 txd
->ctl2
|= HW_ATL_A0_TXD_CTL2_CTX_EN
;
485 /* Tx checksum offloads */
487 txd
->ctl
|= HW_ATL_A0_TXD_CTL_CMD_IPCSO
;
489 if (buff
->is_udp_cso
|| buff
->is_tcp_cso
)
490 txd
->ctl
|= HW_ATL_A0_TXD_CTL_CMD_TUCSO
;
492 if (unlikely(buff
->is_eop
)) {
493 txd
->ctl
|= HW_ATL_A0_TXD_CTL_EOP
;
494 txd
->ctl
|= HW_ATL_A0_TXD_CTL_CMD_WB
;
499 ring
->sw_tail
= aq_ring_next_dx(ring
, ring
->sw_tail
);
502 hw_atl_a0_hw_tx_ring_tail_update(self
, ring
);
503 return aq_hw_err_from_flags(self
);
506 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s
*self
,
507 struct aq_ring_s
*aq_ring
,
508 struct aq_ring_param_s
*aq_ring_param
)
510 u32 dma_desc_addr_lsw
= (u32
)aq_ring
->dx_ring_pa
;
511 u32 dma_desc_addr_msw
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
513 hw_atl_rdm_rx_desc_en_set(self
, false, aq_ring
->idx
);
515 hw_atl_rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
517 hw_atl_reg_rx_dma_desc_base_addresslswset(self
, dma_desc_addr_lsw
,
520 hw_atl_reg_rx_dma_desc_base_addressmswset(self
,
524 hw_atl_rdm_rx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
526 hw_atl_rdm_rx_desc_data_buff_size_set(self
,
527 AQ_CFG_RX_FRAME_MAX
/ 1024U,
530 hw_atl_rdm_rx_desc_head_buff_size_set(self
, 0U, aq_ring
->idx
);
531 hw_atl_rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
532 hw_atl_rpo_rx_desc_vlan_stripping_set(self
, 0U, aq_ring
->idx
);
534 /* Rx ring set mode */
536 /* Mapping interrupt vector */
537 hw_atl_itr_irq_map_rx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
538 hw_atl_itr_irq_map_en_rx_set(self
, true, aq_ring
->idx
);
540 hw_atl_rdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
541 hw_atl_rdm_rx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
542 hw_atl_rdm_rx_head_dca_en_set(self
, 0U, aq_ring
->idx
);
543 hw_atl_rdm_rx_pld_dca_en_set(self
, 0U, aq_ring
->idx
);
545 return aq_hw_err_from_flags(self
);
548 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s
*self
,
549 struct aq_ring_s
*aq_ring
,
550 struct aq_ring_param_s
*aq_ring_param
)
552 u32 dma_desc_lsw_addr
= (u32
)aq_ring
->dx_ring_pa
;
553 u32 dma_desc_msw_addr
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
555 hw_atl_reg_tx_dma_desc_base_addresslswset(self
, dma_desc_lsw_addr
,
558 hw_atl_reg_tx_dma_desc_base_addressmswset(self
, dma_desc_msw_addr
,
561 hw_atl_tdm_tx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
563 hw_atl_a0_hw_tx_ring_tail_update(self
, aq_ring
);
565 /* Set Tx threshold */
566 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self
, 0U, aq_ring
->idx
);
568 /* Mapping interrupt vector */
569 hw_atl_itr_irq_map_tx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
570 hw_atl_itr_irq_map_en_tx_set(self
, true, aq_ring
->idx
);
572 hw_atl_tdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
573 hw_atl_tdm_tx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
575 return aq_hw_err_from_flags(self
);
578 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s
*self
,
579 struct aq_ring_s
*ring
,
580 unsigned int sw_tail_old
)
582 for (; sw_tail_old
!= ring
->sw_tail
;
583 sw_tail_old
= aq_ring_next_dx(ring
, sw_tail_old
)) {
584 struct hw_atl_rxd_s
*rxd
=
585 (struct hw_atl_rxd_s
*)&ring
->dx_ring
[sw_tail_old
*
588 struct aq_ring_buff_s
*buff
= &ring
->buff_ring
[sw_tail_old
];
590 rxd
->buf_addr
= buff
->pa
;
594 hw_atl_reg_rx_dma_desc_tail_ptr_set(self
, sw_tail_old
, ring
->idx
);
596 return aq_hw_err_from_flags(self
);
599 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s
*self
,
600 struct aq_ring_s
*ring
)
603 unsigned int hw_head
= hw_atl_tdm_tx_desc_head_ptr_get(self
, ring
->idx
);
605 if (aq_utils_obj_test(&self
->flags
, AQ_HW_FLAG_ERR_UNPLUG
)) {
609 ring
->hw_head
= hw_head
;
610 err
= aq_hw_err_from_flags(self
);
616 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s
*self
,
617 struct aq_ring_s
*ring
)
619 for (; ring
->hw_head
!= ring
->sw_tail
;
620 ring
->hw_head
= aq_ring_next_dx(ring
, ring
->hw_head
)) {
621 struct aq_ring_buff_s
*buff
= NULL
;
622 struct hw_atl_rxd_wb_s
*rxd_wb
= (struct hw_atl_rxd_wb_s
*)
623 &ring
->dx_ring
[ring
->hw_head
* HW_ATL_A0_RXD_SIZE
];
625 unsigned int is_err
= 1U;
626 unsigned int is_rx_check_sum_enabled
= 0U;
627 unsigned int pkt_type
= 0U;
629 if (!(rxd_wb
->status
& 0x5U
)) { /* RxD is not done */
631 hw_atl_reg_rx_dma_desc_status_get(self
, ring
->idx
)) {
632 hw_atl_rdm_rx_desc_en_set(self
, false, ring
->idx
);
633 hw_atl_rdm_rx_desc_res_set(self
, true, ring
->idx
);
634 hw_atl_rdm_rx_desc_res_set(self
, false, ring
->idx
);
635 hw_atl_rdm_rx_desc_en_set(self
, true, ring
->idx
);
639 (hw_atl_rdm_rx_desc_head_ptr_get(self
,
642 } else if (!(rxd_wb
->status
& 0x1U
)) {
643 struct hw_atl_rxd_wb_s
*rxd_wb1
=
644 (struct hw_atl_rxd_wb_s
*)
645 (&ring
->dx_ring
[(1U) *
646 HW_ATL_A0_RXD_SIZE
]);
648 if ((rxd_wb1
->status
& 0x1U
)) {
649 rxd_wb
->pkt_len
= 1514U;
657 buff
= &ring
->buff_ring
[ring
->hw_head
];
659 if (0x3U
!= (rxd_wb
->status
& 0x3U
))
662 is_err
= (0x0000001CU
& rxd_wb
->status
);
663 is_rx_check_sum_enabled
= (rxd_wb
->type
) & (0x3U
<< 19);
664 pkt_type
= 0xFFU
& (rxd_wb
->type
>> 4);
666 if (is_rx_check_sum_enabled
) {
667 if (0x0U
== (pkt_type
& 0x3U
))
668 buff
->is_ip_cso
= (is_err
& 0x08U
) ? 0 : 1;
670 if (0x4U
== (pkt_type
& 0x1CU
))
671 buff
->is_udp_cso
= (is_err
& 0x10U
) ? 0 : 1;
672 else if (0x0U
== (pkt_type
& 0x1CU
))
673 buff
->is_tcp_cso
= (is_err
& 0x10U
) ? 0 : 1;
675 /* Checksum offload workaround for small packets */
676 if (rxd_wb
->pkt_len
<= 60) {
677 buff
->is_ip_cso
= 0U;
678 buff
->is_cso_err
= 0U;
685 if (is_err
|| rxd_wb
->type
& 0x1000U
) {
686 /* status error or DMA error */
689 if (self
->aq_nic_cfg
->is_rss
) {
691 u16 rss_type
= rxd_wb
->type
& 0xFU
;
693 if (rss_type
&& rss_type
< 0x8U
) {
694 buff
->is_hash_l4
= (rss_type
== 0x4 ||
696 buff
->rss_hash
= rxd_wb
->rss_hash
;
700 if (HW_ATL_A0_RXD_WB_STAT2_EOP
& rxd_wb
->status
) {
701 buff
->len
= rxd_wb
->pkt_len
%
703 buff
->len
= buff
->len
?
704 buff
->len
: AQ_CFG_RX_FRAME_MAX
;
709 buff
->next
= aq_ring_next_dx(ring
,
711 ++ring
->stats
.rx
.jumbo_packets
;
716 return aq_hw_err_from_flags(self
);
719 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s
*self
, u64 mask
)
721 hw_atl_itr_irq_msk_setlsw_set(self
, LODWORD(mask
) |
722 (1U << HW_ATL_A0_ERR_INT
));
723 return aq_hw_err_from_flags(self
);
726 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s
*self
, u64 mask
)
728 hw_atl_itr_irq_msk_clearlsw_set(self
, LODWORD(mask
));
729 hw_atl_itr_irq_status_clearlsw_set(self
, LODWORD(mask
));
731 if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self
))
732 atomic_inc(&self
->dpc
);
734 return aq_hw_err_from_flags(self
);
737 static int hw_atl_a0_hw_irq_read(struct aq_hw_s
*self
, u64
*mask
)
739 *mask
= hw_atl_itr_irq_statuslsw_get(self
);
740 return aq_hw_err_from_flags(self
);
743 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
745 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s
*self
,
746 unsigned int packet_filter
)
750 hw_atl_rpfl2promiscuous_mode_en_set(self
,
751 IS_FILTER_ENABLED(IFF_PROMISC
));
752 hw_atl_rpfl2multicast_flr_en_set(self
,
753 IS_FILTER_ENABLED(IFF_MULTICAST
), 0);
754 hw_atl_rpfl2broadcast_en_set(self
, IS_FILTER_ENABLED(IFF_BROADCAST
));
756 self
->aq_nic_cfg
->is_mc_list_enabled
=
757 IS_FILTER_ENABLED(IFF_MULTICAST
);
759 for (i
= HW_ATL_A0_MAC_MIN
; i
< HW_ATL_A0_MAC_MAX
; ++i
)
760 hw_atl_rpfl2_uc_flr_en_set(self
,
761 (self
->aq_nic_cfg
->is_mc_list_enabled
&&
762 (i
<= self
->aq_nic_cfg
->mc_list_count
)) ?
765 return aq_hw_err_from_flags(self
);
768 #undef IS_FILTER_ENABLED
770 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s
*self
,
772 [AQ_HW_MULTICAST_ADDRESS_MAX
]
778 if (count
> (HW_ATL_A0_MAC_MAX
- HW_ATL_A0_MAC_MIN
)) {
782 for (self
->aq_nic_cfg
->mc_list_count
= 0U;
783 self
->aq_nic_cfg
->mc_list_count
< count
;
784 ++self
->aq_nic_cfg
->mc_list_count
) {
785 u32 i
= self
->aq_nic_cfg
->mc_list_count
;
786 u32 h
= (ar_mac
[i
][0] << 8) | (ar_mac
[i
][1]);
787 u32 l
= (ar_mac
[i
][2] << 24) | (ar_mac
[i
][3] << 16) |
788 (ar_mac
[i
][4] << 8) | ar_mac
[i
][5];
790 hw_atl_rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_A0_MAC_MIN
+ i
);
792 hw_atl_rpfl2unicast_dest_addresslsw_set(self
,
794 HW_ATL_A0_MAC_MIN
+ i
);
796 hw_atl_rpfl2unicast_dest_addressmsw_set(self
,
798 HW_ATL_A0_MAC_MIN
+ i
);
800 hw_atl_rpfl2_uc_flr_en_set(self
,
801 (self
->aq_nic_cfg
->is_mc_list_enabled
),
802 HW_ATL_A0_MAC_MIN
+ i
);
805 err
= aq_hw_err_from_flags(self
);
811 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s
*self
)
816 if (self
->aq_nic_cfg
->itr
) {
817 if (self
->aq_nic_cfg
->itr
!= AQ_CFG_INTERRUPT_MODERATION_AUTO
) {
818 u32 itr_
= (self
->aq_nic_cfg
->itr
>> 1);
820 itr_
= min(AQ_CFG_IRQ_MASK
, itr_
);
822 itr_rx
= 0x80000000U
| (itr_
<< 0x10);
824 u32 n
= 0xFFFFU
& aq_hw_read_reg(self
, 0x00002A00U
);
826 if (n
< self
->aq_link_status
.mbps
) {
829 static unsigned int hw_timers_tbl_
[] = {
832 0x039U
, /* 5Gbit 5GS */
833 0x073U
, /* 2.5Gbit */
835 0x1FFU
, /* 100Mbit */
838 unsigned int speed_index
=
839 hw_atl_utils_mbps_2_speed_index(
840 self
->aq_link_status
.mbps
);
842 itr_rx
= 0x80000000U
|
843 (hw_timers_tbl_
[speed_index
] << 0x10U
);
846 aq_hw_write_reg(self
, 0x00002A00U
, 0x40000000U
);
847 aq_hw_write_reg(self
, 0x00002A00U
, 0x8D000000U
);
853 for (i
= HW_ATL_A0_RINGS_MAX
; i
--;)
854 hw_atl_reg_irq_thr_set(self
, itr_rx
, i
);
856 return aq_hw_err_from_flags(self
);
859 static int hw_atl_a0_hw_stop(struct aq_hw_s
*self
)
861 hw_atl_a0_hw_irq_disable(self
, HW_ATL_A0_INT_MASK
);
862 return aq_hw_err_from_flags(self
);
865 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s
*self
,
866 struct aq_ring_s
*ring
)
868 hw_atl_tdm_tx_desc_en_set(self
, 0U, ring
->idx
);
869 return aq_hw_err_from_flags(self
);
872 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s
*self
,
873 struct aq_ring_s
*ring
)
875 hw_atl_rdm_rx_desc_en_set(self
, 0U, ring
->idx
);
876 return aq_hw_err_from_flags(self
);
879 const struct aq_hw_ops hw_atl_ops_a0
= {
880 .hw_set_mac_address
= hw_atl_a0_hw_mac_addr_set
,
881 .hw_init
= hw_atl_a0_hw_init
,
882 .hw_reset
= hw_atl_a0_hw_reset
,
883 .hw_start
= hw_atl_a0_hw_start
,
884 .hw_ring_tx_start
= hw_atl_a0_hw_ring_tx_start
,
885 .hw_ring_tx_stop
= hw_atl_a0_hw_ring_tx_stop
,
886 .hw_ring_rx_start
= hw_atl_a0_hw_ring_rx_start
,
887 .hw_ring_rx_stop
= hw_atl_a0_hw_ring_rx_stop
,
888 .hw_stop
= hw_atl_a0_hw_stop
,
890 .hw_ring_tx_xmit
= hw_atl_a0_hw_ring_tx_xmit
,
891 .hw_ring_tx_head_update
= hw_atl_a0_hw_ring_tx_head_update
,
893 .hw_ring_rx_receive
= hw_atl_a0_hw_ring_rx_receive
,
894 .hw_ring_rx_fill
= hw_atl_a0_hw_ring_rx_fill
,
896 .hw_irq_enable
= hw_atl_a0_hw_irq_enable
,
897 .hw_irq_disable
= hw_atl_a0_hw_irq_disable
,
898 .hw_irq_read
= hw_atl_a0_hw_irq_read
,
900 .hw_ring_rx_init
= hw_atl_a0_hw_ring_rx_init
,
901 .hw_ring_tx_init
= hw_atl_a0_hw_ring_tx_init
,
902 .hw_packet_filter_set
= hw_atl_a0_hw_packet_filter_set
,
903 .hw_multicast_list_set
= hw_atl_a0_hw_multicast_list_set
,
904 .hw_interrupt_moderation_set
= hw_atl_a0_hw_interrupt_moderation_set
,
905 .hw_rss_set
= hw_atl_a0_hw_rss_set
,
906 .hw_rss_hash_set
= hw_atl_a0_hw_rss_hash_set
,
907 .hw_get_regs
= hw_atl_utils_hw_get_regs
,
908 .hw_get_hw_stats
= hw_atl_utils_get_hw_stats
,
909 .hw_get_fw_version
= hw_atl_utils_get_fw_version
,